LM4935 Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC 1.0 General Description j Supply Voltage Range The LM4935 is an integrated audio subsystem that supports both analog and digital audio functions. The LM4935 includes a high quality stereo DAC, a mono ADC, a multipurpose SAR ADC, a stereo headphone amplifier, which supports output cap-less (OCL) or AC-coupled (SE)modes of operation, a mono earpiece amplifier and a mono high efficiency loudspeaker amplifier. It is designed for demanding applications in mobile phones and other portable devices. The LM4935 features a bi-directional I2S serial interface for full range audio and an I2C or SPI compatible interface for control. The stereo DAC path features an SNR of 88 dB with an 18-bit 48 kHz input. In SE mode the headphone amplifier delivers at least 33 mWRMS to a 32Ω single-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono earpiece amplifier delivers at least 115 mWRMS to a 32Ω bridged-tied load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono speaker amplifier delivers up to 600 mW into an 8Ω load with less than 1% distortion when LS_VDD = 3.3V and up to 1.3W when LS_VDD = 5.0V. The LM4935 also contains a general purpose SAR ADC for housekeeping duties such as battery and temperature monitoring. This can also be used for analog volume control of the output stages and can trigger interrupt events. The LM4935 employs advanced techniques to reduce power consumption, to reduce controller overhead to speed development time and to eliminate click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. It is therefore ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area and cost are primary requirements. 2.0 Applications n n n n n Smartphones Mobile Phones and Multimedia Terminals PDAs, Internet Appliances and Portable Gaming Portable DVD/CD/AAC/MP3 Players Digital Cameras/Camcorders 3.0 Key Specifications n n n n n PHP (AC-COUP) @ A_VDD = 3.3V, 32Ω, 1% THD 33 mW PHP (OCL) @ A_VDD = 3.3V, 32Ω, 1% THD 31 mW PLS @ LS_VDD = 5V, 8Ω, 1% THD 1.3 W PLS @ LS_VDD = 4.2V, 8Ω, 1% THD 900 mW PLS @ LS_VDD = 3.3V, 8Ω, 1% THD 600 mW BB_VDD = 1.8V to 4.5V, D_VDD & PLL_VDD = 2.7V to 4.5V LS_VDD & A_VDD = 2.7V to 5.5V n n n n n Shutdown Current PSRR @ 217 Hz, A_VDD = 3.3V, (Headphone) SNR (Stereo DAC to AUXOUT) 88 SNR (Mono ADC from Cell Phone In) 90 SNR (Aux In to Headphones) 98 1.1 µA 60 dB dB (typ) dB (typ) dB (typ) 4.0 Features n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n 18-bit stereo DAC 16-bit mono ADC 12-bit 4 input multipurpose SAR ADC 8 kHz to 48 kHz stereo audio playback 8 kHz to 48 kHz mono recording 1 Hz to 13.888 kHz sample rate on all 4 SAR channels Bidirectional PCM/I2S compatible audio interface Sigma-Delta PLL for operation from any clock at any sample rate Low power clock network operation if 12 MHz system clock is available Read/write I2C or SPI compatible control interface 33mW stereo headphone amplifier at 3.3V OCL or AC-coupled headphone operation Automatic headphone & microphone detection Support for internal and external microphones Automatic gain control for microphone input High efficiency BTL 8Ω amplifier, 600 mW @ 3.3V 115 mW earpiece amplifier at 3.3V Differential audio I/O for external cellphone module Mono differential auxiliary output Stereo auxiliary inputs Differential microphone input for internal microphone Flexible audio routing from input to output 32 Step volume control for mixers with 1.5 dB steps 16 Step volume control for microphone in 2 dB steps Programmable sidetone attenuation in 3 dB steps DC Volume Control Two configurable GPIO ports Programmable voltage triggers on SAR channels Multi-function IRQ output Micro-power shutdown mode Available in the 4 x 4 mm 49 bump microfil package Boomer ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201341 www.national.com LM4935 Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC October 2005 LM4935 5.0 LM4935 Overview 20134101 FIGURE 1. Conceptual Schematic www.national.com 2 LM4935 6.0 Typical Application 20134102 FIGURE 2. Example Application in Multimedia Mobile Phone 3 www.national.com LM4935 Table of Contents 1.0 General Description ..................................................................................................................................... 1 2.0 Applications .................................................................................................................................................. 1 3.0 Key Specifications ........................................................................................................................................ 1 4.0 Features ....................................................................................................................................................... 1 5.0 LM4935 Overview ........................................................................................................................................ 2 6.0 Typical Application ........................................................................................................................................ 3 7.0 Connection Diagrams ................................................................................................................................... 6 7.1 PIN TYPE DEFINITIONS .......................................................................................................................... 7 8.0 Absolute Maximum Ratings ........................................................................................................................ 8 9.0 Operating Ratings ........................................................................................................................................ 8 10.0 Electrical Characteristics ........................................................................................................................... 8 11.0 System Control ......................................................................................................................................... 16 11.1 I2C SIGNALS ......................................................................................................................................... 16 11.2 I2C DATA VALIDITY ............................................................................................................................... 16 11.3 I2C START AND STOP CONDITIONS .................................................................................................. 16 11.4 TRANSFERRING DATA ........................................................................................................................ 16 11.5 I2C TIMING PARAMETERS ................................................................................................................. 18 12.0 Status & Control Registers ...................................................................................................................... 20 12.1 BASIC CONFIGURATION REGISTER ................................................................................................. 21 12.2 CLOCKS CONFIGURATION REGISTER ............................................................................................. 22 12.3 LM4935 CLOCK NETWORK ................................................................................................................ 23 12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC ....................................................................... 24 12.5 PLL M DIVIDER CONFIGURATION REGISTER .................................................................................. 25 12.6 PLL N DIVIDER CONFIGURATION REGISTER .................................................................................. 26 12.7 PLL P DIVIDER CONFIGURATION REGISTER .................................................................................. 27 12.8 PLL N MODULUS CONFIGURATION REGISTER ............................................................................... 28 12.9 FURTHER NOTES ON PLL PROGRAMMING ..................................................................................... 29 12.10 ADC_1 CONFIGURATION REGISTER ............................................................................................... 31 12.11 ADC_2 CONFIGURATION REGISTER ............................................................................................... 32 12.12 AGC_1 CONFIGURATION REGISTER ............................................................................................. 33 12.13 AGC_2 CONFIGURATION REGISTER ............................................................................................. 34 12.14 AGC_3 CONFIGURATION REGISTER ............................................................................................. 35 12.15 AGC OVERVIEW ................................................................................................................................. 36 12.16 MIC_1 CONFIGURATION REGISTER ............................................................................................... 37 12.17 MIC_2 CONFIGURATION REGISTER ............................................................................................... 38 12.18 SIDETONE ATTENUATION REGISTER ............................................................................................. 39 12.19 CP_INPUT CONFIGURATION REGISTER ........................................................................................ 40 12.20 AUX_LEFT CONFIGURATION REGISTER ........................................................................................ 41 12.21 AUX_RIGHT CONFIGURATION REGISTER ...................................................................................... 42 12.22 DAC CONFIGURATION REGISTER .................................................................................................. 43 12.23 CP_OUTPUT CONFIGURATION REGISTER .................................................................................... 44 12.24 AUX_OUTPUT CONFIGURATION REGISTER .................................................................................. 45 12.25 LS_OUTPUT CONFIGURATION REGISTER ..................................................................................... 46 12.26 HP_OUTPUT CONFIGURATION REGISTER .................................................................................... 47 12.27 EP_OUTPUT CONFIGURATION REGISTER .................................................................................... 48 12.28 DETECT CONFIGURATION REGISTER ............................................................................................ 49 12.29 HEADSET DETECT OVERVIEW ........................................................................................................ 50 12.30 STATUS REGISTER ........................................................................................................................... 53 12.31 AUDIO INTERFACE CONFIGURATION REGISTER ......................................................................... 54 12.32 DIGITAL AUDIO DATA FORMATS ...................................................................................................... 55 12.33 GPIO CONFIGURATION REGISTER ................................................................................................. 56 12.34 SAR CHANNELS 0 & 1 CONFIGURATION REGISTER .................................................................... 57 12.35 SAR CHANNELS 2 & 3 CONFIGURATION REGISTER .................................................................... 58 12.36 SAR DATA 0 TO 3 REGISTERS ......................................................................................................... 59 12.37 SAR OVERVIEW ................................................................................................................................. 60 12.38 DC VOLUME CONFIGURATION REGISTER .................................................................................... 62 12.39 SAR TRIGGER 1 CONFIGURATION REGISTER .............................................................................. 63 12.40 SAR TRIGGER 1 MSBs CONFIGURATION REGISTER ................................................................... 64 12.41 SAR TRIGGER 2 CONFIGURATION REGISTER .............................................................................. 65 12.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER ................................................................... 66 12.43 DEBUG REGISTER ........................................................................................................................... 67 13.0 Typical Performance Characteristics ....................................................................................................... 68 www.national.com 4 14.0 15.0 16.0 17.0 18.0 LM4935 Table of Contents (Continued) LM4935 Demonstration Board Schematic Diagram .............................................................................. Demoboard PCB Layout ........................................................................................................................ Product Status Definitions ...................................................................................................................... Revision History ...................................................................................................................................... Physical Dimensions .............................................................................................................................. 5 104 105 110 111 112 www.national.com LM4935 7.0 Connection Diagrams 49 Bump Microfil 49 Bump Microfil Marking 201341P5 Top View XY — Date Code TT — Die Traceability G — Boomer F4 — LM4935WL/WLX 201341P3 Top View (Bump Side Down) Order Number LM4935 See NS Package Number WLA49VVA Pin Descriptions Pin Pin Name Type Direction A1 EP_NEG Analog Output Description A2 A_VDD Supply Input Headphone and mixer VDD A3 INT_MIC_POS Analog Input Internal microphone positive input A4 EXT_MIC Analog Input External microphone input A5 VSAR2 Analog Input Input to SAR channel 2 A6 VSAR1 Analog Input Input to SAR channel 1 A7 PLL_VSS Supply Input PLL VSS B1 A_VSS Supply Input B2 EP_POS Analog Output B3 INT_MIC_NEG Analog Input Internal microphone negative input B4 BYPASS Analog Inout A_VDD/2 filter point B5 TEST_MODE/CS Digital Input If SPI_MODE = 1, then this pin becomes CS. If SPI_MODE = 0, and TEST_MODE/CS = 1, then this places the LM4935 into test mode. B6 PLL_FILT Analog Inout Filter point for PLL VCO input B7 PLL_VDD Supply Input C1 HP_R Analog Output Headphone Right Output C2 EXT_BIAS Analog Output External microphone supply (2.0/2.5/2.8/3.3V) C3 INT_BIAS Analog Output 2.0V/2.5V ultra-clean supply for internal microphone C4 AUX_R Analog Input Right Analog Input C5 GPIO_2 Digital Inout General Purpose I/O 2 C6 SDA Digital Inout Control Data, I2C_SDA or SPI_SDI C7 SCL Digital Input D1 HP_L Analog Output D2 VREF_FLT Analog Inout Filter point for the microphone power supply D3 AUX_L Analog Input Left Analog Input D4 SPI_MODE Digital Input Control mode select 1 = SPI, 0 = I2C (or test) D5 GPIO_1 Digital Inout General Purpose I/O 1 Earpiece negative output Headphone and mixer VSS Earpiece positive output PLL VDD Control Clock, I2C_SCL or SPI_SCK Headphone Left Output D6 BB_VDD Supply Input Baseband VDD for the digital I/Os D7 D_VDD Supply Input Digital VDD E1 HP_VMID Analog Inout Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input www.national.com 6 Pin Descriptions LM4935 7.0 Connection Diagrams (Continued) (Continued) Pin Pin Name Type Direction E2 HP_VMID_FB Analog Inout VMID Feedback in OCL mode, otherwise a 2nd headset detection input Description E3 MIC_DET Analog Input Headset insertion/removal and Microphone presence detection input E4 CPI_NEG Analog Input E5 IRQ Digital Output E6 I2S_SDO Digital Output E7 I2S_SDI Digital Input I2S Serial Data Input F1 LS_VDD Supply Input Loudspeaker VDD Cell Phone analog input negative Interrupt request signal (NOT open drain) I2S Serial Data Out F2 LS_VDD Supply Input Loudspeaker VDD F3 CPI_POS Analog Input Cell Phone analog input positive F4 CPO_NEG Analog Output Cell Phone analog output negative F5 AUX_OUT_NEG Analog Output Auxiliary analog output negative F6 I2S_WS Digital Inout F7 I2S_CLK Digital Inout G1 LS_POS Analog Output I2S Word Select Signal (can be master or slave) I2S Clock Signal (can be master or slave) Loudspeaker positive output G2 LS_VSS Supply Input G3 LS_NEG Analog Output Loudspeaker negative output G4 CPO_POS Analog Output Cell Phone analog output positive G5 AUX_OUT_POS Analog Output Auxiliary analog output positive G6 D_VSS Supply Input Digital VSS G7 MCLK Digital Input Input clock from 0.5 MHz to 30 MHz Loudspeaker VSS 7.1 PIN TYPE DEFINITIONS Analog Input — A pin that is used by the analog and is never driven by the device. Supplies are part of this classification. Digital Output — Analog Output — A pin that is driven by the device and should not be driven by external sources. Analog Inout — A pin that is typically used for filtering a DC signal within the device, Passive components can be connected to these pins. Digital Input — A pin that is used by the digital but is Digital Inout — 7 never driven. A pin that is driven by the device and should not be driven by another device to avoid contention. A pin that is either open drain (I2C_SDA) or a bidirectional CMOS in/out. In the later case the direction is selected by a control register within the LM4935. www.national.com LM4935 8.0 Absolute Maximum Ratings Thermal Resistance θJA – WLA49 (soldered down to PCB with 2in2 1oz. copper plane) (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage (A_VDD & LS_VDD) Digital Supply Voltage (BB_VDD & D_VDD & PLL_VDD) 60˚C/W Soldering Information 6.0V See AN-1279 for MicrofilTM package information. Peak reflow temperature should not exceed 235˚C. 6.0V 9.0 Operating Ratings Storage Temperature −65˚C to +150˚C Power Dissipation (Note 3) Internally Limited ESD Susceptibility Human Body Model (Note 4) Machine Model (Note 5) 2500V 200V Junction Temperature 150˚C Temperature Range −40˚C to +85˚C Supply Voltage D_VDD/PLL_VDD BB_VDD LS_VDD/A_VDD 2.7V to 4.5V 1.8V to 4.5V 2.7V to 5.5V 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units DC CURRENT CONSUMPTION Chip Mode ’00’, fMCLK = 13MHz DISD DIST DIDD Digital Shutdown Current Digital Standby Current Digital Active Current Chip Mode ’00’, fMCLK = 19.2MHz 0.7 0.7 µA 5 µA (max) Chip Mode ’01’, fMCLK = 13MHz 1.5 Chip Mode ’01’, fMCLK = 19.2MHz 2.2 Chip Mode ’10’, fMCLK = 13MHz, DAC, ADC, SAR OFF 1.5 mA Chip Mode ’10’, fMCLK = 19.2MHz, DAC, ADC, SAR OFF 2.2 mA Chip Mode ’10’, fMCLK = 13MHz DAC, ADC, SAR ON 11.2 mA Chip Mode ’10’, fMCLK = 19.2MHz, DAC, ADC, SAR ON 16.2 20 mA (max) 0.2 3 µA (max) 3 µA (max) mA 3 mA (max) AISD Analog Shutdown Current Chip Mode ’00’ AIST Analog Standby Current Chip Mode ’01’, No headset inserted 0.2 All Outputs OFF, SE MODE 6.1 mA All Outputs OFF, OCL MODE 5.7 mA All Outputs ON, SE MODE 18.3 mA AIDD Analog Active Current All Outputs ON, OCL MODE PLLIDD ADCIDD www.national.com PLL Active Current ADC Active Current 18.7 28 mA (max) fMCLK = 13 MHz fPLLOUT = 12 MHz, PLL ON only 4.2 mA fMCLK = 19.2 MHz fPLLOUT = 12 MHz, PLL ON only 6.2 mA fMCLK = 13MHz, ADC ON only 2.5 mA fMCLK = 19.2MHz, ADC ON only 3.6 mA 8 LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units DC CURRENT CONSUMPTION DACIDD DAC Active Current fMCLK = 13MHz, DAC ON only; PLL OFF, fS = 48kHz 7.4 mA fMCLK = 19.2MHz, DAC ON only PLL OFF; fS = 48kHz 10.7 mA fMCLK = 13MHz, SAR ON only 1.6 mA SARIDD SAR Active Current LSIDD Loudspeaker Quiescent Current HPIDD Headphone Quiescent Current HP ON only, OCL MODE 3.9 mA EPIDD Earpiece Quiescent Current EP ON only 4.4 mA AUXIDD AUXOUT Quiescent Current AUXOUT ON only 4.8 mA CPOUTIDD CPOUT Quiescent Current CPOUT ON only 4.8 mA 8Ω load, LS_VDD = 5V 1.3 W 8Ω load, LS_VDD = 4.2V 0.9 W fMCLK = 19.2MHz, SAR ON only 2.3 mA LS ON only 8.8 mA HP ON only, SE MODE 3.5 mA LOUDSPEAKER AMPLIFIER PLS Max Loudspeaker Power 8Ω load, LS_VDD = 3.3V 0.6 LSTHD+N Loudspeaker Harmonic Distortion 8Ω load, LS_VDD = 3.3V, PO = 400mW 0.4 % LSEFF Efficiency 0 dB Input MCLK = 12.000 MHz 84 % PSRRLS Power Supply Rejection Ration (Loudspeaker) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz 54 dB SNRLS Signal to Noise Ratio From 0 dB Analog AUX input at 1 kHz, A-weighted 76 dB eN Output Noise A-weighted 350 µV VOS Offset Voltage 7 mV 0.44 W (min) HEADPHONE AMPLIFIER PHP PSRRHP Headphone Power Power Supply Rejection Ratio (Headphones) 32Ω load, 3.3V, SE 33 20 mW (min) 16Ω load, 3.3V, SE 52 mW 32Ω load, 3.3V, OCL, VCM = 1.5V 31 mW 32Ω load, 3.3V, OCL, VCM = 1.2V 20 mW 16Ω load, 3.3V, OCL, VCM = 1.5V 50 mW 16Ω load, 3.3V, OCL, VCM = 1.2V 32 mW SE Mode 60 dB OCL Mode VCM = 1.2V 68 dB OCL Mode VCM = 1.5V 65 dB AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P fRIPPLE = 217 Hz 9 www.national.com LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units HEADPHONE AMPLIFIER From 0dB Analog AUX input A-weighted SNRHP Signal to Noise Ratio SE Mode 98 dB OCL Mode VCM = 1.2V 97 dB OCL Mode VCM = 1.5V 96 dB HPTHD+N Headphone Harmonic Distortion 32Ω load, 3.3V, PO = 7.5mW eN Output Noise A-weighted ∆ACH-CH Stereo Channel-to-Channel Gain Mismatch XTALK Stereo Crosstalk 0.05 % 12 µV 0.3 dB SE Mode 61 dB OCL Mode 63 dB EARPIECE AMPLIFIER PEP Earpiece Power 16Ω load, 3.3V 150 mW PSRREP Power Supply Rejection Ratio (Earpiece) AUX inputs terminated CBYPASS = 1.0 µF VRIPPLE = 200 mVP-P FRIPPLE = 217 Hz 65 dB SNREP Signal to Noise Ratio From 0dB Analog AUX input, A-weighted 98 dB 0.04 % 24 µV 15 mV 32Ω load, 3.3V EPTHD+N Earpiece Harmonic Distortion 32Ω load, 3.3V, PO = 50mW eN Output Noise A-weighted VOS Offset Voltage 115 100 mW (min) AUXOUT AMPLIFIER THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5kΩ load 0.02 % PSRR Power Supply Rejection Ratio AUX inputs terminated CBYPASS = 1.0µF VRIPPLE = 200mVPP fRIPPLE = 217Hz 70 dB 0.02 % 68 dB CP_OUT AMPLIFIER THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5kΩ load PSRR Power SUpply Rejection Ratio CBYPASS = 1.0µF VRIPPLE = 200mVPP fRIPPLE = 217Hz MONO ADC RADC ADC Ripple PBADC ADC Passband SBAADC ADC Stopband Attenuation SNRADC ADC Signal to Noise Ratio ADCLEVEL ADC Full Scale Input Level www.national.com ± 0.25 dB Lower (HPF Mode 1), fS = 8 kHz 300 Hz Upper 3470 Hz Above Passband 60 dB HPF Notch, 50 Hz/60 Hz (worst case) 58 dB From CPI, A-weighted 90 dB 1 VRMS 10 LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units STEREO DAC RDAC DAC Ripple 0.1 dB PBDAC DAC Passband 20 kHz SBADAC DAC Stopband Attenuation 70 dB SNRDAC DAC Signal to Noise Ratio 88 dB DRDAC DAC Dynamic Range 96 dB DACLEVEL DAC Full Scale Output Level 1 VRMS Min 0.5 MHz Max 30 MHz A-weighted, AUXOUT PLL FIN Input Frequency Range I2S/PCM fI2SCLK fPCMCLK DCI2S_CLK I2S CLK Frequency PCM CLK Frequency I2S_CLK Duty Cycle fS = 48kHz; 16 bit mode 1.536 MHz fS = 48kHz; 25 bit mode 2.4 MHz fS = 8kHz; 16 bit mode 0.256 MHz fS = 8kHz; 25 bit mode 0.4 MHz fS = 48kHz; 16 bit mode 0.768 MHz fS = 48kHz; 25 bit mode 1.2 MHz fS = 8kHz; 16 bit mode 0.128 MHz fS = 8kHz; 25 bit mode 0.2 MHz Min Max DCI2S_WS I2S_WS Duty Cycle 40 % (min) 60 % (max) 50 % I2C TI2CSET I2C Data Setup Time Refer to Pg. 18 for more details 100 ns (min) TI2CHOLD I2C Data Hold Time Refer to Pg. 18 for more details 300 ns (min) SPI TSPISETENB Enable Setup Time 100 ns (min) TSPIHOLD-ENB Enable Hold Time 100 ns (min) TSPISETD Data Setup Time 100 ns (min) TSPIHOLDD Data Hold Time 100 ns (min) TSPICL Clock Low Time 500 ns (min) TSPICH Clock High Time 500 ns (min) VOLUME CONTROL Minimum Gain w/ AUX_BOOST OFF VCRAUX VCRDAC VCRCPIN AUX Volume Control Range DAC Volume Control Range CPIN Volume Control Range –46.5 dB 0 dB Minimum Gain w/ AUX_BOOST ON –34.5 dB Maximum Gain w/ AUX_BOOST ON 12 dB Minimum Gain w/ DAC_BOOST OFF –46.5 dB 0 dB Minimum Gain w/ DAC_BOOST ON –34.5 dB Maximum Gain w/ DAC_BOOST ON 12 dB Maximum Gain w/ AUX_BOOST OFF Maximum Gain w/ DAC_BOOST OFF Minimum Gain –34.5 dB Maximum Gain 12 dB 11 www.national.com LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units VOLUME CONTROL VCRMIC MIC Volume Control Range Minimum Gain 6 dB Maximum Gain 36 dB Minimum Gain –30 dB VCRSIDE SIDETONE Volume Control Range 0 dB SSAUX AUX VCR Stepsize 1.5 dB SSDAC DAC VCR Stepsize 1.5 dB SSCPIN CPIN VCR Stepsize 1.5 dB SSMIC MIC VCR Stepsize 2 dB SSSIDE SIDETONE VCR Stepsize 3 dB www.national.com Maximum Gain 12 LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer) Loudspeaker Audio Path Gain Minimum Gain from AUX input, BOOST OFF –34.5 dB Maximum Gain from AUX input, BOOST OFF 12 dB –22.5 dB Maximum Gain from CPI input 24 dB Minimum Gain from AUX input, BOOST OFF –52.5 dB Maximum Gain from AUX input, BOOST OFF –6 dB Minimum Gain from CPI input Headphone Audio Path Gain Minimum Gain from CPI input –40.5 dB Maximum Gain from CPI input 6 dB Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB –30 dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB 0 dB Minimum Gain from AUX input, BOOST OFF –40.5 dB Maximum Gain from AUX input, BOOST OFF 6 dB –28.5 dB Maximum Gain from CPI input 18 dB Minimum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB –18 dB Maximum Gain from MIC input using SIDETONE path w/ VCRMIC gain = 6dB 12 dB Minimum Gain from AUX input, BOOST OFF –46.5 dB Maximum Gain from AUX input, BOOST OFF 0 dB Minimum Gain from CPI input Earpiece Audio Path Gain AUXOUT Audio Path Gain CPOUT Audio Path Gain Minimum Gain from CPI input –34.5 dB Maximum Gain from CPI input 12 dB Minimum Gain from AUX input, BOOST OFF –46.5 dB Maximum Gain from AUX input, BOOST OFF 0 dB Minimum Gain from MIC input 6 dB Maximum Gain from MIC input 36 dB 13 www.national.com LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 Symbol Parameter Conditions Typical (Note 6) Limit (Note 7) Units Total DC Power Dissipation DAC (fS = 48kHz) and HP ON MP3 Mode Power Dissipation fMCLK = 12MHz, PLL OFF 57 mW fMCLK = 13MHz, PLL ON fPLLOUT = 12MHz 63 mW fMCLK = 19.2MHz, PLL ON fPLLOUT = 12MHz 64 mW 24 mW AUX Inputs selected and HP ON FM Mode Power Dissipation fMCLK = 12MHz, PLL OFF fMCLK = 13MHz, PLL OFF 25 mW fMCLK = 19.2MHz, PLL OFF 27 mW fMCLK = 12MHz, PLL OFF 49 mW fMCLK = 13MHz, PLL OFF 50 mW fMCLK = 19.2MHz, PLL ON fPLLOUT = 12MHz 56 mW mW PCM DAC (fS = 8kHz) + ADC (fS = 8kHz) and EP ON VOICE CODEC Mode Power Dissipation CP IN selected. EP and CPOUT ON VOICE Module Mode Power Dissipation www.national.com fMCLK = 12MHz, PLL OFF 30 fMCLK = 13MHz, PLL OFF 31 mW fMCLK = 19.2MHz, PLL OFF 33 mW 14 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 2: All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device. Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor. Note 5: Machine model: 220pF – 240pF discharged through all pins. Note 6: Typical values are measured at 25˚C and represent the parametric norm. Note 7: Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level). Note 8: Best operation is achieved by maintaining 3.0V < A_VDD < 5.0 and 3.0V < D_VDD < 3.6V and A_VDD > D_VDD. Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled. Note 10: Disabling or bypassing the PLL will usually result in an improvement in noise measurements. 15 www.national.com LM4935 10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25˚C. (Continued) LM4935 11.0 System Control Method 1. I2C Compatible Interface 11.1 I2C SIGNALS In I2C mode the LM4935 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM4935 is 00110102. 11.2 I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when SCL is LOW. 201341Q1 I2C Signals: Data Validity 11.3 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 201341Q2 11.4 TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LM4935 address is 00110102. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. 201341Q3 I2C Chip Address Register changes take an effect at the SCL rising edge during the last ACK from slave. www.national.com 16 LM4935 11.0 System Control (Continued) 201341Q5 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by slave) rs = repeated start Example I2C Write Cycle 17 www.national.com LM4935 11.0 System Control (Continued) When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 201341Q6 Example I2C Read Cycle 201341P9 I2C Timing Diagram 11.5 I2C TIMING PARAMETERS Symbol Parameter Limit Min Units Max 1 Hold Time (repeated) START Condition 0.6 2 Clock Low Time 1.3 µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time (Output direction, delay generated by LM4935) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 8 Fall Time of SDA and SCL 15+0.1Cb 300 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 µs Cb Capacitive Load for Each Bus Line 10 100 NOTE: Data guaranteed by design www.national.com µs 18 ns 200 ns ns pF LM4935 11.0 System Control (Continued) Method 2. SPI/Microwire Control/3–wire Control The LM4935 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the chip_select as follows: 20134106 FIGURE 3. SPI Write Transaction If the application requires read access to the register set; for example to determine the cause of an interrupt request or to read back a SAR data field, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-only locations above 0x80h: 20134107 FIGURE 4. SPI Read Transaction Three Wire Mode Write Bus Timing 20134109 FIGURE 5. SPI Timing 19 www.national.com LM4935 12.0 Status & Control Registers TABLE 1. Register Map Address Register 7 6 0x00h BASIC OCL STEREO 0x01h CLOCKS 0x02h PLL_M 0x03h PLL_N 0x04h PLL_P RSVD 0x05h PLL_MOD RSVD 0x06h ADC_1 5 4 CAP_SIZE 3 2 USE_OSC PLL_ENB 1 CHP_MODE R_DIV PLLINPUT ADCLK PLL_M DACCLK RSVD PLL_N Q_DIV PLL_P DITHER_LEVEL HPF_MODE ADC_2 0x08h AGC_1 IF216 0x09h AGC_2 0x0Ah AGC_3 AGC_ATTACK 0x0Bh MIC_1 INT_EXT 0x0Ch MIC_2 0x0Dh SIDETONE RIGHT ADC_I2SM AGC_FRAME_TIME NOISE_GATE_THRESHOLD NG_ON AGC_TIGHT RSVD PLL_N_MOD SAMPLE_RATE 0x07h LEFT CPI ADCMUTE COMPND AGC_TARGET AGC_DECAY AGC_HOLD_TIME SE_DIFF MUTE PREAMP_GAIN BTNTYPE MIC_BIAS_VOLTAGE CP_INPUT MUTE CPI_LEVEL AUX_LEFT AUX_DAC MUTE BOOST AUX_LEFT_LEVEL 0x10h AUX_RIGHT AUX_DAC MUTE BOOST AUX_RIGHT_LEVEL DACMUTE BOOST USAXLVL DAC CP_OUTPUT 0x13h AUX OUTPUT 0x14h LS_OUTPUT 0x15h HP_OUTPUT 0x16h EP_OUTPUT 0x17h DETECT DAC_LEVEL MICGATE MUTE LEFT RIGHT MIC MUTE LEFT RIGHT CPI MUTE LEFT RIGHT CPI MUTE LEFT RIGHT CPI SIDE MUTE LEFT RIGHT CPI HS_DBNC_TIME GPIN STATUS 0x19h AUDIO_IF 0x1Ah GPIO GPIODATA 0x1Bh SAR_SLT0/1 SLT1ENB 0x1Ch SAR_SLT2/3 0x1Dh SAR_DATA_0 SLOT0_DATA 0x1Eh SAR_DATA_1 SLOT1_DATA 0x1Fh SAR_DATA_2 SLOT2_DATA 0x20h SAR_DATA_3 SLOT3_DATA 0x21h DC_VOL TRIG_1 0x23h TRIG_1_MSB 0x24h TRIG_2 0x25h TRIG_2_MSB 0x26h DEBUG TEMP TEMP_INT BTN_INT 0x18h 0x22h VCMVOLT SIDETONE_ATTEN 0x0Fh 0x11h U/ALAW AGC_MAX_GAIN BTN_DEBOUNCE_TIME 0x12h MIC AGC_ENB 0x0Eh I2S_SDO_DATA PCM_LNG SARTRG2 SARTRG1 PCMCLMS PCMSYMS I2SCLKMS I2SWSMS I2S_MODE MIC SAR_CH_SEL SLOT1_FS SLT2VBB BTN SLT3ENB STEREO HEADSET GPIO_SEL SLT0ENB SLOT0_FS SLT2ENB SLOT2_FS TRIG_1 [3:0] SIDE DET_INT AUDIO_IF_MODE MAX_LVL EFFECT DCVLENB SOURCE DIR ENB SOURCE DIR ENB RSVD RSVD TRIG_1 [11:4] TRIG_2 [3:0] TRIG_2 [11:4] GPIO_TEST _MODE RSVD RSVD RSVD SOFT RESET RSVD For all registers, the default setting of data bits 7 through 0 are all set to zero. RESERVED bits should always be set to zero. www.national.com 0 20 LM4935 12.0 Status & Control Registers (Continued) 12.1 BASIC CONFIGURATION REGISTER This register is used to control the basic function of the chip. TABLE 2. BASIC (0x00h) Bits Field 1:0 CHIP_MODE Description The LM4935 can be placed in one of four modes which dictate its basic operation. When a new mode is selected the LM4935 will change operation silently and will re-configure the power management profile automatically. The modes are described as follows: CHIP MODE Audio System Detection System Typical Application 002 Off Off Power-down Mode 012 Off On Stand-by mode with headset event detection 102 On Off Active without headset event detection 112 On On Active with headset event detection 2 PLL_ENABLE 3 USE_OSC If set the power management and control circuits will assume that no external clock is available and will resort to using an on-chip oscillator for SAR, headset detection and analog power management functions such as click and pop. 5:4 CAP_SIZE Programs the extra delays required to stabilize once charge/discharge is complete, based on the size of the bypass capacitor. 6 STEREO 7 OCL If set the PLL can be used. CAP_SIZE Bypass Capacitor Size 002 0.1 µF Turn-off/on time 45 ms/75 ms 012 1 µF 45 ms/140 ms 102 2.2 µF 45 ms/260 ms 112 4.7 µF 45 ms/500 ms If set, the mixers assume that the signals on the left and right internal busses are highly correlated and when these signals are combined their levels are reduced by 6 dB to allow enough headroom for them to be summed at the Loudspeaker, Earpiece, CPOUT, and AUXOUT amplifiers. For the Headphone amplifier, if this bit is set, the left and right signal levels are routed to the corresponding left or right headphone output; if this bit is cleared, the left and the right signals are added and routed to both headphone outputs and their levels are reduced by 6dB to allow enough headroom. If set the part is placed in OCL (Output Capacitor Less) mode. For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by setting bit 0 of CHIP_MODE: The OCL-bit (Cap / Capless headphone interface; bit 7 of this register) The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h)) The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch)) The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch)) All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered while the audio sub-system is active. If the analog or digital levels are below −12 dB then it is not necessary to set the stereo bit allowing greater output levels to be obtained for such signals. 21 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.2 CLOCKS CONFIGURATION REGISTER This register is used to control the clocks throughout the chip. TABLE 3. CLOCKS (0x01h) Bits Field 0 DAC_CLK 1 ADC_CLK Description Selects the clock to be used by the audio DAC system. DAC_CLK DAC Input Source 0 PLL Input (MCLK or I2S_CLK) 1 PLL Output Selects the clock to be used by the audio ADC system. ADC_CLK 7:2 www.national.com R_DIV Audio ADC Input Source 0 MCLK 1 PLL Output Programs the R divider (divides from an expected 12.000 MHz input). R_DIV Divide Value 0 Bypass 1 Bypass 2 1.5 3 2 4 2.5 5 3 6 3.5 7 4 8 4.5 9 5 10 5.5 11 6 12 6.5 13 to 61 7 to 31 62 31.5 63 32 22 LM4935 12.0 Status & Control Registers (Continued) 12.3 LM4935 CLOCK NETWORK The audio ADC operates at 125*fs, so it requires a 1.000 MHz clock to sample at 8 kHz (at point C as marked on the following diagram). The stereo DAC operates at 250*fs, i.e. 12.000 MHz (at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system unless a 12.000 MHz master clock is supplied and the sample rate is always a multiple of 8 kHz, in which case the PLL can be bypassed to reduce power, clock division instead being performed by the Q and R dividers. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL output divided by 2*FSDAC/FSADC or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback. MCLK must be less than or equal to 30 MHz, the I2S clock should be an integer multiple of the DAC’s sampling frequency and should be below 6 MHz. When using the Class D amplifier with the DAC the Class D clock generator will assume 12 MHz at point A, if this is not the case then the DAC and power stage may become unsynchronized and SNR performance may be reduced. The LM4935 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. This is used to drive the power management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly beyond this range. 20134110 FIGURE 6. LM4935 Clock Network 23 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC The DAC has an over sampling rate of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point B for various clock sample rates in the different DAC modes: TABLE 4. Common DAC Clock Frequencies DAC Sample Rate (kHz) Clock Required at B (MHz) 8 2 11.025 2.75625 12 3 16 4 22.05 5.5125 24 6 32 8 44.1 11.025 48 12 The ADC has an over sampling ratio of 125 so the table below shows the required clock frequency at point C. TABLE 5. Common ADC Clock Frequencies ADC Sample Rate (kHz) Clock Required at C (MHz) 8 1 11.025 1.378125 12 1.5 16 2 22.05 2.75625 24 3 Methods for producing these clock frequencies are described in the PLL Section. www.national.com 24 LM4935 12.0 Status & Control Registers (Continued) 12.5 PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input section of the PLL. TABLE 6. PLL_M (0x02h) Bits Field 0 RSVD 6:1 PLL_M 7 PLL_INPUT Description RESERVED PLL_M Input Divider Value 0 1 1 2 2 3 3 4 4...62 5...63 63 64 Programs the PLL input multiplexer to select between: PLL_INPUT PLL Input Source 0 MCLK 1 I2S_CLK The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. The division of the M divider is derived from PLL_M such that: M = PLL_M + 1 Note 11: See Further Notes on PLL Programming for more detail. 25 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.6 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control the feedback divider of the PLL. TABLE 7. PLL_N (0x03h) Bits Field 7:0 PLL_N Description Programs the PLL feedback divider as follows: PLL_N Feedback Divider Value 0 to 10 10 11 11 12 12 13 13 14 14 … … 249 249 250 to 255 250 The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting VCO frequency, FVCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as Fcomp (comparison frequency) or Fref (reference frequency), in this document Fcomp is used. The integer division of the N divider is derived from PLL_N such that: For 9 < PLL_N < 251: N = PLL_N Note 12: See Further Notes on PLL Programming for further details. www.national.com 26 LM4935 12.0 Status & Control Registers (Continued) 12.7 PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the output divider of the PLL. TABLE 8. PLL_P (0x04h) Bits Field 0 RSVD 3:1 PLL_P 6:4 7 Q_DIV RSVD Description RESERVED PLL_P Output Divider Value 0002 1 0012 2 0102 3 0112 4 1002 5 1012 6 1102 7 1112 8 Programs the Q Divider (divides from an expected 12.000 MHz input). Q_DIV Divide Value 0002 2 0012 3 0102 4 0112 6 1002 8 1012 10 1102 12 1112 13 RESERVED The division of the P divider is derived from PLL_P such that: P = PLL_P + 1 Note 13: See Further Notes on PLL Programming for more details. 27 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.8 PLL N MODULUS CONFIGURATION REGISTER This register is used to control the modulation applied to the feedback divider of the PLL. TABLE 9. PLL_N_MOD (0x05h) Bits Field 4:0 PLL_N_MOD 6:5 DITHER_LEVEL 7 RSVD Description Programs the PLL N divider’s fractional component: PLL_N_MOD Fractional Addition 0 0/32 1 1/32 2 to 30 2/32 to 30/32 31 31/32 Allows control over the dither used by the N divider: DITHER_LEVEL Value 002 Medium 012 Small 102 Large 112 Off RESERVED The complete N divider is a fractional divider as such: N = PLL_N + PLL_N_MOD/32 If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin*N)/(M*P) Note 14: See Further Notes on PLL Programming for more details. www.national.com 28 LM4935 12.0 Status & Control Registers (Continued) 12.9 FURTHER NOTES ON PLL PROGRAMMING The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 30 MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48 kHz and 44.1 kHz sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within 1 Hz of the correct sample rate although this is highly unlikely to be a problem. 20134111 FIGURE 7. PLL Overview TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P Fout (MHz) 11 48 11 60 5 10 60 0 4 12 12.288 48 4 19.53125 5 3 19 17 4 12 13 48 13 60 5 12 60 0 4 12 14.4 48 9 37.5 5 8 37 16 4 12 16.2 48 27 100 5 26 100 0 4 12 16.8 48 14 50 5 13 50 0 4 12 19.2 48 13 40.625 5 12 40 20 4 12 19.44 48 27 100 6 26 100 0 5 12 19.68 48 21 64.03125 5 20 64 1 4 12 19.8 48 17 51.5 5 16 51 16 4 12 11 44.1 11 55.125 5 10 55 4 4 11.025 11.2896 44.1 8 39.0625 5 7 39 2 4 11.025 12 44.1 5 22.96875 5 4 22 31 4 11.025 13 44.1 13 55.125 5 12 55 4 4 11.025 14.4 44.1 12 45.9375 5 11 45 30 4 11.025 16.2 44.1 9 30.625 5 8 9 20 4 11.025 16.8 44.1 17 55.78125 5 16 30 25 4 11.025 19.2 44.1 16 45.9375 5 15 45 30 4 11.025 19.44 44.1 14 39.6875 5 13 39 22 4 11.025 19.68 44.1 21 47.0625 4 20 47 2 3 11.025 19.8 44.1 11 30.625 5 10 30 204 4 11.025 29 www.national.com LM4935 12.0 Status & Control Registers (Continued) These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done by increasing the P divider value or using the R/Q dividers. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams). Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz. So for P = 3 to 5, sweep the M inputs from 1 to 3. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison frequency of 1.5 MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact frequency match cannot be found. The I2S should be master on the LM4935 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than the PLL. The LM4935 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8, 13, 26, 52 kHz modes from a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR. The actual ADC and DAC sample rates are set up by the PLL and internal clock dividers. www.national.com 30 LM4935 12.0 Status & Control Registers (Continued) 12.10 ADC_1 CONFIGURATION REGISTER This register is used to control the LM4935’s audio ADC. TABLE 11. ADC_1 (0x06h) Bits Field 0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal. Description 1 CPI_SELECT If set the cell phone input is added to the ADC input signal. 2 LEFT_SELECT 3 RIGHT_SELECT If set the left stereo bus is added to the ADC input signal. If set the right stereo bus is added to the ADC input signal. 5:4 ADC_SAMPLE_ RATE Programs the closest expected sample rate of the mono ADC, which is a variable required by the AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC. ADC_SAMPLE_RATE 7:6 HPF_MODE Sample Rate 002 8 kHz 012 12 kHz 102 16 kHz 112 24 kHz Sets the HPF of the ADC HPF-MODE HPF Response 002 No HPF 012 FS = 8 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz FS = 12 kHz, −0.5 dB @ 450 Hz, Notch @ 82 Hz FS = 16 kHz, −0.5 dB @ 600 Hz, Notch @ 110 Hz 102 FS = 8 kHz, −0.5 dB @ 150 Hz, Notch @ 27 Hz FS = 12 kHz, −0.5 dB @ 225 Hz, Notch @ 41 Hz FS = 16 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz 112 No HPF 31 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.11 ADC_2 CONFIGURATION REGISTER This register is used to control the LM4935’s audio ADC. TABLE 12. ADC_2 (0x07h) Bits Field 0 ULAW/ALAW Description If COMPAND is set then the data across the PCM interface to the DAC and from the ADC is companded as follows: ULAW/ALAW Commanding Type 0 µ-law 1 A-law 1 COMPAND If set the 16 bit PCM data from the ADC is companded before the PCM interface and the PCM data to the DAC is treated as companded data. 2 ADC_MUTE If set the analog inputs to the ADC are muted. 5:3 AGC_FRAME_TIME 6 ADC_I2S_M 7 AUDIO_IF_2_16BIT This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC’s peak detector determines the peak value of the incoming microphone audio signal and compares this value to the target value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in order to adjust the microphone preamplifiers gain accordingly. AGC_FRAME_TIME basically sets the sample rate of the AGC to adjust for a wide variety of speech patterns. (Note 15) AGC_FRAME_TIME Time (ms) 0002 96 0012 128 0102 192 0112 256 1002 384 1012 512 1102 768 1112 1000 If set the DAC clock system is enabled to drive the I2S in master mode. The Point B frequency should be double that at Point C. This bit should be set when using the I2S interface in master mode to read SAR information whenever both the audio ADC and DAC are inactive. If set the PCM and I2S interfaces are 16 bits per word in master mode. The 2 last clock cycles per word are 25% shorter to allow generation. Note 15: Refer to the AGC overview for further detail. www.national.com 32 LM4935 12.0 Status & Control Registers (Continued) 12.12 AGC_1 CONFIGURATION REGISTER This register is used to control the LM4935’s Automatic Gain Control. (Note 16) TABLE 13. AGC_1 (0x08h) Bits Field 0 AGC_ENABLE If set the AGC controls the analog microphone preamplifier gain into the system. The microphone input must be passed to the ADC. Description 3:1 AGC_TARGET Programs the target level of the AGC. This will depend on the expected transients and desired headroom. Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail. AGC_TARGET Target Level 0002 −6 dB 0012 −8 dB 0102 −10 dB 0112 −12 dB 1002 −14 dB 1012 −16 dB 1102 −18 dB 1112 −20 dB 4 NOISE_GATE_ON If set, signals below the noise gate threshold are muted.The noise gate is only activated after a set period of signal absence. 7:5 NOISE_ GATE_ THRES This field sets the expected background noise level relative to the peak signal level. The sole presence of signals below this level will not result in an AGC gain change of the input and will be gated from the ADC output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is required by the AGC algorithm. NOISE_GATE_THRES Level 0002 −72 dB 0012 −66 dB 0102 −60 dB 0112 −54 dB 1002 −48 dB 1012 −42 dB 1102 −36 dB 1112 −30 dB Note 16: See the AGC overview. 33 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.13 AGC_2 CONFIGURATION REGISTER This register is used to control the LM4935’s Automatic Gain Control. TABLE 14. AGC_2 (0x09h) Bits Field Description 3:0 AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier. 6:4 7 AGC_DECAY AGC_TIGHT AGC_TIGHT = 0 AGC_TIGHT = 1 AGC_MAX_GAIN Max Preamplifier Gain 00002 6 dB 00012 8 dB 00102 10 dB 00112 12 dB 01002 to 11002 14 dB to 30 dB 11012 32 dB 11102 34 dB 11112 36 dB Programs the speed at which the AGC will increase gains if it detects the input level is a quiet signal. AGC_DECAY Step Time (ms) 0002 32 0012 64 0102 128 0112 256 1002 512 1012 1024 1102 2048 1112 4096 If set the AGC algorithm controls the microphone preamplifier more exactly. (Note 17) AGC_TARGET Min Level Max Level 0002 −6 dB −3 dB 0012 −8 dB −4 dB 0102 −10 dB −5 dB 0112 −12 dB −6 dB 1002 −14 dB −7 dB 1012 −16 dB −8 dB 1102 −18 dB −9 dB 1112 −20 dB −10 dB 0002 −6 dB −3 dB 0012 −8 dB −5 dB 0102 −10 dB −7 dB 0112 −12 dB −9 dB 1002 −14 dB −11 dB 1012 −16 dB −13 dB 1102 −18 dB −15 dB 1112 −20 dB −17 dB Note 17: The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for recording on the ADC. When the analog path is used this bit should be set to ensure the target is tightly adhered to. If the ADC is the only destination of the microphone or the desired analog mixer level is line level then AGC_TIGHT should be cleared, allowing greater dynamic rage of the recorded signal. For further details see the AGC overview. www.national.com 34 LM4935 12.0 Status & Control Registers (Continued) 12.14 AGC_3 CONFIGURATION REGISTER This register is used to control the LM4935’s Automatic Gain Control. (Note 18) TABLE 15. AGC_3 (0x0Ah) Bits Field 4:0 AGC_HOLDTIME 7:5 AGC_ATTACK Description Programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone preamplifier. AGC_HOLDTIME No. of speech segments 000002 0 000012 1 000102 2 000112 3 001002 to 111002 4 to 28 111012 29 111102 30 111112 31 Programs the speed at which the AGC will reduce gains if it detects the input level is too large. AGC_ATTACK Step Time (ms) 0002 32 0012 64 0102 128 0112 256 1002 512 1012 1024 1102 2048 1112 4096 Note 18: See the AGC overview. 35 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.15 AGC OVERVIEW The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level of the source is unknown. A target level for the output is set so that any transients on the input won’t clip during normal operation. The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone preamplifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range of the ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone level. In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients closely to the target level. To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone preamplifier gain, the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is consistently below target, the gain will be increased at a programmable rate (AGC_DECAY). If the signal ever exceeds the target level (AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demonstrated below: 20134112 AGC Operation Example The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the gain ((1) → (2)). After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases the gain at a faster rate ((2) → (3)) to allow the elimination of typical popping noises. Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm. The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC, the ADC’s HPF should always be enabled. www.national.com 36 LM4935 12.0 Status & Control Registers (Continued) 12.16 MIC_1 CONFIGURATION REGISTER This register is used to control the microphone configuration. TABLE 16. MIC_1 (0x0Bh) Bits Field 3:0 PREAMP_GAIN 4 MIC_MUTE 5 INT_SE_DIFF 6 INT_EXT Description Programs the gain applied to the microphone preamplifier if the AGC is not in use. PREAMP_GAIN Gain 00002 6 dB 00012 8 dB 00102 10 dB 00112 12 dB 01002 to 11002 14 dB to 30 dB 11012 32 dB 11102 34 dB 11112 36 dB If set the microphone preamplifier is muted. If set the internal microphone is assumed to be single ended and the negative connection is connected to the ADC common mode point internally. This allows a single-ended internal microphone to be used. If set the single ended external microphone is used and the negative microphone input is grounded internally, otherwise internal microphone operation is assumed. (Note 19) Note 19: On changing INT_EXT from internal to external note that the dc blocking cap will not be charged so some time should be taken (300 ms for a 1 µF cap) between the detection of an external headset and the switching of the output stages and ADC to that input to allow the DC points on either side of this cap to stabilize. This can be accomplished by deselecting the microphone input from the audio outputs and ADC until the DC points stabilize. An active MIC path to CPOUT or the ADC may result in the microphone DC blocking caps causing audio pops under the following situations: 1) Switching between internal and external microphone operation while in chip modes ’10’ or ’11’. 2) Toggling in and out of powerdown/standby modes. 3) Toggling between chip modes ’10’ and ’11’ whenever external microphone operation is selected. 4) The insertion/removal of a headset while in chip modes ’10’ or ’11’ whenever external microphone operation is selected. To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC until the DC points stabilize. 37 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.17 MIC_2 CONFIGURATION REGISTER This register is used to control the microphone configuration. TABLE 17. MIC_2 (0x0Ch) Bits Field 0 OCL_ VCM_ VOLTAGE 2:1 MIC_ BIAS_ VOLTAGE 3 BUTTON_TYPE 5:4 BUTTON_ DEBOUNCE_ TIME Description Selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the available supply and the power output requirements of the headphone amplifiers. OCL_VCM_VOLTAGE Voltage 0 1.2V 1 1.5V Selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE should be set to ’11’ only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = ’00’ (EXT_BIAS = 2.0V) should not be used to generate the EXT_BIAS supply for a cellular headset external microphone. Please refer to Table 18 for more detail. MIC_BIAS_VOLTAGE EXT_BIAS INT_BIAS 002 2.0V 2.0V 012 2.5V 2.5V 102 2.8V 2.8V 112 3.3V 3.3V If set the LM4935 assumes that the button (if used) in the headset is in series (series push button) with the microphone, opening the circuit when pressed. The default is for the button to be in parallel (parallel push button), shorting out the microphone when pressed. Sets the time used for debouncing the pushing of the button on a headset with a parallel push button. BUTTON_DEBOUNCE_TIME Time (ms) 002 0 012 8 102 16 112 32 In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS - OCL_VCM_ VOLTAGE) and the maximum output power possible from the headphones. A lower OCL_VCM_VOLTAGE gives a higher microphone supply voltage but a lower maximum output power from the headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_VSS. TABLE 18. External MIC Supply Voltages in OCL Mode Available A_VDD Recommended EXT_MIC_BIAS OCL_VCM_VOLT = 1.5V OCL_VCM_VOLT = 1.2V > 3.4V 3.3V 1.8V 2.1V 2.9V to 3.4V 2.8V 1.3V 1.6V 2.8V to 2.9V 2.5V 1.0V 1.3V 2.7V to 2.8V 2.5V - 1.3V www.national.com Supply to Microphone 38 LM4935 12.0 Status & Control Registers (Continued) 12.18 SIDETONE ATTENUATION REGISTER This register is used to control the analog sidetone attenuation. (Note 20) TABLE 19. SIDETONE (0x0Dh) Bits Field 3:0 SIDETONE_ ATTEN Description Programs the attenuation applied to the microphone preamp output to produce a sidetone signal. SIDETONE_ATTEN Attenuation 00002 -Inf 00012 −30 dB 00102 −27 dB 00112 −24 dB 01002 −21 dB 01012 to 10102 −18 dB to −3 dB 10112 to 11112 0 dB Note 20: An active SIDETONE path to an audio output may result in the microphone DC blocking caps causing audio pops under the following situations: 1) Switching between internal and external microphone operation while in chip modes ’10’ or ’11’. 2) Toggling in and out of powerdown/standby modes. 3) Toggling between chip modes ’10’ and ’11’ whenever external microphone operation is selected. 4) The insertion/removal of a headset while in chip modes ’10’ or ’11’ whenever external microphone operation is selected. To avoid potential pop noises, it is recommended to set SIDETONE_ATTEN to ’0000’ until DC points have stabilized whenever the SIDETONE path is used. 39 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.19 CP_INPUT CONFIGURATION REGISTER This register is used to control the differential cell phone input. TABLE 20. CP_INPUT (0x0Eh) Bits Field 4:0 CPI_LEVEL 5 CPI_MUTE www.national.com Description Programs the gain/attenuation applied to the cell phone input. CPI_LEVEL Level 000002 −34.5 dB 000012 −33 dB 000102 −31.5 dB 000112 −30 dB 00100 to 111002 −28.5 dB to +7.5 dB 111012 +9 dB 111102 +10.5 dB 111112 +12 dB If set the CPI input is muted at source. 40 LM4935 12.0 Status & Control Registers (Continued) 12.20 AUX_LEFT CONFIGURATION REGISTER This register is used to control the left aux analog input. TABLE 21. AUX_LEFT (0x0Fh) Bits Field 4:0 AUX_ LEFT_ LEVEL 5 AUX_ LEFT_ BOOST 6 AUX_L_MUTE 7 AUX_OR_DAC_L Description Programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (Note 21) AUX_LEFT_LEVEL Level (With Boost) Level (Without Boost) −46.5 dB 000002 −34.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.5 dB 111012 +9 dB −3 dB 111102 +10.5 dB −1.5 dB 111112 +12 dB 0 dB If set the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above). If set the AUX LEFT input is muted. If set the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be passed to the mixer. Note 21: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. 41 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.21 AUX_RIGHT CONFIGURATION REGISTER This register is used to control the right aux analog input. TABLE 22. AUX_RIGHT (0x10h) Bits Field 4:0 AUX_ RIGHT_ LEVEL 5 AUX_ RIGHT_BOOST 6 AUX_R_MUTE 7 AUX_OR_DAC_R Description Programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (Note 22) AUX_RIGHT_LEVEL Level (With Boost) Level (Without Boost) −46.5 dB 000002 −34.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.5 dB 111012 +9 dB −3 dB 111102 +10.5 dB −1.5 dB 111112 +12 dB 0 dB If set the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above). If set the AUX RIGHT input is muted. If set the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be passed to the mixer. Note 22: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. www.national.com 42 LM4935 12.0 Status & Control Registers (Continued) 12.22 DAC CONFIGURATION REGISTER This register is used to control the DAC levels to the mixer. TABLE 23. DAC (0x11h) Bits Field 4:0 DAC_LEVEL 5 USE_AUX_ LEVELS 6 BOOST 7 DAC_MUTE Description Programs the gain/attenuation applied to the DAC input to the mixer. (Note 23) DAC_LEVEL Level (With Boost) Level (Without Boost) −46.5 dB 000002 −34.5 dB 000012 −33 dB −45 dB 000102 −31.5 dB −43.5 dB 000112 −30 dB −42 dB 00100 to 111002 −28.5 dB to +7.5 dB −40.5 dB to −4.5 dB 111012 +9 dB −3 dB 111102 +10.5 dB −1.5 dB 111112 +12 dB 0 dB If set the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing a stereo balance to be applied. If set the gain of the DAC inputs to the mixer is increased by 12 dB (see above). If set the stereo DAC input is muted on the next zero crossing. Note 23: The output from the DAC is 1V RMS for a full scale digital input. This can be boosted by 12 dB if enough headroom is available. Clipping may occur if the analog power supply is insufficient to cater for the required gain. 43 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.23 CP_OUTPUT CONFIGURATION REGISTER This register is used to control the differential cell phone output. (Note 24) TABLE 24. CP_OUTPUT (0x12h) Bits Field 0 MIC_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 CPO_MUTE 4 MIC_NOISE_GATE Description If set the microphone channel of the mixer is added to the cellphone output signal. If set the right channel of the mixer is added to the cellphone output signal. If set the left channel of the mixer is added to the cellphone output signal. If set the CPOUT output is muted. If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be gated if the signal is determined to be noise by the AGC (that is, if the signal is below the set noise threshold). Note 24: The gain of cell phone output amplifier is 0 dB. www.national.com 44 LM4935 12.0 Status & Control Registers (Continued) 12.24 AUX_OUTPUT CONFIGURATION REGISTER This register is used to control the differential auxiliary output. (Note 25) TABLE 25. AUX_OUTPUT (0x13h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 AUX_MUTE Description If set the cell phone input channel of the mixer is added to the aux output signal. If set the right channel of the mixer is added to the aux output signal. If set the left channel of the mixer is added to the aux output signal. If set the aux output is muted. Note 25: The gain of the auxiliary output amplifier is 0 dB. If a second (external) loudspeaker amplifier is to be used its gain should be set to 12 dB to match the onboard loudspeaker amplifier gain. 45 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.25 LS_OUTPUT CONFIGURATION REGISTER This register is used to control the loudspeaker output. (Note 26) TABLE 26. LS_OUTPUT (0x14h) Bits Field 0 CPI_SELECT 1 RIGHT_SELECT 2 LEFT_SELECT 3 LS_MUTE Description If set the cell phone input channel of the mixer is added to the loudspeaker output signal. If set the right channel of the mixer is added to the loudspeaker output signal. If set the left channel of the mixer is added to the loudspeaker output signal. If set the loudspeaker output is muted. Note 26: The gain of the loudspeaker output amplifier is 12 dB. www.national.com 46 LM4935 12.0 Status & Control Registers (Continued) 12.26 HP_OUTPUT CONFIGURATION REGISTER This register is used to control the stereo headphone output. (Note 27) TABLE 27. HP_OUTPUT (0x15h) Bits Field 0 SIDETONE_SELECT If set the sidetone channel of the mixer is added to both of the headphone output signals. Description 1 CPI_SELECT If set the cell phone input channel of the mixer is added to both of the headphone output signals. 2 RIGHT_SELECT If set the right channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the right channel is added to the right headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. 3 LEFT_SELECT 4 HP_MUTE If set the left channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set, the left channel is added to the left headphone output signal only. If the STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output signals. If set the headphone output is muted. Note 27: The gain of the headphone output amplifier is –6 dB for the cell phone input channel and sidetone channel of the mixer. When the STEREO bit (0x00h) is set, headphone output amplifier gain is –6 dB for the left and right channel. When the STEREO bit (0x00h) is cleared, the headphone output amplifier gain is –12 dB for the left and right channel (to allow enough headroom for adding them and routing them to both headphone amplifiers). 47 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.27 EP_OUTPUT CONFIGURATION REGISTER This register is used to control the mono earpiece output. (Note 28) TABLE 28. EP_OUTPUT (0x16h) Bits Field 0 SIDETONE_SELECT 1 CPI_SELECT 2 RIGHT_SELECT 3 LEFT_SELECT 4 EP_MUTE Description If set the sidetone channel of the mixer is added to the earpiece output signal. If set the cell phone input channel of the mixer is added to the earpiece output signal. If set the right channel of the mixer is added to the earpiece output signal. If set the left channel of the mixer is added to the earpiece output signal. If set the earpiece output is muted. Note 28: The gain of the earpiece output amplifier is 6 dB. www.national.com 48 LM4935 12.0 Status & Control Registers (Continued) 12.28 DETECT CONFIGURATION REGISTER This register is used to control the headset detection system. TABLE 29. DETECT (0x17h) Bits Field 0 DET_INT If set an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ that has been triggered by the headset detect. Description 1 BTN_INT If set an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that has been triggered by a button event. 2 TEMP_INT If set an IRQ is raised during a temperature event. If cleared, the LM4935 will still automatically cycle the power amplifiers off if the internal temperature is too high. This bit should not be set whenever the loudspeaker amplifier is turned on. Clearing this bit will clear an IRQ that has been triggered by a temperature event. 6:3 HS_ DBNC_TIME Sets the time used for debouncing the analog signals from the detection inputs used to sense the insertion/removal of a headset. HS_DBNC_TIME Time (ms) 00002 0 00012 8 00102 16 00112 32 01002 48 01012 64 01102 96 01112 128 10002 192 10012 256 10102 384 10112 512 11002 768 11012 1024 11102 1536 11112 2048 49 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.29 HEADSET DETECT OVERVIEW The LM4935 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM4935 updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no analog supply current when the headset is absent. The LM4935 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will be disconnected from the MIC_BIAS amplifier, irrespective of control register settings. The LM4935 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series button-type (in series with the headset microphone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected in stand-by mode; this consumes 10 µA of analog supply current for a series type push button and 100 µA for a parallel type push button. Upon button press, the LM4935 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected (INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN (bit 3 of STATUS (0x18h)) can be read. The LM4935 can also be programmed to raise an interrupt on the IRQ pin when button press is sensed by setting bit 1 of DETECT. The LM4935 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button. Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch). Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the debounce time for series button press in defined by HS_DBNC_TIME. Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push button detection all following bits should be defined before enabling the headset detection system: 1) the OCL-bit (AC-Coupled / Capless headphone interface (bit 7 of BASIC (0x00h)) 2) the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h)) 3) the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch)) 4) the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch)) Figure 8 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from the MIC_DET pin to ground when a headset is not inserted. www.national.com 50 LM4935 12.0 Status & Control Registers (Continued) 20134113 FIGURE 8. Headset Configurations Supported by the LM4935 The wiring of the headset jack to the LM4935 will depend on the intended mode of the headphone amplifier: 51 www.national.com LM4935 12.0 Status & Control Registers (Continued) 20134114 FIGURE 9. Connection of Headset Jack to LM4935 Depends on the Mode of the Headphone Amplifier. www.national.com 52 LM4935 12.0 Status & Control Registers (Continued) 12.30 STATUS REGISTER This register is used to report the status of the device. TABLE 30. STATUS (0x18h) Bits Field 0 HEADSET This field is high when headset presence is detected (only valid if the detection system is enabled). (Note 29) Description 1 STEREO_ HEADSET This field is high when a headset with stereo speakers is detected (only valid if the detection system is enabled). (Note 29) 2 MIC This field is high when a headset with a microphone is detected (only valid if the detection system is enabled). (Note 29) 3 BTN This field is high when the button on the headset is pressed (only valid if the detection system is enabled). IRQ is cleared when the button has been released and this register has been written to. 4 SAR TRIG 1 If this field is high then an event has happened on SAR trigger 1 (write to this register to clear IRQ). 5 SAR TRIG 2 If this field is high then an event has happened on SAR trigger 2 (write to this register to clear IRQ). 6 TEMP If this field is high then a temperature event has occurred (write to this register to clear IRQ). This field will stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid whenever the loudspeaker amplifier is turned off. 7 GPIN When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back here. Note 29: The detection IRQ is cleared when this register has been written to. 53 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.31 AUDIO INTERFACE CONFIGURATION REGISTER This register is used to control the configuration of the audio data interfaces. TABLE 31. AUDIO_IF (0x19h) Bits Field 1:0 AUDIO_IF_MODE Description Selects the function of the 6 audio interface IOs. AUDIO_IF_MODE I2S_ CLK pin I2S_ WS pin I2S_ SDI pin I2S_ SDO pin GPIO_1 pin GPIO_2 pin 002 I 2S CLK I2S WS I 2S SDI I2S SDO GPIO 1 GPIO 2 012 PCM CLK PCM SYNC - PCM SDO GPIO 1 GPIO 2 102 PCM CLK PCM SYNC PCM SDI PCM SDO GPIO 1 GPIO 2 112 I 2S CLK I2S WS I 2S SDI PCM SDO PCM CLK PCM SYNC 2 I2S_WS_MS If set the I2S_WS is produced by the LM4935 and the I2S_WS pin will be an output. 3 I2S_CLK_MS If set the I2S_CLK is produced by the LM4935 and the I2S_CLK pin will be an output. 4 PCM_SYNC_MS If set the PCM_SYNC is produced by the LM4935 and the relevant pin will be an output. 5 PCM_CLK_MS If set the PCM_CLK is produced by the LM4935 and the relevant pin will be an output. 7:6 I2S_SDO_DATA The two ADCs on the LM4935 can both be read via the isochronous I2S interface. The most recent valid sample is output from the following source: (Please refer to the GPIO configuration register (0x1Ah) for more information on SAR_CH_SEL) www.national.com I2S_SDO_DATA LEFT RIGHT 002 AUDIO ADC SAR_CH_SEL 012 SAR VSAR 1 SAR_CH_SEL 102 SAR VSAR 2 SAR_CH_SEL 112 A_VDD/2 SAR_CH_SEL 54 LM4935 12.0 Status & Control Registers (Continued) 12.32 DIGITAL AUDIO DATA FORMATS I2S master mode can only be used when the DAC is enabled unless the ADC_I2S_M bit is set. PCM Master mode can only be used when the ADC is enabled. If the PCM receiver interface is operated in slave mode the clock and sync should be enabled at the same time as the PCM receiver uses the first PCM frame to calculate the PCM interface format. This format can not be changed unless a soft reset is issued. It is strongly recommended that the LM4935 is operated in master mode as this eliminates the risk of sample rate mismatch between the data converters and the audio interfaces. In master mode the I2S_CLK has a 60/40 duty cycle and a frequency of 50*fs. In slave mode the PCM and I2S receivers only record the 1st 16 and 18 bits of the serial words respectively. The I2S format is as follows: 20134115 FIGURE 10. I2S Serial Data Format (Default Mode) 20134116 FIGURE 11. PCM Serial Data Format (16 bit Slave Example) When SAR SDO data is passed to the I2S, it is left aligned (MSB aligned) to allow lower I2S resolutions to be used. If the DAC is driven from the PCM interface then the left channel of the DAC is used and the right channel is inactive. 55 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.33 GPIO CONFIGURATION REGISTER This register is used to control the GPIO system. TABLE 32. GPIO (0x1Ah) Bits Field 2:0 GPIO_SEL Description This sets the function of the GPIOs when the Audio Interface is not using them. GPIO_SEL GPIO 1 GPIO 2 0002 0 0 0012 READABLE SPI_SDO 0102 LS_AMP_ENABLE SPI_SDO 0112 GPIO_DATA SPI_SDO 1002 0 SPI_SDO 1012 READABLE SAR_SDO 1102 LS_AMP_ENABLE SAR_SDO 1112 GPIO_DATA SAR_SDO Setting GPIO_SEL = “010” with the GPIO_TEST_MODE bit (register 0X26h) set configures the GPIOs for digital mic operation. With this setting, GPI01 will output VADC_CLK_OUT to provide a clock for the digital mic. GPIO2 will accept digital mic data. GPIO1’s LS_AMP_ENABLE setting will be logic high whenever the loudspeaker amplifier is enabled. This is useful for enabling an external amplifier for stereo loudspeaker applications. 4:3 SAR_CH_SEL This field selects the SAR output channel for the 2nd (Right) I2S channel or for SAR_SDO via GPIO2. SAR_CH_SEL Selected Channel 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 5 I2S_MODE If set the I2S operates in left justified mode (sometimes referred to as DSP mode). See example below. (Note 30) 6 PCM_LONG If set the PCM interface uses LONG frame sync which is essentially an inverted short frame sync. 7 GPIO_DATA If GPIO_SEL is set to GPIO_DATA then the content of this field is passed to GPIO1 as an output. Note 30: The left justified I2S mode is similar to normal I2S other than there is no delay between a change in WS to the MSB: 20134117 FIGURE 12. I2S Serial Data Format (Left Justified Mode) www.national.com 56 LM4935 12.0 Status & Control Registers (Continued) 12.34 SAR CHANNELS 0 & 1 CONFIGURATION REGISTER This register is used to control channel 0 and 1 of the SAR system. (Note 31) TABLE 33. SAR_SLOT01 (0x1Bh) Bits Field 2:0 SLOT_0_FS 3 SLOT_0_ENB 6:4 SLOT_1_FS 7 SLOT_1_ENB Description Programs the sampling frequency of SAR channel 0: SLOT_0_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz If set then VSAR 1 is sampled into SAR slot 0 which also activates the SAR ADC. Programs the sampling frequency of SAR channel 1: SLOT_1_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz If set then VSAR 2 is sampled into SAR slot 1 which also activates the SAR ADC. Note 31: See the section SAR Overview for more details on this register. 57 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.35 SAR CHANNELS 2 & 3 CONFIGURATION REGISTER This register is used to control channel 2 and 3 of the SAR system. (Note 31) TABLE 34. SAR_SLOT23 (0x1Ch) Bits Field 2:0 SLOT_2_FS Description Programs the sampling frequency of SAR channels 2 and 3: SLOT_2_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz 3 SLOT_2_ENB If set then D_VDD / 2 or BB_VDD (depending on SLOT2_VBB) is sampled into SAR slot 2 which also activates the SAR ADC. 4 SLOT_3_ENB If set then A_VDD / 2 is sampled into SAR slot 3 which also activates the SAR ADC. 5 SLOT_2_VBB If set then BB_VDD input is used as input to SAR slot 2 rather than the D_VDD. www.national.com 58 LM4935 12.0 Status & Control Registers (Continued) 12.36 SAR DATA 0 TO 3 REGISTERS These registers are used to read the 8 MSBs from the 4 SAR channels. TABLE 35. SAR_DATA_0 Register (0x1Dh) Bits Field 7:0 SLOT_0_DATA Description Latest slot 0 sample bits 11:4. TABLE 36. SAR_DATA_1 Register (0x1Eh) Bits Field 7:0 SLOT_1_DATA Description Latest slot 1 sample bits 11:4. TABLE 37. SAR_DATA_2 Register (0x1Fh) Bits Field 7:0 SLOT_2_DATA Description Latest slot 2 sample bits 11:4. TABLE 38. SAR_DATA_3 Register (0x20h) Bits Field 7:0 SLOT_3_DATA Description Latest slot 3 sample bits 11:4. 59 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.37 SAR OVERVIEW The SAR controller works via a scheduler that allocates time slots for each of the four channels. All four channels can operate up to the same maximum frequency. When the sampling frequency of a channel is to be reduced the time slot allocated to that channel is simply enabled less often. For example if one slot is to work at a quarter of the frequency of the others then only one in four of its allocated slot triggers the SAR to activate: 20134118 FIGURE 13. Internal SAR Control Signals to SAR Module Each time slot is used to sample a single fixed input, slot 0 is used for VSAR 1, slot 1 for VSAR 2, slot 2 for either D_VDD or BB_VDD* and slot 3 for the A_VDD. When a particular time slot is activated the correct mux, clock and enable controls to the ADC module are produced and the output sampled when ready. If the D_VDD or the A_VDD are being sampled then a voltage divider is used to half the input to below the full scale reference of 2.5V. As this results in a current path to ground it is only inserted while the ADC is settling to reduce power consumption. Using this method, samples can be taken using as little power as possible while allowing sample rates as low as 1 Hz. The data can either be read directly or used to trigger interrupts when set voltages are passed. This reduces the baseband controllers software overhead and IO bandwidth, further reducing system power. The full scale digital output from the SAR is equal to 2.5V. The A_VDD and D_VDD inputs are divided by two during sampling. The SAR ADC can be activated at any time, even while the chip is in shutdown mode (chip mode ’00’). This allows the LM4935 to perform housekeeping duties such as voltage monitoring with minimal power consumption. *Depending on SLOT_2_VBB in SAR_SLOT23 (0x1Ch). www.national.com 60 LM4935 12.0 Status & Control Registers (Continued) Only the 8 MSBS [11:4] from the 12 bits of SAR output data can be read back using the I2C interface. The SPI interface can be used to access all 12 bits of the SAR output data. In this case, GPIO2 should be set to SAR_SDO by setting GPIO_SEL in register (0x1Ah). The SAR channel selected by SAR_CH_SEL in the GPIO register is then output onto GPIO2 as follows: 20134108 FIGURE 14. SPI SAR Read Transaction (GPIO2 set to SAR_SDO) In applications where the 8 MSBS [11:4] from the SAR output data is enough resolution, GPIO2 should be set to SPI_SDO by setting GPIO_SEL in register (0x1Ah). The SAR data is then output on GPIO2 as follows: 20134107 FIGURE 15. SPI SAR Read Transaction (GPIO2 set to SPI_SDO) If the user performs a write to the GPIO register the changes will not take effect until the next SPI operation so SAR data can be read while the next channel is being selected. The SAR data is sampled at the start of the SPI transaction to ensure that the data is stable during the read operation. All 12 bits of the SAR output data for up to 2 SAR channels can be read back simultaneously through the bi-directional I2S interface. This is accomplished by setting I2S_SDO_DATA (bit [7:6] of (0x19h)) to the desired SAR channel(s). As mentioned previously in the Digital Audio Data Formats section, when SAR SDO is passed to the I2S bus, the SAR SDO’s MSB is aligned with the MSB of I2S_SDO. 61 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.38 DC VOLUME CONFIGURATION REGISTER This register is used to control the DC volume control system. TABLE 39. DC_VOLUME (0x21h) Bits Field 0 DC_VOL_ENB 1 DC_VOL_EFFECT 3:2 Description MAX_LEVEL Enables the DC volume control system to use the voltage applied on the VSAR 1 pin to set the gain of the DC volume control. (Note 32) Selects which volume is altered: DC_VOL_EFFECT Source 0 AUX/DAC 1 CPI Programs the maximum level that can be applied by the system MAX_LEVEL LEVEL 002 0 dB 012 −3 dB 102 −6 dB 112 −12 dB Note 32: The correlation between the voltage on VSAR1 to the attenuation on the AUX/DAC channel is as follows: 201341P4 FIGURE 16. DC Volume Transfer Function For AUX/DAC www.national.com 62 LM4935 12.0 Status & Control Registers (Continued) 12.39 SAR TRIGGER 1 CONFIGURATION REGISTER This register is used to setup a voltage trigger on one of the SAR outputs. TABLE 40. TRIG_1 (0x22h) Bits Field 0 TRIG_1_ENB Enables the 1st SAR trigger interrupt, if cleared will clear the IRQ. 1 TRIG_1_DIR Selects the direction the voltage should be moving: 3:2 7:4 TRIG_1_SOURCE TRIG_1_LSB Description TRIG_1_DIR Trigger if signal passes: 0 Above Threshold 1 Below Threshold Programs the channel used by the trigger. TRIG_1_SOURCE Source 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 Sets bits 3:0 of the threshold used by the trigger. 63 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.40 SAR TRIGGER 1 MSBs CONFIGURATION REGISTER This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. TABLE 41. TRIG_1_MSB (0x23h) Bits Field 7:0 TRIG_1_MSB www.national.com Description Sets bits 11:4 of the threshold used by the trigger. 64 LM4935 12.0 Status & Control Registers (Continued) 12.41 SAR TRIGGER 2 CONFIGURATION REGISTER This register is used to setup a voltage trigger on one of the SAR outputs. TABLE 42. TRIG_2 (0x24h) Bits Field 0 TRIG_2_ENB Enables the 2nd SAR trigger interrupt, if cleared will clear the IRQ. 1 TRIG_2_DIR Selects the direction the voltage should be moving: 3:2 7:4 TRIG_2_SOURCE TRIG_2_LSB Description TRIG_2_DIR Trigger if signal passes: 0 Above Threshold 1 Below Threshold Programs the channel used by the trigger TRIG_2_SOURCE Source 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 Sets bits 3:0 of the threshold used by the trigger. 65 www.national.com LM4935 12.0 Status & Control Registers (Continued) 12.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. TABLE 43. TRIG_2_MSB (0x25h) Bits Field 7:0 TRIG_2_MSB www.national.com Description Sets bits 11:4 of the threshold used by the trigger. 66 LM4935 12.0 Status & Control Registers (Continued) 12.43 DEBUG REGISTER This register is used to set test modes within the device. TABLE 44. DEBUG (0x26h) Bits Field 0 RSVD Reserved Description 1 RSVD Reserved 2 RSVD 3 SOFT_RESET 4 RSVD Reserved 5 RSVD Reserved 6 RSVD 7 GPIO_TEST_MODE Reserved This field can be used to reset the chip without a power cycle. Reserved If set and GPIO_SEL = ’010’, then the GPIOs are configured to interface with the LMV1026 digital microphone as long as AUDIO_IF_MODE (0x19h) is not set to ’11’. GPIO_SEL GPIO 1 GPIO 2 RSVD 0002 RSVD 0012 RSVD RSVD 0102 VADC_CLOCK_OUT DIG_MIC_IN 0112 RSVD RSVD 1002 RSVD RSVD 1012 RSVD RSVD 1102 RSVD RSVD 1112 RSVD RSVD 67 www.national.com LM4935 13.0 Typical Performance Characteristics (For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified. Stereo DAC Frequency Response Zoom fS = 8kHz Stereo DAC Frequency Response fS = 8kHz 20134136 20134137 Stereo DAC Frequency Response Zoom fS = 16kHz Stereo DAC Frequency Response fS = 16kHz 20134138 20134139 Stereo DAC Frequency Response Zoom fS = 24kHz Stereo DAC Frequency Response fS = 24kHz 20134140 www.national.com 20134141 68 Stereo DAC Frequency Response fS = 32kHz (Continued) Stereo DAC Frequency Response Zoom fS = 32kHz 20134142 20134143 Stereo DAC Frequency Response Zoom fS = 48kHz Stereo DAC Frequency Response fS = 48kHz 20134145 20134144 THD+N vs Stereo DAC Input Voltage (0dB DAC, AUXOUT) Stereo DAC Crosstalk (0dB DAC, HP SE) 20134147 20134146 69 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics MONO ADC Frequency Response fS = 8kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 8kHz, 6dB MIC 20134148 20134149 MONO ADC Frequency Response Zoom fS = 8kHz, 36dB MIC MONO ADC Frequency Response fS = 8kHz, 36dB MIC 20134150 20134151 MONO ADC Frequency Response Zoom fS = 16kHz, 6dB MIC MONO ADC Frequency Response fS = 16kHz, 6dB MIC 20134152 www.national.com (Continued) 20134153 70 MONO ADC Frequency Response fS = 16kHz, 36dB MIC (Continued) MONO ADC Frequency Response Zoom fS = 16kHz, 36dB MIC 20134154 20134155 MONO ADC Frequency Response Zoom fS = 24kHz, 6dB MIC MONO ADC Frequency Response fS = 24kHz, 6dB MIC 20134156 20134157 MONO ADC Frequency Response Zoom fS = 24kHz, 36dB MIC MONO ADC Frequency Response fS = 24kHz, 36dB MIC 20134158 20134169 71 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics MONO ADC Frequency Response fS = 32kHz, 6dB MIC MONO ADC Frequency Response Zoom fS = 32kHz, 6dB MIC 20134159 20134160 MONO ADC Frequency Response Zoom fS = 32kHz, 36dB MIC MONO ADC Frequency Response fS = 32kHz, 36dB MIC 20134161 20134162 MONO ADC HPF Frequency Response fS = 16kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) MONO ADC HPF Frequency Response fS = 8kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) 20134163 www.national.com (Continued) 20134164 72 MONO ADC HPF Frequency Response fS = 24kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) (Continued) MONO ADC HPF Frequency Response fS = 32kHz, 36dB MIC (from left to right: HPF_MODE ’00’, ’10’, ’01’) 20134165 20134166 MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 36dB MIC) MONO ADC THD+N vs MIC Input Voltage (fS = 8kHz, 6dB MIC) 20134168 20134167 MONO ADC PSRR vs Frequency AVDD = 5V, 6dB MIC MONO ADC PSRR vs Frequency AVDD = 3.3V, 6dB MIC 20134170 20134171 73 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics MONO ADC PSRR vs Frequency AVDD = 3.3V, 36dB MIC (Continued) MONO ADC PSRR vs Frequency AVDD = 5V, 36dB MIC 20134172 20134173 AUXOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) 20134174 20134175 AUXOUT PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI inputs terminated) AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI inputs terminated) 20134176 www.national.com 20134177 74 AUXOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) LM4935 13.0 Typical Performance Characteristics (Continued) AUXOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) 20134178 20134179 CPOUT PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) 20134180 20134181 CPOUT PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC inputs selected) CPOUT PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC inputs selected) 20134182 20134183 75 www.national.com LM4935 13.0 Typical Performance Characteristics CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC (EXTMIC inputs terminated, AGC on) (Continued) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC (EXTMIC inputs terminated, AGC on) 20134185 20134187 CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC on) 20134188 20134189 CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC on) 20134190 20134191 www.national.com 76 (Continued) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC on) 20134192 20134193 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.0V (INTMIC DIFF inputs terminated, AGC on) 20134196 20134197 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.5V (INTMIC DIFF inputs terminated, AGC on) 20134198 20134199 77 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics (Continued) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 2.8V (INTMIC DIFF inputs terminated, AGC on) 201341A0 201341A1 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 3.3V (INTMIC DIFF inputs terminated, AGC off) CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC, MICBIAS = 3.3V (INTMIC DIFF inputs terminated, AGC on) 201341A2 201341A3 CPOUT PSRR vs Frequency AVDD = 5V, 36dB MIC (INTMIC SE input terminated, AGC on) CPOUT PSRR vs Frequency AVDD = 3.3V, 36dB MIC (INTMIC SE input terminated, AGC on) 201341A5 www.national.com 201341A7 78 Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) LM4935 13.0 Typical Performance Characteristics (Continued) Earpiece PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 201341A8 201341A9 Earpiece PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) 201341B0 201341B1 Earpiece PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) Earpiece PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) 201341B2 201341B3 79 www.national.com LM4935 13.0 Typical Performance Characteristics Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.2V (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.2V (AUX inputs terminated) 201341B4 201341B5 Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.2V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.2V (CPI input terminated) 201341B6 201341B7 Headphone PSRR vs Frequency AVDD = 5V, 0dB ADC, OCL 1.2V (DAC input selected) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB ADC, OCL 1.2V (DAC input selected) 201341B8 www.national.com (Continued) 201341B9 80 Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, OCL 1.5V (AUX inputs terminated) LM4935 13.0 Typical Performance Characteristics (Continued) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, OCL 1.5V (AUX inputs terminated) 201341C0 201341C1 Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, OCL 1.5V (CPI input terminated) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, OCL 1.5V (CPI input terminated) 201341C2 201341C3 Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, OCL 1.5V (DAC input selected) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, OCL 1.5V (DAC input selected) 201341C4 201341C5 81 www.national.com LM4935 13.0 Typical Performance Characteristics Headphone PSRR vs Frequency AVDD = 3.3V, 0dB AUX, SE (AUX inputs terminated) Headphone PSRR vs Frequency AVDD = 5V, 0dB AUX, SE (AUX inputs terminated) 201341C6 201341C7 Headphone PSRR vs Frequency AVDD = 5V, 0dB CPI, SE (CPI input terminated) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB CPI, SE (CPI input terminated) 201341C8 201341C9 Headphone PSRR vs Frequency AVDD = 5V, 0dB DAC, SE (DAC input selected) Headphone PSRR vs Frequency AVDD = 3.3V, 0dB DAC, SE (DAC input selected) 201341D0 www.national.com (Continued) 201341D1 82 Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB AUX (AUX inputs terminated) LM4935 13.0 Typical Performance Characteristics (Continued) Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB AUX (AUX inputs terminated) 201341N6 201341N7 Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB CPI (CPI input terminated) Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB CPI (CPI input terminated) 201341N8 201341N9 Loudspeaker PSRR vs Frequency AVDD = 5V, 0dB DAC (DAC input selected) Loudspeaker PSRR vs Frequency AVDD = 3.3V, 0dB DAC (DAC input selected) 201341O0 201341O1 83 www.national.com LM4935 13.0 Typical Performance Characteristics INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.0V INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.0V 201341D2 201341D3 INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.5V INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.5V 201341D4 201341D5 INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 2.8V INT/EXT MICBIAS PSRR vs Frequency AVDD = 3.3V, MICBIAS = 2.8V 201341D6 www.national.com (Continued) 201341D7 84 INT/EXT MICBIAS PSRR vs Frequency AVDD = 5V, MICBIAS = 3.3V (Continued) AUXOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ 201341D9 201341D8 CPOUT THD+N vs Frequency AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ AUXOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ 201341E0 201341E1 Earpiece THD+N vs Frequency AVDD = 3.3V, 0dB, POUT = 500mW, 32Ω CPOUT THD+N vs Frequency AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ 201341E2 201341E3 85 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics (Continued) Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.5V, 0dB POUT = 7.5mW, 32Ω Earpiece THD+N vs Frequency AVDD = 5V, 0dB, POUT = 50mW, 32Ω 201341E4 201341E5 Headphone THD+N vs Frequency AVDD = 3.3V, OCL 1.2V, 0dB POUT = 7.5mW, 32Ω Headphone THD+N vs Frequency AVDD = 5V, OCL 1.5V, 0dB POUT = 10mW, 32Ω 201341E6 201341N1 Headphone THD+N vs Frequency AVDD = 3.3V, SE, 0dB POUT = 7.5mW, 32Ω Headphone THD+N vs Frequency AVDD = 5V, OCL 1.2V, 0dB POUT = 10mW, 32Ω 201341E7 www.national.com 201341E8 86 LM4935 13.0 Typical Performance Characteristics (Continued) Loudspeaker THD+N vs Frequency AVDD = 3.3V, POUT = 400mW 15µH+8Ω+15µH Headphone THD+N vs Frequency AVDD = 5V, SE, 0dB POUT = 10mW, 32Ω 201341E9 201341O2 Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 16Ω Loudspeaker THD+N vs Frequency AVDD = 5V, POUT = 400mW 15µH+8Ω+15µH 201341F0 201341O3 Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 32Ω Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 16Ω 201341F1 201341F2 87 www.national.com LM4935 13.0 Typical Performance Characteristics Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 32Ω 201341F3 201341F4 Earpiece THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 32Ω Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 16Ω 201341F5 201341F6 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω Earpiece THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 32Ω 201341F7 www.national.com (Continued) 201341F8 88 (Continued) Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 16Ω 201341F9 201341G0 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB DAC fOUT = 1kHz, 32Ω 201341G1 201341G2 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 16Ω 201341G3 201341G4 89 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB DAC fOUT = 1kHz, 32Ω 201341G5 201341G6 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 16Ω 201341G7 201341G8 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB DAC fOUT = 1kHz, 32Ω 201341G9 www.national.com (Continued) 201341H0 90 (Continued) Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 16Ω 201341H1 201341H2 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB DAC fOUT = 1kHz, 32Ω 201341H3 201341H4 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 16Ω 201341H5 201341H6 91 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB DAC fOUT = 1kHz, 32Ω 201341H7 201341H8 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 12dB DAC fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 16Ω 201341H9 201341I0 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 12dB DAC fOUT = 1kHz, 32Ω 201341I1 www.national.com (Continued) 201341I2 92 (Continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω 201341I3 201341I4 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 16Ω 201341I5 201341I6 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω 201341I7 201341I8 93 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 12dB AUX fOUT = 1kHz, 32Ω 201341I9 201341J0 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 16Ω 201341J1 201341J2 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.2V, 0dB CPI fOUT = 1kHz, 32Ω 201341J3 www.national.com (Continued) 201341J4 94 (Continued) Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω 201341J5 201341J6 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 16Ω 201341J7 201341J8 Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω 201341J9 201341K0 95 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 12dB AUX fOUT = 1kHz, 32Ω 201341K1 201341K2 Headphone THD+N vs Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 16Ω 201341K3 201341N2 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, OCL 1.5V, 0dB CPI fOUT = 1kHz, 32Ω 201341N3 www.national.com (Continued) 201341N4 96 (Continued) Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB AUX fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 16Ω 201341K4 201341N5 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 16Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB AUX fOUT = 1kHz, 32Ω 201341K5 201341K6 Headphone THD+N vs Output Power AVDD = 3.3V, SE, 0dB CPI fOUT = 1kHz, 32Ω Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 16Ω 201341K7 201341K8 97 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 15µH+8Ω+15µH Headphone THD+N vs Output Power AVDD = 5V, SE, 0dB CPI fOUT = 1kHz, 32Ω 201341K9 201341O4 Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB AUX fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB AUX fOUT = 1kHz, 15µH+8Ω+15µH 201341O5 201341O6 Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB CPI fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 15µH+8Ω+15µH 201341O7 www.national.com (Continued) 201341O8 98 (Continued) Loudspeaker THD+N vs Output Power AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB CPI fOUT = 1kHz, 15µH+8Ω+15µH 201341O9 201341P0 Loudspeaker THD+N vs Output Power AVDD = 5V, 0dB DAC fOUT = 1kHz, 15µH+8Ω+15µH Loudspeaker THD+N vs Output Power AVDD = 4.2V, 0dB DAC fOUT = 1kHz, 15µH+8Ω+15µH 201341P1 201341P2 AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ 201341L0 201341L1 99 www.national.com LM4935 13.0 Typical Performance Characteristics LM4935 13.0 Typical Performance Characteristics AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB CPI fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB CPI fOUT = 1kHz, 5kΩ 201341L2 201341L3 AUXOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ 201341L4 201341L5 AUXOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ AUXOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ 201341L6 www.national.com (Continued) 201341L7 100 LM4935 13.0 Typical Performance Characteristics (Continued) CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB AUX fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB AUX fOUT = 1kHz, 5kΩ 201341L8 201341L9 CPOUT THD+N vs Output Voltage AVDD = 5V, 0dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 3.3V, 0dB DAC fOUT = 1kHz, 5kΩ 201341M1 201341M0 CPOUT THD+N vs Output Voltage AVDD = 5V, 6dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 3.3V, 6dB MIC fOUT = 1kHz, 5kΩ 201341M2 201341M3 101 www.national.com LM4935 13.0 Typical Performance Characteristics CPOUT THD+N vs Output Voltage AVDD = 5V, 12dB DAC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 3.3V, 12dB DAC fOUT = 1kHz, 5kΩ 201341M4 201341M5 CPOUT THD+N vs Output Voltage AVDD = 5V, 36dB MIC fOUT = 1kHz, 5kΩ CPOUT THD+N vs Output Voltage AVDD = 3.3V, 36dB MIC fOUT = 1kHz, 5kΩ 201341M6 201341M7 Headphone Crosstalk vs Frequency OCL 1.2V, 0dB AUX, 32Ω Headphone Crosstalk vs Frequency OCL 1.5V, 0dB AUX, 32Ω 201341M8 www.national.com (Continued) 201341M9 102 LM4935 13.0 Typical Performance Characteristics (Continued) Headphone Crosstalk vs Frequency SE, 0dB AUX, 32Ω 201341N0 103 www.national.com www.national.com 104 14.0 LM4935 Demonstration Board Schematic Diagram 20134135 LM4935 LM4935 15.0 Demoboard PCB Layout 20134132 Top Silkscreen 105 www.national.com LM4935 15.0 Demoboard PCB Layout (Continued) 20134131 Top Layer www.national.com 106 LM4935 15.0 Demoboard PCB Layout (Continued) 20134129 Mid Layer 1 107 www.national.com LM4935 15.0 Demoboard PCB Layout (Continued) 20134130 Mid Layer 2 www.national.com 108 LM4935 15.0 Demoboard PCB Layout (Continued) 20134128 Bottom Layer 109 www.national.com LM4935 16.0 Product Status Definitions Datasheet Status Product Status Definition Advance Information Formative or in Design This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This data sheet contains preliminary data. Supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production This data sheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Obsolete Not in Production This data sheet contains specifications on a product that has been discontinued by National Semiconductor Corporation. The datasheet is printed for reference information only. National Semiconductor B.V reserves the right to make changes without notice to any products herein to improve reliability, function or design. National does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the right of others. www.national.com 110 LM4935 17.0 Revision History Rev Date Description 1.0 5/11/05 Filled in the actual limits (for TBDs) under Limit and edited few Typical values, all under the EC table. Edits from Alvin F. 1.1 7/29/05 Input more edits. Replaced the correct boards. Replaced the Schematic Diagram (pg 60). 1.2 9/8/05 Added the 1st set of Typ Perf curves. 1.3 9/21/05 Added a couple of tables. 1.4 9/30/05 Input text edits. 1.5 10/5/05 Input more edits. 1.6 10/11/05 More edits. 1.7 10/12/05 First D/S WEB release. 1.8 10/14/5 Input more text edits after the 1st released. 1.9 10/17/05 Input some text edits, then re-released D/S to the WEB. 2.0 10/18/05 More text edits. Also used graphic 20134107 back. 111 www.national.com LM4935 Audio Sub-System with Dual-Mode Stereo Headphone & Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC 18.0 Physical Dimensions inches (millimeters) unless otherwise noted 49 Bump Microfil Package Order Number LM4935 Dimensions: X1 = 3.925 mm, X2 = 3.925 mm, X3 = 0.6 mm NS Package Number WLA49VVA National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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