XILINX XCR22LV10

0
XCR22LV10: 3V Zero Power,
TotalCMOS, Universal PLD Device
R
DS047 (v1.1) February 10, 2000
0
0*
Product Specification
Features
Description
•
The XCR22LV10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or
other power down schemes. To achieve this, Xilinx has
used their FZP design technique, which replaces conventional sense amplifier methods for implementing product
terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates.
This results in the combination of low power and high
speed that has previously been unattainable in the PLD
arena. For 5V operation, Xilinx offers the XCR22V10 that
offers high speed and low power in a 5V implementation.
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Industry's first TotalCMOS™ SPLD - both CMOS
design and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and high speed
- Static current of less than 45 µA
- Dynamic current substantially below that of
competing devices
- Pin-to-pin delay of only 10 ns
True Zero Power device with no turbo bits or power
down schemes
Function/JEDEC map compatible with Bipolar,
UVCMOS, EECMOS 22V10s
Multiple packaging options featuring PCB-friendly
flow-through pinouts (SOL and TSSOP)
- 24-pin TSOIC–uses 93% less in-system space than
a 28-pin PLCC
- 24-pin SOIC
- 28-pin PLCC with standard JEDEC pinout
Available in commercial and industrial operating ranges
Supports mixed voltage systems—5V tolerant I/Os
Advanced 0.5µ E2CMOS process
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Varied product term distribution with up to 16 product
terms per output for complex functions
Programmable output polarity
Synchronous preset/asynchronous reset capability
Security bit prevents unauthorized access
Electronic signature for identification
Design entry and verification using industry standard
CAE tools
Reprogrammable using industry standard device
programmers
DS047 (v1.1) February 10, 2000
The XCR22LV10 uses the familiar AND/OR logic array
structure, which allows direct implementation of
sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum
of products feeds an "Output Macro Cell" (OMC), which can
be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.
Functional Description
The XCR22LV10 implements logic functions as
sum-of-products expressions in a programmableAND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into
the array. User-configurable output structures in the form of
I/O macrocells further increase logic flexibility (Figure 1).
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1
.
CLK/I0
1
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39 40
24
VCC
43
AR
0
1
DAR
9
SP
Q
Q
1
1
0
0
0
1
0
1
23
F9
1
1
0
0
0
1
0
1
22
F8
1
1
0
0
0
1
0
1
21
F7
1
1
0
0
0
1
0
1
20
F6
1
1
0
0
0
1
0
1
19
F5
1
1
0
0
0
1
0
1
18
F4
1 0
1 1
0 0
0 1
17
F3
1
1
0
0
0
1
0
1
16
F2
1
1
0
0
0
1
0
1
15
F1
1
1
0
0
0
1
0
1
14
F0
13
I11
0
1
10
DAR
20
I1
SP
Q
Q
0
1
2
21
DAR
SP
33
I2
Q
Q
0
1
3
34
DAR
SP
Q
Q
48
I3
0
1
4
49
DAR
SP
Q
Q
65
I4
0
1
5
66
Programmable connection.
DAR
SP
Q
Q
82
I5
0
1
6
83
DAR
SP
Q
Q
97
I6
0
1
7
98
DAR
SP
110
I7
Q
Q
0
1
8
111
DAR
121
I8
SP
Q
Q
0
1
9
122
DAR
130
SP
I9
10
SP
131
I10 11
GND 12
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39 40
Q
Q
0
1
43
NOTE:
SP00059
Figure 1: XCR22LV10 Logic Diagram
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Architecture Overview
44 input lines:
• 24 input lines carry the True and Complement of the
signals applied to the 12 input pins
• 20 additional lines carry the True and Complement
values of feedback or input signals from the ten I/Os
• 132 product terms:
• 120 product terms (arranged in two groups of 8, 10, 12,
14, and 16) used to form logical sums
• Ten output enable terms (one for each I/O)
• One global synchronous preset product term
• One global asynchronous clear product term
The XCR22LV10 architecture is illustrated in Figure. Twelve
dedicated inputs and ten I/Os provide up to 22 inputs and
ten outputs for creation of logic functions. At the core of the
device is a programmable electrically-erasable AND array
which drives a fixed-OR array. With this structure, the
XCR22LV10 can implement up to ten sum-of-products logic
expressions.
Associated with each of the ten OR functions is an I/O macrocell which can be independently programmed to one of
four different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions with either active High or active Low polarity.
At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term
which is connected to both the True and Complement of an
input signal will always be FALSE, and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a Don't Care state exists and
that term will always be TRUE.
AND/OR Logic Array
The programmable AND array of the XCR22LV10 (shown
in the Logic Diagram, Figure 1) is formed by input lines
intersecting product terms. The input lines and product
terms are used as follows:
CLK/I0
I1 – I11
1
11
PROGRAMMABLE AND ARRAY
(44 ×
8
10
12
14
16
16
14
12
10
8
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
PRESET
RESET
132)
SP00060A
Figure 2: Functional Diagram
Variable Product Term Distribution
The XCR22LV10 provides 120 product terms to drive the
ten OR functions. These product terms are distributed
among the outputs in groups of 8, 10, 12, 14, and 16 to
form logical sums (see Logic Diagram). This distribution
allows optimum use of device resources.
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. the ability to configure each
output independently permits users to tailor the configura3
tion of the XCR22LV10 to the precise requirements of their
designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 3 consists of a
D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell of the XCR22LV10 is determined by the two EEPROM bits controlling these
multiplexers. These bits determine output polarity, and output type (registered or non-registered). Equivalent circuits
for the macrocell configurations are illustrated in Figure 4.
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DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
.
1
AR
D
Q
SP
1
1
0
0
0
Q
CLK
0
F
1
S1
S0
0
0
Registered/Active-LOW/Macrocell feedback
OUTPUT CONFIGURATION
0
1
Registered/Active-HIGH/Macrocell feedback
1
0
Combinatorial/Active-LOW/Pin feedback
1
1
Combinatorial/Active-HIGH/Pin feedback
0 = Unprogrammed fuse
1 = Programmed fuse
S1
S0
0
1
SP00484
Figure 3: Output Macrocell Logic Diagram
S0 = 0
S1 = 0
AR
D
Q
CLK
S0 = 0
S1 = 1
F
F
Q
SP
a. Registered/Active-LOW
S0 = 1
S1 = 0
AR
D
c. Combinatorial/Active-LOW
Q
S0 = 1
S1
F
F
Q
CLK
SP
d. Combinatorial/Active-HIGH
b. Registered/Active-HIGH
SP00376
Figure 4: Output Macrocell Configurations
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Output Type
The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type
flip-flop (registered function). The D-type flip-flop latches
data on the rising edge of the clock and is controlled by the
global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set
High at the next rising edge of the clock input. Satisfying the
asynchronous clear term will set Q LOW, regardless of the
clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
Program/Erase Cycles
The XCR22LV10 is 100% testable, erases/programs in
seconds, and guarantees 1000 program/erase erase
cycles.
Output Polarity
Each macrocell can be configured to implement active High
or active Low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bidirectional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically FALSE and
the I/O will function as a dedicated input.
can be used as a dedicated input, a dedicated output, or a
bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a
reset condition and the Q output will be low. The actual output of the XCR22LV10 will depend on the programmed output polarity. The VCC rise must be monotonic.
Design Security
The XCR22LV10 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been
programmed. Once the security bit is set, it is impossible to
verify (read) or program the XCR22LV10 until the entire
device has first been erased with the bulk-erase function.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS SPLD, both in process technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer SPLDs which are
both high performance and low power, breaking the paradigm that to have low power, you must accept low performance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR22LV10 TotalCMOS SPLD.
Table 1: Typical ICC vs. Frequency @ VCC = 3.3V, 25°C
Register Feedback Select
When the I/O macrocell is configured to implement a registered function (S1=0) (Figure 4a or Figure 4b), the feedback signal to the AND array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial function (S1=1) (Figure 4c or Figure 4d), the feedback signal is taken from the I/O pin. In this case, the pin
5
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Frequency (MHz)
1
10
20
30
40
50
60
70
80
90
100
110
120
130
Tupical ICC (mA)
0.2
1.5
3.0
4.5
6.0
7.4
8.9
10.4
11.8
13.2
14.5
15.8
17.0
18.2
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
30
TYPICAL
25
20
ICC
(mA)
15
10
5
0
1
10
20
30
40
50
60
70
80
90
100
110
120
130
FREQUENCY (MHz)
SP00443
Figure 5: Typical ICC vs. Frequency @ VCC = 3.3V, 25°C (10-bit counter)
Absolute Maximum Ratings1
Symbol
VCC
Parameter
Supply voltage
Min.
Max.
Unit
–0.5
4.6
V
V
VI
Input voltage
–0.5
5.52
VOUT
Output voltage
–0.5
5.52
V
IIN
Input current
–30
30
mA
IOUT
Output current
–100
100
mA
TR
Allowale thermal rise ambient to junction
0
75
°C
TJ
Maximum junction temperature
–40
150
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation
at these or any other condition above those indicated in the operational and programming specification is not implied..
2. Except F7, where max = VCC + 0.5V.
Operating Range
Product Grade
Commercial
Industrial
DS047 (v1.1) February 10, 2000
Temperature
0 to +70°C
–40 to +85°C
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Voltage
3.3V ± 10%
3.3V ± 10%
6
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.03.6V ≤ VCC ≤ 3.6V
Symbol
VIL
VIH
VI
VOL
VOH
II
Parameter
Input voltage Low
Input voltage High
Input clamp voltage
Output voltage Low
Output voltage High
Input leakage current
IOZL
3-stated output leakage current
ICCQ
ICCD1
Standby current
Dynamic current
IOS
Short circuit output current
CIN
CCLK
CI/O
Notes:
Input pin capacitance
Clock input capacitance
I/O pin capacitance
Test Conditions
VCC = 3.0V
VCC = 3.6V
VCC = 3.0V, IIN = –18 mA
VCC = 3.0V, IOL = 8 mA
VCC = 3.0V, IOH = –4 mA
VIN = 0V to VCC
VIN = VCC to 5.5V 2
VIN = 0V to VCC
VIN = VCC to 5.5V 2
VCC = 3.6V, TAMB = 0°C
VCC = 3.6V, TAMB = 0°C at 1 MHz
VCC = 3.6V, TAMB = 0°C at 50 MHz
One pin at a time for no longer than 1
second
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
Min.
Typ.
Max.
0.8
2
–1.2
0.5
2.4
–10
–10
–10
–10
25
0.5
10
–15
5
10
10
10
10
45
2
15
–100
8
12
10
Unit
V
V
V
V
V
µA
µA
µA
mA
mA
mA
pF
pF
pF
1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This
parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where
current may be affected.
2. Does not apply to F7.
7
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
AC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ + 70°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
-B
Parameter
Min.
tPD
Propagation delay time, input or feedback to non-registered output
tSU
Setup time from input, feedback or SP to Clock
tCO
Clock to output
tCF
Clock to feedback1
tH
Holt time
Asynchronous Reset to registered output
tAR
tARW
Asynchronous Reset width
tARR
Asynchronous Reset recovery time
tSPF
Synchronou Preset recovery time
tWL
Width of Clock Low
tWH
Width of Clock High
Input rise time
tR
tF
Input fall time
fMAX1
Maximum FF toggle rate2 (1/tSU + tCF)
fMAX2
Maximum internal frequency1 (1/tSU + tCO)
fMAX3
Maximum external frequency1 (1/tWL + tWH)
tEA
Input to output enable
Input to output disable
tER
Capacitance
CIN
Input pin capacitance
COUT
Output capacitance
-D
Max.
15
Min.
Max.
10
Unit
9
9
9
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
MHz
MHz
MHz
ns
ns
10
10
10
10
pF
pF
4.5
3.5
10
6
0
17
5
9
4.5
0
17
5
6
6
3
3
6
6
3
3
20
20
95
69
167
20
20
125
80
167
Notes:
1. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may
be affected.
2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is not
100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: –40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
VIL
VIH
VI
VOL
VOH
II
Parameter
Input voltage Low
Input voltage High
Input clamp voltage
Output voltage Low
Output voltage High
Input leakage current
IOZL
3-stated output leakage current
ICCQ
ICCD1
Standby current
Dynamic current
IOS
Short circuit output current
CIN
CCLK
CI/O
Notes:
Input pin capacitance
Clock input capacitance
I/O pin capacitance
Test Conditions
VCC = 3.0V
VCC = 3.6V
VCC = 3.0V, IIN = –18 mA
VCC = 3.0V, IOL = 8 mA
VCC = 3.0V, IOH = –4 mA
VIN = 0V to VCC
VIN = VCC to 5.5V 2
VIN = 0V to VCC
VIN = VCC to 5.5V 2
VCC = 3.6V, TAMB = –40°C
VCC = 3.6V, TAMB = –40°C at 1 MHz
VCC = 3.6V, TAMB = –40°C at 50 MHz
One pin at a time for no longer than 1
second
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
TAMB = 25°C, f = 1 MHz
Min.
Typ.
Max.
0.8
2
–1.2
0.5
2.4
–10
–10
–10
–10
30
0.5
10
–15
5
10
10
10
10
45
3
20
–100
8
12
10
Unit
V
V
V
V
V
µA
µA
µA
mA
mA
mA
pF
pF
pF
1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This
parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where
current may be affected.
2. Does not apply to F7.
9
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DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
AC Electrical Characteristics For Industrial Grade Devices
Industrial: –40°C ≤ TAMB ≤ +85°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
Parameter
tPD
Propagation delay time, input or feedback to non-registered output
tSU
Setup time from input, feedback or SP to Clock
tCO
Clock to output
tCF
Clock to feedback1
tH
Holt time
Asynchronous Reset to registered output
tAR
tARW
Asynchronous Reset width
tARR
Asynchronous Reset recovery time
tSPF
Synchronou Preset recovery time
tWL
Width of Clock Low
tWH
Width of Clock High
Input rise time
tR
tF
Input fall time
fMAX1
Maximum FF toggle rate2 (1/tSU + tCF)
fMAX2
Maximum internal frequency1 (1/tSU + tCO)
fMAX3
Maximum external frequency1 (1/tWL + tWH)
tEA
Input to output enable
Input to output disable
tER
Capacitance
CIN
Input pin capacitance
COUT
Output capacitance
Min.
Max.
15
Unit
11
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
MHz
MHz
MHz
ns
ns
10
12
pF
pF
5
10.5
6
0
17
5
6
6
3
3
20
20
91
65
167
Notes:
1. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified
where current may be affected.
2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is
not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
DS047 (v1.1) February 10, 2000
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Test Load Circuit
VCC
C1
+3.3V
S1
C2
R1
F0
I0
R2
DUT
CL
INPUTS
Fn
In
OE
CK
GND
NOTE:
C1 and C2 are to bypass VCC to GND.
R1 = 300Ω, R2 = 300Ω, CL = 35pF.
SP00478
Thevenin Equivalent
VL = 1.65V
150Ω
DUT OUTPUT
35 pF
Voltage Waveform
+3.0V
90%
10%
0V
tR
tF
1.5ns
1.5ns
SP00368
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
11
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Switching Waveforms
INPUT OR
FEEDBACK
INPUT OR
FEEDBACK
VT
VT
tPD
tS
COMBINATORIAL
OUTPUT
tH
CLOCK
VT
VT
tCO
REGISTERED
OUTPUT
Combinatorial Output
VT
Registered Output
INPUT
VT
tWH
tER
CLOCK
tEA
VT
VOH – 0.5V
OUTPUT
VT
VOL + 0.5V
tWL
Clock Width
Input to Output Disable/Enable
tARW
INPUT ASSERTING
ASYNCHRONOUS
RESET
INPUT ASSERTING
SYNCHRONOUS
PRESET
VT
VT
tAR
REGISTERED
OUTPUT
tS
CLOCK
VT
tSPR
VT
tARR
CLOCK
tH
VT
tCO
REGISTERED
OUTPUT
VT
VT
Asynchronous Reset
Synchronous Preset
NOTES:
1. VT = 1.5V.
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 2.0 ns max.
SP00483
"AND" Array: (I,B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
P, D
P, D
P, D
STATE
CODE
STATE
CODE
STATE
CODE
INACTIVE 1
O
TRUE
H
COMPLEMENT
L
STATE
DON’T CARE
CODE
—
SP00008
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XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Pin Configurations
Pin Descriptions
I2
I1
IO/CLK
NC
VCC
F9
F8
28-pin PLCC
4
3
2
1
28
27
26
I3
5
25 F7
I4
6
24 F6
I5
7
23 F5
NC
8
22 NC
I6
9
21 F4
I7
10
20 F3
I8
11
Pin Label
I1-I11
NC
F0-F9
I0/CLK
VCC
Description
Dedicated input
Not Connected
Macrocell Input/Output
Dedicated Input/Clock Output
Supply Voltage
GND
Ground
13
14
15
16
17
18
I9
I10
GND
NC
I11
F0
F1
19 F2
12
SP00474
24-pin SOIC and 24-pin TSOIC
IO/CLK
1
24 VCC
I1
2
23 F9
I2
3
22 F8
I3
4
21 F7
I4
5
20 F6
I5
6
19 F5
I6
7
18 F4
I7
8
17 F3
I8
9
16 F2
I9 10
15 F1
I10 11
14 F0
GND 12
13 I11
AP00475
13
www.xilinx.com
1-800-255-7778
DS047 (v1.1) February 10, 2000
R
XCR22LV10: 3V Zero Power, TotalCMOS, Universal PLD
Ordering Information
Example: XCR22LV10 -10 PC 28 C
Temperature Range
Device Type
Number of Pins
Speed Options
Package Type
Temperature Range
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
Speed Options
-15: 15 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
Packaging Options
SO24: 24-pin SOIC
VO24: 24-pin TSOIC
PC28: 28-pin PLCC
Component Availability
Pins
Type
Code
XCR22LV10
24
Plastic SOIC
SO24
-15
-10
Plastic Thin SOIC
VO24
C, I
C
28
Plastic PLCC
PC28
C, I
C
Revision History
Date
8/4/99
2/10/00
Version #
1.0
1.1
Revision
Initial Xilinx release.
Convert to Xilinx Format
DS047 (v1.1) February 10, 2000
www.xilinx.com
1-800-255-7778
14