0 R XCR3064XL 64 Macrocell CPLD DS017 (v2.4) September 15, 2008 0 14 Product Specification Features Description • • • • • The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are as fast as 5.5 ns with a maximum system frequency of 192 MHz. - TotalCMOS Design Technique for Fast Zero Power Advanced 0.35 micron five layer metal EEPROM process - • Fast Zero Power CMOS design technology 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance) Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - • • • • • • Full IEEE Standard 1149.1 boundary-scan (JTAG) Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins CoolRunner XPLA3 CPLDs offer a TotalCMOS solution, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3064XL TotalCMOS CPLD (data taken with four resetable up/down, 16-bit counters at 3.3V, 25° C). 45 40 35 Typical ICC (mA) • Low power 3.3V 64 macrocell CPLD 5.5 ns pin-to-pin logic delays System frequencies up to 192 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages - 44-pin VQFP (36 user I/O pins) - 48-ball CS BGA (40 user I/O pins) - 56-ball CP BGA (48 user I/O pins) - 100-pin VQFP (68 user I/O pins) Optimized for 3.3V systems - Ultra-low power operation - Typical Standby Current of 17 μA at 25°C - 5V tolerant I/O pins with 3.3V core supply 30 25 20 15 10 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access 5 0 0 20 40 60 80 100 120 140 160 180 Frequency (MHz) Refer to XPLA3 family data sheet (DS012) for architecture description DS017_01_062502 Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C) Frequency (MHz) 0 1 5 10 20 40 60 80 Typical ICC (mA) 0.017 0.24 1.09 2.15 4.28 8.50 12.85 16.80 100 120 140 160 180 20.80 25.72 29.89 33.53 36.27 © 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS017 (v2.4) September 15, 2008 Product Specification www.xilinx.com 1 R XCR3064XL 64 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol VOH(2) Parameter(1) Output High voltage Test Conditions Typical Min. Max. Unit VCC = 3.0V to 3.6V, IOH = –8 mA - 2.4 - V VCC = 2.7V to 3.0V, IOH = –8 mA - 2.0 - V IOH = –500 μA - 90% VCC(3) - V VOL Output Low voltage for 3.3V outputs IOL = 8 mA - - 0.4 V IIL(4) Input leakage current VIN = GND or VCC to 5.5V - –10 10 μA IIH(4) I/O High-Z leakage current VIN = GND or VCC to 5.5V - –10 10 μA ICCSB(8) Standby current VCC = 3.6V 24.5 - 100 μA ICC Dynamic current(5,6) f = 1 MHz - - 0.75 mA f = 50 MHz - - 15 mA CIN Input pin capacitance(7) f = 1 MHz - - 8 pF CCLK Clock input capacitance(7) f = 1 MHz - - 12 pF CI/O I/O pin capacitance(7) f = 1 MHz - - 10 pF Notes: 1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. Typical leakage current is less than 1 μA. 5. See Table 1, and Figure 1 for typical values. 6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 7. Typical values, not tested. 8. Typical value at 70°C. 100 90 IOL (3.3V) 80 70 mA 60 50 IOH (3.3V) 40 30 IOH (2.7V) 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts DS012_10_031802 Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C 2 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification R XCR3064XL 64 Macrocell CPLD AC Electrical Characteristics Over Recommended Operating Conditions -6 Parameter(1,2) -7 -10 Min. Max. Min. Max. Min. Max. Unit - 5.5 - 7.0 - 9.1 ns - 6.0 - 7.5 - 10.0 ns - 4.0 - 5.0 - 6.5 ns Setup time (fast input register) 2.5 - 2.5 - 3.0 - ns Setup time (single p-term) 3.5 - 4.3 - 5.4 - ns TSU2 Setup time (OR array) 4.0 - 4.8 - 6.3 - ns TH(4) Hold time 0 - 0 - 0 - ns TWLH(4) Global Clock pulse width (High or Low) 2.5 - 3.0 - 4.0 - ns TPLH(4) P-term clock pulse width 4.0 - 5.0 - 6.0 - ns TAPRPW Asynchronous preset/reset pulse width (High or Low) 4.0 - 5.0 - 6.0 - ns TR(4) TL(4) Input rise time - 20 - 20 - 20 ns Input fall time - 20 - 20 - 20 ns Symbol TPD1 Propagation delay time (single p-term) array)(3) TPD2 Propagation delay time (OR TCO Clock to output (global synchronous pin clock) TSUF TSU1 (4) fSYSTEM (4) - 192 - 119 - 95 MHz time(5) - 60 - 60 - 60 μs TINIT(4) ISP initialization time - 60 - 60 - 60 μs TPOE(4) P-term OE to output enabled - 7.5 - 9.3 - 11.2 ns TPOD(4) P-term OE to output disabled(6) - 7.5 - 9.3 - 11.2 ns P-term clock to output - 7.0 - 8.3 - 10.7 ns P-term set/reset to output valid - 8.0 - 9.3 - 11.2 ns TCONFIG TPCO (4) TPAO(4) (4) Maximum system frequency Configuration Notes: 1. Specifications measured with one output switching. 2. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 6 mA at 3.6V. 6. Output CL = 5 pF. DS017 (v2.4) September 15, 2008 Product Specification www.xilinx.com 3 R XCR3064XL 64 Macrocell CPLD Internal Timing Parameters -6 Parameter(1, 2) Symbol -7 -10 Min. Max. Min. Max. Min. Max. Unit Buffer Delays TIN Input buffer delay - 1.3 - 1.6 - 2.2 ns TFIN Fast Input buffer delay - 2.3 - 3.0 - 3.1 ns TGCK Global Clock buffer delay - 0.8 - 1.0 - 1.3 ns TOUT Output buffer delay - 2.2 - 2.7 - 3.6 ns TEN Output buffer enable/disable delay - 4.2 - 5.0 - 5.7 ns - 1.3 - 1.6 - 2.0 Internal Register and Combinatorial Delays TLDI Latch transparent delay TSUI Register setup time 1.0 - 1.0 - 1.2 - ns THI Register hold time 0.3 - 0.5 - 0.7 - ns TECSU Register clock enable setup time 2.0 - 2.5 - 3.0 - ns TECHO Register clock enable hold time 3.0 - 4.5 - 5.5 - ns TCOI Register clock to output delay - 1.0 - 1.3 - 1.6 ns TAOI Register async. S/R to output delay - 2.5 - 2.3 - 2.1 ns TRAI Register async. recovery - 4.0 - 5.0 - 6.0 ns TPTCK Product term clock delay - 2.5 - 2.7 - 3.3 ns TLOGI1 Internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns TLOGI2 Internal logic delay (PLA OR term) - 2.5 - 3.2 - 4.2 ns - 0.7 - 2.9 - 3.5 ns Feedback Delays TF ZIA delay Time Adders TLOGI3 Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns TUDA Universal delay - 1.5 - 2.0 - 2.5 ns TSLEW Slew rate limited delay - 4.0 - 5.0 - 6.0 ns Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model. 4 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification R XCR3064XL 64 Macrocell CPLD Switching Characteristics VCC S1 Component R1 R2 C1 R1 Values 390Ω 390Ω 35 pF VIN VOUT R2 Measurement TPOE (High) TPOE (Low) TP C1 S1 Open Closed Closed S2 Closed Open Closed Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV. S2 DS017_03_102401 Figure 3: AC Load Circuit 5.6 +3.0V 90% 5.5 5.4 (ns) 5.3 10% 0V 5.2 5.1 TR 5.0 1.5 ns 4.9 TL 1.5 ns 4.8 4.7 4.6 1 2 4 8 16 Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Number of Adjacent Outputs Switching 3.3V, 25°C DS017_04_062502 DS017_05_042800 Figure 5: Voltage Waveform Figure 4: Derating Curve for TPD2, 3.3V, 25°C DS017 (v2.4) September 15, 2008 Product Specification www.xilinx.com 5 R XCR3064XL 64 Macrocell CPLD Pin Descriptions Table 3: XCR3064XL I/O Pins Function Block Table 2: XCR3064XL User I/O Pins PC44(1) VQ44 CS48 CP56 VQ100 36 36 40 48 68 Total User I/O Pins 1. This is an obsolete package type. It remains here for legacy support only Table 3: XCR3064XL I/O Pins Function Block 6 Macrocell PC44(1) VQ44 Macrocell PC44(1) VQ44 CS48 CP56 VQ100 2 14 11 5 D3 E3 12 2 15 12 6 D1 F1 13 2 16 - - - - 14 3 1 32(2) 26(2) E5(2) F10(2) 62(2) 3 2 31 25 E7 G8 61 3 3 - - - - 60 3 4 29 23 F7 H10 58 CS48 CP56 VQ100 3 5 - - - - 57 1 1 41 35 C5 C8 85 3 6 - - - - 56 1 2 40 34 A6 A8 84 3 7 - - F6 K8 54 1 3 - - - - 83 3 8 - - - K10 52 1 4 - - - A9 81 3 9 28 22 G7 K9 48 1 5 - - - A5 80 3 10 27 21 G6 J10 47 1 6 - - A7 A10 79 3 11 26 20 F5 H8 46 1 7 - - - - 76 3 12 25 19 G5 H7 45 1 8 39 33 B6 B10 75 3 13 24 18 F4 H6 44 1 9 38(2) 32(2) 73(2) 3 14 - - - - 42 1 10 37 31 D4 D8 71 3 15 - - - K7 41 1 11 36 30 C6 E8 69 3 16 - - - - 40 1 12 - - - - 68 4 1 13(2) 7(2) D2(2) G1(2) 15(2) 1 13 - - - - 67 4 2 14 8 E1 F3 16 1 14 34 28 D6 F8 65 4 3 - - - - 17 1 15 33 27 D7 E10 64 4 4 16 10 F1 G3 19 1 16 - - - - 63 4 5 17 11 G1 J1 20 2 1 4 42 A2 C4 92 4 6 - - - - 21 2 2 5 43 A1 C3 93 4 7 - - - - 23 2 3 6 44 C4 A1 94 4 8 - - - K1 25 2 4 - - - - 96 4 9 18 12 E4 K4 29 2 5 - - - B1 97 4 10 19 13 F2 K2 30 2 6 - - - - 98 4 11 20 14 G2 K3 31 2 7 - - - A2 99 4 12 21 15 F3 H3 32 2 8 - - B2 A3 100 4 13 - - G3 H4 33 2 9 7(2) 1(2) B1(2) C1(2) 4(2) 4 14 - - - - 35 2 10 8 2 C2 D1 6 4 15 - - - K5 36 2 11 9 3 C1 D3 8 4 16 - - - - 37 2 12 - - - - 9 2 13 - - - - 10 B7(2) C10(2) Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. JTAG pins. www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification R XCR3064XL 64 Macrocell CPLD Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type PC44(1) VQ44 CS48 CP56 VQ100 IN0 / CLK0 2 40 A3 C5 90 IN1 / CLK1 1 39 B4 C6 89 IN2 / CLK2 44 38 A4 C7 88 IN3 / CLK3 43 37 B5 A6 87 TCK 32 26 E5 F10 62 TDI 7 1 B1 C1 4 TDO 38 32 B7 C10 73 TMS 13 7 D2 G1 15 PORT_EN 10(2) 4(2) C3(2) E1(2) 11(2) VCC 3, 15, 23, 35 9, 17, 29, 41 B3, C7, E2, G4 A4, D10, H1, H5 3, 18, 34, 39, 51, 66, 82, 91 GND 22, 30, 42 16, 24, 36 A5, E3, E6 A7, G10, K6 26, 38, 43, 59, 74, 86, 95 No Connects - - - - 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for more information. Device Part Marking R XCRxxxxXL TQ144 Device Type Package 7C Speed Operating Range This line not related to device part number 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · · · · Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 3064XL. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C1 = CS48, C2 = CSG48, C3 = CP56, C4 = CPG56. DS017 (v2.4) September 15, 2008 Product Specification www.xilinx.com 7 R XCR3064XL 64 Macrocell CPLD Ordering Combination Information Device Ordering and Part Marking Number Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) XCR3064XL-6VQ44C 6 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3064XL-6VQG44C 6 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3064XL-6CS48C 6 ns CS48 48 Chip Scale Package (CSP) C XCR3064XL-6CSG48C 6 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3064XL-6CP56C 6 ns CP56 56 Chip Scale Package (CSP) C XCR3064XL-6CPG56C 6 ns CPG56 56 Chip Scale Package (CSP); Pb-Free C XCR3064XL-6VQ100C 6 ns VQ100 100 Very Thin Quad Flat Package (VQFP) C XCR3064XL-6VQG100C 6 ns VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free C XCR3064XL-7VQ44C 7.5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3064XL-7VQG44C 7.5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3064XL-7CS48C 7.5 ns CS48 48 Chip Scale Package (CSP) C XCR3064XL-7CSG48C 7.5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3064XL-7CP56C 7.5 ns CP56 56 Chip Scale Package (CSP) C XCR3064XL-7CPG56C 7.5 ns CPG56 56 Chip Scale Package (CSP); Pb-Free C XCR3064XL-7VQ100C 7.5 ns VQ100 100 Very Thin Quad Flat Package (VQFP) C XCR3064XL-7VQG100C 7.5 ns VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free C XCR3064XL-7VQ44I 7.5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) I XCR3064XL-7VQG44I 7.5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free I XCR3064XL-7CS48I 7.5 ns CS48 48 Chip Scale Package (CSP) I XCR3064XL-7CSG48I 7.5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free I XCR3064XL-7CP56I 7.5 ns CP56 56 Chip Scale Package (CSP) I XCR3064XL-7CPG56I 7.5 ns CPG56 56 Chip Scale Package (CSP); Pb-Free I XCR3064XL-7VQ100I 7.5 ns VQ100 100 Very Thin Quad Flat Package (VQFP) I XCR3064XL-7VQG100I 7.5 ns VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free I XCR3064XL-10VQ44C 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3064XL-10VQG44C 10 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3064XL-10CS48C 10 ns CS48 48 Chip Scale Package (CSP) C XCR3064XL-10CSG48C 10 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3064XL-10CP56C 10 ns CP56 56 Chip Scale Package (CSP) C XCR3064XL-10CPG56C 10 ns CPG56 56 Chip Scale Package (CSP); Pb-Free C XCR3064XL-10VQ100C 10 ns VQ100 100 Very Thin Quad Flat Package (VQFP) C XCR3064XL-10VQG100C 10 ns VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free C XCR3064XL-10VQ44I 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) I XCR3064XL-10VQG44I 10 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free I XCR3064XL-10CS48I 10 ns CS48 48 Chip Scale Package (CSP) I XCR3064XL-10CSG48I 10 ns CSG48 48 Chip Scale Package (CSP); Pb-Free I XCR3064XL-10CP56I 10 ns CP56 56 Chip Scale Package (CSP) I 8 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification R XCR3064XL 64 Macrocell CPLD Ordering Combination Information (Continued) Speed (pin-to-pin delay) Pkg. Symbol XCR3064XL-10CPG56I 10 ns CPG56 56 Chip Scale Package (CSP); Pb-Free I XCR3064XL-10VQ100I 10 ns VQ100 100 Very Thin Quad Flat Package (VQFP) I XCR3064XL-10VQG100I 10 ns VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free I Device Ordering and Part Marking Number No. of Pins Package Type Operating Range(1) Notes: 1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C DS017 (v2.4) September 15, 2008 Product Specification www.xilinx.com 9 R XCR3064XL 64 Macrocell CPLD Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Additional Information CoolRunner XPLA3 CPLD Data Sheets and Application Notes Device Packages Device Package User Guide Revision History The following table shows the revision history for this document. 10 Date Version Revision 06/01/00 1.0 Initial Xilinx release. 08/30/00 1.1 Added 48-ball CS BGA package. 11/18/00 1.2 Updated to full production data sheet; corrected note in Table 4 to read: "port enable pin is brought High". 12/08/00 1.3 Added PC44 package. 04/11/01 1.4 Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. 04/19/01 1.5 Updated Typical I/V curve, Figure 2: added voltage levels. 01/08/02 1.6 Moved ICC vs. Freq Figure 1 and Table 1 to page 1. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TSUF and TFIN spec to match software timing. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement. Updated note 5 in AC Characteristics table lowering typical current draw during configuration. 04/02/02 1.7 Updated the following specs based on characterization of product after move to UMC fabrication: VOH, FSYSTEM, TPCO (added TPTCK parameter), TF, and TLOGI3. Added typical leakage current note to DC table. Also updated Typical ICC vs. Frequency and Derating Curve for TPD2 (improved to 5.4 ns for 16 outputs switching) per new characterization data. 01/27/03 1.8 Corrected typical ICC vs. Frequency (Figure 1) and Derating Curve for TPD2 (Figure 4). Updated FMAX for -6 speed, ICC @ f=1 MHz based on characterization of product after move to UMC fabrication. Updated Ordering Information format. 07/15/03 1.9 Updated Device Part Marking. Updated test conditions for IIL and IIH. 08/21/03 2.0 Updated Package Device Marking Pin 1 orientation. 02/13/04 2.1 Add soldering temperature. Add links to application notes and data sheets and packages. 04/08/05 2.2 Added ICCSB Typical and TAPRPW specifications. Removed TSOL specification. 03/31/06 2.3 Added Warranty Disclaimer. Added Pb-Free information to ordering table. 09/15/08 2.4 Added notes to Table 2, Table 3 and Table 4 to indicate the PC44 package is obsolete. Removed part number references to the obsolete PC44C and PCG44C packages in the Ordering Combination Information. See Product Discontinuation Notice xcn07022.pdf. www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification