XILINX XCR3128A

APPLICATION NOTE
0
XCR3128A: 128 Macrocell
CPLD with Enhanced Clocking

DS035 (v1.2) August 10, 2000
0
14*
Product Specification
Features
Description
•
The XCR3128A CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner® family of CPLDs
from Xilinx. These devices combine high speed and zero
power in a 128 macrocell CPLD. With the FZP design technique, the XCR3128A offers true pin-to-pin speeds of 7.5
ns, while simultaneously delivering power that is less than
100 µA at standby without the need for ‘turbo bits' or other
power-down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the patented full CMOS FZP design technique.
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Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
3V, In-System Programmable (ISP) using a JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by multiple ISP programming platforms
- 4-pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG commands include: Bypass, Idcode
High-speed pin-to-pin delays of 7.5 ns
Ultra-low static power of less than 100 µA
5V tolerant I/Os to support mixed voltage systems
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
Up to 20 clocks available
Support for complex asynchronous clocking
Innovative XPLA™ architecture combines high-speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
Advanced 0.35µ E2CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
Reprogrammable using industry standard device
programmers
Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
- Up to two, asynchronous clocks
Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
Available in TQFP and VQFP packages
Available in both commercial and industrial grades
Industrial grade operates from 2.7V to 3.6V
DS035 (v1.2) August 10, 2000
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high-speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 1.5 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9 ns from any pin to any
other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR3128A CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional
and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Logic Block Architecture
The XCR3128A CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128A also includes an industry-standard, IEEE
1149.1, JTAG interface through which In-System Programming (ISP) and reprogramming of the device are supported.
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells’ flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Architecture section for details). The PAL array consists of a programmable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed
path through the array, while the PLA array provides
increased product term density.
XPLA Architecture
Figure 1 shows a high-level block diagram of a 128 macrocell device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin tPD of the XCR3128A device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 1.5 ns.
So the total pin-to-pin tPD for the XCR3128A using six to 37
product terms is 9 ns (7.5 ns for the PAL + 1.5 ns for the
PLA).
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
MC0
MC1
I/O
MC0
LOGIC
BLOCK
36
36
16
16
16
16
36
36
16
16
16
16
LOGIC
BLOCK
MC15
I/O
MC0
LOGIC
BLOCK
LOGIC
BLOCK
MC15
I/O
ZIA
LOGIC
BLOCK
36
16
16
16
16
36
36
16
16
16
16
LOGIC
BLOCK
MC1
I/O
MC15
MC0
I/O
I/O
MC0
36
MC15
MC1
MC1
MC15
MC0
MC1
I/O
MC15
MC0
MC1
MC1
MC0
LOGIC
BLOCK
MC15
LOGIC
BLOCK
MC1
I/O
MC15
SP00464
Figure 1: Xilinx XPLA CPLD Architecture
DS035 (v1.2) August 10, 2000
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
36 ZIA INPUTS
6
CONTROL
TO 16 MACROCELLS
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner XCR3128A. The macrocell can be configured as either a D- or T-type flip-flop or a combinatorial logic
function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of six sources. Four of the clock sources (CLK0, CLK1,
CLK2, CLK3) are connected to low-skew, device-wide clock
networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges.
Clock 0 (CLK0) is designated as a "synchronous" clock and
must be driven by an external source. Clock 1 (CLK1),
Clock 2 (CLK2), and Clock 3 (CLK3) can be used as "synchronous" clocks that are driven by an external source, or
as "asynchronous" clocks that are driven by a macrocell
equation. CLK0, CLK1, CLK2, and CLK3 can clock the
macrocell flip-flops on either the rising edge or the falling
edge of the clock signal. The other clock sources are two of
the six control terms (CT2 and CT3) provided in each logic
block. These clocks can be individually configured as either
a PRODUCT term or SUM term equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the
tCO time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the
clock network, and the tSU time is reduced.
The six control terms of each logic block are used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disable of the output buffers in each macrocell. Control terms CT0 and CT1 are used to control the asynchro-
nous Preset/Reset of the macrocell’s flip-flop. Note that the
Power-on Reset leaves all macrocells in the "zero" state
when power is properly applied, and that the Preset/Reset
feature for each macrocell can also be disabled. Control
terms CT2 and CT3 can be used as a clock signal to the
flip-flops of the macrocells, and as the Output Enable of the
macrocell’s output buffer. Control terms CT4 and CT5 can
be used to control the Output Enable of the macrocell’s output buffer. Having four dedicated Output Enable control
terms ensures that the CoolRunner devices are PCI compliant. The output buffers can also be always enabled or
always disabled. All CoolRunner devices also provide a
Global 3-state (GTS) pin, which, when enabled and pulled
Low, will 3-state all the outputs of the device. This pin is
provided to support "In-Circuit Testing" or "Bed-of-Nails"
testing.
There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin feedback path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the input signal will be fed
into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on Terminations in this data sheet and the application note Terminating Unused I/O Pins in Xilinx XPLA1
and XPLA2 CoolRunner CPLDs.
TO ZIA
PAL
D/T
INIT
(P or R)
GTS
GND
CT0
CT1
GND
CT2
CT3
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
Q
CT4
CT5
V CC
GND
PLA
SP00558
Figure 3: XCR3128A Macrocell Architecture
DS035 (v1.2) August 10, 2000
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Simple Timing Model
because the timing models of competing architectures are
very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other competing architectures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
INPUT PIN
INPUT PIN
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
D
Q
REGISTERED
tCO
OUTPUT PIN
OUTPUT PIN
GLOBAL CLOCK PIN
SP00553
Figure 4: CoolRunner Timing Model
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high-performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of the XCR3128A TotalCMOS CPLD (data
taken with eight up/down, loadable 16-bit counters at 3.3V,
25°C).
70
60
50
40
ICC
(mA)
30
20
10
0
1
20
40
60
80
100
FREQUENCY (MHz)
120
SP00617
Figure 5: ICC vs. Frequency @ VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz)
Typical ICC (mA)
0
0.03
DS035 (v1.2) August 10, 2000
1
0.7
20
12.7
40
25.5
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38.1
80
50.5
100
62.8
120
74.7
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
JTAG Testing Capability
JTAG is the commonly-used acronym for the
Boundary-scan Test (BST) feature defined for integrated
circuits by IEEE Standard 1149.1. This standard defines
input/output pins, logic control functions, and commands
which facilitate both board and device level testing without
the use of specialized test equipment. The Xilinx
XCR3128A devices use the JTAG Interface for In-System
Programming/Reprogramming. Although only a subset of
the full JTAG command set is implemented (see Table 2),
the devices are fully capable of sitting in a JTAG scan chain.
The Xilinx XCR3128A’s JTAG interface includes a TAP Port
defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx XCR3128A, the TAP Port includes four
of the five pins (refer to Table 3) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Xilinx XCR3128A
saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR3128A supports the test reset functionality through the use of its power-up reset circuit, which
is included in all Xilinx CPLDs. The pins associated with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG signals from floating when they are not
being used. In the Xilinx XCR3128A, the four mandatory
JTAG pins each require a unique, dedicated pin on the
device. The devices come from the factory with these I/O
pins set to perform JTAG functions, but through the software, the final function of these pins can be controlled. If
the end application will require the device to be reprogrammed at some future time with ISP, then the pins can be
left as dedicated JTAG functions, which means they are not
available for use as general purpose I/O pins. However,
unlike competing CPLDs, the Xilinx XCR3128A allow the
macrocells associated with these pins to be used as buried
logic when the JTAG/ISP function is enabled. This is the
default state for the software, and no action is required to
leave these pins enabled for the JTAG/ISP functions. If,
however, JTAG/ISP is not required in the end application,
the software can specify that this function be turned off and
that these pins be used as general purpose I/O. Because
the devices initially have the JTAG/ISP functions enabled,
the JEDEC file can be downloaded into the device once,
after which the JTAG/ISP pins will become general purpose
I/O. This feature is good for manufacturing because the
devices can be programmed during test and assembly of
the end product and yet still use all of the I/O pins after the
programming is done. It eliminates the need for a costly,
separate programming step in the manufacturing process.
Of course, if the JTAG/ISP function is never required, this
feature can be turned off in the software and the device can
be programmed with an industry-standard programmer,
leaving the pins available for I/O functions. Table 4 defines
the dedicated pins used by the four mandatory JTAG signals for each of the XCR3128A package types.
Table 2: XCR3128A Low-level JTAG Boundary-scan Commands
Instruction
(Instruction Code)
Register Used
Bypass
(1111)
Bypass Register
Idcode
(0001)
Boundary-scan Register
7
Description
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation. The Bypass instruction can be entered by holding TDI at a
constant high value and completing an Instruction-scan cycle.
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind
interrogation of the components assembled onto a printed circuit board. Thus, in
circumstances where the component population may vary, it is possible to determine
what components exist in a product.
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Table 3: JTAG Pin Description
Pin
TCK
Name
Test Clock Output
TMS
Test Mode Select
TDI
Test Data Input
TDO
Test Data Output
Description
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
Serial input pin selects the JTAG instruction mode. TMS should be driven High
during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is 3-stated if data is not being shifted out of the device.
Table 4: XCR3128A JTAG Pinout by Package Type
Device
XCR3128A
100-pin VQFP
128-pin TQFP
(Pin Number / Macrocell #)
TMS
TDI
15/C15
4/B15
21/C15
8/B15
TCK
62/F15
82/F15
3.3V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
•
•
Design
- Faster time-to-market
- Debug partitioning and simplified prototyping
- Printed circuit board reconfiguration during debug
- Better device and board level testing
Manufacturing
- Multi-functional hardware
- Reconfigurability for test
- Eliminates handling of "fine lead-pitch" components
for programming
- Reduced inventory and manufacturing costs
DS035 (v1.2) August 10, 2000
•
TDO
73/G15
95/G15
- Improved quality and reliability
Field Support
- Easy remote upgrades and repair
- Support for field configuration, reconfiguration, and
customization
The Xilinx XCR3128A allows for 3.3V in-system programming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally provided supervoltages, so that the XCR3128A
may be easily programmed on the circuit board using only
the 3V supply required by the device for normal operation.
A set of low-level ISP basic commands implemented in the
XCR3128A enable this feature. The ISP commands implemented in the Xilinx XCR3128A are specified in Table 5.
Please note that an ENABLE command must precede all
ISP commands unless an ENABLE command has already
been given for a preceding ISP command.
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Table 5: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
Verify
(ISP Shift Register)
Instruction Code
1001
Enables the Erase, Program, and Verify commands.
1010
Erases the entire EEPROM array.
1011
Programs the data in the ISP Shift Register into the addressed
EEPROM row.
Transfers the data from the addressed row to the ISP Shift
Register. .
1100
Terminations
The CoolRunner XCR3128A CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR3128A
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR3128A device be left
unconnected.
9
Description
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10kΩ
pull-up resistors. These pins can be directly connected to
VCC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recommended that 10kΩ pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Letting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the application notes JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs for more information.
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated circuits. The Xilinx XCR3128A supports the following methods:
•
•
PC parallel port
Workstation or PC serial port
•
•
•
•
Embedded Processor
Automated test equipment
Third party programmers
High-end ISP tools
For more details on JTAG and ISP for the XCR3128A, refer
to the related application note: JTAG and ISP Overview for
Xilinx XPLA1 and XPLA2 CPLDs
Table 6: Programming Specifications
Symbol
DC Parameters
VCCP
ICCP
VIH
VIL
VSOL
VSOH
TDO_IOL
TDO_IOH
AC Parameters
fMAX
PWE
PWP
PWV
INIT
TMS_SU
TDI_SU
TMS_H
TDI_H
TDO_CO
Parameter
VCC supply program/verify
Min.
Max.
Unit
3.0
3.6
V
200
mA
ICC limit program/verify
Input voltage (High)
Input voltage (Low)
Output voltage (Low)
Output voltage (High)
Output current (Low)
Output current (High)
2.0
10
100
10
10
100
10
10
25
25
MHz
ms
ms
µs
µs
ns
ns
ns
ns
0.8
0.5
CLK maximum frequency
Pulse width erase
Pulse width program
Pulse width verify
Initialization time
TMS setup time before TCK goes High
TDI setup time before TCK goes High
TMS hold time after TCK goes High
TDI hold time after TCK goes High
TDO valid after TCK goes Low
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2.4
8
-8
V
V
V
V
mA
mA
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Absolute Maximum Ratings1
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply voltage 2
-0.5
4.6
V
VI
Input voltage
-1.2
5.75
V
VOUT
Output voltage
-0.5
5.5
V
IIN
Input current
-30
30
mA
TJ
Maximum junction temperature
-40
150
°C
Tstr
Storage temperature
-65
150
°C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Commercial
Industrial
Temperature
0 to +70 °C
-40 to +85°C
Voltage
3.0 to 3.6 V
2.7 to 3.6 V
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
0.8
V
VIL
Input voltage Low
VCC = 3.0V
VIH
Input voltage High
VCC = 3.6V
VI
Input clamp voltage
VCC = 3.0V, IIN = -18 mA
-1.2
V
VOL
Output voltage Low
VCC = 3.0V, IOL = 12 mA
0.5
V
VOH
Output voltage High
VCC = 3.0V, IOH = -12 mA
2.4
II
Input leakage current
VIN = 0 to 5.5V
-10
10
µA
-10
10
µA
100
µA
IOZ
2.0
V
V
3-stated output leakage current
VIN = 0 to 5.5V
ICCQ
1
Standby current
VCC = 3.6V, TAMB = 0°C
ICCD
1, 2
Dynamic current
VCC = 3.6V, TAMB = 0°C @ 1 MHz
2
mA
VC = 3.6V, TAMB = 0°C @ 50 MHz
50
mA
-200
mA
8
pF
12
pF
10
pF
3
IOS
Short circuit output current
CIN
Input pin capacitance 3
TAMB = 25°C, f = 1 MHz
CCLK
Clock input capacitance 3
TAMB = 25°C, f = 1 MHz
CI/O
I/O pin capacitance
3
One pin at a time for no longer than one
second
TAMB = 25°C, f = 1 MHz
-50
5
Notes:
1. See Table 2 on page 7 typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
11
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 3.0V ≤ VCC ≤ 3.6V
Symbol
tPD_PAL
tPD_PLA
tCO
tSU_PAL
tSU_PLA
tH
tCH
tCL
tR
tF
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
tPDF_PLA
tCF
tINIT
tER
tEA
tRP
tRR
7
Parameter
Propagation delay time, input (or
feedback node) to output through PAL
Propagation delay time, input (or
feedback node) to output through PAL +
PLA
Clock to out (global synchronous clock
from pin)
Setup time (from input or feedback node)
through PAL
Setup time (from input or feedback node)
through PAL + PLA
Hold time 2
Clock High time 2
Clock Low time 2
Input rise time 2
Input fall time 2
Maximum FF toggle rate 2 1/(tCH + tCL)
Maximum internal frequency 2
1/(tSUPAL + tCF)
Maximum external frequency 2
1/(tSUPAL + tCO)
Output buffer delay time 2
Input (or feedback node) to internal
feedback node delay time through PAL 2
Input (or feedback node) to internal
feedback node delay time through
PAL+PLA 2
Clock to internal feedback node delay
time 2
Delay from valid V CC to valid reset 2
Input to output disable 2, 3
Input to output valid 2
Input to register preset 2
Input to register reset 2
10
12
Unit
Min.
2
Max.
7.5
Min.
2
Max.
10
Min.
2
Max.
12
ns
3
9
3
11.5
3
13.5
ns
2
5.5
2
7
2
8
ns
3.5
4
6
ns
5
5.5
7.5
ns
0
250
143
200
118
167
91
ns
ns
ns
ns
ns
MHz
MHz
111
91
71
MHz
2
2
0
2.5
2.5
100
100
2
2
5.5
3
7
0
3
3
100
100
2
2
7.5
3
9
100
100
2
2
8
ns
ns
3
9.5
ns
3.5
4.5
5
ns
20
8
8
9
9
20
9.5
9.5
9.5
9.5
20
10
10
10
10
µs
ns
ns
ns
ns
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 7 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
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R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 2.7V ≤ VCC ≤ 3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
0.8
V
VIL
Input voltage Low
VCC = 2.7V
VIH
Input voltage High
VCC = 3.6V
VI
Input clamp voltage
VCC = 2.7V, IIN = -18 mA
-1.2
V
VOL
Output voltage Low
VCC = 2.7V, IOL = 8 mA
0.5
V
VCC= 3.0V, IOL = 12 mA
0.5
V
VOH
Output voltage High
II
V
VCC = 2.7V, IOH = -8 mA
2.4
V
VCC = 3.0V, IOH = -12 mA
2.4
V
VIN = 0 to 5.5V
-10
10
µA
3-stated output leakage current VIN = 0 to 5.5V
-10
10
µA
100
µA
Input leakage current
IOZ
2.0
ICCQ
1
Standby current
VCC = 3.6V, TAMB = -40°C
ICCD
12
Dynamic current
VCC = 3.6V, TAMB = -40°C @ 1 MHz
2
mA
VCC = 3.6V, TAMB = -40°C @ 50 MHz
50
mA
-230
mA
8
pF
12
pF
10
pF
3
IOS
Short circuit output current
CIN
Input pin capacitance 3
TAMB = 25°C, f = 1 MHz
CCLK
Clock input capacitance 3
TAMB = 25°C, f = 1 MHz
CI/O
I/O pin capacitance
3
1 pin at a time for no longer than 1 second
TAMB = 25°C, f = 1 MHz
-50
5
Notes:
1. See Table 1 on page 6 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
13
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XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
AC Electrical Characteristics1 For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 2.7V ≤ VCC ≤ 3.6V
Symbol
10
Parameter
15
Min.
Max.
Min.
Max.
Unit
tPD_PAL
Propagation delay time, input (or feedback node) to output through PAL
2
10
2
15
ns
tPD_PLA
Propagation delay time, input (or feedback node) to output through PAL + PLA
3
11.5
3
16.5
ns
tCO
Clock to out (global synchronous clock from pin)
2
7
2
8
ns
tSU_PAL
Setup time (from input or feedback node) through PAL
4
6
ns
tSU_PLA
Setup time (from input or feedback node) through
PAL + PLA
5.5
7.5
ns
tH
Hold time
tCH
Clock High time
3
4
ns
tCL
Clock Low time
3
4
ns
tR
Input rise time
tF
Input fall time
fMAX1
fMAX2
0
Maximum FF toggle rate
2
1/(tCH + tCL)
Maximum internal frequency
2
1/(t SUPAL + tCF)
2
100
ns
100
100
ns
167
125
MHz
111
87
MHz
91
77
MHz
Maximum external frequency
tBUF
Output buffer delay time 2
tPDF_PAL
Input (or feedback node) to internal feedback node delay
time through PAL 2
2
8
tPDF_PLA
Input (or feedback node) to internal feedback node delay
time through PAL+PLA 2
3
9.5
tCF
Clock to internal feedback node delay time 2
tINIT
Input to output disable
tEA
Input to output valid 2
tRP
Input to register preset 2
Input to register reset
2
2, 3
tER
tRR
2
Delay from valid VCC to valid reset
ns
100
fMAX3
1/(t SUPAL + tCO)
0
2
2
ns
2
9
ns
3
10.5
ns
5
5.5
ns
20
20
µs
10
12
ns
10
12
ns
10
12
ns
10
12
ns
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 7 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
DS035 (v1.2) August 10, 2000
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R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Switching Characteristics
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VDD
Component
S1
R1
Values
R1
390Ω
R2
390Ω
C1
35 pF
VIN
VOUT
Measurement
R2
C1
S2
S1
S2
tPZH
Open
Closed
tPZL
Closed
Open
tP
Closed
Closed
NOTE: For tPHZ and tPLZ C = 5 pF, and 3-state levels are
measured 0.5V from steady state active level.
SP00699
VDD = 3.3V, 25°C
6.1
+3.0V
90%
6.0
5.9
10%
0V
5.8
tPD_PAL
(ns)
tF
tR
5.7
1.5ns
1.5ns
5.6
SP00368
5.5
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
5.4
Input Pulses
5.3
Figure 7: Voltage Waveform
5.2
5.1
1
2
4
8
12
16
NUMBER OF OUTPUTS SWITCHING
Table 7: tPD_PAL vs. Number of Outputs Switching
(VCC = 3.3 V, T = 25°C)
SP00698
Figure 6: tPD_PAL vs. Outputs Switching
15
Number of
Outputs
Typical (ns)
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1
2
4
8
12
16
5.3
5.3
5.4
5.6
5.9
6.1
DS035 (v1.2) August 10, 2000
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Pin Function and Laynout
XCR3128A: 100-pin VQFP, and 128-pin TQFP Pin Function Table
Pin
#
Function
100-pin
128-pin
VQFP
TQFP
Pin
#
1
I/O-A2
I/O-A3
33
Function
100-pin
128-pin
VQFP
TQFP
I/O-D5
Pin
#
NC
65
Function
100-pin
128-pin
VQFP
TQFP
I/O-G4
I/O-E15
Pin
#
97
Function
100-pin
128-pin
VQFP
TQFP
I/O-A8
NC
2
I/O-A0
I/O-A2
34
VCC
NC
66
VCC
VCC
98
I/O-A7
NC
3
VCC
I/O-A0
35
I/O-D4
NC
67
I/O-G5
I/O-F0
99
I/O-A5
NC
4
I/O-B15 (TDI)
NC
36
I/O-D2
I/O-C0
68
I/O-G7
NC
100
I/O-A4
I/O-H0
5
I/O-B13
NC
37
I/O-D0/CLK2
GND
69
I/O-G8
NC
101
-
I/O-H2
6
I/O-B12
NC
38
GND
I/O-D15
70
I/O-G10
NC
102
-
I/O-H3
7
I/O-B10
VCC
39
VCC
I/O-D13
71
I/O-G12
I/O-F2
103
-
I/O-H4
8
I/O-B8
I/O-B15 (TDI)
40
I/O-E0/
CLK1
I/O-D12
72
I/O-G13
I/O-F3
104
-
I/O-H5
9
I/O-B7
I/O-B13
41
I/O-E2
I/O-D11
73
I/O-G15
(TDO)
I/O-F4
105
-
I/O-H7
10
I/O-B5
I/O-B12
42
I/O-E4
I/O-D10
74
GND
I/O-F5
106
-
I/O-H8
11
GND
I/O-B11
43
GND
I/O-D8
75
I/O-H0
I/O-F7
107
-
I/O-H10
12
I/O-B4
I/O-B10
44
I/O-E5
I/O-D7
76
I/O-H2
I/O-F8
108
-
VCC
13
I/O-B2
I/O-B8
45
I/O-E7
I/O-D5
77
I/O-H4
I/O-F10
109
-
I/O-H11
14
I/O-B0
I/O-B7
46
I/O-E8
VCC
78
I/O-H5
GND
110
-
I/O-H12
15
I/O-C15
(TMS)
I/O-B5
47
I/O-E10
I/O-D4
79
I/O-H7
I/O-F11
111
-
I/O-H13
16
I/O-C13
GND
48
I/O-E12
I/O-D3
80
I/O-H8
I/O-F12
112
-
I/O-H15
17
I/O-C12
I/O-B4
49
I/O-E13
I/O-D2
81
I/O-H10
I/O-F13
113
-
GND
18
VCC
I/O-B3
50
I/O-E15
I/O-D0/CLK2
82
VCC
I/O-F15
(TCK)
114
-
IN0/CLK0
19
I/O-C10
I/O-B2
51
VCC
GND
83
I/O-H12
I/O-G0
115
-
IN2/gtsn
20
I/O-C8
I/O-B0
52
I/O-F0
VCC
84
I/O-H13
I/O-G2
116
-
IN1
21
I/O-C7
I/O-C15
(TMS)
53
I/O-F2
I/O-E0/
CLK1
85
I/O-H15
I/O-G3
117
-
IN3
22
I/O-C5
I/O-C13
54
I/O-F4
I/O-E2
86
GND
I/O-G4
118
-
VCC
23
I/O-C4
I/O-C12
55
I/O-F5
I/O-E3
87
IN0/CLK0
VCC
119
-
I/O-A15/
CLK3
24
I/O-C2
I/O-C11
56
I/O-F7
I/O-E4
88
IN2/gtsn
I/O-G5
120
-
I/O-A13
25
I/O-C0
VCC
57
I/O-F8
GND
89
IN1
I/O-G7
121
-
I/O-A12
26
GND
I/O-C10
58
I/O-F10
I/O-E5
90
IN3
I/O-G8
122
-
I/O-A12
27
I/O-D15
I/O-C8
59
GND
I/O-E7
91
VCC
I/O-G10
123
-
GND
28
I/O-D13
I/O-C7
60
I/O-F12
I/O-E8
92
I/O-A15/CLK3
I/O-G11
124
-
I/O-A10
29
I/O-D12
I/O-C5
61
I/O-F13
I/O-E10
93
I/O-A13
I/O-G12
125
-
I/O-A8
30
I/O-D10
I/O-C4
62
I/O-F15
(TCK)
I/O-E11
94
I/O-A12
I/O-G13
126
-
I/O-A7
31
I/O-D8
I/O-C3
63
I/O-G0
I/O-E12
95
GND
I/O-G15
(TDO)
127
-
I/O-A5
32
I/O-D7
I/O-C2
64
I/O-G2
I/O-E13
96
I/O-A10
GND
128
-
I/O-A4
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R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
100-pin VQFP
128-pin TQFP
100
103
128
76
102
1
75
1
VQFP
TQFP
TQFP
LQFP
25
51
65
38
26
50
64
39
SP00485A
SP00469B
Ordering Information
Example: XCR3128A -7 VQ 100 C
Temperature Range
Device Type
Number of Pins
Speed Options
Package Type
Temperature Range
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
Speed Options
-15: 15 ns pin-to-pin delay
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
-7: 7.5 ns pin-to-pin delay
Packaging Options
VQ100: 100-pin VQFP
TQ128: 128-pin TQFP
Component Availability
Pins
Type
Code
XCR3128A
-15
-12
-10
-7
100
Plastic VQFP
VQ100
I
C
C, I
C
128
Plastic TQFP
TQ128
I
C
C, I
C
Revision History
Date
7/22/99
2/10/00
8/10/00
17
Version #
1.0
1.1
1.2
Revision
Initial Xilinx release
Converted to Xilinx format and updated.
Updated pinout table.
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