ETC YSS902-F

YSS902
AC3D
Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP
INTRODUCTION
The YSS902 is one chip LSI consisting of two built-in DSP’s ; Dolby Digital (AC-3) / Pro Logic (Main DSP) and a
sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by
down-loading the program and coefficient.
FEATURERS
Dolby Digital 5.1 channel full decode.
24 bit DSP. (Group-A Dolby Digital decoder)
No external memory is required. (Memories for center and surround channel delay are included)
Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
AC-3 karaoke mode.
Original compression modes as well as four compression modes recommended by Dolby.
Dolby Digital decoding latency is fixed to two audio blocks (512 samples).
Included de-emphasis filter.
Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM.
High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original
surround, filtering, virtual surround etc.
Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)
Reads Dolby Digital decode information through the microprocessor interface.
Provide total sixteen I/O ports.
Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
Has a built-in PLL oscillation circuit to generates its own operating clock.
Internal operating clock is 25MHz.
Supply Voltage: 3.3v for core logic. 5v for I/Os.
Power saving mode.
Si-gate CMOS process.
100 QFP.(YSS902-F)
Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation.
Use of this LSI must be licensed by Dolby Laboratories Licensing Corporation.
YSS902 CATALOG
CATALOG No.:LSI-4SS902A4
1999. 7
YSS902
PIN CONFIGURATION
2
YSS902
PIN FUNCTION
No.
Name
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
VDD1
RAMCEN
RAMA16
RAMA15
SDIB0
SDIB1
SDIB2
XI
XO
VSS
AVDD
TEST
TEST
TEST
OVFB
TEST
TEST
TEST
CPO
AVSS
VDD2
SDOA2
SDOA1
SDOA0
RAMA14
RAMA13
RAMA12
RAMA11
RAMA10
VSS
VDD1
OPORT0
OPORT1
OPORT2
OPORT3
OPORT4
OPORT5
OPORT6
OPORT7
VSS
VDD2
RAMA9
RAMA8
RAMA7
SDOB2
SDOB1
SDOB0
SDBCK1
SDWCK1
VSS
VDD2
NONPCM
CRC
MUTE
KARAOKE
O
O
O
I+
I+
I+
I
O
-
+5V power supply (for I/Os)
External SRAM interface /CE
External SRAM interface address 16
External SRAM interface address 15
PCM input 0 to Sub DSP
PCM input 1 to Sub DSP
PCM input 2 to Sub DSP
Crystal oscillator connection (6.125MHz - 50.0MHz)
Crystal oscillator connection
Ground
+3.3 V power supply (for PLL circuit)
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Detection of overflow at Sub DSP
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Output terminal for PLL, to be connected to ground through the external analog filter circuit
Ground (for PLL circuit)
+3.3 V power supply (for core logic)
PCM output from Main DSP (C, LFE)
PCM output from Main DSP (LS, RS )
PCM output from Main DSP (L, R)
External SRAM interface address 14
External SRAM interface address 13
External SRAM interface address 12
External SRAM interface address 11
External SRAM interface address 10
Ground
+5V power supply (for I/Os)
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Ground
+3.3 V power supply (for core logic)
External SRAM interface address 9
External SRAM interface address 8
External SRAM interface address 7
PCM output from Sub DSP
PCM output from Sub DSP
PCM output from Sub DSP
Bit clock input for SDOA, SDIB, SDOB
Word clock input for SDOA, SDIB, SDOB
Ground
+3.3 V power supply (for core logic)
Detection of non-PCM data
Detection of CRC error
Detection of auto mute
Detection of AC-3 karaoke data
O
A
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I+
I+
O
O
O
O
3
YSS902
No.
Name
56
SURENC
57 /SDBCK0
58
RAMA6
59
RAMA5
60
VSS
61
RAMA4
62
/IC
63
TEST
64
RAMA3
65
/CSB
66
/CS
67
SO
68
SI
69
SCK
70
RAMA2
71
VDD1
72
RAMD0
73
RAMD1
74
RAMD2
75
RAMD3
76
RAMD4
77
RAMD5
78
RAMD6
79
RAMD7
80
VSS
81
VDD2
82 SDWCK0
83
SDBCK0
84
SDIA0
85
SDIA1
86
RAMA1
87
RAMA0
88 RAMWEN
89 RAMOEN
90
VSS
91
VDD2
92
IPORT7
93
IPORT6
94
IPORT5
95
IPORT4
96
IPORT3
97
IPORT2
98
IPORT1
99
IPORT0
100
VSS
NOTE) Is:
I+:
O:
Ot:
A:
4
I/O
O
O
O
O
O
Is
O
Is+
Is
Ot
Is
Is
O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I
I
I
I
O
O
O
O
I+
I+
I+
I+
I+
I+
I+
I+
-
FUNCTION
Detection of AC-3 2/0 mode Dolby surround encoded input
Inverted SDBCK0 clock output (refer to Block diagram)
External SRAM interface address 6
External SRAM interface address 5
Ground
External SRAM interface address 4
Initial clear
Test terminal (to be open in normal use)
External SRAM interface address 3
Sub DSP Chip select
Microprocessor interface Chip select input
Microprocessor interface Serial data output
Microprocessor interface / Sub DSP Serial data input
Microprocessor interface / Sub DSP clock input
External SRAM interface address 2
+5V power supply (for I/Os)
External SRAM interface data (STREAM0 output when External SRAM is not in use)
External SRAM interface data (STREAM1 output when External SRAM is not in use)
External SRAM interface data (STREAM2 output when External SRAM is not in use)
External SRAM interface data (STREAM3 output when External SRAM is not in use)
External SRAM interface data (STREAM4 output when External SRAM is not in use)
External SRAM interface data (STREAM5 output when External SRAM is not in use)
External SRAM interface data (STREAM6 output when External SRAM is not in use)
External SRAM interface data (STREAM7 output when External SRAM is not in use)
Ground
+3.3 V power supply (for core logic)
Word clock input for SDIA, SDOA, SDIB, SDOB
Bit clock input for SDIA, SDOA, SDIB, SDOB
AC-3 bitstream (or PCM) data input for Main DSP
AC-3 bitstream (or PCM) data input for Main DSP
External SRAM interface address 1
External SRAM interface address 0
External SRAM interface /WE
External SRAM interface /OE
Ground
+3.3 V power supply (for core logic)
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Ground
Schmidt trigger input terminal
Input terminal with a pull-up resistor
Digital output terminal
Tri-state digital output terminal
Analog terminal
IPORT0 - 7
SDIA Interface
SDIBSEL
ERAMUSE
External RAM
interface
SDIB Interface
AC-3/Pro Logic
decoder
PLL
24 * 24
Main DSP
Delay RAM
SDIBCKSEL
SDOBCKSEL
Data RAM
SDOB Interface
(25MHz)
C, LFE
LS, RS
L, R
SDOACKSEL
24 * 16
Sub DSP
Operating clock
STREAM0 - 7
Input Buffer
SURENC
KARAOKE
MUTE
CRC
NONPCM
/CS
SDIA1
SO
Control Registers
OPORT0 - 7
SDIA0
SI
SDBCK0
SDWCK0
SCK
/SDBCK0
Control signals
SI
Control signals
SCK
Coefficient/
Program RAM
/CSB
Microprocessor
Interface
SDOB2
SDOB1
SDOB0
SDBCK1
SDWCK1
YSS902
BLOCK DIAGRAM
OVFB
RAMA0 - 16
RAMOEN
RAMWEN
RAMCEN
RAMD0 - 7
SDIB2
SDIB1
SDIB0
SDOA2
SDOA1
SDOA0
SDOA Interface
CPO
XO
XI
CRC
SDIASEL
5
YSS902
FUNCTION DESCRIPTION
The YSS902 consist of Main DSP section where AC-3/Pro Logic decoding is executed and Sub DSP section
where various sound field effects are added. Please refer to “BLOCK DIAGRAM” section.
Sub DSP is a 6 ch input / 6 ch output programmable DSP exclusively for the sound field processing. It can apply
such effects as virtual surround, echo and equalizing. In addition, with an SRAM up to 1Mbit connected, it can
produce reverberation for one second or longer. By using this function, it is possible to simulate various sound
fields such as a hall or a church.
* If adopting some technology owned by another company is desired for use in Sub DSP section, note that a
separate contract may be required between the owner of that technology and the user with respect to adoption of the
technology.
1. Clocks
XI, XO, CPO
The crystal oscillation circuit is formed by using XI and XO terminals. Oscillation frequency 50MHz is divided by
2 internally to provide the operating clock signals of 25MHz.
Clock signals should be obtained through self oscillation by using XI and XO terminals, or external clock signals
should be fed through the XI terminal.
This LSI operates in a PLL oscillation mode as well. When the PLL oscillation mode is selected and an external
clock signal whose frequency is lower than 49MHz is fed through the XI terminal and multiplied, connect an
external analog filter between CPO terminal and Ground.
2. Data Interface
SDIA0, SDIA1, SDOA0-2, SDIB0-2, SDOB0-2, SDWCK0, SDBCK0, SDWCK1,
SDBCK1, /SDBCK0
Main DSP section
AC-3 bitstream or PCM data should be fed from SDIA0 or SDIA1 terminal. These signals are processed by AC-3
/ Pro Logic decoding procedure in Main DSP section and then transmitted to Sub DSP section as well as
outputted through SDOA0-2 terminals.
Sub DSP section
In Sub DSP section, various types of processing can be applied to the PCM data decoded in Main DSP section or
inputted through SDIB0-2 terminals. Then, processed signals are outputted from each of SDOB0-2 terminals.
Following parameters can be selected by changing the control register setting.
Selection of Main DSP input signal (SDIA0, SDIA1)
Selection of Sub DSP input signal (Main DSP output, SDIB0-2 input)
Polarity of bit clock and word clock
Format and bit count of input/output data
For more information on the format of the input/output data, please refer to “Serial Data Interface” section.
.
.
.
.
3. Microprocessor Interface
/CS, /CSB, SCK, SI, SO
The control registers can be read/written via the serial microprocessor interface by using /CS, SCK, SI, and SO
terminals.
Please refer to the following format diagram for the details of read/write timing.
6
YSS902
Format diagram for read/write timing
When /CS=1, the SO output becomes high-impedance.
* Be sure to set /CSB to “1” when making an access to the control register.
The sound field processing program used for Sub DSP is down-loaded by using the /CSB, SCK, and SI terminals.
Please refer to Application manual for the details of Sub DSP.
4. External Interface
RAMA0-16, RAMD0-7, RAMCEN, RAMOEN, RAMWEN
An external SRAM can be connected to Sub DSP.
5. General purpose I/O ports
OPORT0-7, IPORT0-7
OPORT0-7 terminals are output ports for general purpose. Data written on the register (address 0x04) are outputted
from these terminals.
IPORT0-7 terminals are input ports for general purpose. Data inputted to these terminals can be read from the
register (address 0x05).
6. Initial clear
/IC
This LSI requires initial clear when turning on the power.
7. LSI test terminals
TEST
Leave the test terminals open in normal use.
7
YSS902
CONTROL REGISTER
The decoding system is controlled by reading and writing the control registers through microprocessor interface.
(/CS, SCK, SI and SO)
Note: All bits are set to “0” by initial clear (/IC=0) except for PLL0(bit 4) of PLL/DSN register (0x00).
address
Name
bit 7
bit 6
bit 5
bit 4
bit 3
0x00
0x01
0x02
0x03
0x04
0x05
PLL/DSN Register
Mute Register
SDIA Register
SDOA Register
OPORT Register
IPORT Register
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
Noise Level Register
NOISELEV7 - 0
Center Delay Register
Surround Delay Register
Noise Register
NOISE
PN/WN
FS Register
L Volume Register
LVOL7 - 0
C Volume Register
CVOL7 - 0
R Volume Register
RVOL7 - 0
LS Volume Register
LSVOL7 - 0
RS Volume Register
RSVOL7 - 0
LFE Volume Register
LFEVOL7 - 0
Compression Register
EMPON
AIBON
VOLON DITHOFF P11OFF
HDYNRNG Register
HDYNRNG7 - 0
LDYNRNG Register
LDYNRNG7 - 0
Mode Register
AC3/PCM PLDECON PLSRMOD
DUALMOD1 - 0
0x30
0x31
0x32
0x33
0x34
0x35
0x36
COEF0-H Register
COEF0-L Register
COEF1-H Register
COEF1-L Register
SDIB Register
SDOB Register
ERAM Register
bit 2
bit 1
PLLUSE
LMUTEN
SDIASEL
PLL2-0
DSNIGN
CMUTEN RMUTEN RSMUTEN LSMUTEN LFEMUTEN
PDOWN
SDIAFMT1 - 0
SDIABIT1 - 0
SDOACKSEL
SDOAFMT1 - 0
SDOABIT1 - 0
OPORT7 - 0
IPORT7 - 0 (Read only)
SDIBCKSEL SDIBSEL
SDOBCKSEL SDBUSE
ERAMUSE
bit 0
DSN2 - 0
AMOFF
SDIAWP SDIABP
SDOAWP SDOABP
DSPMUTEN
CDELAY2 - 0
SRDELAY3 - 0
FS1 - 0
DIALOFF
COMPMOD1 - 0
OUTMOD2 - 0
COEF0-15 - 8
COEF0-7 - 0
COEF1-15 - 8
COEF1-7 - 0
SDIBFMT1 - 0
SDIBBIT1 - 0
SDOBFMT1 - 0
SDOBBIT1 - 0
SDIBWP
SDOBWP
SDIBBP
SDOBBP
Note : Do not write "1" into the cross-hatched bits because they are used for testing the LSI.
The following registers of address 0x18 to 0x2F are read-only (write disabled).
address
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
8
Name
Bitstream Register 0
Bitstream Register 1
Bitstream Register 2
Bitstream Register 3
Bitstream Register 4
Bitstream Register 5
Bitstream Register 6
Bitstream Register 7
Bitstream Register 8
Bitstream Register 9
Bitstream Register 10
Bitstream Register 11
Bitstream Register 12
Bitstream Register 13
bit 7
bit 6
bit 5
bit 4
bit 3
fscod
bit 2
bit 1
bit 0
frmsizecod
bsid
acmod
dsurmod
0
0
0
0
audprodie
audprodi2e
timecod1e
0
copyrightb
0
0
cmixlev
origbs
0
mixlevel
mixlevel2
bsmod
surmixlev
lfeon
0
0
0
dialnorm
dialnorm2
roomtyp
roomtyp2
timecod1
timecod1
timecod2e
langcode
0
langcod2e
timecod2
compre
timecod2
compr2e
0
langcod
0
0
0
YSS902
(Registermap continued)
address
Name
0x26 Bitstream Register 14
0x27 Bitstream Register 15
0x28 Bitstream Register 16
0x29 Bitstream Register 17
0x2A Bitstream Register 18
0x2B
(not used)
0x2C
0x2D
0x2E Data Stream Register
0x2F Status Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
langcod2
compr
compr2
dynrng
dynrng2
(write disable, all “0” out when read)
STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0
0
0
2/0MODE SURENC KARAOKE MUTE
CRC
NONPCM
Address 0x06 to 0x08 and 0x37 to 0x7F are assigned for TEST. Never access to these registers.
Please refer to Application manual for details of Control register.
SERIAL DATA INTERFACE
Data timing of the serial data interface is as follows.
Please refer to Application manual for details of SDIA, SDOA, SDIB, and SDOB registers.
9
YSS902
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Symbol
VDD1
VDD2, AVDD
VI
Tstg
Min.
Max.
Vss-0.5 Vss+7.0
Vss-0.5 VSS+4.6
Vss-0.5 VDD1+0.5
-50
125
Unit
V
V
V
C
2. Recommended Operating Conditions
Parameter
Power Supply Voltage
Operating Temperature
Symbol
Min.
Typ.
Max.
Unit
VDD1
VDD2, AVDD
TOP
4.75
3.0
0
5.0
3.3
25
5.25
3.6
70
V
V
C
3. DC Characteristics (Condition: Under Recommended Operating Conditions)
Parameter
Symbol
Condition
Min.
Input Voltage H Level (1)
Input Voltage H Level (2)
Input Voltage L Level (1)
Input Voltage L Level (2)
Output Voltage H Level
Output Voltage L Level
Input Leakage Current
VIH1
VIH2
VIL1
VIL2
VOH
VOL
ILI
*1
*2
*1
*2
IOH = -80 mA
IOL = 1.6 mA
Terminal without a pull-up
resistor
0.7VDD1
2.2
Pull-up Resistor
RU
Power Consumption
PD
*1
*2
Typ.
Max.
Unit
-10
0.4
10
V
V
V
V
V
V
mA
25
100
kW
120
230
150
350
mW
mW
Min
Typ
Max
Unit
6.125
40
50
50
60
MHz
%
0.2VDD1
0.8
VDD1-1.0
XI=50MHz, PLL not used
VDD1 (5V)
VDD2 (3.3V)
Applicable to XI and /IC input terminals.
Applicable to input terminals except XI and /IC terminals.
4. XI
Parameter
XI clock frequency
XI clock duty
10
Symbol
Xin
Xduty
Conditions
YSS902
EXTERNAL DIMENSIONS
C-PK100FP-1
24.80
0.40
20.00
0.30
0.15
0.05
(LEAD THICKNESS)
51
80
50
100
31
1
18.80 0.40
14.00 0.30
81
30
0.30
0.10
2.95 MAX.
P-0.65TYP
(2.40)
0 MIN.
(STAND OFF)
0-15
1.20 0.20
The figure in the parenthesis ( )
should be used as a reference.
Plastic body dimensions do not
include burr of resin.
UNIT: mm
11
YSS902
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document
without notice. The information contained in this document has been carefully checked
and is believed to be reliable. However, Yamaha assumes no responsibilities for
inaccuracies and makes no commitment to update or to keep current the information
contained in this document.
2. These Yamaha Products are designed only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support
equipment, nuclear facilities, critical care equipment or any other application the failure
of which could lead to death, personal injury or environmental or property damage. Use
of the Products in any such application is at the customer’s sole risk and expense.
3. Yamaha assumes no liability for incidental , consequential, or special damages or injury
that may result from misapplication or improper use or operation of the Products.
4. Yamaha makes no warranty or representation that the Products are subject to
intellectual property license from Yamaha or any third party, and Yamaha makes no
warranty excludes any liability to the Customer or any third party arising from or related
to the Products’ infringement of any third party’s intellectual property rights, including
the patent, copyright, trademark or trade secret rights of any third party.
5. Examples of use described herein are merely to indicate the characteristics and
performance of Yamaha products. Yamaha assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the
examples described herein. Yamaha makes no warranty with respect to the products,
express or implied, including, but not limited to the warranties of merchantability, fitness
for a particular use and title.
The specifications of this product are subject to improvement changes without prior notice.
AGENCY
Address inquiries to:
Semiconductor Sales & Marketing Department
Head Office
Tokyo Office
Osaka Office
U.S.A. Office
All rights reserved  1999
203, Matsunokijima, Toyooka-mura
Iwata-gun, Shizuoka-ken, 438-0192
Electronic Equipment Business section
Tel. 81-539-62-4918
Fax. 81-539-62-5054
2-17-11, Takanawa, Minato-ku,
Tokyo, 108-8568
Tel. 81-3-5488-5431
Fax. 81-3-5488-5088
Namba Tsujimoto Nissei Bldg, 4F
1-13-17, Namba Naka, Naniwa-ku,
Osaka City, Osaka, 556-0011
Tel. 81-6-6633-3690
Fax. 81-6-6633-3691
YAMAHA Systems Technology.
100 Century Center Court, San Jose, CA95112
Tel. 1-408-467-2300
Fax. 1-408-437-8791
Printed in Japan