Z86193 CPS DC-4206-01 P R E L I M I N A R Y PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z86193 CMOS Z8® MICROCONTROLLER MULTIPLIER/DIVIDER/SEARCH/MERGE GENERAL DESCRIPTION The Z86193 is a CMOS ROMless Z8® microcontroller enhanced with a hardwired 16-bit x 16-bit multiplier, 32-bit/16-bit divider, three 16-bit counter/timers, search and merge instructions, Evaluation mode and a Bus Request mode. The device is code compatible with other Z8 family devices, yet it offers more powerful mathematical capabilities, data searching capabilities, and bit manipulation. The Z86193 is offered in a 64-pin VQFP package. The Z86193 provides up to 16 output address lines permitting an address space of up to 64 Kbytes each of Program or Data memory. Eight address outputs are provided by a de-multiplexed 8-bit Address Bus (A7-A0) or by a multiplexed 8-bit Address/Data Bus (AD7-AD0). The remaining eight address lines (A15-A8) can be provided by the software configuration of Port0 to output address. The Z86193 includes a bus which differs from other Z8 devices. The Z86193 provides bus control signals /RD (Read Strobe), /WR (Write Strobe), and ALE (Address Latch Enable). DC-4206-01 (2-3-95) There are 464 8-bit registers located on-chip and organized as 444 general-purpose registers, 16 control and status registers, one reserved register, and up to three I/O port registers. The Register File is partitioned into two Register Pages. Page0 contains 208 registers and Page1 contains 208 registers. The 48 other registers are common to both Register Pages. The Register file is also divided into 29 working register groups of 16 registers each. Configuration of the registers in this format allows the use of short format instructions. There are 17 additional registers implemented in the Expanded Register file in Banks D and E. Two of the registers may be used as general-purpose, while the other 15 are used to supply data and control for the multiplier/divider unit and the additional counter/timers. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VSS VDD 1 Z86193 CPS DC-4206-01 P R E L I M I N A R Y Output Input 16 x 16 Multiplier EVAL /BACK /BREQ /WAIT /SYNC IACK SCLK /RESET /WR Machine Timing, Emulation and Instruction Control UART 32 ÷ 16 Divider /RD VCC GND Port 3 Three 16-Bit Counter/Timers ALE XTAL GENERAL DESCRIPTION (Continued) ALU FLAGS Register Pointers Register File Page 0 256 x 8-Bit Register File Page 1 208 x 8-Bit Program Counter SEARCH Machine MERGE Machine Interrupt Control Port 2 Demultiplexed Address Port 0 4 I/O (Bit Programmable) Low Address Port 1 4 Address or I/O (Nibble Programmable) Z86193 Functional Block Diagram 2 8 Low Address/Data Z86193 CPS DC-4206-01 P R E L I M I N A R Y /BACK P14/AD4 A4 P13/AD3 A3 P12/AD2 A2 P11/AD1 A1 P10/AD0 A0 P07/A15 P06/A14 P05/A13 P04/A12 P03/A11 P01/A9 P02/A10 /BREQ N/C P32 P00/A8 IACK /SYNC P35 VCC GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 Z86193 24 57 VQFP 23 58 22 59 21 60 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/C /RESET /WR /RD ALE N/C N/C P25 P26 P27 P31 P36 GND VCC XTAL2 XTAL1 SCLK P37 P30 /EVAL N/C P33 P34//DM A7 P17//AD7 A6 P16/AD6 A5 P15/AD5 N/C /WAIT P24 P23 P22 P21 GND P20 PIN CONFIGURATION 64-Pin VQFP Package 3 Z86193 CPS DC-4206-01 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA –0.3 –65 † +7.0 +150 † V C C Supply Voltage* Storage Temp Oper Ambient Temp * Voltages on all pins with respect to GND. † See Ordering Information Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). I OL DUT Device Under Test V Commutation 50 pf I OH Test Load Diagram 4 Z86193 CPS DC-4206-01 P R E L I M I N A R Y DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% Min T A = 0 °C to +70 °C Max Sym Parameter VCH VCL VIH VIH VIL Max Input Voltage Clock Input High Voltage 3.8 Clock Input Low Voltage –0.03 Input High Voltage (P0,P1,P2) 2.0 Input High Voltage (P3) 2.2 Input Low Voltage –0.3 VOH VOH VOL VRH VRl Output High Voltge 2.4 Output High Voltage VCC –100mV Output Low Voltage Reset Input High Voltage 3.8 Reset Input Low Voltage –0.03 IIL IOL IIR ICC Input Leakage Output Leakage Reset Input Current Supply Current ICC1 ICC2 IAL Standby Current (HALT Mode) Standby Current Auto Latch Current –16 –2 –2 Typical @ 25 °C U n i t s Conditions 7 VCC 0.8 VCC VCC 0.8 V V V V V V IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator 0.4 VCC 0.8 V V V V V IOH= –2.0 mA IOH = –100 µA IOL = + 4 mA 2 2 –180 120 70 µA µA µA mA Test at 0V, VCC Test at 0V, VCC VRL = 0V @ 40 MHz [1] 30 20 16 20 6 5 mA µA µA HALT Mode VIN = OV, VCC @ 40 MHz [1] STOP Mode VIN = OV, VCC [1] Note: [1] All inputs driven to 0V, or Vcc and outputs floating. [2] Values are preliminary engineering estimates. 5 Z86193 CPS DC-4206-01 P R E L I M I N A R Y AC CHARACTERISTICS External Memory Read/Write Timing Diagram /DM 20 19 Port 0 A8 - A15 21 16 Port 1 D0 - D7 IN A0 - A7 A0 - A7 9 2 3 ALE 10 11 8 4 5 6 /RD 1 Port1 17 D0 - D7 OUT A0 - A7 14 15 7 /WR External I/O or Memory Read/Write Timing Diagram 6 A0-A7 Z86193 CPS DC-4206-01 P R E L I M I N A R Y AC CHARACTERISTICS External I/O or Memory Read/Write Timing Table No Sym Parameter Max 1 2 3 4 TdA(ALE) ThALE(A) TdALE(DI) TwALE Address Valid To ALE Fall Delay ALE Fall To Address Hold Time ALE Fall To Data In Req’d Valid Delay ALE HIGH Width 8 15 5 6 7 8 TdAZ(RD) TwRD TwWR TdRD(DI) Address Float To /RD Fall /RD Low Width /WR Low Width /RD Fall To Data in Req'd Valid Delay 0 60 35 9 10 11 14 ThRD(DI) TdRDWR(A) TdRDWR(ALE) TdDO(WR) /RD Rise to Data In Hold Time /RD or /WR Rise To Address Active Delay /RD or /WR Rise To ALE Delay Data Out To /WR Fall Delay 0 20 16 12 15 16 17 19 ThWR(DO) TdA(DI) TdALE(RD) TdDM(ALE) /WR Rise To Data Out Hold Time Address Valid To Data In Req’d Valid Delay ALE Fall To /RD Fall Delay /DM Valid To ALE Fall Delay 12 20 21 22 TdRDWR(DM) ThRDWR(A) TdXT(SCR) /RD or /WR Rise To /DM Valid Delay /RD or /WR Rise To Adress Valid Hold Time XTAL Falling To SCLK Rising 23 24 25 TdXT(SCF) TdXT(RDF) TdXT(RDR) 26 Max 75 10 40 Units ns ns ns ns ns ns ns ns ns ns ns ns 90 20 10 15 15 ns ns ns ns 30 ns ns ns XTAL Falling To SCLK Falling XTAL Falling To /RD Falling XTAL Falling To /RD Rising 30 40 30 ns ns ns TdXT(WRF) XTAL Falling To/WR Falling 40 ns 27 TdXT(WRR) XTAL Falling To/WR Rising 30 ns 28 TsW(XT) Wait Set Up Time ns 29 ThW(XT) Wait Hold Time ns 30 TsW Wait Width (One Wait Time) ns Notes: 1. Values based on external clock drive with a clock frequency. 2. Values are preliminary and are to be characterized. 3. When using extended memory timing, add 2TpC. 4. Timing numbers are given for minimum TpC. 7 Z86193 CPS DC-4206-01 P R E L I M I N A R Y XTAL1 (External Clock Drive) 22 23 SCLK 25 24 /RD 27 26 /WR XTAL/SCLK To DSR and DSW Timing T1 T2 TW TW XTAL1 SCLK ALE /RD 32 WAIT 30 31 XTAL/SCLK To WAIT Timing 8 TW T3 T1 Z86193 CPS DC-4206-01 P R E L I M I N A R Y AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 2 3 7 T IN 4 5 6 IRQ N 8 9 Additional Timing AC CHARACTERISTICS Additional Timing Table No Symbol Parameter 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Imput Rise & Fall Times Input Clock Width Timer Input Low Width 5 6 7 8A TwTinH TpTin TrTin,TfTin TwIL 8B 9 TwIL TwIH TA = 0°C to +70°C 40 MHz Min Max 25 1000 4 Units Notes 8 75 ns ns ns ns [1] [1] [1] [2] Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times 3 TpC 8 TpC 100 70 ns ns ns ns [2] [2] [2] [2,4] Interrupt Request Input Low Times Interrupt Request Input High Times 5 TpC 3 TpC ns ns [2,5] [2,3] Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31)`. [5] Interrupt request through Port 30. 9 Z86193 CPS DC-4206-01 P R E L I M I N A R Y AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 3 2 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed Output Handshake Timing 10 RDY Z86193 CPS DC-4206-01 P R E L I M I N A R Y AC CHARACTERISTICS Handshake Timing Table N o Direction Symbol 1 2 3 4 TsDI(DAV) ThDI(DAV) TwDAV TdDAVIf(RDYf) Data In Setup Time to /DAV RDY to Data In Hold Time /DAV Width /DAV to RDY Delay 5 6 7 8 TdDAVIr(RDYr) TdRDYOr(DAVIf) TdD0(DAV) TdDAV0f(RDYIf) DAV Rise to RDY Wait Time RDY Rise to DAV Delay Data Out to DAV Delay /DAV to RDY Delay 9 10 11 TdRDYIf(DAVOr) TwRDY TdRDYIr(DAVOf) RDY to /DAV Rise Delay RDY Width RDY Rise to DAV Wait Time Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-conformance with some aspects of the CPS may be Low Margin: Customer is advised that since this is a Preliminary CPS, this product does not meet Zilog’s internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other © 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. T A = 0 °C to +70 °C Parameter Min 0 0 80 120 40 0 TpC 0 120 80 40 Max Data Units ns ns ns ns In In In In ns ns ns ns In In Out Out ns ns ns Out Out Out found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 11