CUSTOMER PROCUREMENT SPECIFICATION Z86C90/C89 ROMLESS CMOS Z8® 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The Z86C90/C89 CCP™ (Consumer Controller Processor) introduces a new level of sophistication to single-chip architecture. The Z86C90/C89 are ROMless members of the Z8 single-chip microcontroller family with 236 bytes of general purpose RAM. The only difference that exists between the Z86C89 and the Z86C90 is that the on-chip oscillator of the Z86C89 can accept an external RC network or other external clock source, while the Z86C90's on-chip oscillator accepts a crystal, ceramic resonator, LC, or external clock source drive. The CCP controllers are housed in a 40-pin DIP, 44-pin Leaded Chip Carrier, or a 44-pin Quad Flat Pack, and are CMOS compatible. The CCP offers the use of external memory which enables this Z8 microcomputer to be used where code flexibility is required. Zilog's CMOS microcomputer offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The Z86C90/C89 architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register mapped peripheral and I/O circuits. The CCP offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many industrial, automotive, computer peripherals, and advanced scientific applications. There are four basic address spaces available to support this wide range of configurations: Program Memory, Register File, Data Memory, and Expanded Register File. The Register File is composed of 236 bytes of general purpose registers, four I/O port registers, and fifteen control and status registers. The Expanded Register File consists of two control registers. To unburden the program from coping with the real-time problems, such as counting/timing and data communication, the Z86C90/C89 offers two on-chip counter/timers. Included are a large number of user selectable modes, and two on-board comparators to process analog signals with a common reference voltage (see Functional Block Diagram). Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS The CCP applications demand powerful I/O capabilities. The Z86C90/C89 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, parallel I/O with or without handshake, and an address/data bus for interfacing external memory. DC-4054-01 (10-17-91) 1 GENERAL DESCRIPTION (Continued) Output Input Vcc GND XTAL /AS /DS R//W Machine Timing & Instruction Control Port 3 Counter/ Timers (2) RESET WDT, POR ALU FLAGS Interrupt Control Two Analog Comparators Register Pointer Register File 256 x 8-Bit Port 2 Port 0 4 I/O (Bit Programmable) Port 1 4 Address or I/O (Nibble Programmable) Functional Block Diagram 2 Program Counter 8 Address/Data or I/O (Byte Programmable) /RESET PIN DESCRIPTION R//W 1 40 /DS P25 2 39 P24 P26 3 38 P23 P27 4 37 P22 P04 5 36 P21 P05 6 35 P20 P06 7 34 P03 P14 8 33 P13 P15 9 P12 P07 32 Z86C90/C89 31 10 DIP VCC 11 30 P02 P16 12 29 P11 P17 13 28 P10 XTAL2 14 27 P01 XTAL1 15 26 P00 P31 16 25 P30 P32 17 24 P36 P33 18 23 P37 P34 19 22 P35 /AS 20 21 /RESET GND 40-Pin DIP Pin Assignments 3 44 43 42 41 40 P00 1 P01 2 P10 3 P11 P02 4 GND P13 5 P12 P03 6 GND P20 PIN DESCRIPTION (Continued) P21 7 39 P30 P22 8 38 P36 P23 9 37 P37 P24 10 36 P35 /DS 11 35 /RESET N/C 12 34 GND R//W 13 Z86C90/C89 PLCC 33 /AS 14 32 P34 15 31 P33 P27 16 30 P32 P04 17 29 P31 P25 P26 XTAL2 XTAL1 P17 P16 VCC VCC P07 P15 P14 P06 P05 18 19 20 21 22 23 24 25 26 27 28 P00 P01 P10 P11 P02 GND GND P12 P13 P03 P20 44-Pin PLCC Pin Assignments 33 32 31 30 29 28 27 26 25 24 23 P21 34 22 P30 P22 35 21 P36 P23 36 20 P37 19 P35 18 /RESET 17 GND P24 37 /DS 38 N/C 39 R//W 40 16 /AS P25 41 15 P34 P26 42 14 P33 P27 43 13 P32 P04 44 12 P31 3 4 5 6 7 8 9 10 11 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1 2 P14 P05 1 P06 Z86C90/C89 QFP 44-Pin QFP Pin Assignments 4 STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). 2.1 KΩ From Output Under Test 150 pF 9.1 KΩ Test Load Diagram ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC T STG TA Supply Voltage (*) Storage Temp Oper Ambient Temp Power Dissipation -0.3 -65° +7.0 +150° † 2.2 V C C W ings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an e x t e n d e d period may affect device reliability. Notes: * Voltage on all pins with respect to GND. † See Ordering Information. Stress greater than those listed under Absolute Maximum Rat- CAPACITANCE T A = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND Parameter Max Input capacitance Output capacitance I/O capacitance 12 pF 12 pF 12 pF PLEASE NOTE These devices will not operate in extended timing mode. Set Register 248, D5 = 0. 5 DC CHARACTERISTICS Sym Notes Parameter Max Input Voltage VCH VCL Clock Input High Voltage Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltge VOL1 Output Low Voltage VOL2 Output Low Voltage VCC T A = 0 °C TA = -40° C Note [3] to 70°C Min Max to 105° C Min Max 3.3V 5.0V 3.3V 0.7 VCC 7 7 VCC+0.3 5.0V 0.7 VCC VCC+0.3 3.3V 0.7 VCC 1.3 0.7 VCC VCC+0.3 2.5 V GND -0.30.2 VCC GND-0.3 0.2 VCC 0.7 V 5.0V GND-0.3 0.2 VCC GND-0.3 0.2 VCC 1.5 V 3.3V 5.0V 3.3V 5.0V 0.7 VCC VCC+0.3 0.7 VCC VCC+0.3 GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC 1.3 2.5 0.7 1.5 V V V V 3.3V 5.0V 3.3V 5.0V 3.3V VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 0.6 0.4 1.2 0.6 0.4 1.2 3.1 4.8 0.2 0.1 0.3 V V V V V 1.2 1.2 0.3 V VCC VCC 0.2 VCC 0.2 VCC 25 25 1.5 2.1 1.1 1.7 10 10 V V mV mV 2 2 2 2 -60 -70 <1 <1 <1 <1 -20 -30 µA µA µA µA µA µA VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 25 25 .8 VCC .8 VCC GND-0.3 GND-0.3 IIL Input Leakage IOL Output Leakage -1 -1 -1 -1 -1 -1 -1 -1 IIR Reset Input Current 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V ICC [4,5] Supply Current VOFFSET 25°C V V V Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage VRl Conditions 7 7 VCC+0.3 5.0V VRH Typ @ Units 1 1 1 1 -45 -55 IIN 250µA IIN 250µA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator IOH = -2.0 mA IOH = -2.0 mA IOH = +4.0 mA IOL = +4.0 mA IOL = +6 mA, 3 Pin Max IOL = +12 mA, 3 Pin Max 3.3V 10 10 4 mA @ 8 MHz 5.0V 15 15 10 mA @ 8 MHz 3.3V 15 15 5 mA @ 12 MHz [4,5] 6 [4,5] 5.0V 20 20 15 mA @ 12 MHz [4,5] Sym Notes ICC1 [4,5] Parameter Standby Current VCC T A = 0°C Note [3] to 70°C Min Max 3.3V T A = -40° C Min 3 5.0V Conditions to 105° C 25°C Max 3 5 Typ @ Units 5 1 2.4 mA HALT Mode mA VIN = OV, VCC @ 8 MHz HALT Mode mA VIN = OV, VCC @ 8 MHz HALT Mode mA VIN = OV, VCC @ 12 MHz HALT Mode [4,5] 3.3V 4 4 1.5 [4,5] 5.0V 6 6 3.2 [4,5] VIN = OV, VCC @ 12 MHz 3.3V 2 2 0.8 mA Clock Divide by 5.0V 4 4 1.8 mA 16 @ 8 MHz Clock Divide by 3.3V 3 3 1.2 mA 16 @ 8 MHz Clock Divide by 5.0V 5 5 2.5 mA 16 @ 12 MHz Clock Divide by [4,5] [4,5] [4,5] [4,5] 16 @ 12 MHz ICC2 Standby Current 3.3V 8 15 1 µA 5.0V 10 20 2 µA 3.3V 500 600 310 µA V IN STOP Mode [6] VIN = OV, VCC WDT is not Running STOP Mode [6] VIN = OV, VCC WDT is not Running STOP Mode [6] = OV, V CC WDT is Running 1000 5.0V 600 µA 800 STOP Mode V IN = OV, V CC WDT is 7 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram R//W 13 12 Port 0, /DM 16 3 19 Port 1 A7 - A0 1 D7 - D0 IN 2 9 /AS 8 18 11 4 5 /DS (Read) 6 17 10 Port1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing 8 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table No Symbol Parameter VCC Note[3] 1 TdA(AS) 2 TdAS(A) Address Valid to /AS Rising Delay /AS Rising to Address Float Delay 3.3 5.0 3.3 5.0 3 TdAS(DR) 4 TwAS /AS Rising to Read Data Required Valid /AS Low Width 3.3 5.0 3.3 5.0 5 Td 6 TwDSR 7 TwDSW T A = 0°C to +70°C 8 MHz 12 MHz Min Max Min Max T A = -40°C to +105°C 8 MHz 12 MHz Min Max Min Max 55 55 70 70 55 55 70 70 35 35 45 45 250 250 [2] 55 55 80 80 55 55 Address Float to 3.3 /DS Falling 5.0 /DS (Read) Low Width 3.3 5.0 0 0 300 300 0 0 200 200 0 0 300 300 0 0 200 200 ns ns ns ns /DS (Write) Low Width 3.3 5.0 TdDSR(DR) /DS Falling to Read 3.3 Data Required Valid 5.0 165 165 110 110 165 165 110 110 ns ns ns ns [1,2] 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) 12 TdR/W(AS) 13 TdDS(R/W) 150 160 250 250 [2] 80 80 260 260 400 400 ns ns ns ns Notes ns ns ns ns 8 400 400 35 35 45 45 Units 260 260 150 160 [1,2] [2] [1,2] [1,2] Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay 3.3 5.0 3.3 5.0 0 0 85 95 0 0 45 55 0 0 85 95 0 0 45 55 ns ns ns ns [2] /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay 3.3 5.0 3.3 5.0 60 70 70 70 30 45 45 45 60 70 70 70 30 45 45 45 ns ns ns ns [2] /DS Rising to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Falling (Write) Delay 3.3 5.0 3.3 5.0 70 70 80 80 45 45 55 55 70 70 80 80 45 45 55 55 ns ns ns ns [2] 15 TdDS(DW) 45 55 70 80 45 55 ns ns ns ns [2] TdA(DR) 3.3 5.0 3.3 5.0 70 80 16 /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid 17 TdAS(DS) 18 TdDI(DS) 19 TdDM(AS) /AS Rising to /DS Falling Delay Data Input Setup to /DS Rising /DM Valid to /AS Falling Delay 3.3 5.0 0.0 5.0 3.3 5.0 100 100 115 75 55 55 14 475 475 310 310 65 65 115 75 35 35 475 475 100 100 115 75 55 55 310 310 65 65 115 75 35 35 ns ns ns ns ns ns [2] [2] [2] [1,2] [2] [1,2] [2] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 5.0V ±0.5V, 3.3V ±0.3V. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 9 AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 T 2 3 7 IN 4 5 6 IRQ N 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Additional Timing 10 AC CHARACTERISTICS Additional Timing Table No Symbol Notes Parameter Note[6] 12 MHz Min Max 8 MHz Min Max 12 MHz Min Max Input Clock Period 3.3V 5.0V Clock Input Rise 3.3V and Fall Times 5.0V 125 100000 125 100000 25 25 83 83 125 100000 125 100000 25 25 83 83 37 37 100 70 26 26 100 70 37 37 100 70 26 26 100 70 TpC 2 TrC,TfC 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH 6 TpTin Timer Input 3.3V High Width 5.0V Timer Input Period 3.3V 5.0V 7 TrTin,TfTinTimer Input Rise and Fall Timers TwIL Interrupt Request Low Time 8B TwIL [1,3] [1,3] 9 TwIH [1,2] TA = -40°C to 105°C 8 MHz Min Max 1 8A TA = 0°C to 70°C VCC 3.3V 5.0V 3.3V 5.0V 3TpC 3TpC 8TpC 8TpC 100 100 100000 100000 15 15 100000 100000 15 15 3TpC 3TpC 8TpC 8TpC 3TpC 3TpC 8TpC 8TpC 3TpC 3TpC 8TpC 8TpC 100 100 100 100 100 100 3.3V 5.0V 3.3V 5.0V 100 70 Int. Request 3.3V 3TpC 3TpC 3TpC 3TpC Low Time 5.0V 3TpC 3TpC 3TpC 3TpC Interrupt Request 3.3V 3TpC 3TpC 3TpC 3TpC Input High Time 5.0V 3TpC 3TpC 3TpC 3TpC 100 70 100 70 100 70 Units ns ns ns ns [1] [1] [1] [1] ns ns ns ns [1] [1] [1] [1] [1] [1] [1] [1] ns ns ns ns [1] [1] [1,2] [1,2] [1,2] 10 Twsm STOP Mode 3.3V Recovery Width Spec 3.3V 5.0V 12 5.0V 12 5TpC 5TpC 12 12 12 12 12 ns 12 ns [7] [8] 11 AC CHARACTERISTICS Additional Timing Table (Continued) No Symbol 11 Tost 12 [5] Twdt T A = 0°C to 70°C 8 MHz 12 MHz Min Max Min Max T A = -40°C to 105°C Units 8 MHz 12 MHz Min Max Min Max Parameter VCC Note[6] Oscillator Startup Time Watchdog Timer 3.3V 5.0V 3.3V 10 10 10 10 ms [4] [4] D0 = 0 Delay Time 5.0V 5 5 5 5 ms D1 = 0 3.3V 30 30 30 30 ms D0 = 1 5.0V 15 15 15 15 ms D1 = 0 3.3V 5.0V 50 25 50 25 50 25 50 25 ms ms D0 = 0 D1 = 1 3.3V 200 200 200 200 ms D0 = 1 5.0V 100 100 100 100 ms D1 = 1 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC 5TpC Notes [5] [5] [5] [5] [5] [5] [5] Notes: [1] Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 0 [5] Reg. WDTMR [6] 5.0V ±0.5V, 3.3V ±0.3V [7] Reg. SMR - D5=0 [8] Reg. SMR - D5=1 12 AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing 13 AC CHARACTERISTICS Handshake Timing Table Symbol Parameter VCC Note[1] TA = 0 °C To 70° C 8 MHz 12 MHz Min Max Min Max T A = -40° C To 105° C 8 MHz 12 MHz Data Min Max Min Max Direc- 1 TsDI(DAV) Data In Setup Time 2 ThDI(DAV) Data In Hold Time 3.3V 5.0V 3.3V 5.0V 0 0 160 115 0 0 160 115 0 0 160 115 0 0 160 115 IN IN IN IN 3 TwDAV Data Available Width 155 110 155 110 155 110 155 110 4 TdDAVI(RDY) DAV Falling to RDY Falling Delay 3.3V 5.0V 3.3V 5.0V IN IN IN IN 5 TdDAVId(RDY) DAV Rising to RDY Falling Delay TdDO(DAV) RDY Rising to DAV Falling Delay 3.3V 5.0V 3.3V 5.0V 0 0 0 0 0 0 0 0 IN IN IN IN TcLDAV0(RDY)Data Out to DAV Falling Delay TcLDAV0(RDY)DAV Falling to RDY Falling Delay 3.3V 5.0V 3.3V 5.0V 63 63 0 0 42 42 0 0 63 63 0 0 42 42 0 0 OUT OUT OUT OUT TdRDY0(DAV) RDY Falling to DAV Rising Delay TwRDY RDY Width 3.3V 5.0V 3.3V 5.0V TdRDY0d(DAV) RDY Rising to DAV Falling Delay 3.3V 5.0V No tion 6 7 8 9 10 11 160 115 160 115 160 115 160 115 120 80 120 80 120 80 120 80 160 115 110 80 160 115 110 80 110 80 160 115 110 80 110 80 160 115 OUT OUT OUT OUT 110 80 OUT OUT 110 80 110 80 Note: [1] 5.0 V ±0.5V, 3.3V ±0.3V © 1991 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be 14 responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 171-980 A/B ZILOG CPTO FAX 408 370-8056/8027