P R E L I M I N A R Y Z86E47-ROM CPS DC-4157-01 PRELIMINARY CUSTOMER PRODUCT SPECIFICATION Z86E47 OTP ROM CMOS Z8® 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The Z86E47 Digital Television Controller (DTC) introduce a new level of sophistication to single-chip architecture. The Z86E47 is a member of the Z8 single-chip microcontroller family with 16 Kbytes of OTP (One-TimeProgrammable) ROM and 236 bytes of RAM. The device is housed in a 64-pin DIP package, and is CMOS compatible. The part features ROMs for program storage and character generation. The Z86E47 microcontroller may be used in prototyping, low volume applications or where code development is required. Zilog’s DTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z86E47 architecture utilizes Zilog’s advanced Superintegration™ design methodology. The device has an 8-bit internal data path controlled by a Z8 microcontroller, On-Screen Display (OSD) logic circuits/Pulse Width Modulators (PWM). On-chip peripherals include five register/ memory mapped I/O ports (Ports 2, 3, 4, 5, and 6), Interrupt control logic (1 software, 2 external and 3 internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support eight rows by 20 columns for 128 kinds of characters. The character color is specified by row. One of the eight rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying high resolution (11x15 dot pattern) characters. DC-4157-01 (2-18-94) A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Seven 6-bit PWM ports are used for controlling audio signal level. Five 8-bit PWM ports are used to vary picture levels. DTC applications demand powerful I/O capabilities. The Z86E47 fulfills this with 35 I/O pins dedicated to input and output. These lines are grouped into five ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Register File and Data Memory. The Data Memory address space contains a number of control registers for the PWMs, OSD, and I/O Ports 4, 5, and 6. Specifically, there are 13 PWM and eight OSD control registers mapped into the external memory address space. Three I/O registers for Ports 4, 5, and 6 reside in data memory space as well. The Register File is composed of 236 bytes of general purpose register, two I/O Port registers and 15 control and status registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the DTC’s offer two on-chip counter/timers with a large number of user selectable modes (see block diagram). Note: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). 1 Z86E47-ROM CPS DC-4157-01 P R E L I M I N A R Y PRODUCT RECOMMENDATIONS Zilog recommends the following programming equipment for use with this one-time-programmable product. Recommended Hardware Device Zilog Support Tool Z86E4700ZDP Z86E47 Programming Adapter If difficulty is encountered in programming a Zilog OTP product, please contact your local Zilog sales office. Some non-Zilog programmers may have different programming waveforms, voltages and timings and not all programmers may meet the programming requirements of Zilog's one-time-programmable products. XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 AFCIN 16K Byte Program ROM Port 2 Z8 CPU Core P27 P26 P25 P24 P23 P22 P21 P20 Port 3/ Interrupt PWM 1 14 -bit 256 Byte Register File PWM 2 to PWM 8 6-bit Port4 Port 0 Port 1 A8:15 AD0:7 PWM 9 to PWM 13 8-bit Port 5 160 Byte Character RAM Port 6 4 KByte Character ROM Functional Block Diagram 2 A On Screen Display PWM 1 PWM 2 PWM 3 PWM 4 PWM 5 PWM 6 PWM 7 PWM 8 PWM 9 PWM 10 PWM 11 PWM 12 PWM 13 OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK Z86E47-ROM CPS DC-4157-01 P R E L I M I N A R Y PIN CONFIGURATION PWM5 1 PWM4 PWM3 2 PWM2 PWM1 P35 P36 P34 P31 64 63 PWM6 PWM7 3 4 62 PWM8 61 PWM9 5 60 PWM10 6 7 59 58 PWM11 PWM12 8 57 56 PWM13 P27 55 P26 54 53 P25 P24 52 P23 51 50 GND P22 49 48 47 P21 46 45 44 P47 P46 P45 43 42 P44 P43 41 40 39 P42 P41 P40 38 37 36 35 VBLANK VBLUE VGREEN VRED 34 VSYNC HSYNC P30 9 10 XTAL1 11 XTAL2 12 13 /RESET P60 14 GND P61 15 16 P62 VCC P63 17 18 19 P64 20 P65 AFCIN 21 22 P50 23 P51 P52 P53 P54 24 25 P55 P56 P57 OSCIN OSCOUT 26 27 28 29 30 31 32 Z86E47 33 VCC P20 Z86E47 OTP ROM Plastic DIP 3 Z86E47-ROM CPS DC-4157-01 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameters Min Max Units Notes VCC VI VI VO IOH Power Supply Voltage † Input Voltage Input Voltage Output Voltage Output Current High –0.3 –0.3 –0.3 –0.3 +7 VCC + 0.3 VCC + 0.3 VCC + 8.0 –10 V V V V mA [1] [2] 1 pin IOH IOL IOL IOL TA TSTG Output Current High Output Current Low Output Current Low Output Current Low,all total Operating Temperature Storage Temperature –100 20 40 200 mA mA mA mA +150 C †† –65 Notes: [1] Port 2 open-drain [2] PWM open-drain outputs [3] Port 5 all total 1 pin [3] (1 pin) † Voltage on all pins with respect to GND. †† See Ordering Information STANDARD TEST CONDITIONS VDD The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Test Load Diagram). RLL From Output Under Test 150 pF Test Load Diagram CAPACITANCE TA=25°C, VCC=GND=0 V, Freq=1.0 MHz, unmeasured pins to GND. Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance 4 Max Units 10 20 25 10 pF pF pF pF RLH Z86E47-ROM CPS DC-4157-01 P R E L I M I N A R Y DC CHARACTERISTICS TA=0°C to +70°C; VCC=+4.5 V to +5.5 V; FOSC=4 MHz TA=0°C to +70°C Min Max Symbol Parameter VIL VILC VIH VIHC Input Voltage Low Input XTAL/Osc In Low Input Voltage High Input XTAL/Osc in High VHY VPU VOL Schmitt Hysteresis Maximum Pull-up Voltage Output Voltage Low V00-01 V01-11 AFC Level 01 In AFC Level 11 In VOH IIR IIL IOL Output Voltage High Reset Input Current Input Leakage Tri-State Leakage ICC ICC1 ICC2 Supply Current 0 0.2 VCC 0.07 VCC VCC VCC 0.7 VCC 0.8 VCC 0.1 VCC 0.5 VCC 1.48 0.98 3.0 3.2 V V V V External Clock Generator Driven 0.8 [2] IOL=1.00 mA IOL=3.2 mA, [1] External Clock Generator Driven 12 0.4 0.4 0.16 0.19 V V V V 0.4 1.5 0.45 VCC 0.75 VCC 0.19 1.00 1.9 3.12 V V V V –80 3.0 3.0 4.75 –46 0.01 0.02 V µA µA µA IOH= –0.75 mA VRL=0 V 0 V,VCC 0 V,VCC 35 6 10 22 3.2 0 mA mA µA All inputs at rail All inputs at rail All inputs at rail [3] VCC–0.4 –3.0 –3.0 Typical @ 25°C Units Conditions IOL=0.75 mA [2] IOL=10 mA [1] Notes: [1] Port 5 [2] PWM Open-Drain [3] XTAL1 Disconnected AC CHARACTERISTICS Timing Diagrams 1 3 7 XTAL1 5 Tin 3 2 2 External Clock 4 6 Counter Timer 5 Z86E47-ROM CPS DC-4157-01 P R E L I M I N A R Y IRQn 8 9 Interrupt Request Vcc 10 11 Internal /RESET 12 External /RESET Power On Reset HSYNC 13 OSC2 On Screen Display 6 14 Z86E47-ROM CPS DC-4157-01 P R E L I M I N A R Y AC CHARACTERISTICS TA=0° C to +70° C; VCC=+4.5 V to +5.5 V; FOSC=4 MHz, No Symbol Parameter Min Max Unit 1 2 3 4 TpC TrC,TfC TwC TwTinL Input clock period Clock input raise and fall Input clock width Timer input low width 250 1000 15 ns ns ns ns 5 6 7 8A TwTinH TpTin TrTin,TfTin TwIL Timer input high width Timer input period Timer input raise and fall Int req input low 3 TpC 8 TpC 100 ns ns 8B 9 10 11 TwIL TwIH TdPOR TdLVIRES 100 ms ns 12 13 14 15 TwRES TdHsOI TdHsOh TdWDT Int request input high Power On Reset delay Low voltage detect to InInternal RESET condition Reset minimum width Hsync start to Vosc stop Hsync end to Vosc start WDT Refresh Time 125 70 70 3 TpC 3 TpC 25 200 5 TpC 2 TpV 3 TpV 1 TpV 12 ms Notes: [1] Refer to DC Characteristics for details on switching levels. * Units in nanoseconds 7 P R E L I M I N A R Y Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-conformance with some aspects of the CPS may be found, © 1993 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 8 Z86E47-ROM CPS DC-4157-01 either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056