Z89331 CP95TEL1400 P R E L I M I N A R Y PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION Z89331 OTPDIGITAL TELEVISIONCONTROLLER FEATURES n Part Number Z89331 ROM (KB) RAM* (Bytes) 24 640 Speed (MHz) 12 n Serial Interfacing I2C Port n Fully Customized Character Set n Character-Control and Closed-Caption Modes n Keypad User Control n TV Tuner Serial Interface n Direct Video Signals n Low-EMI Option *General-Purpose n 42-Pin SDIP Package n 4.75- to 5.25-Volt Operating Range n 0°C to +70°C Temperature Range n One-Time Programmable GENERAL DESCRIPTION The Z89331 One-Time Programmable (OTP) Digital Television Controller is designed to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The Z89331 features a Z89C00 RISC processor core that controls on-board peripheral functions and registers using the standard processor instruction set. Character attributes can be controlled through two modes: the on-screen display Character-Control Mode and the Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Closed-caption text can be decoded directly from the composite video signal and displayed on-screen with the assistance of the processor's digital signal processing (DSP) capabilities. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. CP95TEL1400 11/95 Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tunning adjustments, may be accessed through the industry-standard I2C port. User control can be monitored through the keypad port, or the 16-bit remote control capture register. functions such as color and volume can be controlled by eight 8-bit pulse width modulated scanning Receiver directly ports. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z89331 CP95TEL1400 P R E L I M I N A R Y GENERAL DESCRIPTION (Continued) PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 Capture IRIN Port 17 Port 00 Port 05 Port 04 ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Note: Dotted pin functions not available on 42-pin device. I2C Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset SCL SCD Register Addr/Data RAM 640 x 16 Address Z89C00 Core ROM Addr Data ROM Data Functional Block Diagram 2 OSD V1 V2 V3 BLANK HALFBLNK CPU Port 01/11 Port 02/12 ROM 12K x 16 16K x 16 24K x 16 Port0F Z89331 CP95TEL1400 P R E L I M I N A R Y PWM10 1 42 Port12/I2MSD PWM9 2 41 Port 11/12MSC PWM5 3 40 Port 02/I2SSD PWM4 4 39 Port 01/I2SSC PWM3 5 38 Port 09 PWM2 6 37 Port 08/R<1> PWM1 7 36 IRIN Port 03 8 35 Port 07/CSync Port 04/ADC4 9 34 VCC 33 /Reset 32 XTAL2 Z89331 42-Pin Shrink DIP Port 05/ADC3 10 Port 00/ADC2 11 Port 17/ADC1 12 31 XTAL1 13 30 ANGND Port 10/R<0> 14 29 LPF Port 06/Counter GND 15 28 CVI/ADC0 Port 18/G<0> 16 27 VSync Port 13/G<1> 17 26 HSync Port 14/B<0> 18 25 VBlank Port 15/B<1> 19 24 V1 Port 16/SCLK 20 23 V2 Port 0F/HalfBlnk 21 22 V3 42-Pin Shrink DIP Pin Configuration 3 Z89331 CP95TEL1400 P R E L I M I N A R Y PIN DESCRIPTIONS Z89331 Pin Name Function VCC +5 V GND 0V IRIN ADC[5:0] a Infrared Remote Capture Input 4-Bit Analog to Digital Converter Input b 14-Bit Pulse Width Modulator Output PWM9 PWM[8:1]c Port0[F:0]d Z89331 42-Pin SDIP 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Configuration Direction Reset 34 PWR PWR 13,30 PWR PWR 36 –,9,10,11,12,2,8 I AI I I 1,2 OD O –,–,–,3,4 5,6,7 21,–,–,–,–,–, 38,37,35,–,–, 15,8,40,39,11 –,16,12,20, 19,18,17,42, 41,14 OD OD B I B I Port1[9:0] e Bit Programmable Input/Output Ports MSSCLf I2C Clock I/O 41 BOD MSSCD g SSCL h SSCD i I2C Data I/O I2C Clock I/O I2C Data I/O 42 39 40 BOD BOD BOD XTAL1 XTAL2 Crystal Oscillator Input Crystal Oscillator Output 31 32 AI AO AI AO LPF Loop Filter 29 AB AB HSYNC VSYNC H_Sync V_Sync 26 27 B B I I /RESET Device Reset 33 I I V[3:1] 22,23,24 O O Blank Half Blankh OSD Video Output (Typically Drive B, G, and R Outputs) OSD Blank Output OSD Half Blank Output 25 21 O O O I RGB Digital Outputs i SCLKk R[1:0],G[1:0], and B[1:0] Outputs of the RGB Matrix Internal Processor SCLK 37,14,17, 16,19,18 20 O I O I Notes: a) ADC1 input is shared with Port 17, ADC2 input Pin is shared with Port 00. ADC3 input pin is shared with Port 05 and ADC4 input pin is shared with Port 04. b) ADC0 and ADC5 have a clamp circuit that facilitates Composite video input. c) PWM[8,7] is not available on the 42-pin DIP version. d) Port0[F:A] is not available on the 42-pin DIP version. 4 e) f) g) h) i) k) I I I Port19 is not available on the 42-pin DIP version. SCL I/O pin is shared with Port01 or Port11. SCD I/O pin is shared with Port02 or Port12. Half Blank output is a function shared with Port0F. Digital RGB outputs and the internal SCLK are shared with Port1[5:0]. Internal processor SCLK is shared with Port16. Z89331 CP95TEL1400 P R E L I M I N A R Y V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V VCC = 5.25 V Condition Limit Output Voltage Bit = 11 Bit = 10 3.9 V +/– 0.3 V 3.0 V +/– 0.3 V Bit = 01 Bit = 00 1.8 V +/– 0.3 V 0.6 V +/– 0.3 V Settling Time 70% of DC Level, 10pf Load < 50 nsec V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75V VCC = 4.75V Condition Limit Output Voltage Bit = 11 Bit = 10 3.5 V +/– 0.3 V 2.6 V +/– 0.3 V Bit = 01 Bit = 00 1.6 V +/– 0.3 V 0.5 V +/– 0.3 V Settling Time 70% of DC Level, 10pf Load < 50 nsec 5 Z89331 CP95TEL1400 P R E L I M I N A R Y DC CHARACTERISTICS TA = 0°C to + 70°C; VCC = + 4.75 V to + 5.25V Symbol Parameter TA = 0° to + 70°C Min Max VIL VIH Input Voltage Low Input Voltage High 0 0.7 VCC VHY VPU VOL Schmitt Hysteresis 0.1 VCC Maximum Pull-Up Voltage Output Voltage Low VOH IIR IIL IOL Output Voltage High Reset Input Current Input Leakage Tri-State Leakage Note: [1] Port 0, 1 [2] PWM Open-Drain 6 0.2 VCC VCC Units 1.48 3.0 V V 0.8 [2] IOL = 1.00 mA IOL = mA, [1] IOL =0.75 mA, [2] IOH = –0.75 mA VRL = 0 V 0 V, VCC 0 V, VCC 13.2 0.4 0.4 0.4 0.16 0.19 0.19 V V V V V –80 3.0 3.0 4.75 –46 0.01 0.02 V µA µA µA V CC –0.4 –3.0 –3.0 Typical @ 25°C Conditions P R E L I M I N A R Y Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con- © 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Z89331 CP95TEL1400 formance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com 7