ZILOG Z89393

Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
PRELIMINARY
CUSTOMERPROCUREMENTSPECIFICATION
Z89323/373/393
16-BITDIGITAL
SIGNAL PROCESSORS
FEATURES
DSP ROM
OTP
DSP RAM
Device (K Words) (K Words) (Words)
Z89323
Z89373
Z89393
8
8
64*
Max Core
MIPS
512
512
512
20
16
20
Package
Device
Z89323
Z89373
Z89393
44-Pin
PLCC
68-Pin
PLCC
44-Pin
QFP
✔
✔
✔
✔
✔
✔
80-Pin 100-Pin
QFP
QFP
✔
✔
✔
* External
Operating Temperature Ranges:
0°C to +70°C (Standard)
–40°C to +85°C (Extended)
On-Board Peripherals
■
4-Channel, 8-Bit Analog to Digital Converter (A/D)
4.5- to 5.5-Volt Operating Range
■
On-Board Serial Peripheral Interface (SPI)
DSP Core
■
Up to 40 Bits of Programmable I/O
■
20 MIPS @ 20 MHz, 16-Bit Fixed Point DSP
■
Two Channels of Programmable
Pulse Width Modulators (PWM)
■
50 ns Instruction Cycle Time
■
Three General-Purpose Timer/Counters
■
Single-Cycle Multiply and ALU Operations
■
Two Watch-Dog Timers (WDT)
■
Two Internal Data Buses and Address Generators
■
Programmable PLL
■
Six Register Address Pointers
■
■
Optimized Instruction Set (30 Instructions)
Three Vectored Interrupts Servicing Eight
Interrupt Sources
■
Power-Down and Power-On Reset
■
■
GENERAL DESCRIPTION
The Z89323/373/393 DSP family of products builds on
Zilog's first generation Z893XX DSP core, integrating several
peripherals especially well suited for cost-effective voice,
telephony, and control applications.
various peripherals, such as a high-speed 4-channel, 8-bit
A/D, an SPI, three timers with PWM and WDT support, the
Z893X3 family provides a compact system solution and
reduces overall system cost.
These DSP devices feature a modified Harvard architecture
supported by one program bus and two on-chip data
buses. This bus structure is supported by two address
generators and six register pointers to ensure that the
20 MIPS DSP CPU is continually active.
To support a wide variety of development needs, the
Z893X3 DSP product family features the cost-effective
Z89323 with 8 Kwords of on-chip ROM, and the Z89373, a
16-MIPS OTP version of the Z89323, ideal for prototypes
and early production builds. For systems requiring more
than 8 Kwords of program memory, the Z89393 device can
address up to 64 Kwords of external program memory.
The Z893X3 DSP family is designed to provide a complete
DSP and control system on a single chip. By integrating
DS95DSP0101 Q4/95
1
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
GENERAL DESCRIPTION (Continued)
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
The Z893X3 DSP family is 100 percent source and objectcode compatible with the existing Z89321/371/391 devices,
providing users, who can benefit from increased integration
and reduced system cost, an easy migration path from one
DSP product to the next.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
Throughout this specification, references to the Z89323
device applies equally to the Z89373 and Z89393, unless
otherwise specified.
Program
ROM/OTP
8192x16
PD0-15
Data RAM0
256x16
Data RAM1
256x16
PDATA
PA0-15
PADDR
VSS
Port 0
16-Bit
Program
I/O
/EXTEN
EA0-2
EXT0-15/P00-15
/DS
WAIT
RD//WR
DDATA
/PAZ
XDATA
X
Y
Multiplier
P0
P0
P1
P1
P2
P2
DP0-3
DP4-6
ADDR
GEN0
ADDR
GEN1
AN0
AN1
AN2
AN3
8-Bit
A/D
Port 1
HALT
P
/ROMEN
/RES
Shifter
P10-17
or
INT2
CLKOUT
SIN
SOUT
SK
SS
UI0-1
8-Bit I/O
CLKI
CLKO
AGND
ANVCC
Program
Control
Unit
Arithmetic
Logic Unit
(ALU)
16-Bit Timer,
Counter
VALO
VALI
VSS
Port 2
Accumulator
P20-27
or
16-Bit Timer,
Counter, PWM
VDD
16-Bit Timer,
Counter, PWM
UI2
8-Bit I/O
UO0-2
INT0-1
SPI
Port 3
4 Inputs
4 Outputs
P30-33
P34-37
Figure 1. Z893X3 Functional Block Diagram
2
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
P20/INT0
2
1
VSS
EXT12/P012
3
EXT0/P00
EXT13/P013
4
EXT1/P01
EXT14/P014
5
EXT2/P02
VSS
6
VSS
EXT15/P015
PIN DESCRIPTION
EXT3/P03
7
44 43 42 41 40
39
/RES
EXT4/P04
8
38
WAIT
VSS
9
37
P24/UO2
EXT5/P05
10
36
P22/UO0
EXT6/P06
11
35
CLKO
EXT7/P07
12
34
CLKI
INT1/P21
13
33
/DS
EXT8/P08
14
32
P23/UO1
EXT9/P09
15
31
EA2
VSS
16
30
EA1
EXT10/P010
17
29
EA0
Z89323/373
44-Pin PLCC
RD//WR
VDD
ANVCC
AN2
AN3
AN1
AN0
VALO
ANGND
VAHI
EXT11/P011
18 19 20 21 22 23 24 25 26 27 28
Figure 2. 44-Pin PLCC Z89323/373 Pin Configuration
Table 1. 44-Pin PLCC Z89323/373 Pin Description
No.
Symbol
Function
Direction
No.
Symbol
Function
1
2
3
4
5
P20/INT0
EXT12/P012
EXT13/P013
EXT14/P014
VSS
Port20/Interrupt0
ExtData12/Port012
ExtData13/Port013
ExtData14/Port014
Ground
In/Output
In/Output
In/Output
In/Output
23
24
25
26
27
AN1
AN2
AN3
ANVCC
VDD
A/DInput1
A/DInput2
A/DInput3
AnalogPower
Power
6
7
8
9
10
EXT15/P015
EXT3/P03
EXT4/P04
VSS
EXT5/P05
ExtData15/Port015
ExtData3/Port03
ExtData4/Port04
Ground
ExtData5/Port05
In/Output
In/Output
In/Output
In/Output
28
29
30
31
32
RD//WR
EA0
EA1
EA2
P23/UO1
R/WExternalBus
ExtAddress0
ExtAddress1
ExtAddress2
Port23/UserOutput1
Output
Output
Output
Output
In/Output
11
12
13
14
15
EXT6/P06
EXT7/P07
P21/INT1
EXT8/P08
EXT9/P09
ExtData6/Port06
ExtData7/Port07
Port21/Interrupt1
ExtData8/Port08
ExtData9/Port09
In/Output
In/Output
In/Output
In/Output
In/Output
33
34
35
36
37
/DS
CLKI
CLKO
P22/UO0
P24/UO2
ExtDataStrobe
Clock/CrystalIn
Clock/CrystalOut
Port22/UserOutput0
Port24/UserOutput2
Output
Input
Input
In/Output
In/Output
16
17
18
19
20
21
22
VSS
EXT10/P010
EXT11/P011
VAHI
VALO
ANGND
AN0
Ground
ExtData10/Port010
ExtData11/Port011
AnalogHighRef.
AnalogLowRef.
AnalogGround
A/DInput0
In/Output
In/Output
Input
Input
Input
Input
38
39
40
41
42
43
44
WAIT
/RES
VSS
EXT0/P00
EXT1/P01
EXT2/P02
VSS
WaitforExt
Reset
Ground
ExtData0/Port00
ExtData1/Port01
ExtData2/Port02
Ground
DS95DSP0101 Q4/95
Direction
Input
Input
Input
Input
Input
Input
In/Output
In/Output
In/Output
3
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
P12/SIN
2
1
VDD
P20/INT0
3
VSS
EXT12/P012
4
EXT0/P00
EXT13/P013
5
EXT1/P01
VDD
6
EXT2/P02
EXT14/P014
7
P10
VSS
8
VSS
EXT15/P015
9
P11/CLKOUT
NC
PIN DESCRIPTION (Continued)
NC
10
68 67 66 65 64 63 62 61
60
EXT3/P03
11
59
/RES
EXT4/P04
12
58
WAIT
VSS
13
57
P25/UI2
VSS
VDD
14
56
P22/UO0
EXT5/P05
15
55
P26
SOUT/P13
16
54
CLKO
EXT6/P06
17
53
CLKI
SS/P14
18
52
P24/UO2
EXT7/P07
19
51
/DS
SK/P15
20
50
P23/UO1
P27
21
49
VDD
EXT8/P08
22
48
NC
EXT9/P09
23
47
EA2
Z89323/373
68-Pin PLCC
HALT
RD//WR
VDD
ANVCC
P21/INT1
AN3
VSS
AN2
AN1
AN0
AGND
VALO
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
UI1/P17
26
UI0/P16
EA0
VSS
VSS
EA1
45
VAHI
46
25
VDD
24
EXT11/P011
VSS
EXT10/P010
Figure 3. 68-Pin PLCC Z89323/373 Pin Configuration
4
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Table 2. 68-Pin PLCC Z89323/373 Pin Description
No.
Symbol
Function
Direction
No.
Symbol
Function
Direction
1
2
3
4
5
P12/SIN
P20/INT0
EXT12/P012
EXT13/P013
VDD
Port12/SerialInput
Port20/Interrupt0
ExtData12/Port012
ExtData13/Port013
Power
In/Output
In/Output
In/Output
In/Output
35
36
37
38
39
AN0
AN1
AN2
AN3
VSS
A/DInput0
A/DInput1
A/DInput2
A/DInput3
Ground
Input
Input
Input
Input
6
7
8
9
10
EXT14/P014
VSS
EXT15/P015
NC
NC
ExtData14/Port014
Ground
ExtData15/Port015
NoConnection
NoConnection
In/Output
40
41
42
43
44
P21/INT1
ANVCC
VDD
RD//WR
HALT
Port21/Interrupt1
AnalogPower
Power
R/WExternalBus
HaltExecution
11
12
13
14
15
EXT3/P03
EXT4/P04
VSS
VDD
EXT5/P05
ExtData3/Port03
ExtData4/Port04
Ground
Power
ExtData5/Port05
In/Output
In/Output
In/Output
45
46
47
48
49
EA0
EA1
EA2
NC
VDD
ExtAddress0
ExtAddress1
ExtAddress2
NoConnection
Power
16
17
18
19
20
P13/SOUT
EXT6/P06
P14/SS
EXT7/P07
P15/SK
Port13/SerialOutput
ExtData6/Port06
Port14/SerialSelect
ExtData7/Port07
Port15/SerialClock
In/Output
In/Output
In/Output
In/Output
In/Output
50
51
52
53
54
P23/UO1
/DS
P24/UO2
CLKI
CLKO
Port23/UserOutput1
ExtDataStrobe
Port24/UserOutput2
Clock/CrystalIn
Clock/CrystalOut
In/Output
Output
In/Output
Input
Input
21
22
23
24
P27
EXT8/P08
EXT9/P09
VSS
Port27
ExtData8/Port08
ExtData9/Port09
Ground
In/Output
In/Output
In/Output
55
56
57
58
P26
P22/UO0
P25/UI2
WAIT
Port26
Port22/UserOutput0
Port25/UserInput2
WaitforExt
In/Output
In/Output
In/Output
Input
25
26
27
28
29
EXT10/P010
VSS
EXT11/P011
VDD
VAHI
ExtData10/Port010
Ground
ExtData11/Port011
Power
AnalogHighRef.
In/Output
Input
59
60
61
62
63
/RES
VSS
VDD
VSS
EXT0/P00
Reset
Ground
Power
Ground
ExtData0/Port00
30
31
32
33
34
VSS
P16/UI0
VALO
P17/UI1
ANGND
Ground
Port16/UserInput0
AnalogLowRef.
Port17/UserInput1
AnalogGround
In/Output
Input
In/Output
Input
64
65
66
67
68
EXT1/P01
EXT2/P02
P10/INT2
VSS
P11/CLKOUT
ExtData1/Port01
ExtData2/Port02
Port10/Interrupt2
Ground
Port11/ClockOutput
DS95DSP0101 Q4/95
In/Output
In/Output
In/Output
Input
Input
Output
Input
Output
Output
Output
Input
In/Output
In/Output
In/Output
In/Output
In/Output
5
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
VSS
EXT0/P00
EXT1/P01
VSS
EXT2/P02
P20/INT0
EXT12/P012
EXT13/P013
VSS
EXT14/P014
EXT15/P015
PIN DESCRIPTION (Continued)
44 43 42 41 40 39 38 37 36 35 34
EXT3/P03
1
33
/RES
EXT4/P04
2
32
WAIT
VSS
3
31
P24/UO2
EXT5/P05
4
30
P22/UO0
EXT6/P06
5
29
CLK0
EXT7/P07
6
28
CLK1
INT1/P21
7
27
/DS
EXT8/P08
8
26
P23/UO1
EXT9/P09
9
25
EA2
VSS
10
24
EA1
EXT10/P010
11
23
EA0
Z89323/373
44-Pin QFP
RD//WR
VDD
ANVCC
AN3
AN2
AN1
AN0
ANGND
VALO
VAHI
EXT11/P011
12 13 14 15 16 17 18 19 20 21 22
Figure 4. 44-Pin QFP Z89323/373 Pin Configuration
Table 3. 44-Pin QFP Z89323/373 Pin Description
No.
Symbol
Function
Direction
No.
Symbol
Function
Direction
1
2
3
4
5
EXT3/P03
EXT4/P04
VSS
EXT5/P05
EXT6/P06
ExtData3/Port03
ExtData4/Port04
Ground
ExtData5/Port05
ExtData6/Port06
In/Output
In/Output
23
24
25
26
27
EA0
EA1
EA2
P23/UO1
/DS
ExtAddress0
ExtAddress1
ExtAddress2
Port23/UserOutput1
ExtDataStrobe
Output
Output
Output
In/Output
Output
6
7
8
9
10
EXT7/P07
P21/INT1
EXT8/P08
EXT9/P09
VSS
ExtData7/Port07
Port21/Interrupt1
ExtData8/Port08
ExtData9/Port09
Ground
In/Output
In/Output
In/Output
In/Output
28
29
30
31
32
CLKI
CLKO
P22/UO0
P24/UO2
WAIT
Clock/CrystalIn
Clock/CrystalOut
Port22/UserOutput0
Port24/UserOutput2
WaitforExt
Input
Input
In/Output
In/Output
Input
11
12
13
14
15
16
EXT10/P010
EXT11/P011
VAHI
VALO
ANGND
AN0
ExtData10/Port010
ExtData11/Port011
AnalogHighRef.
AnalogLowRef.
AnalogGround
A/DInput0
In/Output
In/Output
Input
Input
Input
Input
33
34
35
36
37
38
/RES
VSS
EXT0/P00
EXT1/P01
EXT2/P02
VSS
Reset
Ground
ExtData0/Port00
ExtData1/Port01
ExtData2/Port02
Ground
17
18
19
20
21
22
AN1
AN2
AN3
ANVCC
VDD
RD//WR
A/DInput1
A/DInput2
A/DInput3
AnalogPower
Power
R/WExternalBus
Input
Input
Input
Input
39
40
41
42
43
44
P20/INT0
EXT12/P012
EXT13/P013
EXT14/P014
VSS
EXT15/P015
Port20/Interrupt0
ExtData12/Port012
ExtData13/Port013
ExtData14/Port014
Ground
ExtData15/Port015
6
In/Output
In/Output
Output
Input
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
/RES
VCC
VSS
NC
64
P30
VSS
65
EXT0/P00
EXT2/P02
EXT1/P01
P10/INT2
70
69
68
67
66
VSS
P12/SIN
P11/CLKOUT
72
71
EXT12/P012
75
74
73
P20/INT0
VCC
EXT13/P013
76
EXT14/P014
63
62
61
P25/UI2
56
P26
55
CLKO
54
53
CLKI
52
/DS
P24/U02
P23/U01
50
VCC
49
48
47
46
NC
45
EA0
40
EA2
EA1
P36
44
HALT
43
42
41
NC
P35
RD//WR
VCC
ANVCC
VSS
INT1/P21
AN3
AN2
34
35
36
37
38
39
P22/UO0
51
19
20
EXT10/P010
P33
AN1
VSS
AN0
EXT9/P09
32
33
EXT8/P08
P37
WAIT
58
57
16
17
18
ANGND
P27
VAL0
P15/SK
14
15
P17/UI1
EXT7/P07
12
13
29
30
31
P14/SS
P16/UI0
EXT6/P06
VSS
P13/SOUT
Z89323
80-Pin QFP
10
11
VCC
EXT5/P05
VAHI
VCC
25
26
27
28
VSS
6
7
8
9
EXT11/P011
P32
EXT4/P04
NC
EXT3/P03
4
5
P34
NC
60
59
21
22
23
24
/EXTEN
1
2
3
VSS
NC
EXT15/P015
78
77
P31
80
79
VSS
P R E L I M I N A R Y
Figure 4a. 80-Pin QFP Z89323/373 Pin Configuration
DS95DSP0101 Q4/95
7
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
PIN DESCRIPTION (Continued)
Table 4a. 80-Pin QFP Z89323/373 Pin Description
No.
Symbol
Function
1
2
3
4
5
6
7
8
9
10
NC
EXT15/P015
/EXTEN
NC
EXT3/P03
P32
EXT4/P04
VSS
VDD
EXT5/P05
NoConnection
ExtData15/Port015
ExtEnable
NoConnection
ExtData3/Port03
Port32
ExtData4/Port04
Ground
Power
ExtData5/Port05
11
12
13
14
15
16
17
18
19
20
P13/SOUT
EXT6/P06
P14/SS
EXT7/P07
P15/SK
P27
EXT8/P08
EXT9/P09
VSS
P33
Port13/SerialOutput
ExtData6/Port06
Port14/SerialSelect
ExtData7/Port07
Port15/SerialClock
Port27
ExtData8/Port08
ExtData9/Port09
Ground
Port33
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
21
22
23
24
25
26
27
28
29
30
EXT10/P010
VSS
NC
P34
EXT11/P011
VDD
VAHI
VSS
P16/UI0
VAL0
ExtData10/Port010
Ground
NoConnection
Port34
ExtData11/Port011
Power
AnalogHighRef.
Ground
Port16/UserInput0
AnalogLowRef.
In/Output
31
32
33
34
35
36
37
38
39
40
P17/UI1
ANGND
AN0
AN1
AN2
AN3
VSS
P21/INT1
ANVCC
VDD
Port17/UserInput1
AnalogGround
A/DInput0
A/DInput1
A/DInput2
A/DInput3
Ground
Port21/Interrupt1
AnalogPower
Power
In/Output
Input
Input
Input
Input
Input
8
Direction
In/Output
Input
In/Output
Input
In/Output
In/Output
Input
Output
In/Output
Input
In/Output
Input
In/Output
Input
Input
No.
Symbol
Function
Direction
41
42
43
44
45
46
47
48
49
50
RD//WR
P35
NC
HALT
EA0
P36
EA1
EA2
NC
VDD
R/WExternalBus
Port35
NoConnection
HaltExecution
ExtAddress0
Port36
ExtAddress1
ExtAddress2
NoConnection
Power
51
52
53
54
55
56
57
58
59
60
P23/UO1
/DS
P24/UO2
CLKI
CLKO
P26
P22/UO0
P25/UI2
WAIT
P37
Port23/UserOutput1
ExtDataStrobe
Port24/UserOutput2
Clock/CrystalIn
Clock/CrystalOut
Port26
Port22/UserOutput0
Port25/UserInput2
WaitforExt
Port37
61
62
63
64
65
66
67
68
69
70
/RES
VSS
VDD
NC
VSS
P30
EXT0/P00
EXT1/P01
EXT2/P02
P10/INT2
Reset
Ground
Power
NoConnection
Ground
Port30
ExtData0/Port00
ExtData1/Port01
ExtData2/Port02
Port10/Interrupt2
71
72
73
74
75
76
77
78
79
80
VSS
P11/CLKOUT
P12/SIN
P20/INT0
EXT12/P012
EXT13/P013
VDD
EXT14/P014
VSS
P31
Ground
Port11/ClockOutput
Port12/SerialInput
Port20/Interrupt0
ExtData12/Port012
ExtData13/Port013
Power
ExtData14/Port014
Ground
Port31
Output
Output
Input
Output
Output
Output
Output
In/Output
Output
In/Output
Input
Input
In/Output
In/Output
In/Output
Input
Output
Input
Input
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
Input
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
EXT0/P00
PA0
VSS
VDD
77
76
PA2
82
81
78
EXT2/P02
83
EXT1/P01
P10/INT2
84
PA1
PA3
85
80
79
VSS
P11/CLKOUT
P20/INT0
89
88
87
86
P12/SIN
EXT12/P012
PA4
91
EXT13/P013
PA5
92
VDD
94
93
PA6
EXT14/P14
VSS
95
PA7
97
96
EXT15/P015
98
90
50
PD7
PD6
47
48
49
PD5
RD//WR
PD4
45
46
VDD
PD3
43
44
ANVCC
VSS
INT1/P21
AN3
39
40
41
42
AN2
PD0
VSS
37
38
EXT10/P010
22
23
24
25
AN1
VSS
PA15
AN0
PA14
ANGND
PA13
EXT9/P09
PD2
EXT8/P08
16
17
18
19
20
21
34
35
36
P27
PA12
14
15
UI1/P17
SK/P15
Z89393
100-Pin QFP
VALO
EXT7/P07
12
13
UI0/P16
PA11
SS/P14
10
11
30
31
32
33
EXT6/P06
VSS
SOUT/P13
VAHI
PA10
29
EXT5/P05
6
7
8
9
VDD
VDD
73
72
PD1
PA9
VSS
75
74
EXT11/P011
PA8
EXT4/P04
100
/PAZ
EXT3/P03
1
2
3
4
5
26
27
28
/EXTEN
99
P R E L I M I N A R Y
VSS
/RES
PD15
WAIT
71
PD14
70
69
68
P25/UI2
67
66
PD12
65
CLKO
64
63
62
61
CLKI
60
P23/UO1
PD13
P22/UO0
P26
P24/UO2
PD11
/DS
59
PD10
58
57
56
VDD
55
PD9
/ROMEN
EA2
54
EA1
53
PD8
52
51
EA0
HALT
Figure 5. 100-Pin QFP Z89393 Pin Configuration
DS95DSP0101 Q4/95
9
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
PIN DESCRIPTION (Continued)
Table 4. 100-Pin QFP Z89393 Pin Description
No.
Symbol
Function
Direction
No.
Symbol
Function
1
2
3
4
5
6
7
8
9
10
/EXTEN
EXT3/P03
PA8
EXT4/P04
PA9
VSS
VDD
EXT5/P05
PA10
P13/SOUT
EXTEnable
ExtData3/Port03
ProgramAddress8
ExtData4/Port04
ProgramAddress9
Ground
Power
ExtData5/Port05
ProgramAddress10
Port13/SerialOutput
Input
In/Output
Output
In/Output
Output
In/Output
Output
In/Output
51
52
53
54
55
56
57
58
59
60
HALT
EA0
PD8
EA1
PD9
EA2
/ROMEN
VDD
PD10
P23/UO1
HaltExecution
ExtAddress0
ProgramData8
ExtAddress1
ProgramData9
ExtAddress2
ROMEnable
Power
ProgramData10
Port23/UserOutput1
Input
In/Output
11
12
13
14
15
16
17
18
19
20
EXT6/P06
PA11
P14/SS
EXT7/P07
P15/SK
P27
PA12
EXT8/P08
PA13
EXT9/P09
ExtData6/Port06
ProgramAddress11
Port14/SerialSelect
ExtData7/Port07
Port15/SerialClock
Port27
ProgramAddress12
ExtData8/Port08
ProgramAddress13
ExtData9/Port09
In/Output
Output
In/Output
In/Output
In/Output
In/Output
Output
In/Output
Output
In/Output
61
62
63
64
65
66
67
68
69
70
/DS
PD11
P24/UO2
CLKI
CLKO
P26
PD12
P22/UO0
PD13
P25/UI2
ExtDataStrobe
ProgramData11
Port24/UserOutput2
Clock/CrystalIn
Clock/CrystalOut
Port26
ProgramData12
Port22/UserOutput0
ProgramData13
Port25/UserInput2
Output
Input
In/Output
Input
Input
In/Output
Input
In/Output
Input
In/Output
21
22
23
24
25
26
27
28
29
30
PA14
VSS
PA15
EXT10/P010
VSS
PD0
EXT11/P011
PD1
VDD
VAHI
ProgramAddress14
Ground
ProgramAddress15
ExtData10/Port010
Ground
ProgramData0
ExtData11/Port011
ProgramData1
Power
AnalogHighRef.
Output
Input
71
72
73
74
75
76
77
78
79
80
PD14
WAIT
PD15
/RES
VSS
VDD
VSS
PA0
EXT0/P00
PA1
ProgramData14
WaitforExt
ProgramData15
Reset
Ground
Power
Ground
ProgramAddress0
ExtData0/Port00
ProgramAddress1
31
32
33
34
35
36
37
38
39
40
VSS
P16/UI0
VALO
P17/UI1
PD2
ANGND
AN0
AN1
AN2
AN3
Ground
Port16/UserInput0
AnalogLowRef.
Port17/UserInput1
ProgramData2
AnalogGround
A/DInput0
A/DInput1
A/DInput2
A/DInput3
In/Output
Input
In/Output
Input
Input
Input
Input
Input
Input
81
82
83
84
85
86
87
88
89
90
EXT1/P01
PA2
EXT2/P02
P10/INT2
PA3
VSS
P11/CLKOUT
P12/SIN
P20/INT0
PA4
ExtData1/Port01
ProgramAddress2
ExtData2/Port02
Port10/Interrupt2
ProgramAddress3
Ground
Port11/ClockOutput
Port12/SerialInput
Port20/Interrupt0
ProgramAddress4
In/Output
Output
In/Output
In/Output
Output
41
42
43
44
45
46
47
48
49
50
VSS
P21/INT1
ANVCC
PD3
VDD
PD4
PD5
RD//WR
PD6
PD7
Ground
Port21/Interrupt1
AnalogPower
ProgramData3
Power
ProgramData4
ProgramData5
R/WExternalBus
ProgramData6
ProgramData7
91
92
93
94
95
96
97
98
99
100
EXT12/P012
PA5
EXT13/P013
VDD
EXT14/P014
PA6
VSS
PA7
EXT15/P015
/PAZ
ExtData12/Port012
ProgramAddress5
ExtData13/Port013
Power
ExtData14/Port014
ProgramAddress6
Ground
ProgramAddress7
ExtData15/Port015
Tri-stateProgramBus
In/Output
Output
In/Output
10
Output
In/Output
Input
In/Output
Input
In/Output
Input
Input
Input
Input
Output
Input
Input
Direction
Input
Output
Input
Output
Input
Output
Input
Input
Input
Input
Input
Output
In/Output
Output
In/Output
In/Output
In/Output
Output
In/Output
Output
Output
In/Output
Input
DS95DSP0101 Q4/95
P R E L I M I N A R Y
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
PIN FUNCTIONS
CLKO-CLKI Clock (output/input). These pins act as the
clock circuit input and output.
Priority is: INT2 = lowest, INT0 = highest. (Note: INT2 pin
is not bonded out on the 44-pin QFP or PLCC packages.)
EXT15-EXT0 External Data Bus (input/output). These pins
act as the data bus for user-defined outside registers, such
as an ADC or DAC. The pins are normally tri-stated, except
when the outside registers are specified as destination
registers in the instructions. All the control signals exist to
allow a read or a write through this bus. If user I/O Port 0
is enabled, these signals function as user Programmable
I/O.
/RES Reset (input, active Low). This pin controls the
asynchronous reset signal. The /RES signal must be kept
Low for at least one clock cycle (clock output of the PLL
block). The CPU pushes the contents of the Program
Counter (PC) onto the stack and then fetches a new PC
value from program memory address 0FFCH (or FFFCH for
the Z89393) after the reset signal is released.
RD//WR Read/Write Strobe (output). This pin controls the
data direction signal for the EXT-Bus. Data is available
from the CPU on EXT15-EXT0 when this signal is Low. EXTBus is in input mode (high-impedance) when this signal is
High.
WAIT WAIT State (input). The wait signal is sampled at the
rising edge of the clock with appropriate setup and hold
times. The normal write cycle will continue when wait is
inactive on a rising clock. A single wait-state can be
generated internally by setting the appropriate bits in the
wait state register (Bank 15/Ext 3) (active high).
EA2-EA0 External Address (output). These pins control
the user-defined register address output (latched). One of
eight user-defined external registers is selected by the
processor with these address pins for read or write
operations. Since the addresses are part of the processor
memory map, the processor is simply executing internal
reads and writes. External Addresses are used internally
by the processor if the ADC, bit I/O (Port 0- 2), or SPI are
enabled. (See the banks allocation of the EXT registers in
Tables 6 and 7.)
P00-P015 Port 0 (input/output). These pins control Port 0
input and output when EXT I/F is not in use.
/DS Data Strobe (output). This pin control the data strobe
signal for EXT-Bus. Data is read by the external peripheral
on the rising edge of /DS. Data is also read by the
processor on the rising edge of CK.
P30-P37 Port 3 Port3 (3:0) are four inputs and P3 (7:0) are
four outputs.
HALT Halt State (input). This pin controls Stop Execution.
The CPU continuously executes NOPs and the program
counter remains at the same value when this pin is held
High. An interrupt request must be executed (enabled) to
exit HALT mode. After the interrupt service routine, the
program continues from the instruction after the HALT
(active high).
/INT0-/INT2 Three Interrupts (input, active on rising edge).
These pins control interrupt requests 0-2. Interrupts are
generated on the rising edge of the input signal. Interrupt
vectors for the interrupt service starting address are stored
in the following program memory locations:
Device
/INT0
/INT1
/INT2
Z89323/373
Z89393
1FFFH
FFFFH
1FFEH
FFFEH
1FFDH
FFFDH
DS95DSP0101 Q4/95
P10-P17 Port 1 (input/output). These pins are used for
Port 1 programmable bit I/O when INT2, CLKOUT, SPI, or
UI0-1 are not being used.
P20-P27 Port 2 (input/output). These pins control Port 2
input or output when UI2, UO0-2 or INT0-INT1 are not
being used.
UI1-UI0 Two Input Pins (input). These general-purpose
input pins are directly tested by the conditional branch
instructions. These are asynchronous input signals that
have no special clock synchronization requirements.
UO1-UO0 Two Output Pins (output). These generalpurpose output pins reflect the value of two bits in the
status register S5 and S6. These bits have no special
significance and may be used to output data by writing to
the status register. Note: The user output value is the
opposite of the status register content.
SIN/SOUT. When enabled, these pins control SPI input
and output.
AN0-AN3. These pins are used for Analog-to-Digital
converter input.
ANGND and ANVCC. Analog to Digital ground and power
supply.
11
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
PIN FUNCTIONS (Continued)
VAHI and VALO. Analog to Digital reference voltages.
/PAZ Tri-state Program Bus. This pin enables the Program
Address bus for emulation purposes.
/EXTEN Ext Enable. This pin enables Ext output
continuously for emulation purposes.
/ROMEN ROM Enable. This pin selects internal or external
Program Memory.
ADDRESS SPACE
Program Memory. Programs of up to 8 Kwords can be
masked into internal ROM (OTP for Z89373). Four locations
are dedicated to the vector address for the three interrupts
(IFFDH-IFFFH) and the starting address following a Reset
(IFFCH). Internal ROM is mapped from 0000H to IFFFH,
and the highest location for program is IFFBH.
Internal Data RAM. The Z89323 has an internal 512 x 16bit word data RAM organized as two banks of 256 x 16-bit
words each: RAM0 and RAM1. Each data RAM bank is
addressed by three pointers: Pn:0 (n = 0-2) for RAM0 and
Pn:1 (n = 0-2) for RAM1. The RAM addresses for RAM0 and
RAM1 are arranged from 0-255 and 256-511, respectively.
The address pointers, which may be written to, or read
from, are 8-bit registers connected to the lower byte of the
internal 16-bit D-Bus and are used to perform modulo
addressing. Three addressing modes are available to
access the Data RAM: register indirect, direct addressing,
and short form direct. The contents of the RAM can be read
to, or written from, in one machine cycle per word, without
disturbing any internal registers or status other than the
RAM address pointer used for each RAM. The contents of
each RAM can be loaded simultaneously into the X and Y
inputs of the multiplier.
Registers. The Z89323 has 19 internal registers and eight
external registers and a secondary set of 15 peripheral
control registers. Both external and internal registers are
accessed in one machine cycle. The external registers are
used to access the on-chip peripherals when they are
enabled.
Program Memory
Data Memory
FFFF
FFFF
FFFC
Not Used
Not Used
512 words
DRAM1
DRAM0
01FF
0100
00FF
4 Kwords
INT0-INT2 Vect.
RESET Vector
0000
INT0-INT2 Vect.
RESET Vector
64 Kwords
Or
0FFF
0FFC
0000
On-Chip Memory
(Z89323/371)
Off-Chip Memory
(Z89393)
Figure 6. Memory Map
12
DS95DSP0101 Q4/95
P R E L I M I N A R Y
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
REGISTERS
The internal registers of the Z89323/373/393 are defined
below:
Register
Register Definition
P
X
Y
A
Output of Multiplier, 24-bit
X Multiplier Input, 16-bit
Y Multiplier Input, 16-bit
Accumulator, 24-bit
SR
Pn:b
PC
Status Register, 16-bit
Six Ram Address Pointers, 8-bit each
Program Counter, 16-bit
EXT 0
EXT 1
EXT 2
EXT 3
EXT 4
EXT 5
EXT 6
EXT 7
See Table 6 and Table 7 for the different assignments of
EXT7-EXT0 in the different banks.
Register
Register Definition
EXTn
BUS
Dn:b
External Registers, 16-bit
D-Bus
Eight Data Pointers*
Note:
* These data pointers occupy the first four locations in RAM bank.
P holds the result of multiplications and is read-only.
X and Y are two 16-bit input registers for the multiplier.
These registers can be utilized as temporary registers
when the multiplier is not being used.
A is a 24-bit Accumulator. The output of the ALU is sent to
this register. When 16-bit data is transferred into this
register, it is placed into the 16 MSBs and the least
significant eight bits are set to zero. Only the upper 16 bits
are transferred to the destination register when the
Accumulator is selected as a source register in transfer
instructions.
DS95DSP0101 Q4/95
Pn:b are the pointer registers for accessing data RAM, (n
= 0,1,2 refer to the pointer number) (b = 0,1 refers to RAM
Bank 0 or 1). They can be directly read from or written to,
and can point to locations in data RAM or Program Memory.
EXTn are external registers (n = 0 to 7). There are eight 16bit registers provided here for mapping external devices
into the address space of the processor. Note that the
actual register RAM does not exist on the chip, but would
exist as part of the internal or external device, such as an
ADC.
BUS is a read-only register which, when accessed, returns
the contents of the D-Bus. Bus is used for emulation only.
Dn:b refers to locations in RAM that can be used as a
pointer to locations in program memory which is efficient
for coefficient addressing. The programmer decides which
location to choose from two bits in the status register and
two bits in the operand. Thus, only the lower 16 possible
locations in RAM can be specified. At any one time, there
are eight usable pointers, four per bank, and the four
pointers are in consecutive locations in RAM. For example,
if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/
D3:0 refer to register locations 4/5/6/7 in RAM Bank 0. Note
that when the data pointers are being written to, a number
is actually being loaded to Data RAM, so they can be used
as a limited method for writing to RAM.
SR is the status register (Figure 8) which contains the ALU
status and certain control bits (Table 5).
Table 5. Status Register Bit Functions
Status Register Bit
S15
S14
S13
S12
S11
S10
(N)
(OV)
(Z)
(L)
(UI1)
(UI0)
S9 (SH3)
S8 (OP)
S7 (IE)
S6 (UO1)
S5 (UO0)
S4-S3
S2-S0 (RPL)
Function
ALU Negative
ALU Overflow
ALU Zero
Carry
User Input 1
User Input 0
MPY Output Arithmetically
Shifted Right by three bits
Overflow Protection
Interrupt Enable
User Output 1
User Output 0
“Short Form Direct” bits
RAM Pointer Loop Size
13
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
REGISTERS (Continued)
The Status Register
The status register can always be read in its entirety. S15S10 are set/reset by hardware and can only be read by
software. S9-S0 control hardware looping and can be
written by software (Table 8).
S15-S12 are set/reset by the ALU after an operation. S11S10 are set/reset by the user inputs. S6-S0 are control bits
described in Table 5. S7 enables interrupts. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiple/shift
option is used, then the shifter shifts the result three bits
right. This feature allows the data to be scaled and prevents
overflows.
Table 8. RPL Description
S2
S1
S0
Loop Size
0
0
0
0
0
0
1
1
0
1
0
1
256
2
4
8
1
1
1
1
0
0
1
1
0
1
0
1
16
32
64
128
PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.
N
OV
Z
C
UI1
UI0
SH3
OP
IE
S15
S14
S13
S12
S11
S10
S9
S8
S7
UO1 UO0
S6
S5
RPL
S4
S3
S2
S1
S0
Ram
Pointer
000
001
010
011
100
101
110
111
Negative
Overflow
Zero
Carry
User Input 0-1
(Read Only)
MPY output arithmetically
shifted right by three bits
Loop
Size
256
2
4
8
16
32
64
128
"Short Form Direct" bits
Overflow protection
User Output 0-1*
Global Interrupt Enable
* The output value is the opposite of the status register content.
Figure 7. Status Register
14
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
EXT Register Assignments
The EXT registers support is extended in the Z893X3
family: In addition to up to seven external registers, there
are 28 internal registers on the EXT bus. There are 16
different pages of EXT registers. The same EXT7 register
exist in all the pages and control of the bank switching is
done via EXT7 register.
Banks 0 to 5 support different combinations of external
registers and internal data registers. The user should use
the bank that has the internal data registers and the
number of external registers to support his application and
to use this bank as a working bank to minimize the number
of bank switching. Bank 5 has all the A/D registers. Banks
13 to 15 are control registers bank. These control registers
are usually used only in the initialization routines.
Table 6. EXT Register Assignments Banks 0–4
EXT\Bank
0
1
2
3
4
EXT0
EXT1
EXT2
EXT3
Ext0-user
Ext1-user
Ext2-user
SPI data
Ext0-user
Ext1-user
Ext2-user
Ext3-user
Ext0-user
Ext1-user
Ext2-user
Ext3-user
Ext0-user
Ext1-user
Ext2-user
SPI data
Ext0-user
Ext1-user
Ext2-user
Ext3-user
EXT4
EXT5
EXT6
EXT7
Port0
Port1/Port2
A/D_ch0
Bank/Int_status
Port0
Port1/Port2
A/D_ch1
Bank/Int_status
Ext4-user
Port3
A/D_ch2
Bank/Int_status
Ext4-user
Ext5-user
A/D_ch3
Bank/Int_status
Ext4-user
Ext5-user
Ext6-user
Bank/Int_status
Table 7. EXT Register Assignments Banks 6–15
EXT\Bank
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
5
A/D_ch1
A/D_ch2
A/D_ch3
SPI data
Port0
Port1/Port2
A/D_ch0
Bank/Int_status
DS95DSP0101 Q4/95
6-12
13
14
15
A/D_ch0
Bank/Int_status
A/D control
Timer0 control
Timer0 load
Timer0
Timer0 pr. load
Timer0 prescaler
A/D_ch0
Bank/Int_status
Timer2 load
Timer1 control
Timer1 load
Timer1
Timer1 pr. load
Timer1 prescaler
A/D_ch0
Bank/Int_status
P0 control
P1 control
P2 control
Wait State
SPI control
PLL control
Int. Allocation
Bank/Int_status
15
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
EXT Register Assignments (Continued)
Ext 7 Reg
D15 D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bank Select
0000 : Bank0
0001 : Bank1
:
:
1111 : Bank15
Interrupt Status Bits
Bit 4 = A/D Finish Interrupt
Bit 5 = SPI Interrupt
Bit 6 = Timer0 Interrupt
Bit 7 = Timer1 Interrupt
Bit 8 = Timer2 Interrupt
Bit 9 = INT0 (H/W) Interrupt
Bit 10 = INT1 (H/W) Interrupt
Bit 11 = INT2 (H/W) Interrupt
Reserved
Figure 8. EXT7 Register Bit Assignment
Interrupt Status Bits
When read, these bits provide interrupt information to
identify the source for INT2, or when the DSP works in
Pending Interrupt mode, to warn the DSP of pending
interrupts. These bits also clear the interrupt status bits.
Writing 1 will clear these bits.
Wait-State Register
The Wait-State Control Register enables insertion of Wait
States when the DSP needs to access slow, inexpensive
peripherals. This software-controlled register enables
insertion of one Wait State when accessing EXT bus. (One
Wait State gives 100 nsec access time instead of 50 nsec
16
access time with a 20 MHz oscillator.) When more than one
Wait State is needed, an input pin (WAIT) coupled with
external logic can support more than one Wait State. The
Wait-State Control Register enables mapping specific EXT
register (from EXT0 to EXT6) and specific operation (read
or write) to include insertion of one Wait State. EXT7 is
always internal register, therefore no Wait State is needed
for EXT7.
Note:
When the programmer switches banks it is important to change the Wait
State mapping of the EXT registers to match the desired Wait State
mapping of the new bank.
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Bank15/EXT3 Reg
D15 D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bits 1 - 0 = Wait-State EXT0
Bits 3 - 2 = Wait-State EXT1
Bits 5 - 4 = Wait-State EXT2
Bits 7 - 6 = Wait-State EXT3
Bits 9 - 8 = Wait-State EXT4
Bits 11 -10 = Wait-State EXT5
Bits 13 -12 = Wait-State EXT6
Bit14 = Reserved
Bit 15 = Test Mode
0 Normal Operation (default)
1 Test Mode: Bits 6-5 of the
Status Register drives,
P23 and P22, respectively
(VO0 and VO1).
Figure 8a. Bank 15/EXT3 Register
DS95DSP0101 Q4/95
17
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
FUNCTIONAL DESCRIPTION
Analog to Digital Converter (ADC)
The ADC is an 8-bit half flash converter that uses two
reference resistor ladders for its upper 4 bits (Most
Significant Bits) and lower 4 bits (Least Significant Bits)
conversion. Two reference voltage pins, VA (High) and VA
(Low), are provided for external reference voltage supplies.
During the sampling period from one of the four channel
inputs, the converter is also being auto-zeroed before
starting the conversion. The conversion time is dependent
on the external clock frequency and the selection of the
prescaler value for the internal ADC clock source. The
minimum conversion time is 2.0 µs. (See Figure 9, ADC
Architecture.)
The ADC control register is Bank 13/Ext 0. A conversion
can be initiated in one of four ways: by writing to the
A/D control register, INT1 input pin, Timer 2 or Timer 0
equal 0. These four are programmable selectable. There
are four modes of operation that can be selected: one
channel converted four times with the results written to
each Result register, one channel continuously converted
and one Result channel updated for each conversion, four
channels converted once each and the four results written
to the Result registers, and four channels repeatedly
converted and the Result registers kept updated. The
channel to be converted is programmable and if one of the
four-channel modes is selected then the programmed
channel will be the first channel converted and the other
three will be in sequence following with wraparound from
Channel 3 to Channel 0.
18
The start commands are implemented in such a way as to
begin a conversion at any time, if a conversion is in
progress and a new start command is received, then the
conversion in progress will be aborted and a new conversion
will be initiated. This allows the programmed values to be
changed without affecting a conversion-in-progress. The
new values will take effect only after a new start command
is received.
The clock prescaler can be programmed to derive a
minimum 2 µs conversion time for clock inputs from 4 MHz
to 20 MHz. For example, with a 20 MHz crystal clock the
prescaler should be programmed for divide by 40, which
then gives a 2 µs conversion rate.
The ADC can generate an Interrupt after either the first or
fourth conversion is complete depending on the
programmable selection.
The ADC can be disabled (for low power) or enabled by a
Control Register bit.
Though the ADC will function for a smaller input voltage
and voltage reference, the noise and offsets remain constant
during the specified electrical range. The errors of the
converter will increase and the conversion time may also
take slightly longer due to smaller input signals.
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
INT0
Timer
Start
Converter
A/D
Controller
Register
A/D
Prescaler
Integrated
Logic
VREF
4-Channel
Multiplexer
Sample
and
Hold
4x8
Result
Register
Internal
Bus
Flash
A/D
Converter
Dual
AGND
Scan
A/D
Channel
Register
Channel Select
Figure 9. ADC Architecture
DS95DSP0101 Q4/95
19
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION (Continued)
Channel Select (bits 2, 1, 0)
Bank 13/Ext 0 (low byte)
D7 D6 D5 D4 D3 D2 D1 D0
CSEL2
CSEL0
CSEL1
CSEL2
SCAN
0
0
0
0
CSEL1
CSEL0
Channel
0
0
1
1
0
1
0
1
0
1
2
3
QUAD
D0
D1
D2
Bank 13/Ext 0 (high byte)
D15 D14 D13 D12 D11 D10 D9
Figure 10. ADCTL Register (Low Byte)
D8
ADST0
ADST1
ADIE
Prescaler Values (bits 7, 6, 5)
ADIT
D1
D0
Prescaler
(Crystal divided by)
0
0
0
0
0
0
1
1
0
1
0
1
8
16
24
32
1
1
1
1
0
0
1
1
0
1
0
1
40
48
56
64
D2
Note:
The ADC is currently being characterized. Converter errors are estimated
to increase to 2 LSBs (Integral non-linearity), 1 LSB (Differential nonlinearity) and 10 mV (Zero error at 25°C) if the voltage swing on the
reference ladder is decreased to –3V.
Modes (bits 4, 3)
QUAD
SCAN
0
0
0
1
1
1
0
1
20
Convert selected channel 4 times
then stop.
Convert selected channel then stop.
Convert 4 channels then stop.
Convert 4 channels continuously.
ADCINT
Reserved
ADE
Figure 11. ADCTL Register (High Byte)
ADE (bit 15). A
0
disables any A/D conversions or
access–ing any ADC registers except writing to ADE bit. A
1 Enables all ADC accesses.
Reserved (bits 14, 13). Reserved for future use.
ADCINT (bit 12). This is the ADC Interrupt bit and is Read
Only. The ADCINT will be reset any time this register is
written.
ADIT (bit 11). This bit selects when to set the ADC Interrupt
if ADIE=1. A value of 0 sets the Interrupt after the first A/D
conversion is complete. A value of 1 sets the Interrupt after
the fourth A/D conversion is complete.
ADIE (bit 10). This is the ADC Interrupt Enable. A value of
0 disables setting the ADC Interrupt. A value of 1 enables
setting the ADC Interrupt.
DS95DSP0101 Q4/95
P R E L I M I N A R Y
START (bits 9, 8)
ADST1
ADST0
0
0
0
1
1
0
1
1
Mode
Conversion starts when
this register is written.
Conversion starts on a
rising edge INT1 input pin.
Conversion starts when
Timer 2 times out.
Conversion starts when
Timer 0 times out.
There are four ADC result registers. For their location in the
different banks, see EXT Register Assignments.
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
Figure 12 shows the input circuit of the ADC. When
conversion starts, the analog input voltage from one of the
eight channel inputs is connected to the MSB and LSB
flash converter inputs as shown in the Input Impedance
CKT diagram. This effectively shunts 31 parallel internal
resistance of the analog switches and simultaneously
charges 31 parallel 0.5 pF capacitors, which is equivalent
to seeing a 400 Ohms input impedance in parallel with a
16 pF capacitor. Other input stray capacitance adds about
10 pF to the input load. For input source, resistances up to
2 kOhms can be used under normal operating conditions
without any degradation of the input settling time. For
larger input source resistance longer conversion cycle
time may be required to compensate the input settling time
factor.
CMOS Switch
on Resistance
2-5kΩ
V Ref
R Source
C .5 pF
V Ref
C .5 pF
C Parasitic
V Ref
31 CMOS Digital
Comparators
C .5 pF
Figure 12. Input Impedance of ADC
DS95DSP0101 Q4/95
21
22
Note:
1. SCLK = 20 MHz
DSP Write to ADC
CTL REG
DSP INT
A/D Result
Input Sample
CHAN MUX
INT0
SCLK 1
1
2
3
4
5
6
7
9
10
11
26
Figure 13. ADC Timing Diagram
8
27
28
29
30
31
32
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
FUNCTIONAL DESCRIPTION (Continued)
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
TIMER/COUNTERS
The Z89323/373/393 has two 16-bit Timer/Counters that
can be independently configured to operate in various
modes. Each is implemented as a 16-bit Load Register
(TMLR) and a 16-bit down counter (TMR). Timer/Counter
inputs can be selected from among UI0 or UI1 pins and
outputs from among UO0 or UO1 pins. The Timer/Counter
clock is a scaled version of system clock. Each counter has
an 8-bit clock prescaler with divide count controlled by the
16-bit Prescaler Load Register (TPLR). The clock rates of
the two timer/counters are independent of each other.
External input events occur optionally on the rising edge,
15
Test
14
13 12 11
8
MODE
7
OUT
INV
the falling edge, or both rising and falling edges of the
input. Output actions on external pins can be programmed
to occur with either polarity. The Timer/Counter operational
modes are selected through the 16-bit Control Register
(TCTL). This register defines the operational modes of its
companion Timer (Figure 14).
Each Timer contains a set of five 16-bit Registers. The Ext
Register Assignment specifies the location of each Timer
Registers. All accesses to Timer Registers occur with zero
Wait States.
6
5 4
OUT
SEL
3 2
INP
EVENT
1
INP
SEL
0
CE
Count Enable
Input Select
Input Event
Output Select
Output Invert
Timer Mode
Reserved
Test Mode
Figure 14. TCTL Register
DS95DSP0101 Q4/95
23
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
TIMER/COUNTERS (Continued)
Timer Modes
The Timer modes can be categorized as input modes and
output modes. In input modes, the Timer/Counter is used
for input signals only. In output modes, a selected output
pin is driven. If a Timer/Counter is enabled (CE=1) and an
output pin, UO0 or UO1, is selected to be driven, the DSP
Processor’s Status Register bits 5 or 6 does not affect the
state of that pin.
MODE 5. The Timer/Counter is configured to generate an
output pulse that is asserted under program control, and
de-asserted when a programmable number of input edges
(up to 65,535) have been counted on an input pin (UI0 or
UI1). Assertion may be either logic high or logic low.
MODE 6. The Timer/Counter is configured to generate a
Hardware Reset on time-out unless retriggered by software.
Output Modes
MODE 0. The Timer/Counter is configured to generate a
continuous square wave of 50% duty cycle. Writing a new
value to the TMLR Register takes effect at the end of
current cycle unless TMR is written.
MODE 7. The Timer/Counter is configured to generate a
Hardware Reset on time-out unless retriggered by an
event on one of the input pins UI0 or UI1.
Input Modes
MODE 1. The Timer/Counter is configured to generate a
single pulse of programmable duration. The asserted state
may be either logic high or logic low. Retriggering the oneshot before the end of the pulse causes it to continue for the
new duration.
The input modes use one of the input pins UI0 or UI1. The
signals on these pins are synchronized with the internal
Timer Clock, TMCLK, before being applied to the Timer.
The input signal frequency must be no higher than 1/4th of
TMCLK frequency.
MODE 2. The Timer/Counter is configured to generate a
pulse-width modulated repeating waveform. The duty cycle
ranges from 0–100% (0/256 to 255/256) of a cycle in steps
of 1/256 of a cycle. The asserted state of the waveform may
be either logic high or logic low. Writing a new pulse-width
value to the TMLR Register takes effect at the end of
current cycle unless TMR is written.
MODE 8. The Timer/Counter is configured to measure the
time for which its input is asserted.
MODE 3. The Timer/Counter is configured to generate a
pulse-width modulated repeating waveform. The duty cycle
ranges from 0–100% (0/65,536 to 65,535/65,536) of a
cycle in steps of 1/65,536 of a cycle. The asserted state of
the waveform may be either logic high or logic low. Writing
a new pulse-width value to the TMLR Register takes effect
at the end of current cycle unless TMR is written.
MODE 9. The Timer/Counter is configured to measure the
period from one rising (falling) edge to the next rising
(falling) edge on the input.
MODE 10. The Timer/Counter is configured to count the
number of input edges (up to 65,535). Input edges may be
selected as rising or falling or both.
MODE 11. The Timer/Counter is configured to count the
number of input edges (up to 65,535) in a time window set
by the second timer. Edges are counted until the second
timer under flows. Input edges may be selected as rising
or falling or both.
MODE 4. The Timer/Counter is configured to generate a
series of pulses ranging from 0 to 65,535. The pulses are
actually the Timer Clock (TMCLK), which is gated to the
output until the counter under flows.
24
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Bank 13/EXT1 (Timer0) or Bank 14/EXT1 (Timer1)
Timer Control Register (TCTL)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Timer/Counter
0 Timer/Counter disabled (default)
1 Timer/Counter enabled
Input Select
00 Inputs have no effect
01 Reserved
10 UI0 Pin
11 UI1 Pin
Input Event
00 Low Level or Falling Edge
01 High Level or Rising Edge
10 Both Rising and Falling Edges
11 Reserved
Output Select
00 Outputs Unaffected
01 Reserved
10 Drive UO0 Pin
11 Drive UO1 Pin
Output Invert
0 Output asserted High on Timeout
1 Output asserted Low on Timeout
Timer Mode
Timer Output Modes
0000 Square Wave
0001 One-Shot
0010 PWM short (8-bit)
0011 PWM long (16-bit)
0100 Pulse Count Output
0101 Triggered Count
0110 S/W Watch-Dog Mode
0111 H/W Watch-Dog Mode
Timer Input Modes
1000 Gated Count
1001 Period
1010 Pulse Count
1011 Gated Pulse Count
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Mode 8
Mode 9
Mode 10
Mode 11
Reserved
Test Mode*
0 Normal Operation
1 Factory Test Mode
*Note: The user should always
program this bit to be 0.
Figure 15. Register Bit Fields
DS95DSP0101 Q4/95
25
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
TIMER/COUNTERS (Continued)
Timer Load Register (TMLR)
This 16-bit Register holds a value that is reloaded into timer
upon timer under flow.
15
0
Timer Reload Value
Timer Prescaler Load Register (TPLR)
The 16-bit TPLR Register holds the prescaler reload value
in its lower 8 bits. Bit 15 is the Timer's Interrupt Pending bit.
When set, it signifies an interrupt event in its companion
timer. The IP bit can only be set by the Timer. It can be
cleared only by software when it writes a value to this
register with a "1" in bit position 15; a "0" in bit position 15
will have no effect on the state of IP bit. Bits [14:8] must
always be written with 0s for future compatibility.
15
Test
14
0
8 7
Zeros
Prescaler
Reload Value
Timer Register (TMR)
TMR is a 16-bit down counter that holds the current Timer/
Counter value. It can be read as any ordinary register.
However, writing to TMR is different than writing to an
ordinary register. A write to TMR Register causes the
contents of TMLR Register to be written into it, causing the
Timer to be retriggered. Any data on DSP’s Memory Data
(MD) Bus is ignored during a write to TMR.
15
0
Timer Register
Timer Prescale Register (TPR)
TPR is an 8-bit down counter that holds the current Prescaler
count value. It can be read as any ordinary register.
However, writing to TPR is different than writing to an
ordinary register. A write to TPR Register causes the lower
8-bit contents of TPLR Register to be written into it, causing
the Prescaler to be retriggered. Any data on DSP’s Memory
Data (MD) Bus is ignored during a write to TPR.
0
7
TPR
8-Bit Counter
26
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Prescaler Operation
The Timer/Counter Clock (TMCLK) is generated by the
output of the prescaler. The Prescaler is an 8-bit down
counter, TPR, followed by a divide-by-two flip-flop that
generates a 50 percent duty cycle output clock TMCLK.
The Prescaler’s input clock is the system clock, CLKIN,
divided by two. Thus, the maximum prescaler output
frequency is 1/4 of the system clock frequency.
The 8-bit prescaler counter is loaded with value in TPLR
Register field [7:0] in one of three ways:
Once the prescaler counter is loaded, it decrements at its
clocked frequency and generates an output to the divideby-two flip-flop. When the count reaches 0, the counter is
reloaded from the lower 8 bits of TPLR Register.
3. When companion Timer/Counter TMR is reloaded
upon under flow from its TMLR Register, or
retriggered by writing directly to TMR Register.
15
IP
14
8
Zeros
Clock
(System Clock)
1. When 8-bit prescaler counter, TPR,
decrements to zero.
2. By writing to TPR Register.
7
0
TPLR
Register
Prescaler
Reload Value
DIV
by 2
TPR
8-Bit Counter
TMCLK
Figure 16. Prescaler Block Diagram
15
0
TMLR Register
15
UIO
M
U
X
UI1
TMCLK
0
TMR Register
16-Bit Counter
S
E
L
U00
U01
Figure 17. Counter/Timer Block Diagram
DS95DSP0101 Q4/95
27
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
TIMER/COUNTERS (Continued)
16-Bit General-Purpose Timer/Counter T2
The 16-bit timer/counter is available for general-purpose
use. When the counter counts down to the zero state, the
timer 2 load register loads into timer 2, and if timer 2
interrupt is enabled, an interrupt is received. The counting
operation of the counter can be disabled. The timer/
counter clock source can be selected to be system clock/
2 or UI2.
The counter is defaulted to the Enable state. If the system
designer does not choose to use the timer, the counter can
be disabled.
Bank 14/EXT 0
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Count Value (Down-Counter)
Figure 18. Timer/Counter 2 Load Register
I/O Ports
I/O pin allocation for ports in the different package types is
designed to provide increased flexibility and support for
various modes of operation. The 44-pin package features
the special signals, as well as all packages supporting the
EXT 16-bit bus. In cases where the application does not
require an external EXT bus, these I/O pins can be allocated
to 16-bit general-purpose I/O port (P0), the special signals
port (P1) or additional port (P3). The 80-pin PQFP package
supports up to 40 I/O pins.
Table 9. Various Package I/O Port Allocation
Pin Count
Package
44-Pin
PLCC/PQFP
68-Pin
PLCC
80-Pin
PQFP
100-Pin
PQFP†
P0[15:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
EXT,P0,P1*
EXT,P0
EXT,P0
EXT,P0
P1*
P2*
EXT,P0
EXT,P0
P1*
P2*
P3
EXT,P0
EXT,P0
P1*
P2*
P2[4:0]*
Note:
* Ports with special signals: Interrupts inputs, Serial Peripheral Interface
(SPI), CLKOUT and Timers inputs and outputs.
† (ICE chip)
28
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
16-bit Programmable I/O (Port 0)
When the appropriate bit is set in the Port 1 control register,
Port 0 acts as a 16-bit programmable, bidirectional, CMOScompatible port. Each of the 16 lines can be independently
programmed as an input or an output, or globally as an
open-drain output. When enabled, Bank 0/Ext 4 acts as the
data I/O register. Bank 15/Ext 0 serves as the Port 0
direction register while Bank 15/Ext 1, has specified bits to
enable Port 0 and determine whether Port 0 is globally
configured as open-drain outputs.
Bank 15/Ext 0 Reg
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Port I/O Direction
0 = Output
1 = Input
Figure 19. Port 0 Control Register
Open-Drain
OEN
Pad
Out
In
Auto Latch
R ≈ 500 kOhms
Figure 20. Port 0, 1 and 2 Configuration
DS95DSP0101 Q4/95
29
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
8-Bit Programmable I/O (Port 1)
When the appropriate bit is set in the Port 1 control register,
Port 1 acts as an 8-bit programmable, bi-directional,
CMOS-compatible port. Each of the eight lines can be
independently programmed as an input or an output or
globally as an open-drain output. When enabled,
Bank0/EXT5 (Least Significant Bit) acts as the data I/O
register. Bank15/EXT1 serves as the Port1 direction control
register. Port 1 can also be programmed to provide special
I/O functions.
Table 10. Port 1 Bit Function Selection
Port.Bit
IF (Condition Explanation)
Then
Else
P1.0
P1.1
P1.2
P1.3
Bank15/Ext1(3)=1
Bank15/Ext1(5)=1
Bank15/Ext4(0)=1
Bank15/Ext4(0)=1
INT2
CLKOUT
SIN
SOUT
P10
P11
P12
P13
P1.4
P1.5
P1.6
P1.7
Bank15/Ext4(0)=1 (SPI Enable)
Bank15/Ext4(0)=1 (SPI Enable)
Bank13/Ext1(2-1)=10 or Bank14/Ext1(2-1)=10 (UI0 Enable)
Bank13/Ext1(2-1)=11 or Bank14/Ext1(2-1)=11 (UI0 Enable)
SS
SK
UI0
UI1
P14
P15
P16
P17
(Enable External Interrupt Source INT2)
(CLKOUT Enable)
(SPI Enable)
(SPI Enable)
Bank 15/Ext 1 Reg
D15 D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Pins P0 15-0 Port Allocation
000 : Ext 15-0 (default)
001 : P0 15-8 <= P1 7-0,
P0 7-0 <= Ext 7-0
010 : Reserved
011 : P0 15-8 <= P0 15-8,
P0 7-0 <= Ext 7-0
100 : P0 15-0
101 : P0 15-8 <= P1 7-0
P0 7-0 <= P0 7-0
110 : Reserved
111 : Reserved
1 : Enable External Interrupt Source INT2
0 : Disable External Interrupt Source (default)
1 : Enable External Interrupt Source INT1
0 : Disable External Interrupt Source (default)
1 : CLKOUT Enabled (P11)
0 : CLKOUT Disabled (default)
1 : Port 1 Outputs Open-Drain
0 : Port 1 Outputs Push-Pull (default)
1 : Port 0 Outputs Open-Drain
0 : Port 0 Outputs Push-Pull (default)
Port 1 I/O Directions
1 : Output
0 : Input (default)
Figure 21. Bank15/EXT1 Register
30
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
8-Bit Programmable I/O (Port 2)
Port 2 is an 8-bit programmable, bidirectional, CMOScompatible port. Each of the eight lines can be
independently programmed as an input or an output or
globally as an open-drain output. Port 2 can also be
programmed to provide special I/O functions. When Port 2
acts as programmable I/O, Bank0/EXT5 (MSB) acts as the
data I/O register. Bank15/EXT2 serves as Port 2 control
register.
Table 11. Port 2 Bit Function Selection
Port.Bit
IF (Condition Explanation)
Then
Else
P2.0
P2.1
P2.2
P2.3
Bank15/Ext2(9)=1 (Enable External Interrupt Source INT0)
Bank15/Ext1(4)=1 (Enable External Interrupt Source INT1)
Bank13/Ext1(6-5)=10 or Bank14/Ext1(6-5)=10 (UO0 Enable)
Bank13/Ext1(6-5)=11 or Bank14/Ext1(6-5)=11 (UO0 Enable)
INT0
INT1
UO0
UO1
P20
P21
P22
P23
P2.4
P2.5
P2.6
P2.7
Bank15/Ext2(14)=1 (UO2 Enable)
Bank15/Ext2(13)=1 (Timer2 Clock is UI2)
UO2
UI2
P26
P27
P24
P25
P26
P27
Bank 15/Ext 2 Reg
D15 D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Port 2 I/O Directions
1 : Output
0 : Input (default)
1 : Enable Port 3
0 : Disable Port 3 (default)
1 : Enable External Interrupt Source INT0
0 : Disable External Interrupt Source INT0 (default)
1 : Port 2 Outputs Open-Drain
0 : Port 2 Outputs Push-Pull (default)
1 : Enable Timer 2
0 : Disable Timer 2 (default)
1 : Enable Timer 2 Counting
0 : Disable Timer 2 Counting (default)
1 : Timer 2 Clock is UI2
0 : Timer 2 Clock is System Clock/2 (default)
1 : UO2 Enabled (P24)
0 : UO2 Disabled (default)
Timer2 Test Mode*
0 : Normal Operation (default)
1 : Factory Test Mode
*Note:
The user should always program this bit to be 0.
Figure 22. Bank15/EXT2 Register
8-Bit Programmable I/O (Port 3)
Port 3 is an additional I/O port featured only in the 80-pin
PQFP package. P3[3:0] are inputs and P3[7:4] are outputs.
The purpose of this additional port is to serve applications
that need more than 32 I/O pins. Port 3 enables the
user to support up to 40 I/O pins. Port 3 is not
DS95DSP0101 Q4/95
supported in the 100-pin ICE chip PQFP package,
therefore this port is not supported in the Z893x3
emulator, and use of this port is not
recommended in cases when the other I/O ports
can support the I/O requirements.
31
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Serial Peripheral Interface
Serial Peripheral Interface (SPI). The Z893X3 incorporates
a serial peripheral interface for communication with other
microcontrollers and peripherals. The SPI includes features
such as Master/Slave selection. The SPI consists of two
registers; SPI Control Register (SCON), SPI Receive/Buffer
Register (RxBUF), and SPI Shift Register (Figure 23). Note:
The SPI shift register and Receive/Buffer register are one
in the same and are shown in Figure 41. SCON is located
in bank 15/Ext4 (LSB). This register is a read/write register
that controls; Master/Slave selection, SS polarity, clock
source and phase selection, and error flag. Bit 0 enables/
disables the SPI with the default being SPI disabled. A 1 in
this location enables the SPI, and a 0 disables the SPI.
slave’s SPI Shift Register, through the SIN pin, which has
the same address as the RxBUF Register. After a byte of
data has been received by the SPI Shift Register a Receive
Character Available SPI interrupt and flag is generated.
The next byte of data may be received at this time, but the
RxBUF Register must be cleared, or a Receive Character
Overrun (RxCharOverrun) flag is set in the SCON Register
and the data in the RxBUF Register is overwritten.
Bank15/Ext4 (LSB) Reg
D7 D6 D5 D4 D3 D2 D1 D0
SPI Enable
1 Enable
2 Disable
Receive Character Overrun (Slave)
Clock Frequency (Master)
0 0 Divide-by-2
0 1 Divide-by-4
1 0 Divide-by-8
1 1 Divide-by-16
Bits 1 and 2 of the SCON register in Master Mode selects
the clock rate. The user may choose whether internal clock
is divide by 2, 4, 8, or 16. In Slave Mode, Bit 1 of this register
flags the user if an overrun of the RxBUF Register has
occurred.
The RxCharOverrun flag can only be reset by writing a 0 to
this bit. In slave mode, bit 2 of the Control Register can
disable the data-out I/O function. If a 1 is written to this bit,
the data-out pin is tri-stated. If a 0 is written to this bit, the
SPI will shift out one bit for each bit received. Bit 3 of the
SCON Register is the SS polarity bit. A 0 selects active Low
(default) polarity on SS, and a 1 selects active High. Bit 4
signals that a receive character is available in the RxBUF
Register. If the associated interrupt enable bit is enabled,
an interrupt is generated. Bit 5 controls the clock phase of
the SPI. A 1 in Bit 5 allows for receiving data on the clock’s
falling edge and transmitting data on the clock’s rising
edge. A 0 allows receiving data on the clock’s rising edge
and transmitting on the clock’s falling edge.
DOP (Slave)
0 Enable SOUT as Output
1 Tri-State SOUT
SSP = SS Polarity (Master)
0 = SS Active Low (default)
1 = SS Active High
Received Character Available
CLKP
0 is Transmit on Falling
Receive Data on Rising Edge
1 is Transmit on Rising
Receive Data on Falling Edge
SPI Clock Source Select (Master)
0 is Internal Clock
1 is Timer 0
1 Master 0 Slave
Figure 23. SPI Control Register (SCON)
Bank 0/Ext 3 (LSB) Reg
The SPI clock source is defined in bit 6 for Master mode.
A 1 uses Timer0 output for the SPI clock, and a 0 uses a
division of the internal system clock for clocking the SPI. Bit
7 determines whether the SPI is used as a Master or a
Slave. A 1 puts the SPI into Master mode and a 0 puts the
SPI into Slave mode.
D7 D6 D5 D4 D3 D2 D1 D0
Figure 24. SPI TXRXDATA Register
SPI Operation. The SPI can be used in one of two modes;
either as system slave, or a system master. In the slave
mode, data transfer starts when the slave select
(SLAVESEL) pin goes Low. Data is transferred into the
32
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
When the communication between the master and slave is
complete, the SS goes High. Unless disconnected, for
every bit that is transferred into the slave through the SIN
pin, a bit is transferred out through the SOUT pin on the
opposite clock edge. During slave operation, the SPI clock
pin (SK) is an input (Figure 25). In master mode, the DSP
must first activate a SS through one of it’s I/O ports. Next,
data is transferred through the master’s SOUT pin one bit
per master clock cycle. Loading data into the shift register
initiates the transfer. In master mode, the master’s clock
drives the slave’s clock. At the conclusion of a transfer, a
Receive Character Available SPI interrupt and flag is
generated. Before data is transferred through the SOUT
pin, the SPI Enable bit in the SCON Register must be
enabled. The MSB bit 7 is shifted out first.
SPI Clock. The SPI clock can be driven from three sources;
with T0, a division of the internal system clock, or an
external master when in slave mode. Bit D6 of the SCON
Register controls what source drives the SPI clock. Divided
by 2, 4, 8, or 16 can be chosen as the scaler with bits D2,
D1 in master mode.
Receive Character Available and Overrun. When a
complete data stream is received an interrupt is generated
and the RxCharAvail bit in the SCON Register is set. The
SPI interrupt can be enabled or disabled (default) in the
Interrupt Allocation Register (Bank 15/Ext 6). The
RxCharAvail bit is available for interrupt polling purposes
and is reset when the RxBUF Register is read. RxCharAvail
is generated in both master and slave modes. While in
slave mode, if the RxBUF is not read before the next data
stream is received and loaded into the RxBUF Register,
Receive Character Overrun (RxCharOverrun) occurs. Since
there is no need for clock control in slave mode, bit D1 in
the SPI Control Register is used to log any RxCharOverrun.
SK
(Input/Output
Input
(Active Low)
3
SS
4
2
SOUT
1
SIN
5
Figure 25. SPI Timing
DS95DSP0101 Q4/95
33
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
CLOCK Circuits
The clock generator includes Phase-Locked Loop (PLL)
circuit to enable use of low frequency crystal. The benefits
of using low frequency crystal are low system cost, low
power consumption and low EMI. The PLL circuit can be
bypass (s/w controlled).
DSP (System) clock source is programmable and can be
one of the 4 options: VCO clock, VCO clock divided by 2,
VCO clock divided by 4 or twice the crystal frequency.
Whenever the PLL circuit is switched from Stop VCO to
Enable VCO, a software delay of 10 msec must be used
before switching the system clock from the oscillator to the
PLL, in order to give the PLL time to be stable.
The clock generated by the PLL circuit (VCO clock) is
programmable and controlled by the PLL Divider register.
Table 12. CLOCK Modes
STOP_OSC
STOP_VCO
BYPASS_PLL
Mode
0
0
0
0
0
1
0
1
0
0) Normal - High frequency clock
1) 32 Khz - VCO running (fast switching time)**
2) STOP CLOCK - Oscillator running
0
1
1
1
1
1
1
0
1
3) 32 Khz
4) STOP CLOCK
5) EXTERNAL CLOCK source *
Notes:
* In this clock mode, it is possible to use external clock source instead
of the internal oscillator source.
** Default (power-up) mode of operation.
Off-Chip
On-Chip
VCO
LPF
:2
STOP_VCO
Phase
Detector
00
01
MUX
10
11
8-Bit
Divider
:2
0
:2
MUX
System
Clock
1
BYPASS_PLL
2
[4-3]
Clock Source
1
0
STOP_OSC
[15-8]
PLL Divider
32 kHz
Bank4 / Ext5
Figure 26. PLL Functional Block Diagram
34
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Power Down
Stop Mode
The Z893X3 supports different levels of power-down modes
to minimize device power consumption. The lowest power
consumption is at STOP Clock Mode when the Oscillator
is turned off (clock modes 2 and 4 when there is no external
clock.) The highest power consumption is when the Z893X3
in Normal mode (Clock Mode 0) and there is medium
power consumption mode .The SLOW Clock Mode is when
the DSP is running with 32 kHz clock (Crystal Clock Modes
1 and 3) and disabling all the peripherals which are not
needed in this mode.
The STOP mode provides the lowest possible device
standby current. In this mode of operation the on chip
oscillator and internal system clock are turned off.
Slow Mode
The SLOW mode reduce the chip power consumption by
using the 32 kHz clock (Clock Mode 3) of the crystal as a
DSP clock and disabling in software all the unnecessary
peripherals.
In Clock Mode 2 the Oscillator is running while the system
clock is turned off to enable fast switching (wake up) to the
high frequency.
STOP mode is exited when the recovery source as defined
in Bank4/EXT5[6:5] is toggled to the recovery defined
level. In case of Clock Mode 2 the program resumes
operation starting from the next instruction after the stop
instruction. In case of Clock Mode 4, the program resumes
operation starting from the reset vector address after
executing operations similar to the Power-On Reset
sequence of operations.
Clock Mode 1 also uses the 32 kHz clock, but in this mode
the VCO is still running to enable fast switching (wake up)
to the high frequency.
Bank 15/Ext 5 Reg
D15 D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
STOP_OSC
0 : Oscillator Running
1 : Stop Oscillator
STOP_VCO
0 : VCO Running
1 : Stop VCO
BYPASS_PLL
0 : Clock Source is VCO
1 : Clock Source is Oscillator
DSP (System) Clock Source
00 : VCO Clock
01 : VCO Clock Divided by 2
10 : VCO Clock Divided by 4
11 : Twice the Crystal Frequency
Recovery Source
00 : POR (Power-On Reset) or
Port 2, Bit 0 (INT0)
01 : POR or Port 1, Bit 4 (SS)
10 : POR or Port 1, Bit 6 (UI0)
11 : POR or Port 2, Bit 0 or
Port 1, Bit 4 or Port 1, Bit 6
STOP Recovery Level
0 : Low (Default setting after reset.)
1 : High
Programmable PLL Divider Register
VCO Frequency = Bits 15-8 * 8 * Crystal Frequency (32 kHz)
39 (9.984 MHz) < Bits 15-8 < 158 (40.448 MHz)
Figure 27. PLL Register
DS95DSP0101 Q4/95
35
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Interrupt Controller
There are eight different interrupt sources (when all of them
are enabled). Bits [3:0] of the Interrupt Allocation Register
defines which interrupt source will have the highest priority
and will be allocated into IINT0 (Internal INT0). Bits[7:0] of
the Interrupt Allocation Register defines which interrupt
source will have the second highest priority and will be
allocated into IINT1 (Internal INT1). Bits[15:8] are enable
bits for specific interrupt sources. All the enabled interrupts
which are not already allocated into IINT0 or IINT1 are
allocated into IINT2. When interrupt happen on IINT2 then
IINT2 interrupt routine is reading the Interrupt Status Register
(EXT7 in all the Banks) to determine which interrupt occurred
and decides on the relative priority. The Interrupt Status
Register can be used for polling interrupts mode.
Bank 15/Ext 6 Reg
D15 D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IINT0 Source
0000 : A/D Finish
0001 : SPI
0010 : Timer0
0011 : Timer1
0100 : Timer2
0101 : INT0 H/W
0110 : INT1 H/W
0111 : INT2 H/W
1000 – 1111 : IINT0 Disabled
IINT1 Source
0000 : A/D Finish
0001 : SPI
0011 : Timer1
0010 : Timer0
0100 : Timer2
0101 : INT0 H/W
0111 : INT2 H/W
0110 : INT1 H/W
1000 – 1111 : IINT1 Disabled
Note: An Interrupt that is not selected as a source to IINT0, IINT1 or IINT2 is disabled.
IINT2 Interrupt Sources
Interrupt Interrupt
Enable Disable
Bit 8 = A/D Finish 1
0
Bit 9 = SPI
1
0
Bit 10 = Timer0
1
0
Bit 11 = Timer1
1
0
Bit 12 = Timer2
1
0
Bit 13 = INT0 H/W 1
0
Bit 14 = INT1 H/W 1
0
Bit 15 = INT2 H/W 1
0
Figure 28. Interrupt Allocation Register
36
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION
Instruction Timing. Most instructions are executed in one
machine cycle. Long immediate instructions and Jump or
Call instructions are executed in two machine cycles. A
multiplication or multiplication/accumulate instruction
requires a single cycle. Specific instruction cycle times are
described in the Condition Code section.
Multiply/Accumulate. The multiplier can perform a 16-bit
x 16-bit multiply, or multiply accumulate, in one machine
cycle using the Accumulator and/or both the X and Y
inputs. The multiplier produces a 32-bit result, however,
only the 24 most significant bits are saved for the next
instruction or accumulation. For operations on very small
numbers where the least significant bits are important, the
data should first be scaled by eight bits (or the multiplier
and multiplicand by four bits each) to avoid truncation
errors. Note that all inputs to the multiplier should be
fractional two’s-complement, 16-bit binary numbers (Figure
29). This puts them in the range [–1 to 0.9999695], and the
result is in 24 bits so that the range is [–1 to 0.9999999]. In
addition, if 8000H is loaded into both X and Y registers, the
resulting multiplication is considered an illegal operation
as an overflow would result. Positive one cannot be
represented in fractional notation, and the multiplier will
actually yield the result 8000H x 8000H = 8000H (–1 x –1
= –1).
ALU. The ALU has two input ports, one of which is
connected to the output of the 24-bit Accumulator. The
other input is connected to the 24-bit P-Bus, the upper 16
bits of which are connected to the 16-bit D-Bus. A shifter
between the P-Bus and the ALU input port can shift the
data by three bits right, one bit right, one bit left or no shift
(Figure 30).
DDATA
DDATA
XDATA
Mult. (24)
16
X Register (16)
16
Y Register (16)
Multiplier
24
24
24
Shift Unit *
24
MUX
* Options:
1 Bit Right
3 Bits Right
No Shift
1 Bit Left
24
MUX
P Register (24)
24
Shift Unit *
16
24
* Options:
1 Bit Right
3 Bits Right
No Shift
1 Bit Left
24
Arithmetic Logic Unit (ALU)
24
Accumulator (24)
24
Figure 30. ALU Block Diagram
Figure 29. Multiplier Block Diagram
DS95DSP0101 Q4/95
37
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
FUNCTIONAL DESCRIPTION (Continued)
Hardware Stack. A six-level hardware stack is connected
to the D-Bus to hold subroutine return addresses or data.
The Call instruction pushes PC+2 onto the stack, and the
RET instruction pops the contents of the stack to the PC.
User Inputs. The Z89323 has two inputs, UI0 and UI1,
which may be used by Jump and Call instructions. The
Jump or Call tests one of these pins and if appropriate,
jumps to a new location. Otherwise, the instruction behaves
like a NOP. These inputs are also connected to the status
register bits S10 and S11, which may be read by the
appropriate instruction (Figure 8).
User Outputs. The status register bits S5 and S6 connect
directly to UO0 and UO1 pins and may be written to by the
appropriate instruction. Note: The user output value is the
opposite of the status register content.
Interrupts. The Z89323 has three positive edge-triggered
interrupt inputs serving up to eight interrupt sources. An
interrupt is acknowledged at the end of an instruction
execution. It takes two machine cycles to enter an interrupt
instruction sequence. The PC is pushed onto the stack and
Interrupts are globally disabled. A RET instruction transfers
the contents of the stack to the PC and decrements the
stack pointer by one word. The priority of the interrupts is
IINT0 = highest, IINT2 = lowest. Note: The SIEF instruction
globally enables the interrupts. The SIEF instruction must
be used before exiting an interrupt routine since the
interrupts are automatically disabled when entering the
routine. (See Interrupt Controller section for more details.)
Registers. The Z89323 has 28 physical internal registers,
eight external registers and 15 peripheral control registers.
The EA2-EA0 determines the address of the external
registers. The signals are used to read from or write to the
external registers /DS, WAIT, RD//WR.
I/O Bus. The processor provides a 16-bit, CMOScompatible bus. I/O Control pins provide convenient
communication capabilities with external peripherals, and
single-cycle
access
is
possible.
For
slower
communications, an on-board hardware wait-state
generator can be used to accommodate timing conflicts.
Three latched I/O address pins are used to access external
registers. Disabling a peripheral allows access to these
addresses for general-purpose use.
38
Wait-State Generator. An internal Wait-State generator is
provided to accommodate slow external peripherals. A
single Wait-State can be implemented through a control
register. For additional states, a dedicated pin
(WAIT) can be held High. The WAIT pin is monitored only
during execution of a read or write instruction to external
peripherals (EXT bus).
Analog to Digital Converter. The Z89323 has a 4-channel,
8-bit half-flash analog to digital converter. Two external
reference voltages are available externally. The ADC
prescales to the system clock and can drive an interrupt at
the end of a conversion. There are four channels of input
with the ADC which can be programmed to convert values
either continuously or on an event (timer or interrupt).
Timer/Counter/PWMs (T0, T1). Timer0 and Timer1 are
16-bit timer-counters with 8-bit prescalers. They also offer
the option of being used as PWM generators and have
both hardware and software Watch-Dog capabilities. Both
timers are identical and can be externally or internally
clocked and can drive any of the three hardware interrupts.
Timer/Counter (T2). Timer 2 is a general-purpose 16-bit
timer/counter. It can be externally or internally clocked and
drive either IINT0 and IINT1.
Port 0. Port 0 is a 16-bit user I/O port. Bits can be
configured as input or output or globally as open-drain
output. When enabled, Port 0 consumes the 16 data lines
used by the EXT bus. Port 0 function and EXT use can be
dynamically changed by enabling and disabling Port 0.
Port 1. Port 1 is an 8-bit user I/O port. Bits can be
configured as input or output or globally as open-drain
output.
Port 2. Port 2 has multiple functions. It can be used as an
8-bit user I/O port when the other functions within the port
are not in use. As an I/O port, these bits can be configured
as input or output or globally as open-drain output. Port 2
also supports the SPI, CLKOUT, all three external hardware
interrupt signals and all three timer input and output
signals.
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
RAM ADDRESSING
The address of the RAM is specified in one of three ways (Figure 22):
RAM0
RAM1
%FF
RAM Pointers
%FF
RAM Pointers
P0:0
P1:0
P0:1
256 x 16-Bit
%37
P2:0
256 x 16-Bit
P1:1
@P1:0
%37
P2:1
%0321
%0321
%04
%00
%00
Data Pointers
Internal ROM
D0:0
%1FFF
4K x 16-Bit
@@P1:0
S4 / S3 = 01
%0321
%1234
%0321
D0:1
D1:0
D1:1
D2:0
D2:1
D3:0
D3:1
@D0:1
Each of the following instructions
load %1234 into the Accumulator:
LD A,@@P1:0
LD A,@D0:1
%0000
Figure 31. RAM, ROM, and Pointer Architecture
Register Indirect
Pn:b n = 0-2, b = 0-1
The most commonly used method is a register indirect
addressing method, where the RAM address is specified
by one of the three RAM address pointers (n) for each bank
(b). Each source/destination field in Figures 6 and 9 may
be used by an indirect instruction to specify a register
pointer and its modification after execution of the instruction.
b
D8
D3
D2
n1
n0
D1
D0
RAM Pointer Register
Operation
RAM Bank
Figure 32. Indirect Register
DS95DSP0101 Q4/95
39
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
The register pointer is specified by the first and second bits
in the source/destination field and the modification is
specified by the third and fourth bits according to the
following table:
D3-D0
Meaning
00xx
01xx
10xx
11xx
NOP
+1
–1/LOOP
+1/LOOP
No Operation
Simple Increment
Decrement Modulo the Loop Count
Increment Modulo the Loop Count
xx00
xx01
xx10
xx11
P0:0 or P0:1
P1:0 or P1:1
P2:0 or P2:1
*
*
*
See Short Form Direct
Note:
* If bit 8 is zero, P0:0 to P2:0 are selected;
if bit 8 is one, P0:1 to P2:1 are selected.
Direct Register
The second method is a direct addressing method. The
address of the RAM is directly specified by the address
field of the instruction. Because this addressing method
D15 D14 D13 D12 D11 D10 D9
D8
D7
When LOOP mode is selected, the pointer to which the
loop is referring will cycle up or down, depending on
whether a –LOOP or +LOOP is specified. The size of the
loop is obtained from the least significant three bits of the
Status Register. The increment or decrement of the register
is accomplished modulo the loop size. As an example, if
the loop size is specified as 32 by entering the value 101
into bits 2-0 of the Status Register (S2-S0) and an increment
+LOOP is specified in the address field of the instruction,
for example, the RPi field is 11xx, then the register specified
by RPi will increment, but only the least significant five bits
will be affected. This means the actual value of the pointer
will cycle round in a length 32 loop, and the lowest or
highest value of the loop, depending on whether the loop
is up or down, is set by the three most significant bits. This
allows repeated access to a set of data in RAM without
software intervention. To clarify, if the pointer value is
10101001 and if the loop = 32, the pointer increments up
to 10111111, then drops down to 10100000 and starts
again. The upper three bits remaining unchanged. Note
that the original value of the pointer is not retained.
consumes nine bits (0-511) of the instruction field, some
instructions cannot use this mode (see Figure 33).
D6
D5
D4
D3
D2
D1
D0
RAM Address
Opcode
Figure 33. Direct Internal RAM Address Format
Short Form Direct
Dn:b n = 0-3, b = 0-1
The last method is called Short Form Direct Addressing,
where one out of 32 addresses in internal RAM can be
specified. The 32 addresses are the 16 lower addresses in
RAM Bank 0 and the 16 lower addresses in RAM Bank 1.
Bit 8 of the instruction field determines RAM Bank 0 or 1.
The 16 addresses are determined by a 4-bit code comprised
of bits S3 and S4 of the status register and the third and
fourth bits of the Source/Destination field. Because this
mode can specify a direct address in a short form, all of the
instructions using the register indirect mode can use this
mode (Figure 30). This method can access only the lower
16 addresses in the both RAM banks and as such has
limited use. The main purpose is to specify a data register,
40
located in the RAM bank, which can then be used to point
to a program memory location. This facilitates downloading
lookup tables and other instructions from program memory
to RAM.
b
n3
n2
n1
n0
D8
S4
S3
D3
D2
RAM Address
RAM Bank
Figure 34. Short Form Direct Address
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
INSTRUCTION FORMAT
Table 13. Registers
Source/Destination
Table 14. Register Pointers Field
Register
Source/Destination
Meaning
0000
0001
0010
0011
BUS [1]
X
Y
A
00xx
01xx
10xx
11xx
NOP
+1
–1/LOOP
+1/LOOP
0100
0101
0110
0111
SR
STACK
PC
P [1]
xx00
xx01
xx10
xx11
P0:0 or P0:1[2]
P1:0 or P1:1[2]
P2:0 or P2:1[2]
Short Form Direct Mode[3]
1000
1001
1010
1011
EXT0
EXT1
EXT2
EXT3
1100
1101
1110
1111
EXT4
EXT5
EXT6
EXT7
D15 D14 D13 D12 D11 D10
D9
Notes:
[1] If RAM Bank bit is 0, then Pn:0 are selected.
If RAM Bank bit is 1, then Pn:1 are selected.
[2] Read only.
[3] When the short form direct mode is selected,
00000-01111 or 10000-11111 are used as RAM addresses.
D8
D7
D6
D5
D4
D3
D2
D1
D0
Source field
Destination field
RAM Bank selection
Opcode
Note: Source/Destination fields can specify either register
or RAM address in RAM pointer indirect mode.
Figure 35. General Instruction Format
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Short Immediate Data
000
001
010
011
100
101
110
111
Reg. Pointer
P0:0
P1:0
P2:0
NA
P0:1
P1:1
P2:1
NA
Opcode
00011
Figure 36. Short Immediate Data Load Format
DS95DSP0101 Q4/95
41
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
INSTRUCTION FORMAT (Continued)
D15 D14 D13 D12 D11 D10 D9
1st Word
D8
D7
D6
D5
D4
D3
D2
D1
D0
General Instruction Format
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
2nd Word
Immediate Data
Figure 37. Immediate Data Load Format
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACC Modification Codes
0 0 0 0 ROR Rotate right
0 0 0 1 ROL Rotate left
0 0 1 0 SHR Shift right
0 0 1 1 SHL Shift left
0 1 0 0 INC Increment (LSB)
0 1 0 1 DEC Decrement (LSB)
0 1 1 0 NEG Negate
0 1 1 1 ABS Absolute
Condition Codes
0 0 0 0 TRUE
0 0 0 1 ---0 0 1 0 U01=0
0 0 1 1 UO1=0
0 1 0 0 C =0
0 1 0 1 Z=0
0 1 1 0 OV=0
0 1 1 1 N=0
1xxx ---0 0 0 0 TRUE
0001 ---0 0 1 0 UO0=1
0 0 1 1 UO1=1
0 1 0 0 C=1
0 1 0 1 Z=1
0 1 1 0 OV=1
0 1 1 1 N=1
1xxx ---0 = Negative Condition
1 = Positive Condition
Opcode
1001000
Figure 38. Accumulator Modification Format
42
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
1st Word
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
xxxx
Condition Codes
0 0 0 0 TRUE
0 0 0 1 ---0 0 1 0 UO0=0
0 0 1 1 UO1=0
0 1 0 0 C=0
0 1 0 1 Z=0
0 1 1 0 OV=0
0 1 1 1 N=0
1xxx ---0 0 0 0 TRUE
0001 ---0 0 1 0 UO0=1
0 0 1 1 UO1=1
0 1 0 0 C=1
0 1 0 1 Z=1
0 1 1 0 OV=1
0 1 1 1 N=1
1xxx ---Condition
0 = Negative
Condition
1 = Positive Condition
Opcode
0100110
Branch
0 1 0 0 1 0 0 Call
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
2nd Word
Branch Address
Figure 39. Branching Format
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x x 1 0 Reset C flag
x x 1 1 Set
C flag
x 1 x 0 Reset IE Flag
(Interrupt enable)
x 1 x 1 Set IE Flag
1 x x 0 Reset OP Flag
(Overflow protection)
1 x x 1 Set OP Flag
xxxx
Opcode
1 0 0 1 0 1 0 Mod
Figure 40. Flag Modification Format
DS95DSP0101 Q4/95
43
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
ADDRESSING MODES
This section discusses the syntax of the addressing modes
supported by the DSP assembler.
Table 15. Addressing Modes
Symbolic Name
Syntax
Description
<pregs>
Pn:b
Pointer Register
<dregs>
(Points to RAM)
Dn:b
Data Register
<hwregs>
X,Y,PC,SR,P
EXTn,A,BUS
Hardware Registers
<accind>
(Points to Program Memory)
@A
Accumulator Memory Indirect
<direct>
<expression>
Direct Address Expression
<limm>
#<const exp>
Long (16-bit) Immediate Value
<simm>
#<const exp>
Short (8-bit) Immediate Value
<regind>
(Points to RAM)
@Pn:b
@Pn:b+
@Pn:b–LOOP
@Pn:b+LOOP
Pointer
Pointer
Pointer
Pointer
<memind>
(Points to Program Memory)
@@Pn:b
@Dn:b
@@Pn:b–LOOP
@@Pn:b+LOOP
@@Pn:b+
Pointer Register Memory Indirect
Data Register Memory Indirect
Pointer Register Memory Indirect with Loop Decrement
Pointer Register Memory Indirect with Loop Increment
Pointer Register Memory Indirect with Increment
44
Register Indirect
Register Indirect with Increment
Register Indirect with Loop Decrement
register Indirect with Loop Increment
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
There are eight distinct addressing modes for data transfer.
<pregs>, <hwregs> These two modes are used for simple
loads to and from registers within the chip, such as loading
to the Accumulator, or loading from a pointer register. The
names of the registers need only be specified in the
operand field (destination first, then source).
<regind> This mode is used for indirect accesses to the
data RAM. The address of the RAM location is stored in the
pointer. The “@” symbol indicates “indirect” and precedes
the pointer, therefore @P1:1 instructs the processor to
read or write to a location in RAM1, which is specified by
the value in the pointer.
<dregs> This mode is also used for accesses to the data
RAM, but only the lower 16 addresses in either bank. The
4-bit address comes from the status register and the
operand field of the data pointer. Note that data registers
are typically used not for addressing RAM, but loading
data from program memory space.
<memind> This mode is used for indirect accesses to the
program memory. The address of the memory is located
in a RAM location, which is specified by the value in a
pointer. Therefore, @@P1:1 instructs the processor to
read (write is not possible) from a location in memory,
which is specified by a value in RAM, and the location of
the RAM is in turn specified by the value in the pointer.
Note that the data pointer can also be used for a memory
access in this manner, but only one “@” precedes the
pointer. In both cases, the memory address stored in RAM
is incremented by one, each time the addressing mode is
used, to allow easy transfer of sequential data from
program memory.
<accind> Similar to the previous mode, the address for the
program memory read is stored in the Accumulator. @A in
the second operand field loads the number in memory
specified by the address in A.
<direct> The direct mode allows read or write to data RAM
from the Accumulator by specifying the absolute address
of the RAM in the operand of the instruction. A number
between 0 and 255 indicates a location in RAM0, and a
number between 256 and 511 indicates a location in
RAM1.
<limm> This address mode indicates a long immediate
load. A 16-bit word can be copied directly from the
operand into the specified register or memory.
<simm> This address mode can only be used for immediate
transfer of 8-bit data in the operand to the specified RAM
pointer.
CONDITION CODES
The following Instruction Description defines the condition
codes supported by the DSP assembler. If the instruction
description refers to the <cc> (condition code) symbol in
one of its addressing modes, the instruction will only
execute if the condition is true.
Code
Description
Code
Description
C
EQ
F
IE
MI
NC
NE
NIE
NOV
NU0
Carry
Equal (same as Z)
False
Interrupts Enabled
Minus
No Carry
Not Equal (same as NZ)
Not Interrupts Enabled
Not Overflow
Not User Zero
NU1
NZ
OV
PL
U0
U1
UGE
Not User One
Not zero
Overflow
Plus (Positive)
User Zero
User One
Unsigned Greater Than or
Equal (Same as NC)
Unsigned Less Than (Same as C)
Zero
DS95DSP0101 Q4/95
ULT
Z
45
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
INSTRUCTION DESCRIPTIONS
Inst.
Description
Synopsis
Operands
Words
Cycles
Examples
ABS
AbsoluteValue
ABS[<cc>,]<src>
<cc>,A
A
1
1
1
1
ABSNC,A
ABSA
ADD
Addition
ADD<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
2
3
1
1
1
ADDA,P0:0
ADDA,D0:0
ADDA,#%1234
ADDA,@@P0:0
ADDA,%F2
ADDA,@P1:1
ADDA,X
ADDA,#%12
AND
BitwiseAND
AND<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
2
3
1
1
1
ANDA,P2:0
ANDA,D0:1
ANDA,#%1234
ANDA,@@P1:0
ANDA,%2C
ANDA,@P1:2+LOOP
ANDA,EXT3
ANDA,#%12
CALL
Subroutinecall
CALL[<cc>,]<address>
<cc>,<direct>
<direct>
2
2
2
2
CALLZ,sub2
CALLsub1
CCF
Clearcarryflag
CCF
None
1
1
CCF
CIEF
ClearCarryFlag
CIEF
None
1
1
CIEF
COPF
ClearOPflag
COPF
None
1
1
COPF
CP
Comparison
CP<src1>,<src2>
A,<pregs>
A,<dregs>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A<limm>
A,<simm>
1
1
1
1
1
1
2
1
1
3
1
1
1
2
CPA,P0:0
CPA,D3:1
CPA,@@P0:1
CPA,%FF
CPA,@P2:1+
CPA,STACK
CPA,#%FFCF
CPA,#%12
DEC
Decrement
DEC[<cc>,]<dest>
<cc>A,
A
1
1
1
1
DECNZ,A
DECA
INC
Increment
INC[<cc>,]<dest>
<cc>,A
A
1
1
1
1
INCPL,A
INCA
JP
Jump
JP[<cc>,]<address>
<cc>,<direct>
<direct>
2
2
2
2
JPNIE,Label
JPLabel
46
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Inst.
Description
Synopsis
Operands
LD
Loaddestination
withsource
LD<dest>,<src>
A,<hwregs>
A,<dregs>
A,<pregs>
A,<regind>
A,<memind>
A,<direct>
<direct>,A
<dregs>,<hwregs>
<pregs>,<simm>
<pregs>,<hwregs>
<regind>,<limm>
<regind>,<hwregs>
<hwregs>,<pregs>
<hwregs>,<dregs>
<hwregs>,<limm>
<hwregs>,<accind>
<hwregs>,<memind>
<hwregs>,<regind>
<hwregs>,<hwregs>
Words Cycles Examples
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
2
3
3
1
1
LDA,X
LDA,D0:0
LDA,P0:1
LDA,@P1:1
LDA,@D0:0
LDA,124
LD124,A
LDD0:0,EXT7
LDP1:1,#%FA
LDP1:1,EXT1
LD@P1:1,#1234
LD@P1:1+,X
LDY,P0:0
LDSR,D0:0
LDPC,#%1234
LDX,@A
LDY,@D0:0
LDA,@P0:0–LOOP
LDX,EXT6
Note: When<dest>is<hwregs>,<dest>cannotbeP.
Note: When<dest>is<hwregs>and<src>is<hwregs>,<dest>cannotbeEXTn
if<src>isEXTn,<dest>cannotbeXif<src>isX,<dest>cannotbeSR
if<src>isSR.
Note: When<src>is<accind><dest>cannotbeA.
MLD
Multiply
MLD<srcl>,<srcl>[,<bankswitch>]
<hwregs>,<regind>
<hwregs>,<regind>,<bankswitch>
<regind>,<regind>
<regind>,<regind>,<bankswitch>
1
1
1
1
1
1
1
1
MLDA,@P0:0+LOOP
MLDA,@P1:0,OFF
MLD@P1:1,@P2:0
MLD@P0:1,@P1:0,ON
Note: Ifsrc1is<regind>itmustbeabank1register.Src2’s<regindmustbe
abank0register.
Note: <hwregs>forsrc1cannotbeX.
Note: Fortheoperands<hwregs>,<regind>the<bandswitch>defaultstoOFF.
Fortheoperands<regind>,the<bankswitch>defaultstoON.
MPYA
Multiplyandadd
MPYA<srcl>,<src2>[,<bankswitch>]
<hwregs>,<regind>
<hwregs>,<regind>,<bankswitch>
<regind>,<regind>
<regind>,<regind>,<bankswitch>
1
1
1
1
1
1
1
1
MPYAA,@P0:0
MPYAA,@P1:0,OFF
MPYA@P1:1,@P2:0
MPYA@P0:1,@P1:0,ON
Note: Ifsrc1is<regind>itmustbeabank1register.Src2’s<regind>mustbe
abank0register.
Note: <hwregs>forsrc1cannotbeX.
Note: Fortheoperands<hwregs>,<regind>the<bankswitch>defaultstoOFF.
Fortheoperands<regind>,the<bankswitch>defaultstoON.
DS95DSP0101 Q4/95
47
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
INSTRUCTION DESCRIPTIONS (Continued)
Inst.
Description
MPYS Multiplyand
subtract
Synopsis
Operands
Words Cycles
MPYS<src1>,<src2>[,<bankswitch>] <hwregs>,<regind>
<hwregs>,<regind>,<bankswitch>
<regind>,<regind>
<regind>,<regind>,<bankswitch>
1
1
1
1
1
1
1
1
Examples
MPYSA,@P0:0
MPYSA,@P1:0,OFF
MPYS@P1:1,@P2:0
MPYS@P0:1,@P1:0,ON
Note: Ifsrc1is<regind>itmustbeabank1register.Src2’s<regind>mustbe
abank0register.
Note: <hwregs>forsrc1cannotbeX.
Note: Fortheoperands<hwregs>,<regind>the<bankswitch>defaultstoOFF.
Fortheoperands<regind>,<regind>the<bankswitch>defaultstoON.
NEG
Negate
NEG<cc>,A
<cc>,A
A
1
1
1
1
NEGMI,A
NEGA
NOP
Nooperation
NOP
None
1
1
NOP
OR
BitwiseOR
OR<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
2
3
1
1
1
ORA,P0:1
ORA,D0:1
ORA,#%2C21
ORA,@@P2:1+
ORA,%2C
ORA,@P1:0–LOOP
ORA,EXT6
ORA,#%12
POP
Popvalue
fromstack
POP<dest>
<pregs>
<dregs>
<regind>
<hwregs>
1
1
1
1
1
1
1
1
POPP0:0
POPD0:1
POP@P0:0
POPA
PUSH
Pushvalue
ontostack
PUSH<src>
<pregs>
<dregs>
<regind>
<hwregs>
<limm>
<accind>
<memind>
1
1
1
1
2
1
1
1
1
1
1
2
3
3
PUSHP0:0
PUSHD0:1
PUSH@P0:0
PUSHBUS
PUSH#12345
PUSH@A
PUSH@@P0:0
RET
Returnfromsubroutine
RET
None
1
2
RET
RL
RotateLeft
RL<cc>,A
<cc>,A
A
1
1
1
1
RLNZ,A
RLA
RR
RotateRight
RR<cc>,A
<cc>,A
A
1
1
1
1
RRC,A
RRA
48
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
Inst.
Description
Synopsis
Operands
Words
Cycles
SCF
SetCflag
SCF
SIEF
SetIEflag
SLL
None
1
1
SCF
SIEF
None
1
1
SIEF
Shiftleft
logical
SLL
[<cc>,]A
A
1
1
1
1
SLLNZ,A
SLL A
SOPF
SetOPflag
SOPF
None
1
1
SOPF
SRA
Shiftright
arithmetic
SRA<cc>,A
<cc>,A
A
1
1
1
1
SRANZ,A
SRAA
SUB
Subtract
SUB<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
2
3
1
1
1
SUBA,P1:1
SUBA,D0:1
SUBA,#%2C2C
SUBA,@D0:1
SUBA,%15
SUBA,@P2:0–LOOP
SUBA,STACK
SUBA,#%12
XOR
BitwiseexclusiveOR
XOR<dest>,<src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
A,<direct>
A,<regind>
A,<hwregs>
A,<simm>
1
1
2
1
1
1
1
1
1
2
3
1
1
1
XORA,P2:0
XORA,D0:1
XORA,#13933
XORA,@@P2:1+
XORA,%2F
XORA,@P2:0
XORA,BUS
XORA,#%12
Bank Switch Enumerations. The third (optional) operand
of the MLD, MPYA and MPYS instructions represents
whether a bank switch is set ON or OFF. To more clearly
represent this, the keywords ON and OFF are used to state
DS95DSP0101 Q4/95
Examples
the direction of the switch. These keywords are referenced
in the instruction descriptions through the <bank switch>
symbol. The most notable capability this provides is that a
source operand can be multiplied by itself (squared).
49
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min.
Max.
Units
VCC
TSTG
TA
Supply Voltage (*)
Storage Temp
Oper Ambient Temp
–0.3
–65°
+7.0
+150
†
V
°C
°C
Notes:
* Voltage on all pins with respect to GND.
† See Ordering Information.
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended period may affect
device reliability.
STANDARD TEST CONDITIONS
+5V
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to Ground.
Positive current flows into the referenced pin (Figure 41).
2.1 kOhm
From Output
Under Test
30 pF
9.1 kOhm
Figure 41. Test Load Diagram
DC ELECTRICAL CHARACTERISTICS (20 MHZ)
(VDD= 5V ±10%, TA = 0°C to +70°C, unless otherwise noted.)
fclock = 20 MHz
Symbol
50
Parameter
Condition
IDD
IDC
VIH
SupplyCurrent
DCPowerConsumption
InputHighLevel
VDD=5.5V
VIL
IL
VOH
InputLowLevel
InputLeakage
OutputHighVoltage
VOL
IFL
InputLowVoltage
OutputFloating
LeakageCurrent
Standard Temp
TA = 0° to +70°C
Min.
Max.
60
5
IOL=2.0mA
Units
55
5
mA
mA
V
.8
10
V
µA
V
.5
.5
V
10
10
µA
2.7
IOH=–100µA
Extended Temp
TA = –40° to +85°C
Min.
Max.
2.7
.8
10
VDD-0.2
VDD-02
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS (20 MHZ)
(VDD= 5V ±10%, TA = 0°C to +70°C, unless otherwise noted.)
Standard Temp
T A = 0° to +70°C
Min.
Max.
Symbol
Parameter
Clock
TCY
Tr
Tf
CPW
Clock
Clock
Clock
Clock
I/O
DSVALID
DSHOLD
EASET
EAHOLD
RDSET
RDHOLD
WRVALID
WRHOLD
/DS Valid Time from CLOCK Fall
/DS Valid Time from CLOCK Rise
EA Setup Time to /DS Fall
EA Hold Time from /DS Rise
Data Read Setup Time to /DS Rise
Data Read Hold Time from /DS Fall
Data Write Valid Time from /DS Fall
Data Write Hold Time from /DS Rise
0
4
12
4
14
6
5
ns
ns
ns
ns
ns
ns
ns
ns
Interrupt
INTSET
INTWIDTH
Interrupt Setup Time to CLOCK Fall
Interrupt Low Pulse Width
7
1 TCY
ns
ns
Reset
RRise
RSET
RWIDTH
Reset Rise Time
Reset Setup Time to CLOCK Rise
Interrupt Low Pulse Width
15
2 TCY
ns
ns
ns
Wait State
WSET
WHOLD
Wait Setup Time to CLOCK Rise
Wait Hold Time from CLOCK Rise
23
1
ns
ns
Halt
HSET
HHOLD
Halt Setup Time to CLOCK Rise
Halt Hold Time from CLOCK Rise
3
10
ns
ns
DS95DSP0101 Q4/95
Cycle Time
Rise Time
Fall Time
Pulse Width
50
2
2
23
15
15
18
1000
Units
ns
ns
ns
ns
51
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS (20 MHZ) (Continued)
(VDD= 5V ±10%, TA = 0°C to +70°C, unless otherwise noted.)
Analog to Digital
Min.
Resolution
Integral Non-Linearity
Differential Non-Linearity
Zero Error at 25°C
Supply Range
Power Dissipation, No Load
Clock Frequency
Input Voltage Range
Conversion Time
Input Capacitance on ANA
VAHI Range
VALO Range
VAHI-VALO
Typical
Max
8
0.5
0.5
4.5
5.0
50
VALO
25
VALO +2.5
ANGND
2.5
Units
1
1
45
Bits
LSB
LSB
mV
5.5
85
33
VAHI
2
Volts
mW
MHz
Volts
µsec
40
ANVCC
ANVCC –2.5
ANVCC
pF
Volts
Volts
Volts
DC ELECTRICAL CHARACTERISTICS (10 MHZ)
(VDD= 5V ±10%, TA = 0°C to +70°C, unless otherwise noted.)
fclock = 10 MHz
Symbol
52
Parameter
Condition
IDD
IDC
VIH
SupplyCurrent
DCPowerConsumption
InputHighLevel
VDD=5.5V
VIL
IL
VOH
InputLowLevel
InputLeakage
OutputHighVoltage
VOL
IFL
InputLowVoltage
OutputFloating
LeakageCurrent
Standard Temp
TA = 0° to +70°C
Min.
Max.
30
5
IOL=2.0mA
Units
55
5
mA
mA
V
.8
10
V
µA
V
.5
.5
V
10
10
µA
2.7
IOH=–100µA
Extended Temp
TA = –40° to +85°C
Min.
Max.
2.7
.8
10
VDD-0.2
VDD-02
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS (10 MHZ)
(VDD= 5V ±10%, TA = 0°C to +70°C, unless otherwise noted.)
Standard Temp
T A = 0° to +70°C
Min.
Max.
Symbol
Parameter
Clock
TCY
Tr
Tf
CPW
Clock
Clock
Clock
Clock
I/O
DSVALID
DSHOLD
EASET
EAHOLD
RDSET
RDHOLD
WRVALID
WRHOLD
/DS Valid Time from CLOCK Fall
/DS Valid Time from CLOCK Rise
EA Setup Time to /DS Fall
EA Hold Time from /DS Rise
Data Read Setup Time to /DS Rise
Data Read Hold Time from /DS Fall
Data Write Valid Time from /DS Fall
Data Write Hold Time from /DS Rise
0
6
18
6
21
9
8
ns
ns
ns
ns
ns
ns
ns
ns
Interrupt
INTSET
INTWIDTH
Interrupt Setup Time to CLOCK Fall
Interrupt Low Pulse Width
11
1 TCY
ns
ns
Reset
RRise
RSET
RWIDTH
Reset Rise Time
Reset Setup Time to CLOCK Rise
Interrupt Low Pulse Width
22
2 TCY
ns
ns
ns
Wait State
WSET
WHOLD
Wait Setup Time to CLOCK Rise
Wait Hold Time from CLOCK Rise
35
2
ns
ns
Halt
HSET
HHOLD
Halt Setup Time to CLOCK Rise
Halt Hold Time from CLOCK Rise
5
15
ns
ns
Cycle Time
Rise Time
Fall Time
Pulse Width
Analog to Digital
100
Input Capacitance on ANA
VAHI Range
VALO Range
VAHI-VALO
DS95DSP0101 Q4/95
ns
ns
ns
ns
2
2
48
Min.
Resolution
Integral Non-Linearity
Differential Non-Linearity
Zero Error at 25°C
Supply Range
Power Dissipation, No Load
Clock Frequency
Input Voltage Range
Conversion Time
Units
30
1500
Typical
8
0.5
0.5
4.5
VALO
25
VALO +2.5
ANGND
2.5
25
25
5.0
50
Max
Units
1
1
45
Bits
LSB
LSB
mV
5.5
85
33
VAHI
2
Volts
mW
MHz
Volts
µsec
40
ANVCC
ANVCC –2.5
ANVCC
pF
Volts
Volts
Volts
53
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
TIMING DIAGRAMS
TCY
Tr
Tf
CLOCK
CPW
DSHOLD
DSVALID
/DS
EAHOLD
EASET
EA(2:0)
Valid Address Out
RDHOLD
RD//WR
RDSET
EXT(15:0)
Data In
Figure 42. Read Timing
TCY
CLOCK
WHOLD
WSET
WAIT
/DS
EA(2:0)
Valid Address Out
RD//WR
EXT(15:0)
Data In
Figure 43. Read Timing Using WAIT Pin
54
DS95DSP0101 Q4/95
P R E L I M I N A R Y
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
TCY
CLOCK
DSHOLD
DSVALID
/DS
EASET
EA(2:0)
EAHOLD
Valid Address Out
EASET
EAHOLD
RD//WR
WRHOLD
WRVALID
EXT(15:0)
Data In
Figure 44. Write Timing
TCY
CLOCK
WHOLD
WSET
WAIT
/DS
EA(2:0)
Valid Address Out
RD//WR
EXT(15:0)
Data In
Figure 45. Write Timing Using WAIT Pin
DS95DSP0101 Q4/95
55
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
TIMING DIAGRAMS (Continued)
TCY
CLOCK
INTSET
INT 0,1,2
INTWidth
PROGRAM
ADDRESS
Fetch N –1
EXECUTE
Fetch N
Execute N –1
Fetch N +1
Fetch Int_Addr
Execute N
CALL Int Routine
Fetch I
Fetch I +1
Execute Int Routine
Figure 46. Interrupt Timing
TCY
CLOCK
HHOLD
HSET
HALT
Figure 47. HALT Timing
56
DS95DSP0101 Q4/95
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
P R E L I M I N A R Y
TCY
CLOCK
RSET
RRISE
/RESET
RWIDTH
INTERNAL
RESET
EXECUTE
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Code Exec
RD//WR
/DS
UO0-1
EA0-2
EXT0-15
Tri-Stated
PA0-15
Tri-Stated
RAM/
REGISTERS
Access Reset Vector
Intact*
* The RAM and hardware registers are left intact
during a warm reset. A cold reset will produce
random data in these locations. The status
register is set to zeroes in both cases.
Figure 48. RESET Timing
TCY
CLOCK
PAVALID
PROGRAM
ADDRESS
Valid
Valid
Valid
PDSET
PDHOLD
PROGRAM
DATA
Valid
Valid
Valid
Figure 49. External Program Memory Port Timing
DS95DSP0101 Q4/95
57
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
PACKAGE INFORMATION
44-Pin PLCC Package Diagram
68-Pin PLCC Package Diagram
58
DS95DSP0101 Q4/95
P R E L I M I N A R Y
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
44-Pin QFP Package Diagram
80-Pin QFP Package Diagram
DS95DSP0101 Q4/95
59
P R E L I M I N A R Y
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
PACKAGE INFORMATION (Continued)
100-Pin QFP Package Diagram
60
DS95DSP0101 Q4/95
P R E L I M I N A R Y
Z89323/373/393
16-BIT D IGITAL SIGNAL PROCESSORS
ORDERING INFORMATION
Z89323
Z89373
Z89393
44-Pin PLCC
44-Pin PLCC
100-Pin PQFP
Z8932320VSC
Z8932320VEC
Z8937316VSC
Z8939320FSC
68-Pin PLCC
Z893232XVSC
Z893232XVEC
68-Pin PLCC
Z893731XVSC
44-Pin PQFP
Z8932320FSC
Z8932320FEC
44-Pin PQFP
Z8937316FSC
80-Pin PQFP
Z893232YFSC
Z893232YFEC
80-Pin PQFP
Z893731YFSC
For fast results, contact your local Zilog sales office for
assistance in ordering the part desired.
Package
V = Plastic PLCC
F = Plastic QFP
Temperature
S = 0°C to +70°C
E = –40°C to +85°C
Speed
16 = 16 MHz
20 = 20 MHz
Environmental
C = Plastic Standard
Example:
is a Z89323, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow
Z 89323 20 V S C
Environmental Flow
Temperature
Package
Speed / Bond Out Option*
Product Number
Zilog Prefix
* 2X
20
2Y
1X
16
1Y
DS95DSP0101 Q4/95
=
=
=
=
=
=
20 MHz, 68-pin PLCC style package
20 MHz, 44-pin package
20 MHz, 80-Pin PQFP style package
16 MHz, 68-Pin PLCC style package
16 MHz, 44-Pin package
16 MHz 80-Pin PQFP style package
61