ETC Z9025900ZEM

Z90251 OTP
Z90255 ROM
32 KB TELEVISION CONTROLLER WITH OSD
PRODUCT SPECIFICATION
PS001300-TVC1099
ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008
TELEPHONE: 408.558.8500 • FAX: 408.558.8300 • HTTP://WWW.ZILOG.COM
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Document Disclaimer
© 1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use
of information, devices, or technology as critical components of life support systems is not authorized. No
licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property
rights.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table of Contents
1 OVERVIEW .......................................................................................... 9
1.1
1.2
1.3
Pin Assignment and Description .................................................. 13
Single-Purpose Pin Descriptions .................................................. 15
Multiplexed Pin Descriptions ........................................................ 17
2 MEMORY DESCRIPTION ................................................................. 19
2.1
2.2
2.3
Standard Register File ................................................................... 19
Expanded Register File .................................................................. 19
Program Memory ........................................................................... 19
3 ON-SCREEN DISPLAY ..................................................................... 23
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
OSD Position ..................................................................................
Second Color Feature ....................................................................
Mesh and Halftone Effect ..............................................................
OSD Fade ........................................................................................
Inter-Row Spacing .........................................................................
Character Generation ....................................................................
Character Size and Smoothing Effect ..........................................
Fringing Effect ................................................................................
Display Attribute Control ...............................................................
HV Interrupt Processing ..............................................................
23
27
29
34
37
38
40
41
42
51
4 Z90255 I2C MASTER INTERFACE ................................................... 54
4.1
Controlling the I2C Interface .......................................................... 56
5 INPUT/OUTPUT PORTS ................................................................... 58
6 INFRARED INTERFACE .................................................................... 67
7 PULSE WIDTH MODULATORS ....................................................... 71
7.1
7.2
7.3
PWM Mode Register ...................................................................... 71
PWM1 through PWM11 ................................................................. 73
Digital/Analog Conversion with PWM .......................................... 81
8 ANALOG - TO -DIGITAL CONVERTER ............................................ 82
9 ELECTRICAL CHARACTERISTICS ................................................... 85
9.1
9.2
Absolute Maximum Ratings ......................................................... 85
DC Characteristics .......................................................................... 86
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Preliminary
3
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
9.3
9.4
AC Characteristics .......................................................................... 87
Timing Diagram ............................................................................. 88
10 PACKAGING ..................................................................................... 89
11 Ordering Information ....................................................................... 90
12 ROM Code Submission ................................................................... 90
13 Customer Feedback Form ............................................................... 91
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Preliminary
4
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Code Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Z90255-Based TV System Application . . . . . . . . . . . . . . . . . . . . . . . . . 10
Z90255 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Z90255 and Z90251 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register File Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Positive and Negative Sync Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .
Second Color Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mesh On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Fade (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character Pixel map in CGROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of a Multiple Character Icon . . . . . . . . . . . . . . . . . . . . . . . . .
Smoothing Effect on 2X Character Size . . . . . . . . . . . . . . . . . . . . . . . .
VRAM Data Path for 512 Character Set . . . . . . . . . . . . . . . . . . . . . . . .
HSYNC and VSYNC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Bidirectional Port Pin Pad Multiplexed with I2C Port . . . . . . . . . . . . .
Pulse Width Modulator Timing Diagram, 6 Bit . . . . . . . . . . . . . . . . . .
Pulse Width Modulator Timing Diagram, 14-Bit . . . . . . . . . . . . . . . . .
Analog Signals Generated from PWM Signals . . . . . . . . . . . . . . . . . .
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Requirements of External Inputs . . . . . . . . . . . . . . . . . . . . . . .
42-Lead Shrink Dual-in-line Package (SDIP) . . . . . . . . . . . . . . . . . . . .
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Preliminary
24
29
30
35
38
39
40
43
53
54
73
74
81
84
88
89
5
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
PS001300-TVC1099
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Preliminary
6
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Z90255 Production Device Pin Assignment . . . . . . . . . . . . . . . . . . . . .
Single-Purpose Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OSD Control Register 00H:Bank A (OSD_CNTL) . . . . . . . . . . . . . . . . .
14
15
17
21
23
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Vertical Position Register 01H:Bank A (VERT_POS) . . . . . . . . . . . . . .
Horizontal Position Register 02H:Bank A (HOR_POS) . . . . . . . . . . . . .
Second Color Control Register 07H:Bank A (SNDCLR_CNTRL) . . . . .
Second Color Register 08H:Bank A (SNDCLR) . . . . . . . . . . . . . . . . . .
Mesh Column Start Register 04H: Bank F (MC_St) . . . . . . . . . . . . . . .
Mesh Column End Register 05H: Bank F (MC_End) . . . . . . . . . . . . . .
Mesh Row Enable Register 06H: Bank F (MR_En) . . . . . . . . . . . . . . . .
Mesh Control Register 07H: Bank F (MC_Reg) . . . . . . . . . . . . . . . . . .
BGR Mesh Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fade Position Register 1 05H: Bank A (FADE_POS1) . . . . . . . . . . . . .
Fade Position Register 2 06H: Bank A (FADE_POS2) . . . . . . . . . . . . .
Row Space Register 04H: BankA (ROW_SPACE) . . . . . . . . . . . . . . . . .
RGB Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Attribute Register 03H: Bank A (DISP_ATTR) . . . . . . . . . . . . .
VRAM Structure and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . .
Color Palette Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Color Index Register 09H: Bank C (CLR_IDX) . . . . . . . . . . . . . . . . . . . .
Color Palette 0 Register 09H: Bank A (CLR_P0) . . . . . . . . . . . . . . . . . .
Color Palette 1 Register 0AH: Bank A (CLR_P1) . . . . . . . . . . . . . . . . . .
Color Palette 2 Register 0BH: Bank A (CLR_P2) . . . . . . . . . . . . . . . . . .
Color Palette 3 Register 0CH: Bank A (CLR_P3) . . . . . . . . . . . . . . . . . .
Color Palette 4 Register 0DH: Bank A (CLR_P4) . . . . . . . . . . . . . . . . . .
Color Palette 5 Register 0EH: Bank A (CLR_P5) . . . . . . . . . . . . . . . . . .
Color Palette 6 Register 0FH: Bank A (CLR_P6) . . . . . . . . . . . . . . . . . .
Row Attribute Register (ROW_ATTR) . . . . . . . . . . . . . . . . . . . . . . . . . .
HV Interrupt Status Register 07H: Bank C (INT_ST) . . . . . . . . . . . . . .
Master I2C Control Register 0CH: Bank C (I2C_CNTL) . . . . . . . . . . . . .
25
26
27
28
30
31
31
32
34
36
36
37
41
42
44
46
46
47
47
48
48
49
49
49
50
51
Table 33
Table 34
Table 35
55
Master
Command Register 0BH: Bank C
. . . . . . . . . . . 56
2
2
Master I C Data Register 0AH: Bank C (I C_DATA) . . . . . . . . . . . . . . . 56
Master I2C Bus Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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I2C
(I2C_CMD)
Preliminary
7
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Port configuration Register 00H: Bank F (PCON) . . . . . . . . . . . . . . . . .
Port 2 Mode Register F6H: P2M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Data Register 02H: P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 4 Pin-Out Selection Register 08H: Bank C (PIN_SLT) . . . . . . . . .
Port 4 Data Register 05H: Bank C (PRT4_DTA) . . . . . . . . . . . . . . . . . .
Port 4 Direction Control Register 06H: Bank C (PRT4_DRT) . . . . . . . .
PWM Mode Register 0DH: Bank B (P_MODE) . . . . . . . . . . . . . . . . . . .
Port 5 Data Register CH: Bank B (PRT5_DTA) . . . . . . . . . . . . . . . . . . .
Port 5 Direction Control Register 0EH: Bank B (PRT5_DRT) . . . . . . . .
Port 6 Data Register 03H: Bank F (PRT6_DTA) . . . . . . . . . . . . . . . . . . .
Port 6 Direction Control Register 02H: Bank F (PRT6_DRT) . . . . . . . .
Timer Control Register 0 01H: Bank C (TCR0) . . . . . . . . . . . . . . . . . . .
Timer Control Register 1 02H: Bank C (TCR1) . . . . . . . . . . . . . . . . . . .
IR Capture Register 0 03H: Bank C (IR_CP0) . . . . . . . . . . . . . . . . . . . . .
IR Capture Register 1 04H: Bank C (IR_CP1) . . . . . . . . . . . . . . . . . . . . .
PWM Mode Register 0DH: Bank B (P_MODE) . . . . . . . . . . . . . . . . . . .
Port 4 Pin-Out Selection Register 08H: Bank C (PIN_SLT) . . . . . . . . .
PWM 1 Data Register 02H: Bank B (PWM1) . . . . . . . . . . . . . . . . . . . . .
PWM 2 Data Register 03H: Bank B (PWM2) . . . . . . . . . . . . . . . . . . . . .
PWM 3 Data Register 04H: Bank B (PWM3) . . . . . . . . . . . . . . . . . . . . .
PWM 4 Data Register 05H:Bank B (PWM4) . . . . . . . . . . . . . . . . . . . . .
PWM 5 Data Register 06H: Bank B (PWM5) . . . . . . . . . . . . . . . . . . . . .
PWM 6 (6-bit)Data Register 07H: Bank B (PWM6) . . . . . . . . . . . . . . . .
PWM 7 Data Register 08H: Bank B (PWM7) . . . . . . . . . . . . . . . . . . . . .
PWM 8 Data Register 09H: Bank B (PWM8) . . . . . . . . . . . . . . . . . . . . .
PWM 9 Data Register 0AH: Bank B (PWM9) . . . . . . . . . . . . . . . . . . . .
PWM 10 Data Register 0BH: Bank B (PWM10) . . . . . . . . . . . . . . . . . . .
PWM 6 (14-bit) High Data Register 08H: Bank F (PWM6H) . . . . . . . . .
PWM 6 (14-bit) Low Data Register 09H: Bank F (PWM6L) . . . . . . . . .
PWM 11 High Data Register 00H: Bank B (PWM11H) . . . . . . . . . . . . .
PWM 11 Low Data Register 01H: Bank B (PWM11L) . . . . . . . . . . . . . .
3-Bit ADC Data Register 00H: Bank C (3ADC_DTA) . . . . . . . . . . . . . . .
4-Bit ADC Data Register 01H: Bank F (4ADC_DTA) . . . . . . . . . . . . . . .
Operational Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Preliminary
58
59
59
60
61
62
63
63
64
65
66
67
68
69
70
71
72
75
75
75
76
76
77
77
77
78
78
79
79
79
80
83
83
85
86
87
89
8
Z90255 ROM and Z90251 OTP
32 KB Television Controller with On-Screen Display
1
OVERVIEW
The Z90255 and Z90251 are the ROM and OTP versions of a Television Controller with
On-Screen Display (OSD) that contains 32 KB of program memory.
•
The Z90251 is the one-time programmable (OTP) controller used to develop code
or prototypes for specific television applications or initial limited production.
Program ROM and Character Generation ROM (CGROM) in the Z90251 are both
programmable.
The Z90251 requires Zilog’s Z90259ZEM Emulator with its proprietary Zilog
Developmental Studio (ZDS) software for programing. To view how code is
working, the emulator uses a ZOSD board which connects directly to a television
screen. Refer to Figure 1.
Z90259 In-Circuit
Emulator (ICEbox)
ZOSD Board
Z90259
Z90251
Develop
code on PC
Download Code to
Z90259 ICE chip
Converts to
Video Display
Review Code
on TV Display
Program the
Z90251 OTP
Figure 1
•
Code Development Environment
The Z90255 incorporates the ROM code developed by the customer with the
Z90251. Customer code is masked into both program ROM and CGROM.
ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008
TELEPHONE: 408.558.8500 • FAX: 408.558.8300 • HTTP://WWW.ZILOG.COM
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
An application-specific controller designed to provide complete audio and video control
of television receivers and video recorders, the Z90255 provides advanced OSD features.
Figure 2 illustrates a typical TV system application using the Z90255. Figure 3 is a block
diagram of the Z90255 architecture.
FM Audio
Audio
Color
Decoder
Television
Tuner
IF Demodulator
R.G.B.
R.G.B.
MUX
Composite
Video
RGB
Output
Stages
CRT
HSYNC, VSYNC
Deflection
Unit
R.G.B.
SYNC
Tuning
Control
Control
Z90255 Television
OSD Controller
VBLANK
I2C Bus
Front Panel
Keypad
I/R
Detector
Figure 2
Z90255-Based TV System Application
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10
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
XTAL1
XTAL2
RESET
ADC0
ADC1
ADC2
ADC3
4-Bit
ADC
IRIN
IR
Counter
P60
P61
P62
P63
Port 6
PWM11
PWM6
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
P50
P51
P52
P53
P54
P55
P56
Figure 3
32 KB
Program ROM
or
32 KB
Program OTP
Oscillator
WDT
RESET
Counter
Timer
Counter
Timer
Port 2
P20
P21
P22
P23
P24
P25
P26
P27
Port 4
P40
P41
P42
P43
P44
P45
P46
P47
Internal
Microprocessor
Core
Register File
300 Byte
PWM 11 & 6
(14-bit)
Character RAM
240 x 12-Bit
& 10 x 8-Bit
PWM 1
to
PWM 10
(6-bit)
Character
ROM or OTP
18 KB by 7-Bit
Port 5
I2C
Interface
On-Screen
Display
SCLK0
SDATA0
SCLK1
SDATA1
OSDX1
OSDX2
HSYNC
VSYNC
R
G
B
VBLANK
HLFTN
Z90255 Block Diagram
Note: PWM 6 can be either a 6-bit or 14-bit output.
The Z90255 takes full advantage of Zilog’s Z8 expanded register file space to offer greater
flexibility in creating a user-friendly On-Screen Display (OSD).
Three basic addressing spaces are available: Program memory, Video RAM (VRAM) and
the Register file. The register file is composed of 300 bytes of general-purpose registers,
16 control and status registers, one I/O port register and three reserved registers.
The OSD module supports 10 rows by 24 columns of characters. Each character color can
be specified. There are eight foreground colors and eight background colors. When the
foreground and background colors are the same, the background is transparent.
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11
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
If Row, Second color and Character set are defined, an analog bar line can be displayed for
volume control, signal levels, and tuning.
The OSD can display four character sizes:
•
•
•
•
1X (14 x 18 pixels)
2X (28 x 36 pixels)
Double width (28 x 18 pixels)
Double height (14 x36 pixels)
Inter-row spacing can be programmed within 0 to 15 Horizontal scan lines. Using
multiple characters with zero inter-row spacing allows the creation of large psuedo icons.
A 14-bit Pulse Width Modulator (PWM) port provides necessary voltage resolution for a
voltage synthesizer tuning system. Ten 6-bit PWM ports are used to control audio (base,
treble, balance and volume) and video (contrast, brightness, color, tint and sharpness)
signal levels.
There are 27 I/O pins grouped into four ports. These I/O pins can be configured through
software to provide timing, status signals, serial and parallel input and output.
For real-time events, such as counting, timing and data communication, two on-chip
counter/timers are implemented. The Z90255 is packaged in a 42-pin SDIP and provides
an ideal, reliable solution for high-volume consumer television applications.
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12
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
1.1 Pin Assignment and Description
Figure 4 shows the pin numbers for production and OTP device format.
PWM11/P56
PWM6/P55
PWM5/P54
PWM4/P53
PWM3/P52
PWM2/P51
PWM1/P50
P40
P60/ADC3
P61/ADC2
P41/ADC1
P62/ADC0
AGND
P42
P43
P63
P44/PWM7
P45/PWM8
P46/PWM9
P47/PWM10
P20/HLFTN
Figure 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Z90251
or
Z90255
(Top View)
42
41
40
39
38
P27/SDATA1
P26/SCLK1
P25/SDATA0
P24/SCLK0
P23
37
P22
36
35
34
33
32
31
30
IRIN
P21
VCC
29
28
27
26
25
24
23
OSDX2
OSDX1
VSYNC
HSYNC
VBLANK
R
G
22
B
RESET
XTAL2
XTAL1
GND
Z90255 and Z90251 Pin Assignments
Note:
1.
The pins on the Z90255 and Z90251 are assigned to perform the functions identified
in Tables 1,2 and 3.
2.
PWM 6 can be either 6-bit or 14-bit PWM outputs.
3.
All signals with an overbar are active Low.
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Preliminary
13
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 1
Z90255 Production Device Pin Assignment
Name
Pin Function
Package 42-Pin SDIP Direction
POR
VCC
+5 Volts
34
Power
Power
GND, AGND
0 Volts
30, 13
Power
Power
IRIN
Infrared Remote Capture Input
36
I
I
PWM11
14-bit Pulse Width Modulator
Output
1
O
N/A
PWM10-PWM11
6-Bit Pulse Width Modulator
Output
20, 19, 18, 17, 2, 3, 4, 5, 6, O
7
N/A
P5 (6-0)
Bit Programmable I/O Ports
1, 2, 3, 4, 5, 6, 7
I/O
I
P2 (7-0)
Bit-Programmable I/O Ports
42, 41, 40, 39, 38, 37, 35,
21
I/O
I
HLFTN
Halftone Output
21
O
N/A
SDATA0, SDATA1
I2C
Data, Bidirectional (Send/
Receive) Serial Data Lines
40,
422
I/O
N/A
SCLK0, SCLK1
I2C Clock
39, 412
I/O
N/A
P6 (3-0)
Bit-Programmable I/O Ports
16, 12, 10, 9
I/O
I
P4 (7-0)
Bit-Programmable I/O Ports
20, 19, 18, 17, 15, 14, 11, 8 I/O
I
XTAL1
Crystal Oscillator Input
31
I
I
XTAL2
Crystal Oscillator Output
32
O
O
OSDX1
Dot-Clock Oscillator Input
28
I
I
OSDX2
Dot-Clock Oscillator Output
29
O
O
HSYNC
Horizontal Synchronization
26
I
I
VSYNC
Vertical Synchronization
27
I
I
VBLANK
Video Blanking
25
O
O
R,G,B
Video Red, Green, Blue
24, 23, 22
O
O
ADC3-ADC0
4-Bit Analog-to-Digital
Converter Input
9, 10, 11, 12
AI
I
RESET
Device Reset
33
I/O
I
Note:
1.
PWM 6 can be either 6-bit or 14-bit PWM outputs.
2.
When Pins 39-42 are configured for I2C, pins 39 and 40 comprise one channel,
and pins 41 and 42 comprise another channel
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14
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
1.2 Single-Purpose Pin Descriptions
Table 2 lists the single-purpose pin acronyms, pin names, and descriptions.
Table 2
Single-Purpose Pin Descriptions
Acronym
Pin Name(s)
Description
AGND
Analog Ground
Analog Ground
B
Blue
CMOS output of the blue video signal B. Video blue
can be programmed for either polarity.
G
Green
CMOS output of the green video signal G. Video
green can be programmed for either polarity.
GND
Ground
Ground
HSYNC
Horizontal Sync
Input pin for external horizontal synchronization
signal
IRIN
IR Capture Input
Infrared Remote capture input
OSDX1, OSDX2 On-Screen Display Dot
Clock Oscillators
These oscillator input and output pins for on-screen
display circuits are connected to an inductor and two
capacitors to generate the character dot clock. The
dot clock frequency determines the character pixel
width and phase synchronized to HSYNC
P21, P22, P23
Port 2 bits 1 - 3
Bidirectional digital port, configured to read digital
data or to send output to an attached device.
P40, P42, P43
Port 4 bit 0, bits 2 and 3
Bidirectional digital port, configured to read digital
data or to send output to an attached device.
P63
Port 6 bit 3
P63 input can be read directly at 03H. A negative
edge event is latched to IRQ3. An IRQ3-vectored
interrupt occurs if appropriately enabled. A typical
application places the device in Stop mode when
P63 goes Low (IRQ3 interrupt routine). When P63
subsequently goes High, a Stop-Mode Recovery is
initiated.
R
Red
CMOS output of the red video signal R. Video red can
be programmed for either polarity.
RESET
System Reset
System reset
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15
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 2
Single-Purpose Pin Descriptions
Acronym
Pin Name(s)
Description
VBLANK
Video Blank
CMOS output, programmable polarity. This pin is
used as a super-impose control port to display
characters from video RAM. The signal controls Ysignal output of CRTs and turns off the incoming
video display while the characters in video RAM are
super-imposed on the screen. The output ports of
color data directly drive three electron guns on the
CRT; at the same time VBLANK output turns off the Y
signal.
VCC
Power Supply
Power supply
VSYNC
Vertical Sync
Input pin for external vertical synchronization signal.
XTAL1, XTAL2 Time-Based
Input
Output
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These pins connect to the internal parallel-resonant
clock crystal oscillator circuit with two capacitors to
GND. XTAL1 can be used as an external clock input.
Preliminary
16
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
1.3 Multiplexed Pin Descriptions
Table 3 lists the Multiplexed Pin acronyms, pin names, and descriptions.
Table 3
Multiplexed Pin Descriptions
Acronym
Pin Name(s)
Description
P20/HLFTN
Port 2 bit 0 or Halftone
Output
Port 2 bit 0 can be programmed as an input or
output line.
P24/SCLK0
Port 2 bit 4 or I2C Clock
Port 2 bit 4 or I2C Clock
P25/SDATA0
Port 2 bit 5 or I2C Data
Port 2 bit 5 or I2C Data
P26/SCLK1
P27/SDATA1
Port 2 bit 6 or I2C Clock
Port 2 bit 7 or I2C Data
Port 2 bit 6 or I2C Clock
Port 2 bit 7 or I2C Data
P62/ADC0
Port 6 bit 2 or
P62 can be read directly. A negative edge event is
Analog-to-Digital Converter latched into IRQ2 to initiate an IRQ2-vectored
Channel 0
interrupt if appropriately enabled.
P60/ADC3
Port 6 bit 0 or
Port 6 bit 0 can be programmed as an input or
Analog-to-Digital Converter output line.
Channel 3
P61/ADC2
Port 6 bit 1 or
Port 6 bit 1 can be programmed as an input or
Analog-to-Digital Converter output line.
Channel 2
P41/ADC1
Port 4 bit1 can be programmed as an input or output
Port 4 bit 1 or
Analog-to-Digital Converter line.
Channel 1
P44/PWM7
Port 4 bit 4 or Pulse Width
Modulator 7
P45/PWM8
Port 4 bit 5 or Pulse Width
Modulator 8
P46/PWM9
Port 4 bit 6 or Pulse Width
Modulator 9
P47/PWM10
Port 4 bit 7 or Pulse Width
Modulator 10
PWM11/P56
Pulse Width Modulator 11
or Port 5 bit 6
PWM6/P55
Pulse Width Modulator 6 or
Port 5 bit 5
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These port pins can be programmed as input or
output ports. Each PWM channel has 6-bit
resolution.
The PWM signal-generator channel has 14-bit
resolution. Port 5 bit 6 and port 5 bit 5 can be
programmed as inputs or outputs.
Preliminary
17
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 3
Multiplexed Pin Descriptions (Continued)
Acronym
Pin Name(s)
PWM6/P55
Pulse Width Modulator 6 or These port pins can be programmed as input or
Port 5 bit 5
output ports. Each PWM signal-generator channel
has 6-bit resolution.
Pulse Width Modulator 5 or
Port 5 bit 4
PWM5/P54
Description
PWM4/P53
Pulse Width Modulator 4 or
Port 5 bit 3
PWM3/P52
Pulse Width Modulator 3 or
Port 5 bit 2
PWM2/P51
Pulse Width Modulator 2 or The PWM signal-generator channel has 6-bit
Port 5 bit 1
resolution. Port 5 bit 1 and Port 5 bit 0 can be
programmed as an input or output port.
PWM1/P50
Pulse Width Modulator 1 or The PWM signal-generator channel has 6-bit
Port 5 bit 0
resolution. Port 5 bit 0 can be programmed as an
input or output port.
Note: PWM6 can be either 6-bit or 14-bit output.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
2
MEMORY DESCRIPTION
A total of 300 bytes of general purpose register memory is implemented in the Z90255.
These registers are composed of 236 registers from the standard register file and 64
registers from the expanded register file.
2.1 Standard Register File
The Z90255 Standard Register File consists of two I/O port registers (02h and 03h), 236
general purpose registers (04h-EFh) and 15 (F1h-FFh) control and status registers.
Registers 00h, 01h, and F0h are reserved. Figure 5 is the register file map. Instructions can
access registers directly or indirectly with an 8-bit address field. This also allows short 4bit addressing using the Register Pointer. In the 4-bit mode, the register file is divided into
sixteen working register groups. The upper nibble of the Register Pointer (FDh) addresses
the starting location of the active working-register group.
Note: Registers E0h-EFh are only accessed through a working-register and indirect
addressing mode.
2.2 Expanded Register File
The register file has been expanded to provide additional system control registers,
additional general purpose registers, and expanded mapping of peripheral devices and I/O
ports in the register address area.
The lower nibble of the Register Pointer (FDh) addresses the Expanded Register File
(ERF) Bank. The 0h value in the lower nibble identifies the Standard Register File to be
addressed. Any other value from 1h to Fh selects an ERF Bank. When an ERF Bank is
selected, register addresses from 00h to 0Fh access the sixteen ERF Bank registers, which
in effect replace the first sixteen locations of the Z90255 Standard Register File. Only ERF
Bank 4, ERF Bank 5, ERF Bank 6, ERF Bank 7, ERF Bank A, ERF Bank B, ERF Bank C
and ERF Bank F are implemented in the Z90255 controller (Table 4).
2.3 Program Memory
The Z90255 has 32KB of program memory. Refer to Figure 6. The first 12 bytes of the
program memory are reserved for the interrupt vectors. These locations contain six 16-bit
vectors that correspond to interrupt and program control routine addresses which are
passed to the specified vector address. The IRQ0 vector is permanently assigned to the IR
interrupt request. The IRQ1 vector is permanently assigned to the VSYNC and HSYNC
interrupt request. Program memory starts at address 000Ch after being reset.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Reset Condition
D7 D6 D5 D4 D3 D2 D1 D0
Register
Register Pointer
D7 D6 D5 D4 D3 D2 D1 D0
Working Register
Group Pointer
Expanded Register
Bank Pointer
Z8 Register File
%FF
%F0
%FF
SPL
x
x
x
x
x
x
x
x
%FE
SPH
x
x
x
x
x
x
x
x
%FD
RP
0
0
0
0
0
0
0
0
%FC
FLAGS
x
x
x
x
x
x
x
x
%FB
IMR
0
x
x
x
x
x
x
x
%FA
IRQ
0
0
0
0
0
0
0
0
%F9
IPR
x
x
x
x
x
x
x
x
%F8
P01M
1
1
1
1
1
1
1
1
%F7
P2CNTL
0
0
0
0
0
0
0
1
%F6
P2M
1
1
1
1
1
1
1
1
%F5
PRE0
x
x
x
x
x
x
x
0
%F4
T0
x
x
x
x
x
x
x
x
%F3
PRE1
x
x
x
x
x
x
0
0
%F2
T1
x
x
x
x
x
x
x
x
%F1
TMR
0
0
0
0
0
0
0
0
%F0
Reserved
Expanded Register Bank (F)
Register
Reset Condition
%(F)0F WDTMR
x
x
x
x
x
1
x
x
0
0
1
0
0
0
0
0
%(F)0E Reserved
%(F)0D Reserved
%7F
%(F)0C Reserved
%(F)0B SMR
%(F)0A Reserved
(C)
(B)
%0F
%00
(7) (A)
(6)
(5)
(4)
Reserved Expanded
Register
%(F)09 PWM6H
x
x
0
0
0
0
0
0
%(F)08 PWM6L
0
0
0
0
0
0
0
0
%(F)07 MC_Reg
0
0
0
0
0
0
0
0
%(F)06 MR_En
0
0
0
0
0
0
0
0
%(F)05 MC_End
x
x
x
0
0
0
0
0
%(F)04 MC_St
x
x
x
0
0
0
0
0
%(F)03 PRT6_DTA
1
1
1
1
1
1
1
1
%(F)02 PRT6_DRT
1
1
1
1
1
1
1
1
%(F)01 4ADC_DTA
0
0
0
0
x
x
x
x
%(F)00 PCON
1
1
1
1
1
1
1
0
Register
Reset Condition
%(0)03 Reserved
%(0)02
x = undefined
P2
x
x
x
x
x
x
x
x
%(0)01 Reserved
%(0)00 Reserved
Figure 5
Register File Map
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20
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 4
Register File Map
BANK 4
BANK 5
Address Description
00h-0Fh Gen. Pur. Reg.
Address Description
00h-0Fh Gen. Pur. Reg.
BANK 6
BANK A
BANK B
Address Description
00h OSD Control Register(OSD_CNTL)
01h Vertical Position Register(VERT_POS)
02h Horizontal Position Register(HOR_POS)
03h Display Attribute Register(DISP_ATTR)
04h Row Space Register (ROW_SPACE)
05h Fade Position1 Register(FADE_POS1)
06h Fade Position2 Regisiter(FADE_POS2)
07h Second Color Control
Register(SNDCLR_CNTRL)
08h Second Color Position
Register(SNDCLR_POS)
09h Color Palette0 Register(CLR_P0)
0Ah Color Palette1 Register(CLR_P1)
0Bh Color Palette2 Register(CLR_P2)
0Ch Color Palette3 Register(CLR_P3)
0Dh Color Palette4 Register(CLR_P4)
0Eh Color Palette5 Register(CLR_P5)
0Fh Color Palette6 Register(CLR_P6)
BANK C
Address Description
00h 3-bit ADC Data Register(3ADC_DTA)
01h Timer Control Register0(TCR0)
02h Timer Control Register1(TCR1)
03h IR Capture Register0(IR_CP0)
04h IR Capture Register1(IR_CP1)
05h Port4 Data Register(PRT4_DTA)
06h Port4 Direction Register(PRT4_DRT)
07h Interrupt Status Register(INT_ST)
08h Port4 Pin_out Selection Register(PIN_SLT)
09h Color Index Register(CLR_IDX)
0Ah I2C Data Register(I2C_DATA)
0Bh I2C Command Register(I2C_CMD)
0Ch I2C Control Register(I2C_CNTL)
0Dh
0Eh
0Fh
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BANK 7
Address Description Address Description
00h-0Fh Gen. Pur. Reg. 00h-0Fh Gen. Pur. Reg.
Preliminary
Address
00h
01h
02h
03h
04h
05h
06h
07h
Description
PWM11-High Data Register(PWM11H)
PWM11-Low Data Register(PWM11L)
PWM1 Data Register(PWM1)
PWM2 Data Register(PWM2)
PWM3 Data Register(PWM3)
PWM4 Data Register(PWM4)
PWM5 Data Register(PWM5)
PWM6(6-bit) Data Register(PWM6_6)
08h
PWM7 Data Register(PWM7)
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PWM8 Data Register(PWM8)
PWM9 Data Register(PWM9)
PWM10 Data Register(PWM10)
Port 5 Data Register(PRT5_DTA)
PWM Mode Register(P_MODE)
Port 5 Direction Register(PRT5_DRT)
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
BANK F
Description
Port Configuration Register(PCON)
4-bit ADC Data Register (4ADC_DTA)
Port6 Direction Register(PRT6_DRT)
Port6 Data Register (PRT6_DTA)
Mesh Column Start Register(MC_ST)
Mesh Column End Register(MC_END)
Mesh Row Enable Register(MR_EN)
Mesh Control Register(MC_REG)
PWM6 High Data Register(PWM6H_14)
PWM6 Low Data Register (PWM6L_14)
Stop Mode Register(SMR)
WDT Mode Register(WDTMR)
21
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
IR IRQ0(High Byte)
0000h
IR IRQ0(Low Byte)
0001h
HVSYNC IRQ1(High Byte)
0002h
HVSYNC IRQ1(Low Byte)
0003h
P62 IRQ2(High Byte)
0004h
P62 IRQ2(Low Byte)
0005h
P63 IRQ3(High Byte)
0006h
P63 IRQ3(Low Byte)
0007h
T0 IRQ4(High Byte)
0008h
FBFFh
T0 IRQ4(Low Byte)
0009h
FC00h
T1 IRQ5(High Byte)
000Ah
T1 IRQ5(Low Byte)
000Bh
Reset Start Address
000Ch
8000h
Reserved
Video
Refresh
RAM
On Chip Program Space
(32KB)
7FFFh
Figure 6
FFFFh
Program Memory Map
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22
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3
ON-SCREEN DISPLAY
The On-Screen Display (OSD) module generates and displays a 10 row by 24 columns of
512 characters at 14 x 18-dots resolution. The color of each character can be specified
independently.
The televison OSD controller uses HSYNC and VSYNC signals to synchronize its internal
circuitry to the video signal, then outputs RGB and Video Blank (VBLANK) signals. The
VBLANK signal is used to multiplex the OSD signal and video signal onto the screen. The
result is that the On-Screen Display is superimposed over the TV picture.
The display results from the successful timing of several components:
•
•
•
•
•
•
OSD Positioning
Second Color Feature
Mesh and Halftone Effect
OSD Fade
Inter-Row Spacing
Character Generation
3.1 OSD Position
OSD Positioning is controlled by programming the following registers:
•
•
•
OSD Control Register (Table 5)
Vertical Position Register (Table 6)
Horizontal Position Register (Table 7)
OSD Control Register
Table 5
Bit
R/W
Reset
OSD Control Register 00h:Bank A (OSD_CNTL)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
x
x
x
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position R/W Value Description
OSD Blank
7
R/W
0
1
Enable OSD - POR default
Disable OSD
VRAM Mode
6, 5
R/W
00
01
10
11
Select 10-row buffer mode
Reserved
Select 2-row buffer mode
Reserved
Sync Polarity
4
R/W
0
1
Positive
Negative
Character Size
3
R/W
0
1
1X
2X
Vertical Retrace Blanking
2, 1, 0
R/W
Retrace Blanking
Bit 4, Sync Polarity, provides the polarity of the HSYNC and VSYNC signals. HSYNC and
VSYNC must have the same polarity (see Figure 7). This feature is designed to provide
flexibility for TV chassis designers.
Positive SYNC
Negative SYNC
Figure 7
Positive and Negative Sync Signals
Bit 3, Character Size, sets the size of the characters that are displayed. Character sizes 1X,
2X, double width and double height are supported. The default value is 1X.
To change the size of the characters in a row, alter the value of the bit during the previous
horizontal interrupt. The character size of the first row is programmed during vertical
interrupt (VSYNC) processing. Character size is a row attribute.
Bits 2, 1, and 0, Vertical Retrace Blanking, set a time period when the OSD is disabled
while the electron gun returns from the bottom to the top of the screen, and all VBLANK
and RGB output are disabled. The blanking period is determined by counting horizontal
pulses according to the following formula:
Blanking Period=(4 x (Vertical Retrace Blanking)+2) x THL
THL: one horizontal period
The retrace blanking bits, OSD_CNTL (2,1,0) must be set to deactivate the electron
guns during the retrace period.
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24
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Vertical Position Register
The Vertical Position Register (Table 6) sets the vertical placement of the OSD on the
screen. The unit of measure for placement is the number of scan lines from the top of the
TV field.
Table 6
Vertical Position Register 01h:Bank A (VERT_POS)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
reserved
7
R/W Value Description
Character double 6
height
Vertical Position
5,4,3,2,1,0
R
W
0
1
Return 0
No effect
R/W
0
Normal when bit 3 of OSD_CNTL is 0.
2X when bit 3 of OSD_CNTL is 1.
1
Double height when bit 3 of
OSD_CNTL is 0.
Double width when bit 3 of
OSD_CNTL is 1.
R/W
Vertical position control
The value required for this register can be computed using the following equation:
VERT_POS = (VPOS - 6) / 4
VERT_POS represents the contents of bits 5,4,3,2,1,0 of the Vertical Position Register
(VERT_POS). The default value is 0. When the value is 0, the OSD is at the top-most
OSD position on the screen, with an offset of 06h scan lines above the OSD area.
VERT_POS is the number of scan lines from the VSYNC to the OSD start position. VPOS
must be a positive integer with a minimum value of Ah incrementing by 4.
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25
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Horizontal Position Register
The Horizontal Position Register sets the horizontal start position of the OSD (Table 7).
The unit of measure for placement is the number of pixels from the left of the display
screen.
Table 7
Horizontal Position Register 02h:Bank A (HOR_POS)
Bit
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
1
1
Reset
NOTE: R = Read W = Write X = Indeterminate
Register Field
Bit Position R/W
Data
Description
Progressive mode
7-------
R/W
0
1
Normal
Support progressive sync inputs
Reserved
-6------
R
W
Return 1
No effect
Horizontal position
5,4,3,2,1,0
R/W
Horizontal position control
Note: When working with Progressive mode, fringing does not work with 2X mode or
double height mode, nor does Mesh work the same way as in Interlace mode.
The value required for this register can be computed using the following equation:
HOR_POS = (HPOS - 1) / 4
HOR_POS represents the contents of bits 5,4,3,2,1,0 of the Horizontal Position
Register (HOR_POS). The default value is 3h. When the value is 3h, the OSD is at the
left-most OSD position on the screen.
HPOS is the number of pixels from the left of the screen to the OSD start position. HPOS
must be a positive integer with a minimum value of 5 incrementing by 4.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.2 Second Color Feature
Second Color feature is the logical division of each column into two parts along each row
for changing foreground color. The number of each half-column is called the Second
Color Position.
The Second Color feature can be used to implement an analog bar for volume control,
tuning, etc. The change step for color is half the character size. Refer to Tables 8 and 9.
Second Color Control Register
The Second Color Position is the place where the foreground color changes to the color
defined in the Second Color Control Register.
Table 8
Second Color Control Register 07h:Bank A (SNDCLR_CNTRL)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position R/W Value Description
Second Color Enable
7
R/W
Second Color
6, 5, 4
R/W
R, G, B respectively. Defines the
second color after the second color
position defined in SNDCLR
register.
Row Address
3, 2, 1, 0 R/W
Defines one of the 10 rows (from 0,
the first row, to 9, the 10th row).
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Preliminary
0
1
Disables the second color feature
Enables the second color feature
27
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Second Color Register
Table 9
Bit
R/W
Reset
Second Color Register 08h:Bank A (SNDCLR)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7
R/W
Value Description
R
W
0
1
Return 1
No effect
HVSYNC Interrupt Option 6
R/W
0
1
Interrupt Pending Disabled
Interrupt Pending Enabled
Second Color Position
R/W
5,4,3,2,1,0
Specifies start position of
the color change to the
second color.
Note: Column increment is 0.5. Offset is 03h. System software requires that the offset be
added to the increment for the second color in the bar display. The bar position
must be defined before the second color is enabled.
Bit 6, HVSYNC Interrupt Option, defines the procedure for processing when a second
interrupt is issued before the first interrupt has completed processing. If bit 6 is set to 0,
bit 6 is not pending the other interrupt (HSYNC or VSYNC) while one is in service. If bit 6
is set to 1, bit 6 is pending the other interrupt (HSYNC or VSYNC) while one is in service.
Figure 8 is an example of second color display in the eighth row of the OSD. Each of the
small grid squares represents one pixel. Each column has two areas for second color
display. In this example, the second color is at Position 6. The second color position for
the first column has a value of 3 because the OSD is offset from the left of the TV screen at
a distance equal to 03h. Each column is the size of one display character. Each Second
color column is a half character column. The screen position offset is added to Second
color position. Because the offest is 03h, the Second color postions begin with 3 = (3+0),
4 = (3+1), 5 = (4+1), and so forth.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
7th Row
8 th Row
9th Row
(3)
(4 )
1st Column
(5)
(6)
2nd Column
(7)
(8)
3 r d Column
(9)
Bar Column Position
Figure 8
Second Color Display
3.3 Mesh and Halftone Effect
Mesh is a grid-like area that contains an alternating pixel display of OSD and transparent
zones. See Figure 9. The transparent zones allow the TV signal display to appear in part
while the mesh display is active.
Halftone effect is a transparent area that appears slightly darker than the regular picture
carried by the TV signal.
Mesh and halftone effects both serve as backgrounds for menus, action bars, and other
On-Screen Displays. The mesh feature is only for interlaced-mode video systems.
Mesh can be controlled in two ways: through hardware or through software for alternating
pixel display in different fields.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Mesh
Picture Screen
Field 1
Field 2
OSD
Fringing
Figure 9
Mesh On (Mesh Color)
Mesh On
General descriptions of the registers used to control the mesh are contained in Tables 10
through 13.
Table 10
Bit
R/W
Reset
Mesh Column Start Register 04h: Bank F (MC_St)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6, 5
R
W
Return 1
No effect
Mesh Window Start
4, 3, 2, 1, 0
R/W
Defines the start character
number in the mesh window.
Table 11
Value Description
Mesh Column End Register 05h: Bank F (MC_End)
Bit
R/W
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
0
0
0
0
0
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6, 5
Mesh Window End
4, 3, 2, 1, 0 R/W
R/W
Value Description
R
W
Return 1
No effect
Defines the character number after
the mesh window display.
MC_St and MC_End define the width and horizontal position of the mesh window.
Table 12
Bit
R/W
Reset
Mesh Row Enable Register 06h: Bank F (MR_En)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
PS001300-TVC1099
Preliminary
31
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position R/W Value Description
VBLANK Delay
7, 6, 5, 4 R/W
Foreground Character for
Halftone Effect
3
R/W
Reserved
2, 1
R/W
Mesh Window Row
0
R/W
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
No Delay
Delay by 0.5 Dot-Clock Period
Delay by 1.0 Dot-Clock Period
Delay by 1.5 Dot-Clock Period
Delay by 2.0 Dot-Clock Period
Delay by 2.5 Dot-Clock Period
Delay by 3.0 Dot-Clock Period
Delay by 3.5 Dot-Clock Period
Delay by 4.0 Dot-Clock Period
Delay by 4.5 Dot-Clock Period
Delay by 5.0 Dot-Clock Period
Delay by 5.5 Dot-Clock Period
Delay by 6.0 Dot-Clock Period
Delay by 6.5 Dot-Clock Period
Delay by 7.0 Dot-Clock Period
Delay by 7.5 Dot-Clock Period
Not included
Included
Must be 0
0
1
No mesh OSD for Next Row
Mesh OSD for Next Row
Bits 7, 6, 5, and 4, VBLANK Delay, set the amount of time that the VBLANK signal is
properly aligned with the OSD RGB output with delay from external circuitries.
Bit 3, Character Foreground for Halftone Effect, defines whether displaying a foreground
color for character display is included. If bit 3 is set to 0, halftone is disabled for pixels
with foreground color. If bit 3 is set to 1, halftone is active for pixels with both foreground
and background colors.
Bit 0, Mesh Window Row, sets the mesh effect to On or Off for the next row of the OSD.
Table 13
Bit
R/W
Reset
Mesh Control Register 07h: Bank F (MC_Reg)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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32
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
R/W
Value
Description
Halftone Effect Output 7
Delay on P20
R/W
xx/x
00/0
00/1
01/0
01/1
10/0
10/1
11/0
11/1
Mesh Color
6, 5, 4
R/W
P20 for
Halftoning
3
R/W
0
1
Normal Mesh effect
Use P20 Output for Halftoning
Software Field
2
Number/Polarity of
Halftone Effect Output
R/W
0
Even Field/Positive Halftone
Effect Output
Odd Field/Negative Halftone
Effect Output
Software Mesh
1
R/W
0
1
Hardware Defines Field Number
Software Defined Field Number
Mesh Enable
0
R/W
0
1
Mesh is Disabled
Mesh is Enabled
Bits 5, 4 in ROW_SPACE/ bit 7
No Delay
Delay by 0.5 Dot-Clock Period
Delay by 1.0 Dot-Clock Period
Delay by 1.5 Dot-Clock Period
Delay by 2.0 Dot-Clock Period
Delay by 2.5 Dot-Clock Period
Delay by 3.0 Dot-Clock Period
Delay by 3.5 Dot-Clock Period
Defines the mesh color.
B,G,R respectively.
1
Note: When working with Progressive mode, mesh does not work the same way as in
Interlace mode.
Bit 7, Halftone Output Delay on P20, is the amount of time that output of the halftone
signal is delayed to compensate for the amount of delay of OSD RGB from external
circuitries.
Bits 6, 5, and 4, Mesh Color, define the color of the mesh window. The colors are
specified in Blue, Green, Red order, as shown in Table 14.
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33
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 14
BGR Mesh Colors
B
G
R
Color
0
0
0
Black
0
0
1
Red
0
1
0
Green
0
1
1
Yellow
1
0
0
Blue
1
0
1
Magenta
1
1
0
Cyan
1
1
1
White
Bit 3,P20 for Halftone, selects mesh or halftone effect. If bit 3 is set to 1, P20 outputs
halftone. If reset to 0,P20 is a normal I/O pin.
Bit 2, Software Field Number/Polarity of Halftone Output, has several possible values.
The value of this bit remains the same for the entire mesh window; it does not change from
row to row.
If bit 3 is set to 1 (halftone), bit 2 defines the polarity of halftone output. If bit 3 is reset
to 0 and bit 1 is set to 1, then bit 2 defines the field number (even or odd).
Bit 1, Software Mesh, defines whether hardware or software sets the current field number.
When the value equals 0, hardware defines field number. When the value equals 1,
software defines the field number.
Bit 0, Mesh Enable, disables or enables using mesh. This field is used in conjunction with
MR_EN (0). The value of Mesh Enable is changed only when Mesh Window Row equals
0 (the current OSD row is not part of a mesh window). If the value is changed when the
current row is part of the mesh window, partial or missing characters are likely to be
displayed.
3.4 OSD Fade
Fading is the gradual disappearance of the OSD. Fading occurs vertically, up or down.
Figure 10 shows the fade-down effect.
Fade control registers can only be updated during VSYNC, not during row interrupt.
Otherwise, unexpected results can occur.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Figure 10
Video Fade (Example)
This feature is controlled through the FADE_POS1 (Table 15), FADE_POS2 (Table 16),
and ROW_SPACE registers (Table 17).
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35
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 15
Fade Position Register 1 05h: Bank A (FADE_POS1)
Bit
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
0
0
0
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6, 5, 4
R
W
Row Number of the Screen
3, 2, 1, 0
R/W
R/W Value Description
Return 1
No effect
OSD Row number for fading
Bits 3, 2, 1, and 0 define the boundary row for the fade area. The portion of the OSD
above or below the row number fades up or down, as set in Fade Direction,
ROW_SPACE(6).
The fade starts at the scan line set in FADE_POS2 (4,3,2,1,0) within the row
number set in FADE_POS1 (3,2,1,0).
Table 16
Fade Position Register 2 06h: Bank A (FADE_POS2)
Bit
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
0
0
0
0
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6, 5
Scan Line Number
4, 3, 2, 1, 0
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R/W
R
W
R/W
Preliminary
Value
Description
Return 1
No effect
Scan Line Number of a row
36
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.5 Inter-Row Spacing
Inter-Row Spacing can be from 0 to 15 horizontal scan line (HL). A setting of 0 HL is
called Continuous Row Display. A horizontal interrupt is generated at the start of each
row. Software must program the spacing between the current row and the next row during
the current horizontal interrrupt.
The time required to process a row must not exceed the display time of the row. Refer to
Table 17.
Table 17
Row Space Register 04h: BankA (ROW_SPACE)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
Fade On/Off
7
R/W
0
1
Fade feature disabled
Fade feature enabled
Fade Direction
6
R/W
0
Fade area below the defined
fade position
Fade area above the sefined
fade position
Value Description
1
Halftone Effect Output
Delay On P20
5, 4
R/W
Works with bit 7 in MC_Reg
Inter-Row Space
3, 2, 1, 0
R/W
Inter row spacing
Bit 7, Fade ON/OFF, disables or enables the fade effect.
Bit 6, Fade Direction, controls the direction of the fade effect. When Fade Direction is set
to 0, the bottom of the TV screen is faded out. Fading occurs beginning with the row
number set in FADE_POS1 (3,2,1,0) and the scan line number set in FADE_POS2
(4,3,2,1,0). When the Fade Direction is set to 1, the top of the screen is faded out.
Bits 5 and 4, Halftone Effect Delay on P20, work with MC_REG (7).
Bits 3, 2, 1, and 0, Inter-Row Space, specify the number of HL to add between
displayed rows.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.6 Character Generation
Character generation provides the content of the OSD. The Z90255 supports 14-pixel
(horizontal) by 18-pixel (vertical) character display with 512 character sets.
Character Cell Resolution
Characters are mapped pixel-by-pixel in Character Generation Read-Only Memory
(CGROM).
Hex Add
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000a
000b
000c
000d
000e
000f
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
001a
001b
001c
001d
001e
001f
0020
0021
0022
0023
0024
0039
0040
0063
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Left Half
Right Half
7fc0
7fa3
7fa4
7fbf
address GAP
Character Pattern
Figure 11
7fc0
7fc1
7fc2
7fc3
7fc4
7fc5
7fc6
7fc7
7fc8
7fc9
7fca
7fcb
7fcc
7fcd
7fce
7fcf
7fd0
7fd1
7fd2
7fd3
7fd4
7fd5
7fd6
7fd7
7fd8
7fd9
7fda
7fdb
7fdc
7fdd
7fde
7fdf
7fe0
7fe1
7fe2
7fe3
Character Pattern
address GAP
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
Left Half
Right Half
Character Pixel map in CGROM
Figure 11 is an example of a 512 character set where the character pixel map represents
the first and last characters. It is 14 pixels horizontal and 18 pixels vertical. Each row in
the map is 7 bits long, half the width of the character scan line.
Even numbered rows in the map correspond to pixels on the left half of the character scan
line; odd rows in the map correspond to pixels on the right half of the character scan line.
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38
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
The Hex Add column is a hexadecimal number that serves as an address for the group of
pixels from the starting point of the scan line. Addressing begins at 0000h and ends at
0023h for the first character. There is an address gap between characters. The starting
address for the second character is 0040h.
Each bit in the map sets the foreground/background designation of the corresponding
pixel:
0 background pixel
1 foreground pixel
The patterns formed by the bits comprise the characters that are displayed when the scan
line is output to the screen.
Each of these character pixel maps is one character; 512 characters can be mapped.
Several characters can be combined to form a large icon. Figure 12 is an example of a
large icon. Each block marked by the darker grid lines is 14 x 18 pixels, one character.
Row 4
No Spacing
Row 5
No spacing
Row 6
6HL
Spacing
Row 7
Fringing Effect
Figure 12
Example of a Multiple Character Icon
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39
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.7 Character Size and Smoothing Effect
The Z90255 supports four character sizes: 1X, 2X, double width, and double height. The
2X size duplicates each pixel horizontally and vertically to reach double size. Figure 13
shows a character at 1X, 2X without smoothing, and 2X with smoothing.
Smoothing means enhancing a character to improve its appearance. This effect can be
applied to 2X and double width characters, and is enabled and disabled in DISP_ATTR:
03h: Bank A (4).
Check the effect of smoothing on 2X and double width characters before finalizing OSD
programming.
1X
2X
Figure 13
After Smoothing
Smoothing Effect on 2X Character Size
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40
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.8 Fringing Effect
Fringing means surrounding a character with a different color than the foreground and
background colors. Refer back to Figure 8. Fringing adds visual appeal to the character
presentation.
The fringing effect is enabled or disabled in DISP_ATTR: 03h: Bank A (5). The
fringing color is set in INT_ST: 07h: Bank C (7) to either 0, the character
background color, or to 1, a RGB color specified in INT_ST: 07h: Bank C
(6,5,4). The eight RGB colors available for fringing and background are defined in
Table 18.
Note: The fringing feature is NOT available in Progressive Mode.
Table 18
RGB Colors
R
G
B
Color
0
0
0
Black
0
0
1
Blue
0
1
0
Green
0
1
1
Cyan
1
0
0
Red
1
0
1
Magenta
1
1
0
Yellow
1
1
1
White
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41
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.9 Display Attribute Control
Display Attribute Control determines screen display characteristics for the entire screen,
not just the OSD area. The background that covers the entire screen is called the Master
Background. Its color setting can be used to generate a blue screen when the TV signal is
not present. Table 19 shows the Display Attribute Register.
Table 19
Display Attribute Register 03h: Bank A (DISP_ATTR)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
Value
Character Display
7
R/W
0
1
Disable Character Display
Enable Character Display
Master
Background Enable
6
R/W
0
1
No Master Background
Incoming video is swapped
with the background color
Fringe Effect Enable
5
R/W
0
1
Fringe Effect is Disabled
Fringe Effect is Enabled
Smoothing Effect
Enable
4
R/W
0
1
Smoothing enabled
Smoothing disabled
RGB Polarity
3
R/W
0
1
Positive
Negative
Red Master
Background
2
R/W
See Table 18
Green Master
Background
1
R/W
See Table 18
Blue Master
Background
0
R/W
See Table 18
Description
Bit 7, Display Enable, disables or enables using foreground and background color, and
therefore character display. When this bit is set to 0, effective space characters are sourced
from the video RAM. Background On/Off and row background color are programmed
independently. When bit 7 is set to 1, the actual video RAM characters are displayed.
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42
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit 6, Master Background Enable, disables or enables using a background color for the
entire screen instead of the broadcast signal. If this bit is set to 1, the incoming video
signal blanks and the screen background displays color according to the background color
bits. The color is specified in bits 2, 1, 0. If bit 6 is set to 0, the incoming video signal
is displayed.
Bit 5, Fringe Enable, sets the fringe effect ON or OFF.
Bit 4, Smoothing Effect Enable, sets smoothing ON or OFF, and is available for 2X and
double width characters.
Bit 3, RGB Polarity, sets color polarity of OSD color output signals to positive or negative.
Bits 2, 1, and 0 form the color for the master background. The eight possible colors are
the same ones listed in Table 18.
Video Refresh RAM Access
The Z90255 supports 12-bit character data. Nine bits, P8 and P7 through P0, contain
character code. Three additional bits, C2 through C0, contain color palette information.
See Figure 14.
Color Palette Selection bits serve as a 3-bit Color Index to the color palette look-up table.
When software writes Character Byte data (7-0) into VRAM, it also takes the data in the
color index register and writes the corresponding Color Palette Selection Bits (10-8) and
the most significant bit of character data (P8).
When updating 3-bit color index data, the most significant bit of the character data must
also be updated. Table 20 contains VRAM structure and memory mapping.
Color Index Register
D7 D6 D5 D4 D3 D2 D1 D0
CLR_IDX: 09h Bank C
P[8:0] = character code
C[2:0] = character color
512 Character
Set
VRAM D[11:0]
(4+8=12-bit word)
11
10
9
8
7
6
5
4
P8
C2 C1
C0
P7
P6
P5
P4 P3
Character
color
3
1
0
P2 P1
P0
2
Character code
Character Information
Figure 14
VRAM Data Path for 512 Character Set
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43
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 20
VRAM Structure and Memory Map
Character Code Data Bit[11] ,
Character Color C[2:0]
Row0/Column 0 D[11:8]
Character Code Data Bit[7:0]
FE01h
Row0/Column 1 through 22 D[11:8] FE02h
Row 0 Attribute(ROW0_ATTR)
FC00h
Row 0/Column 0 D[7:0]
FC01h
Row 0/Column 1 through 22 D[7:0]
FC02h
FE17h
Row 0/Column 23 D[11:8]
Row1/Column 0 D[11:8]
FE18h
FE21h
Row1/Column 1 through 22 D[11:8] FE22h
FC17h
Row 0/Column 23 D[7:0]
FC18h
Row 1 Attribute(ROW1_ATTR)
FC20h
Row 1/Column 0 D[7:0]
FC21h
Row 1/Column 1 through 22 D[7:0]
FC22h
FE37h
Row 1/Column 23 D[11:8]
Row 2 D[11:8]
FE38h
FC37h
Row 1/Column 23 D[7:0]
FC38h
Row 2 Video RAM buffer
FC40h
FE41h
FC41h
FE58h
FC58h
Row 3 Video RAM buffer
Row 3 D[11:8]
FE61h
FC61h
FE78h
FC78h
Row 4 Video RAM buffer
Row 4 D[11:8]
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FC60h
FC80h
FE81h
FC81h
FE98h
FC98h
Preliminary
44
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 20
VRAM Structure and Memory Map
Character Code Data Bit[11] ,
Character Color C[2:0]
Character Code Data Bit[7:0]
Row 5 Video RAM buffer
Row 5 D[11:8]
FEA1h
FCA1h
FEB8h
FCB8h
Row 6 Video RAM buffer
Row 6 D[11:8]
FCC1h
FED8h
FCD8h
FCE1h
FEF8h
FCF8h
FD00h
FF01h
FD01h
FF18h
FD18h
Row 9 Video RAM buffer
Row 9 D[11:8]
FCE0h
FEE1h
Row 8 Video RAM buffer
Row 8 D[11:8]
FCC0h
FEC1h
Row 7 Video RAM buffer
Row 7 D[11:8]
FCA0h
FD20h
FF21h
FD21h
FF38h
FD38h
Hardware processes the entire 12 bits of data at the same time it processes the OSD.
The Color Palette Selection Bits (10-8) are decoded as described in Table 21.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 21
Color Palette Selection Bits
Color Index, Bit [10:8]
Function
000
Selects background/foreground color in row attribute
001
Selects color palette 0 in the color look-up table
010
Selects color palette 1 in the color look-up table
011
Selects color palette 2 in the color look-up table
100
Selects color palette 3 in the color look-up table
101
Selects color palette 4 in the color look-up table
110
Selects color palette 5 in the color look-up table
111
Selects color palette 6 in the color look-up table
There are eight different foreground/background palettes, including the 000h case that
reads the color(s) from the ROW_ATTR register mapped into video RAM.
Color Table and Color Index Register
Table 22 lists the bits in the Color Index Register.
Table 22
Bit
R/W
Reset
Color Index Register 09h: Bank C (CLR_IDX)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6, 5, 4
Color Index 3, 2, 1, 0
Data
R/W Value Description
R
W
R/W
Return 1
No Effect
Bit 3 defines MSb of the character pointer
data bit and bit [2:0] for character color data
bits
When the Color Index has a value other than 000h, the value indicates the number of the
color palette that contains the RGB foreground and background colors to be displayed. In
the Color Palette register descriptions below, the following notation is used:
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Rnf
R - Red,
n - Palette Number,
f - Foreground
Rnb
R - Red,
n - Palette Number,
b - Background
Gnf
G - Green,
n - Palette Number,
f - Foreground
Gnb
G - Green,
n - Palette Number,
b - Background
Bnf
B - Blue,
n - Palette Number,
f - Foreground
Bnb
B - Blue,
n - Palette Number,
b - Background
The registers for color palettes 0 through 6 are listed in Table 23 through Table 29.
Table 23
Bit
R/W
Reset
Color Palette 0 Register 09h: Bank A (CLR_P0)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R/W Value Description
R
W
Return 1
No Effect
Programming R0f, G0f, B0f, R0b, G0b, B0b
Color Palette 0 5,4,3,2,1,0 R/W
Table 24
Bit
R/W
Reset
Color Palette 1 Register 0Ah: Bank A (CLR_P1)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6
R/W Value Description
R
W
Color Palette 1 5,4,3,2,1,0
Table 25
Bit
R/W
Reset
Return 1
No Effect
R/W
Programming R1f, G1f, B1f, R1b, G1b, B1b
Color Palette 2 Register 0Bh: Bank A (CLR_P2)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R/W Value Description
R
W
Color Palette 2 5,4,3,2,1,0
Table 26
Bit
R/W
Reset
Return 1
No Effect
Programming R2f, G2f, B2f, R2b, G2b,
B2b
R/W
Color Palette 3 Register 0Ch: Bank A (CLR_P3)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
Color Palette 3 5,4,3,2,1,0
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R/W Value Description
R
W
R/W
Preliminary
Return 1
No Effect
Programming R3f, G3f, B3f, R3b, G3b, B3b
48
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 27
Color Palette 4 Register 0Dh: Bank A (CLR_P4)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R/W Value Description
R
W
Color Palette 4 5,4,3,2,1,0
Table 28
Return 1
No Effect
R/W
Programming R4f, G4f, B4f, R4b, G4b, B4b
Color Palette 5 Register 0Eh: Bank A (CLR_P5)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R/W Value Description
R
W
Color Palette 5 5,4,3,2,1,0
Table 29
Return 1
No Effect
R/W
Programming R5f, G5f, B5f, R5b, G5b, B5b
Color Palette 6 Register 0Fh: Bank A (CLR_P6)
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
Reset
NOTE: R = Read W = Write X = Indeterminate
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6
R/W Value Description
R
W
Color Palette 6 5,4,3,2,1,0
Return 1
No Effect
R/W
Programming R6f, G6f, B6f, R6b, G6b, B6b
Row Attribute Register
The Row Attribute Register (Table 30) is mapped to VRAM, as shown in Table 20. This
register controls row background and foreground display. If the Color Index is set to
000h, the display color is read from the Row Attribute Register.
Table 30
Row Attribute Register (ROW_ATTR)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
Row Foreground
Enable
7
R/W
Row Foreground
Color
6, 5, 4
R/W
Row Background
Enable
3
R/W
Row Background
Color
2, 1, 0
R/W
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Value Description
Preliminary
0
1
Row Foreground Color displayed
Row Foreground color disabled
Defines the Character Color R, G, B,
respectively
0
1
Row Background Color disabled
Row Background color displayed
Defines the Row Background Color R,
G, B, respectively
50
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
3.10 HV Interrupt Processing
An interrupt is issued at the beginning of a row and at the leading edge of the VSYNC
signal. The leading edge of the first HSYNC of a row constitutes the beginning of a row.
The Z90255 software tracks this cycle as two recurring events, the Horizontal (HSYNC)
Interrupt and the Vertical (VSYNC) Interrupt.
A VSYNC interrupt marks the time for displaying a new field of a TV frame. Displaying
subsequent rows coincides with the issuance of the HSYNC interrupt. The interrupts mark
the time when displaying a row or start of a field is to occur.
Each text row is comprised of 18 scan lines. Each scan line takes 63.5 µs to be displayed.
So, 1143 µs is the amount of time available to change programming for the next row.
Double-size and double-height characters span 36 scan lines, allowing 2286 µs to program
the next row. Additional programming time is available with inter-row spacing. VRAM is
updated during that time.
If the program has too much to display, black lines appear at the top of the screen.
The HV Interrupt Status Register (Table 31) keeps track of the type of interrupt issued,
horizontal or vertical.
Table 31
HV Interrupt Status Register 07h: Bank C (INT_ST)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position R/W Value Description
Fringe Color Selection
7
R/W
Fringe Color
6, 5, 4
R/W
Palette Mode
3
R/W
0
1
Normal Mode
Color Palette Mode
Horizontal Interrupt
Enable
2
R/W
0
1
No Horizontal Interrupt
Enable Horizontal Interrupt
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0
1
Select Character Background Color
Select Fringe Color RGB*
Defines Fringe Color RGB
51
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position R/W Value Description
Vertical Interrupt
1
R
W
Horizontal Interrupt
0
R
W
0
1
0
1
No Vertical Interrupt
Vertical Interrupt
No Effect
Reset Vertical Interrupt Flag
0
1
0
1
No Horizontal Interrupt
Horizontal Interrupt
No Effect
Reset Horizontal Interrupt Flag
Note: *The fringing feature is not available in Progressive Mode.
Bit 7, Fringe Color Selection, sets the fringe color to the background color or to a Red,
Green, and Blue color specified in bits 6,5,4.
Bit 3, Palette Mode, sets color to Normal or VRAM Mode. When the value is 0 (Normal
Mode), the color attribute of a row is controlled by values in the ROW_ATTR register
which is mapped in VRAM, but the Color Palette Selection Bits are ignored. When the
Palette Mode value is 1, the Color Palette Selection Bits are used, unless they are set to 0s.
In that case, the values in the ROW_ATTR register are used.
Bit 2, Horizontal Interrupt Enable, disables or enables the horizontal (HSYNC) interrupt.
Bit 1, Vertical Interrupt, has different meanings depending on its Read and Write status.
In Read State, a value of 0 indicates that a vertical interrupt was not issued; a value of 1
indicates that a vertical interrupt was issued. In Write State, a value of 0 has no effect; a
value of 1 resets the vertical interrupt flag.
Bit 0, Horizontal Interrupt, has different meanings depending on its status. In Read State,
a value of 0 indicates that a horizontal interrupt was not issued; a value of 1 indicates that
a horizontal interrupt was issued. In Write State, a value of 0 has no effect; a value of 1
resets the horizontal interrupt flag.
When an interrupt is issued while another interrupt is processing, the last-issued interrupt
is pended. The interrupt-flag bit which is in service (the interrupt issued first) must be
cleared or serviced before the pended interrupt can be processed (see SNDCLR(6)).
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
HSYNC and VSYNC Requirements
HSYNC and VSYNC must meet all TV broadcasting specifications. The minimum width of
VSYNCmust conform to the specification in Figure 15.
VT
Field 1
HT
HCYCLE
1/2 HCYCLE
Field 2
VT must be larger than 1.5 x (HCYCLE +HT).
The same timing specification must applied in negative polarity.
Figure 15
HSYNC and VSYNC Specification
The rising edge of VSYNC must not coincide with the rising edge of HSYNC to be sure that
the controller recognizes both rising edges.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
4
Z90255 I2C MASTER INTERFACE
The Z90255 has a hardware module which supports the I2C Master interface. Bus
arbitration and Masters’ arbitration logic is NOT implemented; in other words, the
Z90255 is designed for a Single Master application.
The I2C interface can be configured to run at four different transfer speeds defined by bits
(1,0) in the I2C Control Register (I2C_CNTL: 0Ch, Bank:C).
To circumvent possible problems on both DATA and SCLK lines, digital filters with time
constant equal to 3Tsclk are implemented on all inputs of the I2C bus interface. The
Z90255 has two separate I2C busses which share the same I2C state machine.
The I2C module is enabled by setting bit (2) in the I2C_CNTL register to 1(see Figure 16).
This bit blocks out I2C logic if it is set to 0. To prevent switching the I2C bus during
activation, bits (7,6) of the Port 2 Data Register for I2C selection 1 (bits (5,4) of Port 2
Data Register for I2C selection 0) should be set to 1 before the I2C module is enabled.
Notes:
1.
When the I2C module is enabled, pins used as I2C must be configured as output in
the Port 2 Mode Register (P2M: F6h). If P27/P26 or P25/P24 are used as I2C
pins, then these pins are automatically set to open-drain mode.
2.
Port 2 must be configured in standard drive mode (PCON: 00h: Bank F) when
the I2C interface is active.
VCC
P2CNTL (0)
P2M 1 = Input
0 = Output
PAD
I 2C DATA (Output)
P2 (Output)
1
0 S
I2C Selection
P2 (Input)
I2C DATA (Input)
I2C Enable
Figure 16
For I2C
Bidirectional Port Pin Pad Multiplexed with I2C Port
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 32
Master I2C Control Register 0Ch: Bank C (I2C_CNTL)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
Clock Selection
7
R/W
Reserved
6
R
W
I2C Selection 1
5
R/W
Value Description
0
1
Return 1
No Effect
0
1
I2C Selection 0
4
R/W
1X SCLK for I2C and ADC
0.5X SCLK for I2C and ADC
0
1
P26 selection - POR
P27 selection - POR
SCLK1 selection on P26
SDATA1 selection on P27
P24 selection - POR
P25 selection - POR
SCLK 0 selection on P24
SDATA0 selection on P25
Reserved
3
R/W
Must be 0
I2C Enable
2
R/W
0
1
Disable I2C Interface
Enable I2C Interface
I2C Speed (for 6-MHz
XTAL)
1, 0
R/W
00
01
10
11
10 KHz
50 KHz
100 KHz
330 KHz
If bits 4 and 5 both equal 1, then the I2C Selection 0 prevails.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
4.1 Controlling the I2C Interface
Software controls the I2C module by writing appropriate commands into the I2C
Command Register (I2C_CMD:0Bh:0Ch). See Table 33.
Table 33
Master I2C Command Register 0Bh: Bank C (I2C_CMD)
Bit
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
0
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7
R
W
Return 1
No Effect
I2C Command
6, 5, 4
R
W
Return 1
See Table 35
Reserved
3, 2
R
W
Return 1
No Effect
Reset
1
R
W
Busy
R/W
0
Value Description
0
1
R
0
1
W
Return 1
No Effect
Reset I2C interface
Idle
Busy
No Effect
Software puts data to be transmitted into I2C Data Register (Table 34) and reads received
data from it. Bit 7 in this register is used as an acknowledge bit when receiving data from
a Slave. Bit 0 of I2C_DATA register contains an acknowledgment bit generated by the
Slave. Refer to Table 35.
Table 34
Bit
R/W
Reset
Master I2C Data Register 0Ah: Bank C (I2C_DATA)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Data
7,6,5,4,3,2,1,0
Table 35
Master I2C Bus Interface Commands
R/W Value
Description
R
W
Received data
Data to be sent
Command Description
000
Send a Start bit followed by the address byte specified in the I2C
data register, then fetch the acknowledgment bit in I2C_DATA (0).
Used to initialize communication. Nine SCLK cycles are generated.
001
Send the byte of data specified in the I2C data register, then fetch an
acknowledgment bit stored in bit 0. Used in a Write frame. Nine
SCLK cycles are generated.
010
Send bit 7 of I2C_DATA register as an acknowledgment bit (ACK:
(0XXXXXXX), NAK: (1XXXXXXX)), then receive a data byte. Used in
a Read frame when the next data byte is expected. Nine SCLK cycles
are generated. Received data is read in the I2C data register.
011
Send bit 7 of I2C_DATA register as an acknowledgment bit (ACK:
(0XXXXXXX), NAK: (1XXXXXXX). Used in a Read frame. One SCLK
cycle is generated.
10X
Null operation. Must be used with a Reset bit.
110
Received one data byte. Used in a Read frame to receive the first
data byte after an address byte is transmitted. Eight SCLK cycles are
generated.
111
Send Stop bit. One SCLK cycles are generated.
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
5
INPUT/OUTPUT PORTS
There are 20 input/output (I/O) ports. In addition, seven pulse-width modulators (PWM),
PWM1 through PWM6, and PWM11, can be configured as regular output ports. The
maximum number of I/O ports available is 27. Please refer to the port bank and number
carefully for exact addressing and access. See Table 36 through Table 46.
Table 36
Port configuration Register 00h: Bank F (PCON)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
Value
Low EMI Z8
Oscillator
7
R/W
0
1
Low EMI Noise
Standard-POR
Low EMI Port 6
6
R/W
0
1
Low EMI Noise
Standard-POR
Low EMI Port 2
5
R/W
0
1
Low EMI Noise
Standard-POR
Reserved
4, 3
Low EMI Port 4
and PWMs
2
R/W
0
1
Low EMI Noise
Standard-POR
Low EMI OSD
Oscillator
1
R/W
0
1
Low EMI Noise
Standard-POR
Reserved
0
R/W
R
W
Description
Return 1
Write 1s
Return Unknown
No Effect
Ports 2, 4, and 6 can be set for Standard or Low EMI. The Low EMI option can
also be selected for the microcontroller oscillator or OSD oscillator. Standard (1) is the
High setting. Following Power-On Reset, Bits 1, 2, 5, 6, 7 each has a value of 1.
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Preliminary
58
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 37
Port 2 Mode Register F6h: P2M
Bit
7
6
5
4
3
2
1
0
R/W
W
W
W
W
W
W
W
W
Reset
1
1
1
1
1
1
1
1
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
P27 I/O Definition
7
W
0
1
Defines P27 as Output
Defines P27 as Input
P26 I/O Definition
6
W
0
1
Defines P26 as Output
Defines P26 as Input
P25 I/O Definition
5
W
0
1
Defines P25 as Output
Defines P25 as Input
P24 I/O Definition
4
W
0
1
Defines P24 as Output
Defines P24 as Input
P23 I/O Definition
3
W
0
1
Defines P23 as Output
Defines P23 as Input
P22 I/O Definition
2
W
0
1
Defines P22 as Output
Defines P22 as Input
P21 I/O Definition
1
W
0
1
Defines P21 as Output
Defines P21 as Input
P20 I/O Definition
0
W
0
1
Defines P20 as Output
Defines P20 as Input
R/W
Value Description
When P27/P26 or P25/P24 are used as I2C pins, then these pins are automatically set
to open-drain mode.
Table 38
Bit
R/W
Reset
Port 2 Data Register 02h: P2
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
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Preliminary
59
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
P27
7
R
W
Data input on P27
Data Output on P27
P26
6
R
W
Data input on P26
Data Output on P26
P25
5
R
W
Data input on P25
Data Output on P25
P24
4
R
W
Data input on P24
Data Output on P24
P23
3
R
W
Data input on P23
Data Output on P23
P22
2
R
W
Data input on P22
Data Output on P22
P21
1
R
W
Data input on P21
Data Output on P21
P20
0
R
W
Data input on P20
Data Output on P20
R/W
Value
Description
Port 4 Pin-Out Selection Register
Bits 5,4,3, and 2 control the configuration of multiplexed pins 20, 19, 18, and 17. If a
bit is set to 0, the pin functions as a PWM output port. This value is the default following a
Power-On Reset. If a bit is set to 1, the pin functions as a programmable regular input/
output port. See Table 39.
Table 39
Bit
R/W
Reset
Port 4 Pin-Out Selection Register 08h: Bank C (PIN_SLT)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
1
1
1
1
x
x
NOTE: R = Read W = Write X = Indeterminate
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Preliminary
60
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6
P47/PWM10
5
R/W
0
1
Selects PWM10
Selects P47 - POR
P46/PWM9
4
R/W
0
1
Selects PWM9
Selects P46 - POR
P45/PWM8
3
R/W
0
1
Selects PWM8
Selects P45 - POR
P44/PWM7
2
R/W
0
1
Selects PWM7
Selects P44 - POR
Reserved
1, 0
Table 40
R/W
Value
R
W
Description
Return 1
No Effect
R
W
Return 1
No Effect
Port 4 Data Register 05h: Bank C (PRT4_DTA)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
P47
7
R
W
Data input on P47
Data Output on P47
P46
6
R
W
Data input on P46
Data Output on P46
P45
5
R
W
Data input on P45
Data Output on P45
P44
4
R
W
Data input on P44
Data Output on P44
P43
3
R
W
Data input on P43
Data Output on P43
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R/W
Value
Preliminary
Description
61
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
P42
2
R
W
Data input on P42
Data Output on P42
P41
1
R
W
Data input on P41
Data Output on P41
P40
0
R
W
Data input on P40
Data Output on P40
Table 41
Port 4 Direction Control Register 06h: Bank C (PRT4_DRT)
Bit
R/W
Reset
R/W
Value
Description
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
P47 I/O Definition
7
R/W
0
1
Defines P47 as Output
Defines P47 as Input-POR
P46 I/O Definition
6
R/W
0
1
Defines P46 as Output
Defines P46 as Input-POR
P45 I/O Definition
5
R/W
0
1
Defines P45 as Output
Defines P45 as Input-POR
P44 I/O Definition
4
R/W
0
1
Defines P44 as Output
Defines P44 as Input-POR
P43 I/O Definition
3
R/W
0
1
Defines P43 as Output
Defines P43 as Input-POR
P42 I/O Definition
2
R/W
0
1
Defines P42 as Output
Defines P42 as Input-POR
P41 I/O Definition
1
R/W
0
1
Defines P41 as Output
Defines P41 as Input-POR
P40 I/O Definition
0
R/W
0
1
Defines P40 as Output
Defines P40 as Input-POR
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Preliminary
Value Description
62
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 42
PWM Mode Register 0Dh: Bank B (P_MODE)
Bit
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
1
1
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
Value
6-Bit/14-bit PWM6
7
R/W
0
1
Select 6 bit-POR
Select 14 bit
P56/PWM 11
6
R/W
0
1
Select PWM 11
Select P56-POR
P55/PWM 6*
5
R/W
0
1
Select PWM 6
Select P55-POR
P54/PWM 5
4
R/W
0
1
Select PWM 5
Select P54-POR
P53/PWM 4
3
R/W
0
1
Select PWM 4
Select P53-POR
P52/PWM 3
2
R/W
0
1
Select PWM 3
Select P52-POR
P51/PWM 2
1
R/W
0
1
Select PWM 2
Select P51-POR
P50/PWM 1
0
R/W
0
1
Select PWM 1
Select P50-POR
Description
Note: *PWM6 is either 6-bit or 14-bit depending on the bit status in D7.
Table 43
Bit
R/W
Reset
Port 5 Data Register Ch: Bank B (PRT5_DTA)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
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Preliminary
63
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7
R
W
Return 1
No Effect
P56
6
R
W
Data input on P56
Data Output on P56
P55
5
R
W
Data input on P55
Data Output on P55
P54
4
R
W
Data input on P54
Data Output on P54
P53
3
R
W
Data input on P53
Data Output on P53
P52
2
R
W
Data input on P52
Data Output on P52
P51
1
R
W
Data input on P51
Data Output on P51
P50
0
R
W
Data input on P50
Data Output on P50
Table 44
Value
Description
Port 5 Direction Control Register 0Eh: Bank B (PRT5_DRT)
Bit
R/W
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
1
1
1
1
1
1
1
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7
R
W
P56 I/O Definition
6
R/W
0
1
Defines P56 as Output
Defines P56 as Input-POR
P55 I/O Definition
5
R/W
0
1
Defines P55 as Output
Defines P55 as Input-POR
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R/W
Preliminary
Value Description
Return 1
No Effect
64
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
R/W
P54 I/O Definition
4
R/W
0
1
Defines P54 as Output
Defines P54 as Input-POR
P53 I/O Definition
3
R/W
0
1
Defines P53 as Output
Defines P53 as Input-POR
P52 I/O Definition
2
R/W
0
1
Defines P52 as Output
Defines P52 as Input-POR
P51 I/O Definition
1
R/W
0
1
Defines P51 as Output
Defines P51 as Input-POR
P50 I/O Definition
0
R/W
0
1
Defines P50 as Output
Defines P50 as Input-POR
Table 45
Bit
R/W
Reset
Value Description
Port 6 Data Register 03h: Bank F (PRT6_DTA)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Value
Description
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6, 5, 4
R
W
Return Unknown
No Effect
P63
3
R
W
Data input on P63
Data Output on P63
P62
2
R
W
Data input on P62
Data Output on P62
P61
1
R
W
Data input on P61
Data Output on P61
P60
0
R
W
Data input on P60
Data Output on P60
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R/W
Preliminary
65
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 46
Port 6 Direction Control Register 02h: Bank F (PRT6_DRT)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
P63
7
R/W
0
1
Open-Drain Output
Push-Pull Output - POR
P62
6
R/W
0
1
Open-Drain Output
Push-Pull Output - POR
P61
5
R/W
0
1
Open-Drain Output
Push-Pull Output - POR
P60
4
R/W
0
1
Open-Drain Output
Push-Pull Output - POR
P63 I/O
definition
3
R/W
0
1
Data Output
Data Input - POR
P62 I/O
definition
2
R/W
0
1
Data Output
Data Input - POR
P61 I/O
definition
1
R/W
0
1
Data Output
Data Input - POR
P60 I/O
definition
0
R/W
0
1
Data Output
Data Input - POR
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Value Description
Preliminary
66
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
6
INFRARED INTERFACE
The Z90255 supports the Infrared (IR) Remote Control interface with a minimum of
software overhead.
Two bytes of data are received through the Infrared (IR) Interface. The lower byte, bits 70, is stored in IR Capture Register 0. The upper byte, bits 15-8, is stored in IR Capture
Register 1.
When an IR interrupt occurs, the IR capture registers contain the amount of time passed
from the previous IR interrupt if bit 0 in the TCR0 is set to 0. If bit 0 is set to 1, the IR
capture registers contain the amount of time passed from the last overflow of the IR
capture counter. The IR interrupt flags are reset by the IR interrupt service routine
software. Refer to Table 47 through Table 50.
Timer Control Register 0
Rising edge (falling edge) interrupt is preserved even when a falling edge (rising edge)
interrupt occurs. But it is overridden by a second rising edge (falling edge) if the second
one occurs before the first rising edge (falling edge) is serviced. Preservation of the
interrupt means that it generates the hardware interrupt after the first interrupt is serviced
when two different (rising edge/falling edge) interrupts are already ON.
Table 47
Timer Control Register 0 01h: Bank C (TCR0)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6, 5, 4, 3
R
W
CAPint_r
2
R
R/W
W
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Value Description
Return 0
No Effect
0
1
0
1
Preliminary
No Rising Edge is Captured
Rising Edge is Captured
No Effect
Reset Flag
67
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
CAPint_f
1
R/W
Value Description
R
W
Tout_CAP
0
R
W
0
1
0
1
No Falling Edge is Captured
Falling Edge is Captured
No Effect
Reset Flag
0
1
0
1
No Time-out of the Capture Timer
Time-out of the Capture Timer
No Effect
Reset Flag
During the interrupt service routine, software must read the contents of Timer Control
Register 0. Then it checks which bit is set to 1, indicating the type of edge which
generated the interrupt.
Table 48
Timer Control Register 1 02h: Bank C (TCR1)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
1
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7
R
W
CAP Halt
6
R/W
0
1
Capture Timer Running
Capture Timer Halted
CAP Edge
5, 4
R/W
00
01
10
11
No capture
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Both Edges
CAP Glitch
3, 2
R/W
00
01
10
11
Glitch Filter Disabled
<2SCLK Filtered Out
<8SCLK Filtered Out
<16SCLK Filtered Out
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R/W
Preliminary
Value
Description
Return 0
No Effect
68
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
R/W
Value
CAP Speed
1, 0
R/W
00
01
10
11
Description
SCLK/32
SCLK/4
SCLK/8
SCLK/16
Bit 6 resets the IR Capture Timer. To stop the timer, set this bit to 1. To start the timer, set
the bit to 0.
Bits 5 and 4 set the IR Capture Edge. The rising edge, the falling edge, or both edges of an
input signal can be used as the source of IR interrupts. If both edges are set as interrupt
sources, Timer Control Register 0 (TCR0: 01h: Bank C) must be read and checked by
the Interrupt Service Routine (ISR) in order to identify which edge was captured.
Bits 3 and 2 contain a time constant used in a digital filter to process the IR Capture
module in order to prevent errors.
Bits 1 and 0 set the IR Capture Counter to one of four different speeds.
The IR capture counter is driven by the clock generated by dividing the system clock in
the Z90255.
Table 49
IR Capture Register 0 03h: Bank C (IR_CP0)
Bit
7
6
5
4
3
2
1
0
R/W
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
IR Capture Register 0
7,6,5,4,3,2,1,0
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Preliminary
R/W
R
Value Description
Reading Low Byte of IR
Capture Data
69
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 50
IR Capture Register 1 04h: Bank C (IR_CP1)
Bit
7
6
5
4
3
2
1
0
R/W
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
IR Capture Register 1
PS001300-TVC1099
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Bit
Position
7,6,5,4,3,2,1,0
Preliminary
R/W Value Description
R
Reading High Byte of IR
Capture Data
70
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
7
PULSE WIDTH MODULATORS
The Z90255 has 11 Pulse Width Modulator channels. PWM1 through PWM10 have 6-bit
resolution and are typically used for audio and video level control. PWM11 has 14-bit
resolution and is typically used for voltage synthesis tuning. PWM11 uses two registers to
accommodate its 14-bit resolution. PWM6 can be configured as either 14-bit or 6-bit.
7.1 PWM Mode Register
PWM Mode Register (Table 51) controls the setting of multiplexed pins1-7. These pins
can be configured to function as PWM output ports or regular output ports. If a bit is reset
to 0, the pin outputs the PWM signal. If a bit is set to 1, the pin is a regular output port.
Table 51
PWM Mode Register 0Dh: Bank B (P_MODE)
Bit
R/W
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
1
1
Reset
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
6-bit/14-bit PWM6
7
R/W
0
1
Select 6-bit (POR)
Select 14-bit
PWM 11 / P56
6
R/W
0
1
Select PWM 11
Select P56 - POR
PWM 6* / P55
5
R/W
0
1
Select PWM 6
Select P55 - POR
PWM 5 / P54
4
R/W
0
1
Select PWM 5
Select P54 - POR
PWM 4 / P53
3
R/W
0
1
Select PWM 4
Select P53 - POR
PWM 3 / P52
2
R/W
0
1
Select PWM 3
Select P52 - POR
PWM 2 / P51
1
R/W
0
1
Select PWM 2
Select P51 - POR
PWM 1 / P50
0
R/W
0
1
Select PWM 1
Select P50 - POR
Value Description
Note: *PWM6 can be either 6- or 14-bit depending on the bit status in bit7.
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Preliminary
71
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Port 4 Pin-Out Selection Register
Bits 5, 4, 3, and 2 of the Port 4 Pin-Out Selection Register (Table 52) control the
configuration of multiplexed pins 20, 19, 18, and 17. If a bit is reset to 0, the pin
functions as a PWM output port. This value is the default following a Power-On Reset. If a
bit is set to 1, the pin functions as a programmable regular input/output port.
Table 52
Bit
R/W
Reset
Port 4 Pin-Out Selection Register 08h: Bank C (PIN_SLT)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
1
1
1
1
x
x
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R
W
P47/
PWM 10
5
R/W
0
1
Select PWM 10
Select P47 - POR
P46/
PWM9
4
R/W
0
1
Select PWM 9
Select P46 - POR
P45/
PWM 8
3
R/W
0
1
Select PWM 8
Select P45 - POR
P44/
PWM 7
2
R/W
0
1
Select PWM 7
Select P44 - POR
Reserved
1, 0
R
W
PS001300-TVC1099
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R/W
Preliminary
Value Description
Return 1
No effect
Return 1
No effect
72
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
7.2 PWM1 through PWM11
Two data registers (PWM11H and PWM11L) hold the 14-bit PWM11 ratio. If PWM6 is
configured to 14-bit, two data registers (PWM6H and PWM6L) hold the 14-bit PWM6
ratio. The upper 7 bits control the width of the distributed pulse. The lower 7 bits
distribute the minimum resolution pulse in the various time slots. Using this technique, the
pseudo-repetition of frequency is raised up to 128 times faster than ordinary pulse width
modulation.
There are 128 time slots which start from time slot 7Fh to 0h because a 14-bit binary
down counter is used. When the glitch exceeds 127 pulses, the upper 7 bits take
precedence and fill 128 pulses of the same width in different locations. Generating the
pulse-train output requires the following equation: Time slot (Fts) and one cycle of
frequency (F14).
Fdp (Distribution pulse frequency)=XTAL/128 (Hz)
Fts (Time slot frequency) = XTAL/128 (Hz)
F14 (a cycle/frequency) = XTAL /16384 (Hz)
When the 6-bit data is 00h, the PWM output is Low. The maximum value is 3Fh and emits
High DC-level output.
A selected PWM cycle/frequency is shown in the following equation:
F6 (a cycle/frequency) = XTAL/16/64 (Hz)
Figures 17 and 18 illustrate various timing pulses and resultant frequencies for the 6-bit
and 14-bit PWMs.
F6 = XTAL/16/64
XTAL/2
(A) PWM2 = 00H
(B) PWM2 = 01H
(C) PWM2 = 03H
(D) PWM2 = 20H
(E) PWM2 = 3FH
Figure 17
Pulse Width Modulator Timing Diagram, 6 Bit
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Preliminary
73
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
XTAL/128
Time Slot = 40H
(A) PWM11-0001H
Time Slot = 60H
Time Slot = 20H
Time Slot = 60H Time Slot = 40H
Time Slot = 20H
(B) PWM11-0002H
(C) PWM11-0003H
Tme Slot = 70H Time Slot = 50H
Time Slot = 30H
Time Slot = 10H
(D) PWM11-0004H
70H
50H
40H
30H
10H
(E) PWM11-0005H
(F) PWM11-007FH
Time Slot = 0 (No Pulse)
(G) One of
Distribution
Pulse
XTAL
XTAL/128
(H) PWM11 = 0080H
(I) PWM11 = 0180H
(J) PWM11 = 2000H
(K) PWM11 = 3F80H
Distribution Pulses Added These Places
(L) PWM11 = 0081H
Time Slot = 41H
Figure 18
Time Slot = 40H
Time Slot = 3FH
Time Slot = 3EH
Pulse Width Modulator Timing Diagram, 14-Bit
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74
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Tables 53 through 66 contain data register information for registers PWM1 -PWM11.
Table 53
PWM 1 Data Register 02h: Bank B (PWM1)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R
W
PWM 1 Value
5,4,3,2,1,0
R/W
Table 54
Bit
R/W
Reset
R/W
Value
Description
Return to 0
No effect
PWM 2 Data Register 03h: Bank B (PWM2)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
PWM 2 Value
Table 55
Bit
R/W
Reset
R/W Value
Description
7, 6
R
W
Return to 0
No effect
5,4,3,2,1,0
R/W
PWM 3 Data Register 04h: Bank B (PWM3)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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Preliminary
75
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6
R
W
PWM 3 Value
5,4,3,2,1,0
R/W
Table 56
Bit
R/W
Reset
R/W
Value
Description
Return to 0
No effect
PWM 4 Data Register 05h:Bank B (PWM4)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R
W
PWM 4 Value
5,4,3,2,1,0
R/W
Table 57
Bit
R/W
Reset
R/W
Value
Description
Return to 0
No effect
PWM 5 Data Register 06h: Bank B (PWM5)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
R
W
PWM 5 Value
5,4,3,2,1,0
R/W
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R/W
Preliminary
Value
Description
Return to 0
No effect
76
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 58
PWM 6 (6-bit)Data Register 07h: Bank B (PWM6)
Bit
R/W
Reset
1
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 6 Value
5,4,3,2,1,0
Table 59
R/W
Value
Description
R
W
Return to 0
No effect
R/W
PWM 7 Data Register 08h: Bank B (PWM7)
Bit
R/W
Reset
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 7 Value
5,4,3,2,1,0
Table 60
Bit
R/W
Reset
R/W
Value
R
W
Description
Return to 0
No effect
R/W
PWM 8 Data Register 09h: Bank B (PWM8)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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Preliminary
77
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 8 Value
5,4,3,2,1,0
Table 61
Bit
R/W
Reset
R/W
Value
R
W
Description
Return to 0
No effect
R/W
PWM 9 Data Register 0Ah: Bank B (PWM9)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 9 Value
5,4,3,2,1,0
Table 62
Bit
R/W
Reset
R/W
Value
R
W
Description
Return to 0
No effect
R/W
PWM 10 Data Register 0Bh: Bank B (PWM10)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 10 Value
5,4,3,2,1,0
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R/W
R
W
Value
Description
Return to 0
No effect
R/W
Preliminary
78
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 63
Bit
R/W
Reset
PWM 6 (14-bit) High Data Register 08h: Bank F (PWM6H)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 6 Bits 13 - 8
5,4,3,2,1,0
Table 64
Bit
R/W
Reset
R/W
Value
R
W
Description
Return 0
No effect
R/W
PWM 6 (14-bit) Low Data Register 09h: Bank F (PWM6L)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
PWM 6 Bits 7 - 0
7, 6, 5,4,3,2,1,0 R/W
Table 65
Bit
R/W
Reset
R/W
Value
Description
PWM 11 High Data Register 00h: Bank B (PWM11H)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
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Preliminary
79
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Bit/
Field
Bit
Position
Reserved
7, 6
PWM 11 Bits 13 - 8
5,4,3,2,1,0
Table 66
Bit
R/W
Reset
R/W
Value
R
W
Description
Return 0
No effect
R/W
PWM 11 Low Data Register 01h: Bank B (PWM11L)
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
NOTE: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
R/W
PWM 11 Bits 7 - 0
7, 6, 5,4,3,2,1,0
R/W
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Preliminary
Value
Description
80
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
7.3 Digital/Analog Conversion with PWM
The televison OSD controller can generate square waves which have fixed periods but
variable duty cycles. If this type of signal passes through an RC integrator, the output is a
DC voltage proportional to the pulse width of the square wave. Refer to Figure 19, Cases
A and B show fixed voltage samples while Case C shows a varying voltage example.
DC Signal
PWM Signal
VCC
Voltage
Case A
PWM Signal
DC Signal
VCC
Time
Voltage
Case B
PWM Signal
DC Signal
VCC
Time
Voltage
Case C
PWM Signal
Figure 19
DC Signal
Time
Analog Signals Generated from PWM Signals
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81
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
8
ANALOG - TO -DIGITAL CONVERTER
The Z90255 is equipped with a 4-bit flash analog-to-digital converter (ADC) that can be
used as either three or four bit configurations. There are four multiplexed analog-input
channels. There are two register addresses, one for 3-bit (Table 67) ADC (3ADC_DTA:
00h: Bank C), and one for 4-bit (Table 68) ADC (4ADC_DTA: 01h: Bank F).
Because no default is set, system software must configure the control register for the
preferred ADC.
Converted 3-bit data is available as bits 0, 1, and 2 of the 3-bit ADC data register.
Converted 4-bit data is available as bits 0, 1, 2, and 3 of the 4-bit ADC data register.
Figure 20 illustrates four input pins (P60/ADC3, P61/ADC2, P41/ADC1, and
P62/ADC0) which function as analog-input channels and as digital I/O ports. To support
the analog function, the digital ports must be configured as analog through software.
Analog/digital selection is controlled by bits 4 and 3 of the 3-bit ADC Data Register, and
by bits 5 and 4 of 4-bit ADC Data Register.
•
If ADC Input Selection equals 00, ADC0 is selected; this value is the default
following POR.
•
•
•
If ADC Input Selection equals 01, ADC1 is selected.
If ADC Input Selection equals 10, ADC2 is selected.
If ADC Input Selection equals 11, ADC3 is selected.
Sampling occurs at one-eighth of an ADC-clock tick. One ADC-clock tick equals onehalf, one-third, or one-quarter of a system-clock (SCLK) tick, as set by
3ADC_DTA(6,5) for 3-bit or 4ADC_DTA (7,6) for 4-bit. If ADC speed bits are set
to 00, the ADC is not operative; this is the default value following POR. If these bits
equal 01, ADC speed is based on one-half of a system-clock tick, SCLK/2. If these bits
equal 10, ADC speed is based on one-third of a system-clock tick, SCLK/3. If these bits
equal 11, ADC speed is based on one-quarter of a system-clock tick, SCLK/4.
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Preliminary
82
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
Table 67
3-Bit ADC Data Register 00h: Bank C (3ADC_DTA)
Bit
7
6
5
4
R/W
R/W
R/W
R/W
R/W
Reset
x
0
0
0
NOTE: R = Read W = Write X = Indeterminate
3
2
1
0
R/W
0
R/W
x
R/W
x
R/W
x
Bit/Field
Bit Position
R/W
Reserved
7
R
W
ADC Speed
6, 5
R/W
00
01
10
11
No ADC - POR
SCLK/2
SCLK/3
SCLK/4
ADC Input Selection
4, 3
R/W
00
01
10
11
Select ADC0 - POR
Select ADC 1
Select ADC 2
Select ADC 3
ADC Data
2, 1, 0
R/W
Table 68
Value
Description
Return 1
No effect
Digitized data from
selected ADC input
4-Bit ADC Data Register 01h: Bank F (4ADC_DTA)
Bit
7
6
5
R/W
R/W
R/W
R/W
Reset
0
0
0
NOTE: R = Read W = Write X = Indeterminate
4
3
2
1
0
R/W
0
R/W
x
R/W
x
R/W
x
R/W
x
Bit/Field
Bit Position
R/W
Value
Description
ADC Speed
7, 6
R/W
00
01
10
11
No ADC - POR
SCLK/2
SCLK/3
SCLK/4
ADC Input Selection
5, 4
R/W
00
01
10
11
Select ADC0 - POR
Select ADC 1
Select ADC 2
Select ADC 3
ADC Data
3, 2, 1, 0
R/W
Digitized data from
selected ADC input
P41 must be set to input mode to select ADC1.
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Preliminary
83
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
ADC Block Diagram
VCC
Comparators
Analog
Multiplexer
ADC0
ADC
Data
Register
ADC1
Decoder
ADC2
ADC3
ADC
Control
GND
Figure 20
ADC Block Diagram
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Preliminary
84
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
9
ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
Stress exceeding the levels listed in the Operational Limits can cause permanent damage
to the device. These limits represent stress limits only, not optimal operating levels:
Exposure to maximum rating conditions for extended periods can affect device reliability.
Table 69
Operational Limits
Symbol
Parameters
Min
Max
Units
VCC
Power Supply Voltage
-0.3
+7
V
VI
Input Voltage
-0.3
VCC+0.3
V
VO
Output Voltage
-0.3
VCC+0.3
V
IOH
Output Current - High
-10
mA
One pin
IOH
Output Current - High
-100
mA
Total, all pins
IOL
Output Current - Low
20
mA
One pin
IOL
Output Current - Low
200
mA
Total, all pins
0
70
oC
-55
150
oC
TA
Operating Temperature
TSTG
Storage Temperature
Notes
A typical value is 25oC. Minimum and maximum values are 0oC and 70oC respectively.
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Preliminary
85
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
9.2 DC Characteristics
Table 70
DC Characteristics
Symbol
Parameter
Min
Typical
Max
VCC
Power Supply Voltage
4.5
5.00
5.5
V
VIH
Input Voltage High
0.7VCC
VCC
V
VIL
Input Voltage Low
- 0.3
0.2VCC
V
VIHC
Input XTAL/Oscillator In High
0.7VCC
VCC
V
VILC
Input XTAL/Oscillator In Low
-0.3
0.2VCC
V
VOH_ST1
Output Voltage High
VOL_ST1
Output Voltage Low
Voh_le1
Output Voltage High
Voh_le1
Output Voltage Low
Voh_le2
Output Voltage High
Voh_le2
Output Voltage Low
VHY
Schmitt Hysteresis
IIR
Reset Input Current
IIL
Input Leakage
IOL
Tri-State Leakage
ICC
VCC-0.4
4.75
Units Conditions
V
IOH= -2.00mA
0.4
V
IOL= 2.00mA
VCC - 0.4
V
IOL= -0.98mA
0.4
V
IOL= 0.66mA
VCC - 0.4
V
IOL= -0.18mA
V
IOL= 0.18mA
0.16
0.4
0.1VCC
0.8
V
- 170
- 250
uA
VRL=0V
-3.0
0.01
3.0
uA
0V, VCC
-3.0
0.02
3.0
uA
0V, VCC
Supply Current
25
40
mA
All inputs at rail;
outputs floating
ICC1
Halt Mode Current
3.2
6
mA
All inputs at rail;
outputs floating
ICC2
Stop Mode Current
25
50
uA
All inputs at rail;
outputs floating
Notes:
1.
ST = standard drive, le = low EMI drive
2.
For XTAL2 and OSDX2
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Preliminary
86
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
9.3 AC Characteristics
The numbers in Table 71 correspond to the numbered signal segments in Figure 21.
Table 71
AC Characteristics
No. Symbol
Parameter
Min
Max
Unit
166
1000
ns
25
ns
1
TpC
Input Clock Period
2
TRC, TFC
Clock Input Rise And Fall Time
3
TWC
Input Clock Width
35
ns
4
TWHsyncINL
Hsync Input Low Width
70
ns
5
TWHsyncINH
Hsync Input High Width
3TpC
6
TpHsyncIN
Hsync Input Period
8TpC
7
TRHsyncIN, TFHsyncIN Hsync Input Rise Fall Time
8
TWIL
Interrupt Request Input Low
70
9
TWIH
Interrupt Request Input High
3TpC
10
TDPOR
Power-On Reset Delay
25
11
TDLVIRES
Low Voltage Detect To Internal 200
Reset Condition
12
TWRES
Reset Minimum Width
5TpC
13
TDHSOl
Hsync Start To OSDX2 Stop
2TpV
14
TDHSOH
Hsync Start To OSDX2 Start
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Preliminary
100
ns
ns
100
ms
ns
3TpV
1TpV
87
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
9.4 Timing Diagram
3
1
5
7
XTAL1
Hsync IN
3
4
2
6
2
IRQn
8
9
VCC
11
10
Internal/Reset
12
External/Reset
HSYNC
13
14
OSDX2
Figure 21
Timing Requirements of External Inputs
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Preliminary
88
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
10
PACKAGING
21
1
E1
42
22
D
E
Q1
A2
C
L
S
A1
B
F
Figure 22
42-Lead Shrink Dual-in-line Package (SDIP)
Table 72
Package Dimensions
eA
Millimeter
Inch
Symbol
Min
A1
Max
0.51
Min
Max
.020
A2
4.32
.170
B
0.38
0.56
.015
.022
B1
0.76
1.27
.030
.050
C
0.20
0.30
.008
.012
D
36.70
36.96
1.445
1.455
E
15.24
15.88
.600
.625
E1
13.72
14.22
.540
.560
F
1.78 TYP
.070 TYP
eA
15.49
16.76
.610
.660
L
3.05
3.43
.120
.135
Q1
1.65
1.91
.065
.075
S
0.51
0.76
.020
.030
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Preliminary
89
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
11
Ordering Information
Part
PSI
Description
Z90251
Z9025106PSC
OTP TV Controller
Z90255
Z9025506PSC Rxxxx*
Masked ROM TV Controller
Z9025900ZEM
Z9025900ZEM
Emulator/Programmer
Z9020900TSC
Z9020900TSC
Protopak
* xxxx is a unique ROM number assigned to each customer code
12
ROM Code Submission
ROM Code Submission Instructions
ROM Code can be submitted on ZiLOG’s web site at http://www.zilog.com.
Top Mark Information
Mark Permanency: 3X soak into Alpha 2110 at 63° to 70°C, for 30 seconds duration each
soak. Mechanical brush after each soak.
PS001300-TVC1099
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Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
13
Customer Feedback Form
Z90255 Product Specification
If there are any problems while operating this product, or any inaccuracies in the specification,
please copy and complete this form, then mail or fax it to ZiLOG. Suggestions welcome!
Customer Information
Name
Country
Company
Phone
Address
Fax
City/State/Zip
E-Mail
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
910 E. Hamilton Avenue, Suite 110, MS 4–3
Campbell, CA 95008
Fax: (408) 558-8536
Email: [email protected]
Problem Description or Suggestion
Provide a complete description of the problem or suggestion. For specific problems, include all
steps leading up to the occurrence of the problem. Attach additional pages as necessary.
PS001300-TVC1099
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