P R E L I M I N A R Y Zilog Z90349/Z90348 PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z90349/348 DIGITAL TELEVISION CONTROLLER IN-CIRCUIT EMULATOR (ICE) DEVICE FEATURES ■ Part Number ROM (Word) RAM (Word) Speed (MHz) ■ Direct Closed Caption Decoding Z90349 Z90348 0 0 1K 1K 12 12 ■ TV Tuner Serial Interface ■ Customized Character Set 144-Pin Grid Array (PGA) Package (Z90349) 100-Pin Quad Flat Pack (QFP) Package (Z90348) ■ Character Control Mode ■ 4.5- to 5.5-Volt Operating Range ■ Directly Controlled Receiver Functions ■ Z89C00 RISC Processor Core ■ V-Chip Decode ■ 0°C to +70°C Temperature Range ■ GENERAL DESCRIPTION The Z90349 and Z90348 are ROMless versions of the Z89300 family of Zilog's Digital Television Controllers designed for use in emulators and development boards to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The powerful Z89C00 RISC processor core allows users to control on-board peripheral functions and registers using the standard processor instruction set. In closed caption mode, text can be decoded directly from the composite video signal and displayed on the screen with assistance from the processor's digital signal processing capabilities. The character representation in this mode allows for a simple attribute control through the insertion of control characters. The character control mode provides access to the full set of attribute controls. The modification of attributes is allowed on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Display attributes, including underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency, are made possible through a fully customized 512 character set. CP97TEL2600 Serial interfacing with the television tuner is provided through the tuner serial port. Digital channel tuning adjustments may be accessed through the industrystandard I2C port. Additional hardware provides the capability to display two to three times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Special circuitry can be activated to improve the visibility of text by adding a rightsided shadow effect to the characters. Receiver functions such as color and volume can be directly controlled by six 8-bit pulse width modulated ports. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 P R E L I M I N A R Y Zilog Z90349/Z90348 GENERAL DESCRIPTION (Continued) PWM Capture IRIN CVI Port 17 Port 00 Port 05 Port 04 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC HSYNC2 VSYNC /Reset PWM6 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 I2C SCL/MSCL2 SCD/MSCD2 MSCL1 MSCD1 Register Addr/Data Port 01/11 Port 02/12 OSD V1(R) V2(G) CPU V3(B) RAM 1K x 16 Address Addr Data Data Functional Block Diagram 2 CP97TEL2600 P R E L I M I N A R Y Zilog Z90349/Z90348 PIN DESCRIPTION 144-Pin PGA Configuration 25 26 1 100 Z90348 50 51 76 75 100-Pin QFP Configuration CP97TEL2600 3 P R E L I M I N A R Y Zilog Z90349/Z90348 PIN DESCRIPTION (Continued) Z90349/Z90348 Pin Identification Table Number Pin Name 52 53 46 47 48 49 V1 (R) gnd Blank HSync E3 C1 E2 D1 F3 54 55 56 57 58 50 51 52 53 54 55 int_bus4 VSync P12/I2CMSD2 int_bus5 P11/I2CMSC2 int_bus6 N9 R9 R10 P9 P10 N10 address8 address7 address6 CVI/ADC0 address5 address4 F2 E1 G2 G3 F1 G1 59 60 61 62 63 64 56 57 58 59 60 61 P0E int_bus7 I2CMSD1 VCC I2CMSC1 int_bus8 R11 P11 R12 R13 P12 N11 16 17 18 19 20 VCC gnd address3 LPF address2 H2 H1 H3 J3 J1 62 65 66 67 21 22 23 24 25 address1 address0 IE R/W AGNDF K1 J2 K2 K3 L1 68 69 70 71 72 26 27 28 29 30 sys_clk EA0 EA1 EA2 ADC5 L2 M1 N1 M2 L3 73 74 75 76 77 63 64 65 66 67 68 69 /Reset address 16 address 15 XR/W /XOE XTAL1 XTAL2 int_bus9 gnd data15 data11 GND P13 R14 N12 N13 P14 P15 L13 N15 L14 M15 X13 K14 4 5 6 31 N2 P1 M3 N3 N4 P3 P2 P4 78 data10 data14 data13 data12 _pabus VCC/VDD L15 J14 J13 X15 J15 H14 7 8 9 10 11* 12 32 33 34 35 P04/ADC4 address19 address18 address17 P05/ADC3 gnd P00/ADC2 int_bus0 70 71 72 73 74 75 76 77 78 79 80 _romless data9 data8 data7 stopwdt H15 H13 G13 G15 F15 13* 14 15 16 36 37 38 39 40 41 P17/ADC1 int_bus1 AGND int_bus2 AVCC int_bus3 N5 R3 P5 R4 N6 P6 P0F/strans V3 (B) VCC V2 (G) R5 P7 N7 R6 AGNDX single-stop data6 data5 data4 data3 PWM1 G14 F14 F13 E15 E14 D15 C15 17 42 43 44 45 81 82 83 84 85 86 87 88 89 90 91 data2 data1 data0 VCC D14 E13 C14 B15 23 24 25 Number Pin Name 1 2 3 4 P03 P02/I2CSSC VCC gnd D3 C2 B1 D2 5 6 7 8 9 address12 address11 P0I/I2CSS0 address10 address9 10 11 12 13 14 15 4 144-Pin 100-Pin 79 80 81 82 83 84 85 86 87 88 144-Pin R7 P8 R8 N8 100-Pin 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 18 19 20 21 22 CP97TEL2600 P R E L I M I N A R Y Zilog Number Pin Name 144-Pin 92 93 94 95 PWM2 gnd P1A P1B PIC PWM3 PWM4 D15 C13 B14 A15 C12 B13 A14 27 28 96 97 98 99 100 PWM5 int_bus10 PWM6 int_bus11 P10/4<0> B12 C11 A13 B11 A12 29 30 31 32 33 101 102 103 104 105 int_bus12 P08/R<1> VCC P18/G<0> P13/G<1> C10 B10 A11 B9 C9 34 35 106 107 108 109 110 111 gnd P14/B<0> P15/B<1> int_bus13 P16/SCLK int_bus14 A10 A9 B8 A8 C8 C7 112 113 114 115 116 117 IRIN int_bus15 P0C P0B P0A P19 A7 A6 B7 B6 C6 A5 41 118 119 120 121 122 123 124 P09 V CC P0D address14 P07/CSync address13 P06/Cnter P1D P1E P1F B5 A4 A3 B4 C5 B3 A5 C4 C3 B2 46 CP97TEL2600 Z90349/Z90348 100-Pin 26 36 37 38 39 40 42 43 44 45 47 48 49 50 51 5 P R E L I M I N A R Y Zilog Z90349/Z90348 V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V VCC = 5.25 V Condition Limit Output Voltage Bit = 11 Bit = 10 Bit = 01 Bit = 00 2.10 V ± 0.3 V 1.75 V ± 0.30 V 1.28 V ± 0.30 V 0.0 Setting Time 70% of DC Level, 10pf Load < 50 ns VCC = 4.75 V Condition Limit Output Voltage Bit = 11 Bit = 10 Bit = 01 Bit = 00 1.90 V ± 0.30 V 1.60 V ± 0.30 V 1.20 V ± 0.30 V 0.0 Setting Time 70% of DC Level, 10pf Load < 50 ns V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75 V XTAL1 32.768k 68pF 10 Mohm Z9034X XTAL2 27k 560pF 32K Oscillator Recommended Circuit 6 CP97TEL2600 P R E L I M I N A R Y Zilog Z90349/Z90348 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units Conditions V CC V ID Power Supply Voltage Input Voltage 0 –0.3 7 V CC +0.3 V V Digital Inputs V IA VO IOH IOH IOL IOL Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low –0.3 –0.3 V CC +0.3 V CC +0.3 –10/–1a –100 20/1b 200 V V mA mA mA mA Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output One Pin All Pins One Pin All Pins TA TS Operating Temperature Storage Temperature 0 –65 70 150 °C °C Notes: a) 1 mA max. when output pad impedance is 600 Ω. b) 1 mA max. when output pad impedance is 600 Ω. DC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical 0.2 VCC VCC 0.4 3.6 V V 0.4 0.16 4.75 V V @ IOL = 1 mA @ IOL = 0.75 mA 0.3 VCC 0.75 150 1.0 3.5 0.5 90 V V V µA External Clock Generator Driven On XTAL1 Input Pin V RL = 0 V 3.0 100 0.01 60 µA mA @ 0 V and V CC 300 40 100 5 µA µA Sleep Mode @ 32 KHz Stop Mode V IL V IH Input Voltage Low Input Voltage High 0 0.6 VCC V OL VOH Output Voltage Low Output Voltage High V CC –0.9 V XL V XH V HY IIR Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current IIL ICC Input Leakage Supply Current ICC1 ICC2 Supply Current Supply Current CP97TEL2600 VCC –2.0 3.0 –3.0 Units Conditions 7 P R E L I M I N A R Y Zilog Z90349/Z90348 AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TPC TRC,TFC Input Clock Period Clock Input Rise and Fall 16 100 32 12 µs µs TD POR Power On Reset Delay 0.8 1.2 s Note Depends on Crystal AC CHARACTERISTICS* TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TW RES TD HS Power-On Reset Min. Width H_Sync Incoming Signal Width 5.5 5TPC 12.5 11 µs µs TD VS TD ES V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field 0.15 –12 1.5 +12 1.0 0 ms µs TD OS Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width 20 44 32 µs 2.0 0.5 µs TW HVS Notes: All timing of the I2C bus interface are defined by related specifications of the I2 C bus interface. © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 8 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com CP97TEL2600