ZC0302 VGA & CIF USB PC Camera Controller ZC0302 VGA USB PC Camera Processor Vimicro Corporation Data Sheet Vimicro Corporation reserves the right to make changes without further notice to any product herein to improve reliability, function or design. Vimicro does not assume any liability arising out of the application or use of any project, circuit described herein; neither does it convey any license under its patent nor the right of others. This document contains information of a proprietary nature. None of this information shall be divulged to persons other than Vimicro Corporation employee authorized by the nature of their duties to receive such information, or individuals or organizations authorized by Vimicro Corporation. 1 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller Contents 1. Features 4 1.1. General Features 2. Architecture 4 5 2.1. ZC0302 Block Diagram 2.2. CMOS Image Sensor Interfaces 2.3. USB Features 2.4. Image Signal Processing 2.5. Raster 2.6. Compression Engine 2.7. Audio Interface 2.8. System Controller 3. Pin Definition 5 5 6 6 6 6 6 6 8 3.1. Pin Assignment 3.2. Pin Description 4. Electrical Characteristics 8 8 10 4.1. Absolute Maximum Ratings 4.2. DC Characteristics 4.3. USB Transceiver AC Characteristics 4.4. RESET Timing AC Characteristics 4.5. Clock AC Characteristics 4.6. Input Signal AC Characteristics 4.7. Output Signal AC Characteristic 10 10 10 11 11 12 12 5. Mechanical Information 13 6. Appendix 13 2 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller Illustrations Figure 1 USB PC Camera System Block Diagram Figure 2 Block diagram of ZC0302 Figure 3 48-Pin LQFP Package Figure 4 RESET Timing AC Characteristics Diagram Figure 5 Clock Timing AC Characteristics Diagram Figure 6. Input signal AC characteristics Figure 7. VSYNC/HSYNC output AC characteristics Figure 8. 48-Pin LQFP Package Diagram (OMITTED) Figure 9. Serial Bus Timing Diagram 3 5 8 11 11 12 12 13 13 Tables Table 3.1 ZC0302 Pin Descriptions Table 4.1 Absolute Maximum Ratings Table 4.2 DC Characteristics Table 4.3 Full-Speed Driver Electrical Characteristics Table 4.4 Low-Speed Driver Electrical Characteristics Table 4.5 Reset Signal AC Characteristics Table 4.6 Clock Signal AC Characteristics Table 4.7 CS_D input signal AC Characteristics Table 4.8 Vsync / Hsync input AC Characteristics Table 4.9 Vsync / Hsync output AC characteristics Table 5.1 ZC0302 Package Dimension Table 7. Serial Bus Timing Table 3 8 10 10 10 10 11 11 12 12 13 13 14 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller 1. Features ESDA ESCK EEPROM VSYNC OSCIN HSYNC OSCOUT CRYSTAL 48M Hz DATA[8:0] PCLK ZC0302 ENB USB CABLE Serial Interface CMOS IMAGE SENSORS PC MIC FIGURE 1 USB PC CAMERA SYSTEM BLOCK DIAGRAM The ZC0302 chip provides a cost effective single chip solution for the PC camera application. It communicates with PC host via Universal Serial Bus (USB) port. All major image processing functions, such as image signal processing (ISP), image data compression and data transfer units are built in the chip. Meanwhile ZC0302 also provides high quality audio sampling function for sound recording. The audio function complies with USB audio class 1.0. ZC0302 is designed as a cost-effective single-chip device replacing the complex and costly chip sets used in current PC camera designs with embedded USB device controller and transceiver, 48-QFP package, and no external DRAM requirement. Advanced on-chip image signal processor and JPEG encoder produce images with superior quality. 1.1. General Features Low cost, single chip solution for high resolution USB PC camera applications Audio function complying to USB audio device class 1.0 Support up to 15 fps VGA video display without DRAM USB Device Controller compliant with USB protocol 1.1 USB parameter configurable through EEPROM Support 9/8-bit RGB Bayer pattern raw data input from CMOS image sensors Support programmable color correction and gamma correction Support programmable Auto Exposure/Auto White Balance Support Auto Gain Control Support ISO/IEC 10918-1 (JPEG) standard image compression Support 4 quantization tables for programmable image quality Support raw data output for high quality still image 3.3V I/O, 2.5V core No external DRAM required Flexible system level solution support 4 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller 2. Architecture 2.1. ZC0302 Block Diagram MIC JPEG Encoder Subsample & Raster ISP System Controller UDC (USB Device Controller) Audio Interface EEPROM Interface CIS Interface CIS (CMOS Image Sensor) EEPROM PC HOST ZC0302 FIGURE 2 BLOCK DIAGRAM OF ZC0302 Figure 2 shows the block diagram of ZC0302. The ISP block receives RGB raw data from CMOS image sensor interface and performs various image processing tasks such as white balance, color correction, gamma correction, histogram equalization and so on. The Sub-sample & Raster block handles the input image data scaling and converts input image data to 8x8 block data format required by DCT module. The JPEG Encoder block compresses the image data from ISP block into JPEG format data. The compressed image data is then transferred to PC host via USB Device Controller (UDC) block for display. The Audio Interface takes the audio input in mono 16-bit PCM format, and then transfers it to PC Host through the audio streaming pipe in UDC. 2.2. CMOS Image Sensor Interfaces Support sensors from most CMOS image sensor vendors including Agilent, Hynix, IC Media, TASC, PixArt, Photobit, OmniVision, and Century 9bit/8bit camera input interface 5 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller 2.3. USB Features Built-in USB transceiver Suspend and Remote wakeup 3 interface for video, audio and control Programmable OEM USB parameters by EEPROM including: vendor ID, product ID, MaxPower, serial Number, manufacture descriptor, product descriptor and chip revision. 2.4. Image Signal Processing Hardware Dead Pixel Detection/Concealment 8/9-bit RGB raw data input from CMOS image sensor 2-wire/3-wire serial bus interface to CMOS image sensor Programmable white balance, color correction and gamma correction Support automatic Exposure Control, automatic White Balance, automatic CMOS Reset Level Control, automatic Gain Control and auto/manual Histogram Equalization Support programmable AE/AWB windows Support edge enhancement and noise removal Support 2x2 Sub-Sampling 2.5. Raster The output data format is 4:2:2 YCbCr Change the input image data to 8x8 block data format required by the DCT 2.6. Compression Engine Standard JPEG compression engine comply to ISO/IEC 10918-1 (JPEG) 2 AC and 2 DC Huffman code table 4 quantization tables for different image quality Adjustable compression rate by Bit Rate Control (BRC) engine Simplified JPEG header for better performance are programmable VGA @ 15fps, CIF/SIF up to 30 fps Adjustable frame rate for efficient bandwidth usage 2.7. Audio Interface Built-in 16-bit mono audio ADC for audio recording through microphone Sampling rate @ 8K/16K Hz USB audio device class 1.0 compliance 2.8. System Controller Providing the control to ISP, JPEG, and USB blocks Configuring the control registers Chip clock generation 6 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller Error detection and handling through USB interface 7 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller 3. Pin Definition CS_RSTB CS_EN SDA SCK NC OVDD CS_CLK OVSS HSYNC VSYNC CS_PWDB ESDA 48 47 46 45 44 43 42 41 40 39 38 37 3.1. Pin Assignment CS_D[8] 1 36 PIO[3] CS_D[7] 2 35 ESCK CS_D[6] 3 34 PIO[2] CS_D[5] 4 33 PIO[1] NC 5 32 PIO[0] NC 6 31 TEST CS_D[4] 7 30 NC CS_D[3] 8 29 VCM CS_D[2] 9 28 VREFOUT CS_D[1] 10 27 GND_REF CS_D[0] 11 26 MIC PWUP_RST 12 25 VDD_A 20 21 22 23 24 NC SUSPENDB DVDD SNAPB GND_A 17 DP 19 16 VSS_USB VDD_USB 15 DVSS 18 14 CLKXOUT DM 13 CLKXIN ZSMC ZC0302 – 48 LQFP FIGURE 3 48-PIN LQFP PACKAGE 3.2. Pin Description Pin Type Function CS_D[8] I, PD I, PD I, PD I, PD Sensor data Sensor data Sensor data Sensor data CS_D[7] CS_D[6] CS_D[5] 8 48 Pin LQFP 1 2 3 4 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller Pin Type Function CS_D[4] CS_D[3] CS_D[2] CS_D[1] CS_D[0] PWUP_RST CLKXIN CLKXOUT DVSS VSS_USB DP DM VDD_USB SUSPENDB DVDD SNAPB GND_A VDD_A MIC GND_REF VREFOUT VCM TEST PIO[0] PIO[1] PIO[2] ESCK PIO[3] ESDA CS_PWDB VSYNC HSYNC OVSS OVSS CS_CLK OVDD SCK / SICLK SDA / SIVAL CS_ENB / SI_EN CS_RSTB / AECNT I, PD I, PD I, PD I, PD I, PD I, Schmitt I O P P I/O I/O P O P I, PU P P A A A A I, PD I/O, PD I/O, PD I/O, PD O I/O, PD I/O, Schmitt O I/O, PD I/O, PD P P O P O, PD I/O, Schmitt O, PD O, PD Sensor data Sensor data Sensor data Sensor data Sensor data Power on reset, active low Crystal input Crystal output Core ground USB transceiver ground USB data USB data USB transceiver power Active-low suspend Core power Snapshot and remote wake up, active low IADC analog ground IADC analog power IADC microphone input IADC input ground reference IADC reference voltage IADC common-mode voltage Manufacturing test mode General purpose I/O General purpose I/O General purpose I/O SEEPROM clock General purpose I/O EEPRPOM data Power-down pin controlling DC/DC regulator Vertical synchronous signal Horizontal synchronous signal I/O ground I/O ground Sensor clock I/O power Serial interface clock Serial interface data Sensor power enable / Serial interface enable Sensor reset / auto exposure for TASC VGA sensor 48 Pin LQFP 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 41 41 42 43 45 46 47 48 TABLE 3.1 ZC0302 PIN DESCRIPTIONS 9 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller 4. Electrical Characteristics 4.1. Absolute Maximum Ratings Ambient temperature 0oC to 70oC Storage temperature -40oC to 125oC DC supply voltage 3.0V to 3.6V I/O pin voltage with respect to VSS -0.3V to VDD + 0.3V TABLE 4.1 ABSOLUTE MAXIMUM RATINGS 4.2. DC Characteristics Symbol Parameter Conditions Min Max Unit VDD3V 3.3V Power Supply 3.0 3.6 V VDD2V 2.5V Power Supply 2.25 2.75 V Vil Input Low voltage -0.5 1.0 V Vih Input High voltage 2.3 5.5 V Vol Output Low Voltage - 0.4 V Voh Output High Voltage 2.4 - V Ipd Suspend current - 500 uA Ido Active current - 80 mA TABLE 4.2 DC CHARACTERISTICS 4.3. USB Transceiver AC Characteristics Symbol Min Typ Parameter Conditions Max Unit TFR Rise time CL=50p 4 20 ns TFF Fall time CL=50p 4 20 ns TFRFF Rise and fall time matching TLRLF=TLR/TLF 90 111.11 % TABLE 4.3 FULL-SPEED DRIVER ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min Typ Max TLR Rise time CL=50p CL=600p 75 TLF Fall time CL=50p CL=600p 75 10 Unit 300 ns 300 ns Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller TLRLF Rise and fall time matching TLRLF=TLR/TLF 80 125 % TABLE 4.4 LOW-SPEED DRIVER ELECTRICAL CHARACTERISTICS 4.4. RESET Timing AC Characteristics FIGURE 4 RESET TIMING AC CHARACTERISTICS DIAGRAM Symbol Parameter Conditions Trst Reset Pulse Width Min Max Unit -- 20 ms TABLE 4.5 RESET SIGNAL AC CHARACTERISTICS 4.5. Clock AC Characteristics FIGURE 5 CLOCK TIMING AC CHARACTERISTICS DIAGRAM Symbol Parameter Conditions Min Max Unit 1/Tcyc Oscillator Frequency 48@10PPM - - Mhz Thigh Oscillator Clock High Time 8.3 - Ns 11 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller Tlow Oscillator Clock Low Time 8.3 - Ns TABLE 4.6 CLOCK SIGNAL AC CHARACTERISTICS 4.6. Input Signal AC Characteristics CS_CLK Tsu CS_D Th Valid data Tsu CS_CLK Th VSYNC/HSYNC FIGURE 6. INPUT SIGNAL AC CHARACTERISTICS Symbol Parameter Conditions Tsu Th Input setup time Input hold time Min Max Unit 0 45 - ns ns TABLE 4.7 CS_D INPUT SIGNAL AC CHARACTERISTICS Symbol parameter conditions Tsu Th Input setup time Input hold time Min Max Unit 0 20 - ns ns TABLE 4.8 VSYNC / HSYNC INPUT AC CHARACTERISTICS 4.7. Output Signal AC Characteristic Td CS_CLK VSYNC/HSYNC FIGURE 7. VSYNC/HSYNC OUTPUT AC CHARACTERISTICS Symbol Parameter Td Output delay Conditions Min Max Unit - 1.5 ns TABLE 4.9 VSYNC/HSYNC OUTPUT AC CHARACTERISTICS 12 Mar. 2002 ZC0302 VGA & CIF USB PC Camera Controller 5. Mechanical Information FIGURE 8. 48-PIN LQFP PACKAGE DIAGRAM (OMITTED) Lead Count 48 Body Size D1 7 Stand-Off E1 A1 7 0.1 Body Thickness A2 1.4 Lead Width b 0.2 Lead Thickness c 0.127 Lead Pitch e 0.5 TABLE 5.1 ZC0302 PACKAGE DIMENSION (unit: mm) 6. Appendix FIGURE 9. SERIAL BUS TIMING DIAGRAM Parameter Symbol Min Max. Unit SCK clock frequency Time that I2C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of each bus lines (SDA, SCK) fsck tbuf 0 4.7 100 - KHz us thd;Sta tlow thigh tsu;Sta thd;dat tsu;dat tr tf tsu;Stp Cb 4.0 4.7 4.0 4.7 0 200 4.7 - 1 300 - us us us us us ns us ns us pf TABLE 7. SERIAL BUS TIMING TABLE 13 Mar. 2002