ZL10100 Single Chip Synthesized Downconverter with IF Amplifier Data Sheet Features • April 2005 Single chip synthesised downconverter forming a complete double conversion tuner when combined with the SL2100 or SL2101 • Compatible with digital and analogue system requirements • CTB contribution < -64 dBc, CXM contribution < -62 dBc and spectral spread < -64 dBc • IF amplifier optimized to interface with standard SAW filters • Extremely low phase noise balanced local oscillator, with very low fundamental and harmonic radiation • PLL frequency synthesizer designed for high comparison frequencies and low phase noise • Available in 28 pin SSOP and MLP packages Ordering Information ZL10100/DDE ZL10100/DDF ZL10100/DDE1 ZL10100/DDF1 ZL10100/LDG1 ZL10100/LDF1 Double conversion tuners • Digital Terrestrial tuners • Cable Modems • Cable telephony • MATV All codes Baked an Drypacked -40°C to +85°C Description The ZL10100 is a fully integrated single chip mixer oscillator with on-board low phase noise I2C bus controlled PLL frequency synthesizer. It is intended primarily as the down converter for application in double conversion tuners and is compatible with HIIF frequencies between 1 and 1.3 GHz and all standard tuner IF output frequencies. The device contains all elements necessary, with the exception of local oscillator tuning network, loop filter and crystal reference to fabricate a complete synthesized block converter with IF amplifier, compatible with digital and analogue requirements. RF Input IF Output RF InputB LO LOB IF OutputB VCO Pump 15 Bit Programmable Divider SDA SCL ADD XTAL XTALCAP Tubes Tape & Reel, Tubes Tape & Reel Trays Tape & Reel * Pb free Applications • SSOP SSOP SSOP* SSOP* MLP* MLP* Charge Pump Drive fpd/ 2 I2C Bus Interface Fpd/2 REF OSC Reference Divider Fcomp Figure 1 - ZL10100 Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved. Port P0 ZL10100 Data Sheet Pin Description IFOUTPUTB Vee VccRF Vee RFINPUTB RFINPUT Vee Vee VccD Vee SCL SDA XTAL XTAL CAP IFOUTPUT Vee VccIF Vee VccLO LO LOB VccLO Vee ADD Vee Port P0 DRIVE PUMP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc 1 RFINPUTB 3 RFINPUT VccIF Vee IFOUTPUT nc IFOUTPUTB 28 27 26 25 24 23 22 21 2 nc Vee VccRF Figure 2 - Pin Description SSOP Package Pin 1 Ident nc 20 VccLO 19 LO 6 16 SCL 7 15 9 10 11 12 13 14 ADD nc Port P0 SDA Vee to pad under package 8 DRIVE VccD PUMP VccLO Vee LOB 17 XTAL CAP 18 5 XTAL 4 nc Figure 3 - Pin Description MLP Package 2 Zarlink Semiconductor Inc. ZL10100 Data Sheet Quick Reference Data All data applies with the following conditions unless otherwise stated; a) Output load of 150 Ω, differential b) Input spectrum of 5 channels centred on 1220 MHz, each carrier @ 77 dBµV Characteristic Units RF input operating range 1-1.3 GHz IF output operating range 30-60 MHz Input noise figure, SSB 9 dB Conversion gain, diff to diff 24 dB CTB < −66 dBc CXM < −63 dBc Spectral spread < −70 dBc Local oscillator phase noise SSB @ 10 kHz offset SSB @ 100 kHz offset c -93 c-115 dBc/Hz dBc/Hz Local oscillator phase noise floor -136 dBc/Hz IF output impedance, differential 150 Ω PLL phase noise at phase detector, 1 MHz comparison frequency -152 dBc/Hz 3 Zarlink Semiconductor Inc. ZL10100 1.0 Data Sheet Functional Description The ZL10100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL frequency synthesizer, optimized for application as the down converter in double conversion tuner systems. It also has application in any system where a wide dynamic range broadband synthesized frequency converter is required. The ZL10100 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in the block diagram in Figure 1 and the Pin Description in Figure 2. 1.1 Converter Section In normal application the HIIF input is interfaced through appropriate impedance matching to the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region of 1 to 1.3 GHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and back isolation from the local oscillator section. The typical RF input impedance and matching network for matching to a 1220 MHz HIIF filter, type B1603 are contained in Figures 3 and 4. The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The oscillator block uses an external tuneable network and is optimized for low phase noise. The typical application is shown in Figure 6, and the phase noise performance in Figure 7. This block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator. The output of the mixer is internally coupled to a differential IF amplifier, which provides further gain and provides for a 150 Ω, differential output impedance and drive capability. The IF amplifier allows for IF frequencies between 30 and 60 MHz. The typical IF output impedance is contained in Figure 8. The typical key performance data at 5 V Vcc and 25 deg C ambient are shown in the Quick Reference Data section on Page 2. 1.2 Local Oscillator To maximize the local oscillator phase noise performance, the application circuit as in Figure 5 must be carefully adhered to including the component type and manufacture where applicable, strip line dimension and board material. Any deviation from these parameters may adversely affect phase noise characteristics and so will require re-optimization. 1.3 PLL frequency Synthesizer The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits, and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1. 4 Zarlink Semiconductor Inc. ZL10100 Data Sheet The typical application for the crystal oscillator is contained in Figure 9 which also demonstrates how a 4 MHz reference signal can be coupled out to a further PLL frequency synthesizer, such as the upconverter section in a double conversion tuner. The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to port P0 by programming the device into test mode. The test modes are described in Table 2. 2.0 Programming The ZL10100 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 3, 4 and 5 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one device in an I2C bus system. Table 5 shows how the address is selected by applying a voltage to the 'ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. 2.1 Write Mode With reference to Table 5, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the synthesizer reference divider ratio, see Table 1 and the charge pump setting, see Table 6. Byte 5 controls the test modes, see Table 2 and the output port P0. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. 2.2 Read Mode When the device is in read mode, the status byte read from the device takes the form shown in Table 4. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3 V (at 25°C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. 5 Zarlink Semiconductor Inc. ZL10100 Programmable Features Synthesizer programmable divider Reference programmable divider Charge pump current Function as described above. Function as described above. The charge pump current can be programmed by bits C1 and C0 within data byte 4, as defined in Table 6. The test modes are defined by bits T2-T0 as described in Table 2. The general purpose port can be programmed by bits P0; Logic ’1’ = on Logic ’0’ = off (high impedance) Test mode General purpose ports, P0 CH1 S 11 Data Sheet 1 U FS 26 Jun 2002 14:18:23 -74.777 2.1284 pF 1_: 33.309 B1 4.7V 1 000.000 000 MHz PRm Cor 2_: 29.262 -66.289 1.1 GHz Z0 50 Avg 16 Smo 3_: 24.57 -58.744 1.22 GHz 4_: 22.332 -54.303 1.3 GHz 1 4 3 START 1 000.000 000 MHz 2 STOP 1 300.000 000 MHz Figure 4 - Typical RF Input Impedance 6 5 2.7 pF B1603 8.2 nH ZL10100 2.7 pF 5 6 Figure 5 - RF Input Impedance Matching Network to B1603 HIIF Filter 6 Zarlink Semiconductor Inc. ZL10100 Data Sheet 2.5 pF 23 1 kΩ Varactor line 4.3 nH 22 BB555 Phase noise (@ 10KHz offset), dBc Figure 6 - Oscillator Application -80 -85 -90 -95 -100 -105 -110 1010 1060 1110 1160 1210 LO Frequency (MHz) Figure 7 - Typical Phase Noise Performance with Application as in Figure 6 7 Zarlink Semiconductor Inc. ZL10100 CH1 S 11 1 U FS Data Sheet 25 Jun 2002 06:58:03 -5.6172 944.45 pF 1_: 76.695 30.000 000 MHz B1 PIN1 4.7V PRm Cor Avg 16 Smo 2_: 75.914 -7.2539 44 MHz Z0 75 3_: 75.391 -7.9023 50 MHz 4_: 74.152 -9.207 60 MHz 1 432 START 30.000 000 MHz STOP 60.000 000 MHz Figure 8 - Typical IF Output Impedance Single-Ended 8 Zarlink Semiconductor Inc. ZL10100 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data Sheet R3 R2 R1 R0 Ratio 0 0 0 0 2 0 0 0 1 4 0 0 1 0 8 0 0 1 1 16 0 1 0 0 32 0 1 0 1 64 0 1 1 0 128 0 1 1 1 256 1 0 0 0 Illegal state 1 0 0 1 5 1 0 1 0 10 1 0 1 1 20 1 1 0 0 40 1 1 0 1 80 1 1 1 0 160 1 1 1 1 320 0 0 0 0 Illegal state 0 0 0 1 6 0 0 1 0 12 0 0 1 1 24 0 1 0 0 48 0 1 0 1 96 0 1 1 0 192 0 1 1 1 384 1 0 0 0 Illegal state 1 0 0 1 7 1 0 1 0 14 1 0 1 1 28 1 1 0 0 56 1 1 0 1 112 1 1 1 0 224 1 1 1 1 448 Table 1 - Reference Division Ratios XTALCAP 47 pF XTAL 47 pF 4 MHz 10 pF Reference frequency output Figure 9 - Crystal Oscillator Application 9 Zarlink Semiconductor Inc. ZL10100 T2 0 0 T1 0 0 0 1 0 1 1 1 0 0 1 1 1 1 Data Sheet T0 0 1 Test Mode Description Normal operation Charge pump sink* Status byte FL set to logic ’0’ 0 Charge pump source* Status byte FL set to logic ’0’ 1 Charge pump disabled* Status byte FL set to logic ’1’ 0 Normal operation and Port P0 = Fpd/2 0 Charge pump sink* Status byte FL set to logic ’0’ Port P0 = Fcomp 0 Charge pump source* Status byte FL set to logic ’0’ Port P0 = Fcomp 1 Charge pump disabled* Status byte FL set to logic ’1’ Port P0 = Fcomp Table 2 - Test Modes * clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle status byte bit FL Address Programmable divider Programmable divider Control data Control data MSB 1 1 0 214 26 27 1 C1 T2 T1 Table 3 - Write Data LSB MA1 MA0 0 210 29 28 22 21 20 R2 R1 R0 X 0 P0 Transmitted First) A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Address Status Byte MSB LSB 1 1 0 0 0 MA1 MA0 1 POR FL 0 0 0 0 0 0 Table 4 - Read Data Format (MSB is Transmitted First) A A Byte 1 Byte 2 A : MA1,MA0 : Acknowledge bit Variable address bits (see Table 5) 214-20 C1-C0 R4-R0 T2-T0 P0 POR FL X Programmable division ratio control bits Charge pump current select (see Table 6) Reference division ratio select (see Table 1) Test mode control bits (see Table 2) P0 port output state Power on reset indicator Phase lock flag 'Don't care' : : : : : : : : MA1 0 0 1 1 MA0 0 1 0 1 0 0 0 213 212 211 25 24 23 C0 R4 R3 T0 X X Format (MSB is Address Input Voltage Level 0-0.1 Vcc Open circuit 0.4Vcc - 0.6 Vcc # 0.9 Vcc - Vcc Table 5 - Address Selection # Programmed by connecting a 30 kΩ resistor between pin and Vcc 10 Zarlink Semiconductor Inc. ZL10100 C1 0 0 1 1 Data Sheet Current in µA C0 0 1 0 1 Table 6 Min. Typ. Max. ± 98 ± 130 ± 162 ± 210 ± 280 ± 350 ± 450 ± 600 ± 750 ± 975 ± 1300 ± 1625 - Charge Pump Current Electrical Characteristics - Test conditions (unless otherwise stated) Tamb = -40°C to 85°C, Vee = 0 V, Vcc = 5 V±5%. Input frequency 1220 MHz. IF output frequency 44 MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min. Supply current Input frequency range Typ. Max. Units 120 160 mA 1.3 GHz 1 Composite peak input signal dBµV 86 Input impedance Conditions Operating condition only. See Figure 4. Input Noise Figure 9 11 dB Tamb = 27°C 23 26 dB Differential to differential voltage gain to differential 150 Ω load. Gain variation within channel 0.5 dB Channel bandwidth 8 MHz within operating frequency range. Through gain -30 dB CTB -64 dBc See note 4. CXM -62 dBc See note 4. 1.6 GHz Maximum tuning range determined by application, see note (3), guaranteed by design. Conversion gain LO operating range 20 0.9 LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset -94 -116 LO phase noise floor IF output frequency range 30 -90 -110 See Figure 7. dBc/Hz Application as in Figure 6. dBc/Hz -136 dBc/Hz Application as in Figure 6. 60 IF output impedance 75 MHz Ω Single-ended. See Figure 8. IF output return loss -20 dB See Figure 8, over operating range. All other spurs on IF Output 20 dBµV Within channel bandwidth of 8 MHz. 11 Zarlink Semiconductor Inc. ZL10100 Data Sheet Electrical Characteristics - Test conditions (unless otherwise stated) Tamb = -40°C to 85°C, Vee = 0 V, Vcc = 5 V±5%. Input frequency 1220 MHz. IF output frequency 44 MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min. Typ. Max. Units 5.5 1.5 10 V V µA µA µA V Conditions SYNTHESIZER SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis 3 0 -10 0.4 10 I2C ’Fast mode’ compliant Input voltage = Vcc Input voltage = Vee Vcc = Vee SDA output voltage 0.4 0.6 V V SCL clock rate 400 kHz ±10 nA See Table 6. Vpin = 2 V mA Vpin = 0.7 V See Figure 9 for application. Charge pump output current Charge pump drive output current ±3 0.5 Isink = 3 mA Isink = 6 mA Crystal frequency 2 20 MHz Recommended crystal series resistance 10 200 Ω External reference input frequency 2 20 MHz Sinewave coupled through 10 nF blocking capacitor 0.2 0.5 Vpp Sinewave coupled through 10 nF blocking capacitor 4 MHz External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector Local oscillator programmable divider division ratio SSB, within loop bandwidth dBc/Hz 2 MHz dBc/Hz 250 kHz -152 -158 240 32767 Reference division ratio Output port sink current leakage current 4 MHz parallel resonant crystal See Table 1. 2 Address select Input high current Input low current 10 mA µA See note 2. Vport = 0.7 Vport = Vcc 1 -0.5 mA mA See Table 5 Vin = Vcc Vin = Vee Notes (1) When measuring from a 50 Ω environment, the voltage step up transformation needs to be taken into account. (2) Port powers up in high impedance state. (3) To maximize phase noise the tuning range should be minimised and Q of resonator maximized. The application as in Figure 6 has a tuning range of 200 MHz. (4) Measured with 5 channels @ 77 dBuV centred on desired channel. 12 Zarlink Semiconductor Inc. ZL10100 Data Sheet Absolute Maximum Ratings - All voltages are referred to Vee at 0 V. Characteristic Min. Max. Units Supply voltage -0.3 7 V 117 dBuV RF input voltage All I/O port DC offsets -0.3 Vcc+0.3 V SDA, SCL DC offsets -0.3 6 V Storage temperature -55 150 °C Junction temperature 150 °C Package thermal resistance, chip to case 20 °C/W Package thermal resistance, chip to case 80 °C/W Power consumption at 5.25 V 700 mW ESD protection 3.5 kV 13 Zarlink Semiconductor Inc. Conditions Differential Vcc = Vee to 5.25 V Mil-std 883B method 3015 cat1 ZL10100 Data Sheet vcc 5 RFINPUTB XTAL RFINPUT XTALCAP 6 13 14 200 µA Reference Oscillator RF Inputs VREF 500 K 500 K LO VCC 500 K 23 SCL/SDA LOB * 22 ACK *On SDA only SDA/SCL (pins 12 and 11) Oscillator Inputs VCC 75 Ω 75 Ω IF Output IF OutputB PO 28 17 1 Output Port IF Outputs Figure 10 - Input and Output Interface Circuits 14 Zarlink Semiconductor Inc. ZL10100 Data Sheet vcc 15 vcc Pump 120 K ADD 220 16 19 40 K Drive ADD Input Loop Amplifier Figure 10 - Input and Output Interface Circuits 15 Zarlink Semiconductor Inc. ZL10100 Figure 11 - ZL10100 Evaluation Board Schematic 16 Zarlink Semiconductor Inc. Data Sheet For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE