ZARLINK ZL50234QCC

ZL50234
8 Channel Voice Echo Canceller
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
March 2003
Independent multiple channels of echo
cancellation; from 8 channels of 64ms to 4
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
Independent Power Down mode for each group of
2 channels for power management
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
Passed AT&T voice quality testing for carrier
grade echo cancellers.
Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Patented Advanced Non-Linear Processor with
high quality subjective performance
Protection against narrow band signal divergence
and instability in high echo environments
Sin
Serial
to
Parallel
Fsel
MCLK
F0i
Timing
Unit
-40°C to +85°C
•
•
•
•
•
•
0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
•
•
•
•
•
•
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
Echo Canceller pools
DCME, satellite and multiplexer system
VDD2 (1.8V)
ODE
Parallel
to
Serial
Echo Canceller Pool
Group 0
Group 1
Group 2
Group 3
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
PLL
C4i
ZL50234/QCC 100-Pin LQFP
ZL50234/GDC 208-Ball LBGA
VSS
VDD1 (3.3V)
Rin
Ordering Information
Rout
Sout
Note:
Refer to Figure 4
for Echo Canceller
block diagram
RESET
Microprocessor Interface
DS CS R/W A10-A0 DTA
Test Port
D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50234 Device Overview
1
ZL50234
Data Sheet
Description
VDD1
NC
NC
NC
NC
NC
NC
VSS
IC0
IC0
IC0
NC
Mclk
NC
NC
VDD2
IC0
fsel
IC0
PLLVDD
PLLVSS1
PLLVSS2
VSS
VDD1
ZL50234QC
(100 pin LQFP)
VDD2 = 1.8V
VDD1 = 3.3V
NC
A9
NC
A8
NC
VDD2
VDD1
A7
NC
A6
NC
NC
A5
IC0
A4
A10
VSS
IC0
VSS
A3
A1
A0
NC
VDD1
A2
51
49
39
50
38
48
37
Zarlink Semiconductor Inc.
47
36
46
35
45
44
34
43
33
42
32
41
40
31
29
30
28
27
26
Figure 2 - 100 Pin LQFP
2
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
NC
76
NC
77
D7
78
D6
79
D5
80
D4
81
D3
82
VSS
83
D2
84
D1
85
D0
86
VDD2
87
DTA
88
8
R/W
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
7
CS
89
6
IC0
RESETB
IRQB
DS
90
5
TRSTB
91
4
VSS
92
3
TCK
93
97
2
TDO
94
98
1
TDI
95
99
100
TMS
96
NC
The ZL50234 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation
conforming to ITU-T G.168 requirements. The ZL50234 architecture contains 4 groups of two echo cancellers (ECA
and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds
echo cancellation. This provides 8 channels of 64 milliseconds to 4 channels of 128 milliseconds echo cancellation
or any combination of the two configurations. The ZL50234 supports ITU-T G.165 and G.164 tone disable
requirements.
NC
NC
NC
IC0
IC0
IC0
VSS
IC0
IC0
IC0
IC0
VDD2
C4ib
Foib
Rin
Sin
Rout
Sout
ODE
VSS
NC
NC
NC
NC
NC
ZL50234
Data Sheet
1
1
A
VSS
B
IC0
C
IC0
2
IC0
VSS
3
4
5
VSS
c4i
VDD1
VDD1
F0i
IC0
6
7
8
9
VSS
Sout
VDD1
IC0
VSS
VSS
Rin
VSS
Rout
VDD1
Sin
IC0
13
14
VSS
VSS
IC0
15
16
NC
VSS
VSS
ODE
VSS
VSS
VSS
VDD1
VSS
VDD2
VSS
VDD1
VSS
VDD1
VSS
VSS
VSS
VSS
NC
VSS
VDD1
VDD2
VDD1
VSS
VDD1
VSS
VDD1
VSS
VSS
VDD1
NC
A10
IC0
VDD1
VSS
E
NC
IC0
VSS
VSS
F
NC
NC
VDD1
VDD1
G
NC
MCLK
VSS
VSS
VSS
VSS
VSS
H
NC
Fsel
VDD1
VDD1
VSS
VSS
J
NC
IC0
VDD2
VDD2
VSS
NC
IC0 PLLVSS PLLVDD
VSS
M
12
VSS
NC
L
11
IC0
D
K
10
VDD1
VSS
IC0
A9
VSS
VDD1
IC0
A8
VSS
VDD2
VDD2
NC
A7
VSS
VSS
VSS
VSS
NC
A6
VSS
VSS
VSS
VDD1
VDD1
NC
A5
VSS
VSS
VSS
VSS
VSS
NC
A4
ZL50234GD
NC
NC
VSS
VSS
VDD1
VDD1
NC
A3
TDI
TMS
VDD1
VDD1
VSS
VSS
VSS
A2
TDO
TRST
VSS
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD2
VSS
VDD1
VDD1
A1
TCK
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD2
VSS
VSS
VDD1
A0
IC0
VSS
R/W
VDD1
DTA
VDD1
IRQ
VDD1
DS
VDD1
CS
VSS
VSS
VSS
VDD1
D2
VSS
D3
D4
VSS
D5
VDD1
D6
VSS
D7
VSS
N
P
R
VSS
T
1
D0
RESET VDD1
VSS
D1
- A1 corner is identified by metallized markings.
Figure 3 - 208 Ball LBGA
Zarlink Semiconductor Inc.
3
ZL50234
Data Sheet
Pin Description
PIN #
PIN
Name
208-Ball LBGA
VSS
A1, A3,A7,A11, A13,
5, 18, 32, Ground.
A15, A16, B2, B6, B8, 42, 56, 69,
B12, B14, B15, B16, C3,
81, 98
C5, C7, C9, C11, C12,
C13, C14, C16, D4, D8,
D10, D12, D13, E3, E4,
E14, F13, G3, G4, G7,
G8, G9, G10, H7, H8,
H9, H10, H13, H14, J7,
J8, J9, J10, K7, K8, K9,
K10, K13, K14, L3, L4,
M13, M14, M15, N3, N4,
N5, N7, N9, N11, N13,
P2, P3, P5, P7, P9,P11,
P13, P14, R2, R14,
R15, R16, T1, T3, T7,
T10, T14, T16
VDD1
A5, A9, B10, C4, C8, 27, 48, 77, Positive Power Supply V DD1. Nominally 3.3 Volt.
B4, C10, D3, D5, D7,
100
D9, D11, D14, E13, F3,
F4, F14, H3, H4, J13,
J14, L13, L14, M3, M4,
N6, N8, N10, N14, N15,
P4, P6, P8, P10, P15,
R4, R6, R8, R10, R12,
T5, T12
VDD2
4
Description
100 PIN
LQFP
C6, D6, J3, J4, N12,
P12, G13, G14
14, 37, 64, Positive Power Supply VDD2. Nominally 1.8 Volts.
91
IC0
E15, F15, A12, A10, A6, 7, 41, 43, Internal Connection. These pins must be connected to VSS for
A2, B1, B3, C1, C2, D2, 65, 66, 67, normal operation.
E2, J2, K2, R1
68, 70, 71,
72, 86, 87,
88, 93, 94
NC
A14, C15, D1, D15, E1,
F1, G1, G15, H1, H15,
J1, J15, K1,
K15,L1,L15,F2,L2
IRQ
R9
24, 25, 26, No connection. These pins must be left open for normal
44, 45, 46, operation.
47, 49, 51,
52, 53, 54,
55, 73, 74,
75, 76, 78,
79, 80, 82,
83, 84, 85,
89, 99, 50
9
Interrupt Request (Open Drain Output). This output goes low
when an interrupt occurs in any channel. IRQ returns high when
all the interrupts have been read from the Interrupt FIFO
Register. A pull-up resistor (1K typical) is required at this output.
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Pin Description (continued)
PIN #
PIN
Name
Description
208-Ball LBGA
100 PIN
LQFP
DS
R11
10
Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
CS
R13
11
Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R/W
R5
12
Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
DTA
R7
13
Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1K typical) is required at this output.
D0..D7
T2,T4,T6,T8,T9,T11,
T13,T15
15, 16, 17, Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
19, 20, 21, bidirectional data bus of the microprocessor port.
22, 23
A0..A10 P16,N16,M16,L16,K16, 28, 29, 30, Address A0 to A10 (Input). These inputs provide the A10 - A0
J16,H16,G16,F16,E16, 31, 33, 34, address lines to the internal registers.
D16
35, 36, 38,
39, 40
ODE
B13
57
Output Drive Enable (Input). This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Sout
A8
58
Send PCM Signal Output (Output). Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
Rout
B9
59
Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
Sin
B11
60
Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 8
channels per stream.
Rin
B7
61
Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
F0i
B5
62
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
C4i
A4
63
Serial Clock (Input). 4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK
G2
90
Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Zarlink Semiconductor Inc.
5
ZL50234
Data Sheet
Pin Description (continued)
PIN #
PIN
Name
Description
208-Ball LBGA
100 PIN
LQFP
Fsel
H2
92
PLLVss1
PLLVss2
K3
97, 95
PLLVDD
K4
96
PLL Power Supply. Must be connected to VDD2 = 1.8V
TMS
M2
1
Test Mode Select (3.3V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
TDI
M1
2
Test Serial Data In (3.3V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
N1
3
Test Serial Data Out (Output). JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
TCK
P1
4
Test Clock (3.3V Input). Provides the clock to the JTAG test
logic.
TRST
N2
6
Test Reset (3.3V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL50234 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
RESET
R3
8
Device Reset (Schmitt Trigger Input). An active low resets the
device and puts the ZL50234 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Control and Status
Registers to their default power-up values.
1.0
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 20 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 10 MHz Master Clock input must be applied.
PLL Ground. Must be connected to VSS
Device Overview
The ZL50234 architecture contains 8 echo cancellers divided into 4 groups. Each group has two echo cancellers,
Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-toBack configurations. In Normal configuration, a group of echo cancellers provides two channels of 64ms echo
cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo
cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back
configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both
directions in a single channel, providing full-duplex 64ms echo cancellation.
6
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Each echo canceller contains the following main elements (see Figure 4).
•
Adaptive Filter for estimating the echo channel
•
Subtractor for cancelling the echo
•
Double-Talk detector for disabling the filter adaptation during periods of double-talk
•
Path Change detector for fast reconvergence on major echo path changes
•
Instability Detector to combat instability in very low ERL environments
•
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
•
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
•
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
•
Offset Null filters for removing the DC component in PCM channels
•
0 to -12dB level adjusters at all signal ports
•
Parallel controller interface compatible with Motorola microcontrollers
•
PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the ZL50234 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
µ/A-Law/
Linear
0 to -12dB
Level Adjust
Offset
Null
Σ
Non-Linear
Processor
Adaptive
Filter
Disable Tone
Detector
Instability
Detector
Linear/
µ/A-Law
Microprocessor
Interface
MuteS
Double - Talk
Detector
Path Change
Detector
Narrow-Band
Detector
Rout
(channel N)
0 to -12dB
Level Adjust
Control
Sin
(channel N)
Linear/
µ/A-Law
0 to -12dB
Level Adjust
0 to -12dB
Level Adjust
MuteR
Sout
(channel N)
Disable Tone
Detector
Offset
Null
µ/A-Law/
Linear
Rin
(channel N)
Echo Canceller (N), where 0 < N < 7
Programmable Bypass
Figure 4 - Functional Block Diagram
1.1
Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
Zarlink Semiconductor Inc.
7
ZL50234
1.2
Data Sheet
Double-Talk Detector
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the
relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:
Lsin > Lrin + 20log 10(DTDT)
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence
speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is
reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero,
adaptation is halted completely.
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The ZL50234 allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT(hex) = hex(DTDT(dec) * 32768)
where 0 < DTDT(dec) < 1
Example:For DTDT = 0.5625 (-5 dB), the
hexadecimal value becomes
hex(0.5625 * 32768) = 4800hex
1.3
Path Change Detector
Integrated into the ZL50234 is a Path Change Detector. This permits fast reconvergence when a major change
occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence
is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection
of a major path change.
1.4
Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50234
uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as
well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated
8
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
by the following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following
equation:
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
where 0 < NLPTHR(dec) < 1
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal
by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a
spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the
perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
The patented Advanced NLP provides a number of new and improved features over the original NLP found in
previous generation devices. Differences between the Advanced NLP and the original NLP are summarized in Table
1.
Feature
Register or Bit(s)
Advanced
NLP Default
Value
Original NLP
Default Value
NLP Selection
NLPSel (Control Register 3)
1
0 (feature
not supported)
Reject uncanceled echo as noise
NLRun1 (Control Register 3)
1
0 (feature
not supported)
Reject double-talk as noise
NLRun2 (Control Register 3)
1
0 (feature
not supported)
Noise level estimator ramping scheme
InjCtrl (Control Register 3)
1
0 (feature
not supported)
Noise level ramping rate
NLInc (Noise Control)
5(hex)
C(hex)
Noise level scaling
Noise Scaling
16(hex)
74(hex)
Table 1 - Comparison of NLP Types
The NLPSel bit in Control Register 3 selects which NLP is used. A “1” will select the Advanced NLP, “0” selects the
original NLP. ( See page 29 - Control Register 3 bit description)
The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background
noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3
selects the ramping scheme.
The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the
Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher
value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid.
Zarlink Semiconductor Inc.
9
ZL50234
Data Sheet
The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will
scale the injected noise level down, conversely, raising the value will scale the comfort noise up. Due to differences
in the noise estimator operation, the Advanced NLP requires a different scaling value than the original NLP.
IMPORTANT NOTE: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant values.
Changing these values may result in undesirable comfort noise performance!
The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for
background noise. These features were not present in the original NLP. They can be disabled by setting the NLRun1
and NLRun2 bits in Control Register 3 to “0”.
1.5
Disable Tone Detector
The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every 450 ms (±25
ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector
will trigger.
The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between
0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone
Detector will trigger.
The ZL50234 has two Tone Detectors per channel (for a total of 16) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e. IRQ pin low). Refer to Figure 5 and to the Interrupts section.
Rin
Tone
Detector
Sin
Tone
Detector
ECA
Status reg
TD bit
Echo Canceller A
Rin
Tone
Detector
Sin
Tone
Detector
ECB
Status reg
TD bit
Echo Canceller B
Figure 5 - Disable Tone Detection
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e. IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per
channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.
In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the
Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors
internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by
setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the
interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a
given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state.
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Zarlink Semiconductor Inc.
ZL50234
Data Sheet
1.6
Instability Detector
In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability
problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this ringing
occur, the Instability Detector will activate and suppress the oscillations.
The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.
1.7
Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a
prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow
band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.
The NBSD will be active regardless of the Echo Canceller functional state. However the NBSD can be disabled by
setting the NBDis bit to “1” in Control Register 2.
1.8
Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC
component, the ZL50234 incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
1.9
Adjustable Level Pads
The ZL50234 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be
adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from
0 to -12 dB level, in 3 dB steps. Level values are set using the Gains register.
CAUTION: Gain adjustment can help interface the ZL50234 to a particular system in order to provide optimum echo
cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels
and slow convergence. Exercise great care when adjusting these values.
The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of
attenuation at Rin, and override the values in the Gains register.
1.10
ITU-T G.168 Compliance
The ZL50234 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes
(i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
The ZL50234 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50234
was classified as “carrier grade” echo canceller.
2.0
Device Configuration
The ZL50234 architecture contains 8 echo cancellers divided into 4 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in three
distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.
Zarlink Semiconductor Inc.
11
ZL50234
2.1
Data Sheet
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Sin
channel A
Sout
+
-
echo
path A
Adaptive
Filter (64ms)
channel A
Rout
Rin
PORT2
PORT1
ECA
channel B
+
-
echo
path B
Adaptive
Filter (64ms)
channel B
ECB
Figure 6 - Normal Device Configuration (64ms)
2.2
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64ms echo cancellation. See Figure 7. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Sout
+
Sin
echo
path
Adaptive
Filter (64ms)
Adaptive
Filter (64ms)
echo
path
Rout
PORT2
ECA
+
Rin
ECB
PORT1
Figure 7 - Back-to-Back Device Configuration (64ms)
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller
A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 4 groups of 2 cancellers that can be
configured into Back-to-Back.
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Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
2.3
Extended Delay configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds
echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and the second
timeslot normally associated with ECB contains quiet code.
Sin
channel A
+
Sout
echo
path A
Adaptive Filter
(128 ms)
channel A
Rout
Rin
PORT2
PORT1
ECA
Figure 8 - Extended Delay Configuration (128ms)
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 4 shows the 4 groups of 2 cancellers that can each be configured into 64ms or 128ms echo tail capacity.
3.0
Echo Canceller Functional States
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
3.1
Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet
code.
LINEAR
SIGN/
16 bits
MAGNITUDE
2’s
µ-Law
complement
A-Law
+Zero
(quiet code)
0000hex
80hex
CCITT (G.711)
µ-Law
A-Law
FFhex
D5hex
Table 2 - Quiet PCM Code Assignment
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
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ZL50234
3.2
Data Sheet
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 µs) in order to properly clear the filter.
3.3
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
3.4
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
4.0
ZL50234 Throughput Delay
The throughput delay of the ZL50234 varies according to the device configuration. For all device configurations, Rin
to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
5.0
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for
Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output
streams is for Rout PCM channels, and the other set is for Sout channels. See Figure 9 for channel allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set
of PCM Send and Receive channels, as illustrated in Figure 9.
5.1
Serial Data Interface Timing
The ZL50234 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL50234 automatically detects the
presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling
edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the
way into the bit cell (See Figure 12). In GCI format, every second rising edge of the C4i clock marks the bit boundary,
and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 13).
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Zarlink Semiconductor Inc.
ZL50234
Data Sheet
125 µsec
F0i
ST-BUS
31.25 µsec
F0i
GCI interface
Active Channels
Rin/Sin
Rout/Sout
0 1 2 3 4 5
Disabled Channels with Random Data
6 7
Note: Refer to Figure 12 and Figure 13 for timing details.
Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams
Base
Address +
MS
Byte
LS
Byte
-
00h
-
Echo Canceller A
Base
Address +
Echo Canceller B
MS
Byte
LS
Byte
Control Reg 1
-
20h
Control Reg 1
01h
Control Reg 2
-
21h
Control Reg 2
02h
Status Reg
-
22h
Status Reg
-
03h
Reserved
-
23h
Reserved
-
04h
Flat Delay Reg
-
24h
Flat Delay Reg
-
05h
Reserved
-
25h
Reserved
-
06h
Decay Step Size Reg
-
26h
Decay Step Size Reg
-
07h
Decay Step Number
-
27h
Decay Step Number
-
08h
Control Reg 3
-
28h
Control Reg 3
-
09h
Control Reg 4
-
29h
Control Reg 4
-
0Ah
Noise Scaling
-
2Ah
Noise Scaling
-
0Bh
Noise Control
-
2Bh
Noise Control
0Dh
0Ch
Rin Peak Detect Reg
2Dh
2Ch
Rin Peak Detect Reg
0Fh
0Eh
Sin Peak Detect Reg
2Fh
2Eh
Sin Peak Detect Reg
11h
10h
Error Peak Detect Reg
31h
30h
Error Peak Detect Reg
13h
12h
Reserved
33h
32h
Reserved
15h
14h
DTDT Reg
35h
34h
DTDT Reg
17h
16h
Reserved
37h
36h
Reserved
19h
18h
NLPTHR
39h
38h
NLPTHR
1Bh
1Ah
Step Size, MU
3Bh
3Ah
Step Size, MU
1Dh
1Ch
Gains
3Dh
3Ch
Gains
1Fh
1Eh
Reserved
3Fh
3Eh
Reserved
Table 3 - Memory Mapping of Per Channel Control and Status Registers
Zarlink Semiconductor Inc.
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ZL50234
6.0
Data Sheet
Memory Mapped Control and Status registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0hex to 0BF hex and interfaces to PCM
channel #5 on all serial PCM I/O streams.
As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers.
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
6.1
Normal Configuration
For a given group (group 0 to 3), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
Group
Channels
0
0, 1
1
2, 3
2
4, 5
3
6, 7
Table 4 - Group and Channel allocation
6.2
Extended Delay Configuration
For a given group (group 0 to 3), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries
quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B (Channel 5)
will carry quiet code.
6.3
Back-to-Back Configuration
For a given group (group 0 to 3), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries
quiet code. For example, group 3, Echo Canceller A (Channel 6) will be active and Echo Canceller B (Channel 7)
will carry quiet code.
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Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Group 0
Echo
Cancellers
Registers
Channel 0, ECA Ctrl/Stat Registers
0000h --> 001Fh
Channel 1, ECB Ctrl/Stat Registers
0020h --> 003Fh
Group 1
Echo
Cancellers
Registers
Channel 2, ECA Ctrl/Stat Registers
0040h --> 005Fh
Channel 3, ECB Ctrl/Stat Registers
0060h --> 007Fh
Group 2
Echo
Cancellers
Registers
Channel 4, ECA Ctrl/Stat Registers
0080h --> 009Fh
Channel 5, ECB Ctrl/Stat Registers
00A0h --> 00BFh
Group 3
Echo
Cancellers
Registers
Channel 6, ECA Ctrl/Stat Registers
01C0h --> 01DFh
Channel 7, ECB Ctrl/Stat Registers
01E0h --> 01FFh
Main Control Registers <7:0>
0400h --> 0407h
Interrupt FIFO Register
0410h
Test Register
0411h
Reserved Test Register
0412h ---> FFFFh
Figure 10 - Memory Mapping
6.4
Power Up Sequence
On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put the ZL50234 in power
down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 8
Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to lock.
C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 4 groups of echo
cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control Register.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00hex to Base Address+3Fhex,
to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00hex
to Base Address+3Fhex, for the specific application.
Zarlink Semiconductor Inc.
17
ZL50234
6.5
Data Sheet
Power management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
The typical power consumption can be calculated with the following equation:
PC = 9 * Nb_of_groups + 3.6, in mW
where 0 ≤ Nb_of_groups ≤ 4.
6.6
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that
the Echo cancellers are reset before any call progress tones are applied.
6.7
Interrupts
The ZL50234 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable
is detected and released.
Although the ZL50234 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when
a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status
Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address mapping
of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50234. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<3:0> allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.
7.0
JTAG Support
The ZL50234 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
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Zarlink Semiconductor Inc.
ZL50234
Data Sheet
7.1
Test Access Port (TAP)
The TAP provides access to many test functions of the ZL50234. It consists of four input pins and one output pin.
The following pins are found on the TAP.
•
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
•
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations.
The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1 when it is
not driven from an external source.
•
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent
section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to
VDD1 when it is not driven from an external source.
•
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction register
or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge
of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high
impedance state.
•
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.
7.2
Instruction Register
In accordance with the IEEE 1149.1 standard, the ZL50234 uses public instructions. The JTAG Interface contains a
3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
7.3
Test Data Registers
As specified in IEEE 1149.1, the ZL50234 JTAG Interface contains three test data registers:
•
•
•
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around
the boundary of the ZL50234 core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
Zarlink Semiconductor Inc.
19
ZL50234
8.0
Data Sheet
Register Description
Echo Canceller A (ECA): Control Register 1
Power-up 00hex
Bit 7
Reset
Reset
R/W Address: 00hex + Base Address
Bit 6
INJDis
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BBM
PAD
Bypass
AdpDis
0
ExtDI
Functional Description of Register Bits
When high, the power-up initialization is executed. This presets all register bits including
this bit and clears the Adaptive Filter coefficients.
INJDis
When high, the noise injection process is disabled. When low noise injection is enabled.
BBM
When high, the Back to Back configuration is enabled. When low, the Normal
configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at
the same time. Always set both BBM bits of the two echo cancellers (Control Register 1)
of the same group to the same logic value to avoid conflict.
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,
output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one
128ms echo canceller. When low, Echo Cancellers A and B of the same group operate
independently.
AdpDis
0
ExtDl
Echo Canceller B (ECB): Control Register 1
Power-up 02hex
Bit 7
Reset
Reset
Bit 6
INJDis
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BBM
PAD
Bypass
AdpDis
1
0
Functional Description of Register Bits
When high, the power-up initialization is executed which presets all register bits including
this bit and clears the Adaptive Filter coefficients.
INJDis
When high, the noise injection process is disabled. When low, noise injection is enabled.
BBM
When high, the Back to Back configuration is enabled. When low, the Normal
configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at
the same time. Always set both BBM bits of the two echo cancellers (Control Register 1)
of the same group to the same logic value to avoid conflict.
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,
output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
AdpDis
1
0
20
R/W Address: 20hex + Base Address
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Power-up
00hex
Bit 7
TDis
Bit 6
PHDis
Bit 5
NLPDis
ECA: Control Register 2
R/W Address:
01hex + Base Address
ECB: Control Register 2
R/W Address:
21hex + Base Address
Bit 4
AutoTD
Bit 3
NBDis
Bit 2
HPFDis
Bit 1
MuteS
Bit 0
MuteR
Functional Description of Register Bits
TDis
PHDis
When high, tone detection is disabled. When low, tone detection is enabled. When both
Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled
entirely and are put into Power Down mode.
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless
of the presence/absence of periodic phase reversals. When low, the tone detectors will
trigger only upon the presence of a 2100 Hz tone with periodic phase reversals.
NLPDis
When high, the non-linear processor is disabled. When low, the non-linear processors
function normally. Useful for G.165 conformance testing.
AutoTD
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect
the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of
the 2100 Hz tone detectors.
NBDis
When high, the narrow-band detector is disabled. When low, the narrow-band detector is
enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input
signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
HPFDis
MuteS
MuteR
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350ns and no more than 20us.
Zarlink Semiconductor Inc.
21
ZL50234
Data Sheet
Power-up
00hex
Bit 7
Reserve
Bit 6
TD
ECA: Status Register
R/W Address:
02hex + Base Address
ECB: Status Register
R/W Address:
22hex + Base Address
Bit 5
Bit 4
Bit 3
Bit 2
DTDet
Reserve
Reserve
Reserve
Functional Description of Register Bits
Bit 0
NB
Reserve
TD
DTDet
Logic high indicates the presence of a double-talk condition.
Reserve
Reserved bit.
Reserve
Reserve
TDG
Reserved bit.
Reserved bit.
Tone detection status bit gated with the AutoTD bit. (Control Register 2)
Logic high indicates that AutoTD has been enabled and the tone detector has detected
the presence of a 2100Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
NB
Reserved bit.
Logic high indicates the presence of a 2100Hz tone.
Power-up
00hex
Bit 7
FD7
Bit 6
FD6
Power-up
00hex
Bit 7
NS7
Bit 6
NS6
Power-up
00hex
Bit 7
0
Bit 6
0
Bit 5
FD5
ECA: Flat Delay Register (FD)
R/W Address:
04hex + Base Address
ECB: Flat Delay Register (FD)
R/W Address:
24hex + Base Address
Bit 4
FD4
Bit 3
FD3
Bit 2
FD2
Bit 1
FD1
Bit 0
FD0
ECA: Decay Step Size Register (NS)
R/W Address:
07hex + Base Address
ECB: Decay Step Size Register (NS)
R/W Address:
27hex+ Base Address
Bit 5
NS5
Bit 4
NS4
Bit 3
NS3
Bit 2
NS2
Bit 1
NS1
Bit 0
NS0
ECA: Decay Step Size Control Register (NS)
R/W Address:
06hex + Base Address
ECB: Decay Step Size Control Register (NS)
R/W Address:
26hex + Base Address
Bit 5
0
Bit 4
0
Bit 3
0
Note: Bits marked with “0” are reserved bits and should be written “0”
22
Bit 1
TDG
Zarlink Semiconductor Inc.
Bit 2
SSC2
Bit 1
SSC1
Bit 0
SSC0
ZL50234
Data Sheet
Amplitude of MU
FIR Filter Length (512 or 1024 taps)
1.0
Step Size (SS)
Flat Delay (FD7-0)
2-16
Time
Number of Steps (NS7-0)
Figure 11 - The MU Profile
Functional Description of Register Bits
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS
adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the
performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the
echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo
impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby
improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one
tap is equivalent to 125µs (64ms/512 taps).
FD7-0
Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16 ). The
delay is defined as FD 7-0 x 8 taps. For example; If FD7-0 = 5, then MU=2-16 for the first 40 taps of the
echo canceller FIR filter. The valid range of FD 7-0 is: 0 ≤ FD7-0 ≤ 64 in normal mode and 0 ≤ FD7-0 ≤ 128
in extended-delay mode. The default value of FD 7-0 is zero.
SSC2-0
Decay Step Size Control: This register controls the step size (SS) to be used during the exponential
decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR
filter, where SS = 4 x2 SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64
taps of the FIR filter. The default value of SSC 2-0 is 04 hex.
NS7-0
Decay Step Number: This register defines the number of steps to be used for the decay of MU where
each step has a period of SS taps (see SSC 2-0). The start of the exponential decay is defined as: Filter
Length (512 or 1024) - [Decay Step Number (NS 7-0) x Step Size (SS)] where SS = 4 x2SSC2-0 .
For example; If NS 7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS 7-0 x SS] =
512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps.
Zarlink Semiconductor Inc.
23
ZL50234
Data Sheet
Power-up
FB hex
Bit 7
NLRun2
NLRun2
InjCtrl
NLRun1
R/W Address:
08hex + Base Address
ECB: Control Register 3
R/W Address:
28hex + Base Address
Bit 6
InjCtrl
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLRun1
RingClr
Reserve
PathClr
PathDet
NLPSel
Functional Description of Register Bits
When high, the comfort noise level estimator actively rejects double-talk as being background
noise. When low, the noise level estimator makes no such distinction.
Selects which noise ramping scheme is used. See Table below.
When high, the comfort noise level estimator actively rejects uncancelled echo as being
background noise. When low, the noise level estimator makes no such distinction.
RingClr
When high, the instability detector is activated. When low, the instability detector is disabled.
Reserve
PathClr
Reserved bit. Must always be set to one for normal operation.
When high, the current echo channel estimate will be cleared and the echo canceller will enter
fast convergence mode upon detection of a path change. When low, the echo canceller will keep
the current path estimate but revert to fast convergence mode upon detection of a path change.
Note: this bit is ignored if PathDet is low.
When high, the path change detector is activated. When low, the path change detector is
disabled.
When high, the Advanced NLP is selected. When low, the original NLP is selected. See Table 1
on page 9
PathDet
NLPSel
24
ECA: Control Register 3
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Power-up
54hex
Bit 7
0
0
SupDec
0
Slow
R/W Address:
09hex + Base Address
ECB: Control Register 4
R/W Address:
29hex + Base Address
Bit 6
SD2
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SD1
SD0
0
Slow2
Slow1
Slow0
Functional Description of Register Bits
Must be set to zero.
These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast
convergence state following a path change, Reset or Bypass operation. A value of zero will keep
the echo canceller in fast convergence indefinitely.
Must be set to zero.
Slow convergence mode speed adjustment.(Bits Slow2, Slow1,Slow0)
For Slow = 1, 2, ..., 7, slow convergence speed is reduced by a factor of 2Slow as compared to
normal adaptation.
Flow Slow = 0, no adaptation occurs during slow convergence.
Power-up
16hex
Bit 7
NS7
ECA: Control Register 4
Bit 6
NS6
ECA: Noise Scaling (NS)
R/W Address:
0A hex + Base Address
ECB: Noise Scaling (NS)
R/W Address:
2A hex + Base Address
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NS4
NS3
NS2
NS1
NS0
Functional Description of Register Bits
This register is used to scale the comfort noise up or down. Larger values will increase the relative level of
comfort noise. The default value of 16hex will provide G.168 compliance with the Advanced NLP. A value of
74hex is recommended if the original NLP is used.
Power-up
45 hex
Bit 7
Reserve
Reserve
NLInc
Bit 5
NS5
ECA: Noise Control
R/W Address:
0Bhex + Base Address
ECB: Noise Control
R/W Address:
2Bhex + Base Address
Bit 6
Reserve
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserve
Reserve
NLInc3
NLInc2
NLInc1
NLInc0
Functional Description of Register Bits
Reserved bits. Must be set to 4 hex for normal operation.
Noise level estimator ramping rate. When InjCtrl = 1, a lower value will give faster ramping.
When InjCtrl = 0, a higher value will give faster ramping. The default value of 5 hex will provide
G.168 compliance with InjCtrl = 1. A value of C hex is recommended if InjCtrl = 0.
Zarlink Semiconductor Inc.
25
ZL50234
Data Sheet
Power-up
N/A
Bit 7
RP15
Bit 6
RP14
Power-up
N/A
ECA: Rin Peak Detect Register 2 (RP)
R/W Address:
0Dhex + Base Address
ECB: Rin Peak Detect Register 2 (RP)
R/W Address:
2Dhex + Base Address
Bit 5
RP13
Bit 4
RP12
Bit 3
RP11
Bit 2
RP10
ECA: Rin Peak Detect Register 1 (RP)
Bit 6
RP6
Bit 0
RP8
R/W Address:
0Chex + Base Address
R/W Address:
2Chex + Base Address
Bit 1
Bit 0
RP1
RP0
ECB: Rin Peak Detect Register 1 (RP)
Bit 7
RP7
Bit 1
RP9
Bit 4
Bit 3
Bit 2
RP4
RP3
RP2
Functional Description of Register Bits
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information
is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
Power-up
N/A
Bit 7
SP15
Bit 6
SP14
Power-up
N/A
Bit 5
RP5
ECA: Sin Peak Detect Register 2 (SP)
R/W Address:
0Fhex + Base Address
ECB: Sin Peak Detect Register 2 (SP)
R/W Address:
2Fhex + Base Address
Bit 5
SP13
Bit 4
SP12
Bit 3
SP11
Bit 2
SP10
ECA: Sin Peak Detect Register 1 (SP)
ECB: Sin Peak Detect Register 1 (SP)
Bit 7
SP7
Bit 5
SP5
Bit 0
SP8
R/W Address:
0E hex + Base Address
R/W Address:
2E hex + Base Address
Bit 1
Bit 0
SP1
SP0
Bit 4
Bit 3
Bit 2
SP4
SP3
SP2
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high
byte is in Register 2 and the low byte is in Register 1.
26
Bit 6
SP6
Bit 1
SP9
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Power-up
N/A
Bit 7
EP15
Bit 6
EP14
Power-up
N/A
Bit 7
EP7
Bit 6
EP6
ECA: Error Peak Detect Register 2 (EP)
R/W Address:
11hex + Base Address
ECB: Error Peak Detect Register 2 (EP)
R/W Address:
31hex + Base Address
Bit 5
EP13
Bit 4
EP12
Bit 3
EP11
Bit 2
EP10
Bit 1
EP9
Bit 0
EP8
ECA: Error Peak Detect Register 1 (EP)
R/W Address:
10hex + Base Address
ECB: Error Peak Detect Register 1 (EP)
R/W Address:
30hex + Base Address
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP4
EP3
EP2
EP1
EP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit
2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in
Register 2 and the low byte is in Register 1.
Power-up
48hex
Bit 7
DTDT15
Bit 6
DTDT14
Power-up
00hex
Bit 7
DTDT7
Bit 6
DTDT6
Bit 5
EP5
ECA: Double-Talk Detection Threshold Register 2
R/W Address:
15hex + Base Address
ECB: Double-Talk Detection Threshold Register 2
R/W Address:
35hex + Base Address
Bit 5
DTDT13
Bit 4
DTDT12
Bit 3
DTDT11
Bit 2
DTDT10
ECA: Double-Talk Detection Threshold Register 1
ECB: Double-Talk Detection Threshold Register 1
Bit 1
DTDT9
Bit 0
DTDT8
R/W Address:
14hex + Base Address
R/W Address:
34hex + Base Address
Bit 5
DTDT5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTDT4
DTDT3
DTDT2
DTDT1
DTDT0
Functional Description of Register Bits
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s
complement linear value defaults to 4800hex= 0.5625 or -5 dB. The maximum value is 7FFF hex = 0.9999 or 0
dB. The high byte is in Register 2 and the low byte is in Register 1.
Zarlink Semiconductor Inc.
27
ZL50234
Data Sheet
Power-up
0Chex
Bit 7
NLP15
Bit 6
NLP14
Power-up
E0hex
Bit 7
NLP7
Bit 6
NLP6
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
19hex + Base Address
ECB: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
39hex + Base Address
Bit 5
NLP13
Bit 4
NLP12
Bit 3
NLP11
Bit 2
NLP10
Bit 1
NLP9
Bit 0
NLP8
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
R/W Address:
18hex + Base Address
ECB: Non-Linear Processor Threshold Register 1
(NLPTHR)
R/W Address:
38hex + Base Address
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLP4
NLP3
NLP2
NLP1
NLP0
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit
2’s complement linear value defaults to 0CE0hex = 0.1 or -20.0dB. The maximum value is 7FFFhex = 0.9999 or 0
dB. The high byte is in Register 2 and the low byte is in Register 1.
Power-up
40hex
Bit 7
MU15
Bit 6
MU14
Power-up
00hex
Bit 7
MU7
ECA: Adaptation Step Size Register 2 (MU)
R/W Address:
1B hex + Base Address
ECB: Adaptation Step Size Register 2 (MU)
R/W Address:
3B hex + Base Address
Bit 5
MU13
Bit 4
MU12
Bit 3
MU11
Bit 2
MU10
Bit 1
MU9
Bit 0
MU8
ECA: Adaptation Step Size Register 1 (MU)
R/W Address:
1A hex + Base Address
ECB: Adaptation Step Size Register 1 (MU)
R/W Address:
3A hex + Base Address
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU4
MU3
MU2
MU1
MU0
Functional Description of Register Bits
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to
4000hex = 1.0 The maximum value is 7FFFhex or 1.9999 decimal. The high byte is in Register 2 and the low byte
is in Register 1.
28
Bit 6
MU6
Bit 5
NLP5
Bit 5
MU5
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Power-up
44hex
Bit 7
0
Bit 6
Rin2
Bit 5
Rin1
Power-up
44hex
Bit 7
0
R/W Address:
1Dhex + Base Address
ECB: Gains Register 2
R/W Address:
3Dhex + Base Address
Bit 4
Rin0
Bit 3
0
Bit 2
Rout2
Bit 1
Rout1
Bit 0
Rout0
ECA: Gains Register 1
R/W Address:
1Chex + Base Address
ECB: Gains Register 1
R/W Address:
3Chex + Base Address
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sin0
0
Sout2
Sout1
Sout0
Functional Description of Register Bits
This register is used to select gain values on RIN, ROUT, SIN and SOUT. Gains has the following structure:
RIN ROUT SIN SOUT
Gains = 0xxx 0xxx 0xxx 0xxx
= 0100 0100 0100 0100 (4444 hex) default
Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above), and
has three gain bits. The following table indicates how these gain bits are used:
Bit2
1
0
0
0
0
Bit1 Bit0
0 0
1 1
1 0
0 1
0 0
Bit 6
Sin2
ECA: Gains Register 2
Bit 5
Sin1
Gain Level
0 dB (default)
-3 dB
-6 dB
-9 dB
-12 dB
Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and
will override the settings in Gains.
Zarlink Semiconductor Inc.
29
ZL50234
Data Sheet
Main Control Register 0 (EC Group 0)
Power-up 00hex
Bit 7
WR_all
WR_all
ODE
MIRQ
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MIRQ
MTDBI
MTDAI
Format
Law
PWUP
Functional Description of Register Bits
Write all control bit: When high, Group 0-3 Echo Cancellers Registers are mapped into 0000hex to
0003Fhex which is Group 0 address mapping. Useful to initialize the 4 Groups of Echo Cancellers
as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main Control
Register 0 has the WR_all bit
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE bit
and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or
the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main
Control Register 0 has the ODE bit.
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The
Tone Detectors operate as specified in their Echo Canceller B, Control Register 2.
When low, the Tone Detectors Interrupts are active.
Note: Only the Main Control Register 0 has the MIRQ bit.
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept signmagnitude PCM code.
Law
PWUP
30
R/W Address: 400hex
Bit 6
ODE
A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, accept µ-Law companded
PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo canceller A and B execute their initialization routine which presets their registers, Base
Address+00hex to Base Address+3Fhex, to default power up value and clears the Adaptive Filter
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their
specific application.
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Bit 7
Unused
Unused
MTDBI
MTDAI
Format
Law
PWUP
Main Control Register 1 (EC Group 1)
R/W Address: 401hex
Main Control Register 2 (EC Group 2)
R/W Address: 402hex
Main Control Register 3 (EC Group 3)
R/W Address: 403hex
Power-up 00hex
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
MTDBI
MTDAI
Format
Law
PWUP
Functional Description of Register Bits
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code .
A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select µ-Law companded
PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00hex to Base Address+3Fhex, to default Reset Value and clears the Adaptive Filter
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
Zarlink Semiconductor Inc.
31
ZL50234
Data Sheet
Interrupt FIFO Register
Power-up 00hex
Bit 7
IRQ
IRQ
Unused
Unused
I<4:0>
32
R/W Address: 410hex
Bit 6
Unused
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
I4
I3
I2
I1
I0
Functional Description of Register Bits
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register
is read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bit.
Unused bit.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
1
I/O Supply Voltage (V DD1)
VDD_IO
-0.5
5.0
V
2
Core Supply Voltage (VDD2)
VDD_CORE
-0.5
2.5
V
3
Input Voltage
VI3
VSS - 0.5
VDD1+0.5
V
4
Input Voltage on any 5V Tolerant I/O pins
VI5
VSS - 0.3
7.0
V
5
Continuous Current at digital outputs
Io
20
mA
6
Package power dissipation
PD
2
W
150
°C
7
Storage temperature
TS
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Recommended Operating Conditions
- Voltages are with respect to ground (Vss) unless otherwise stated
Characteristics
1
Operating Temperature
Sym
Min
TOP
-40
Typ‡
Max
Units
+85
°C
2
I/O Supply Voltage (VDD_IO)
VDD1
3.0
3.3
3.6
V
3
Core Supply Voltage (VDD_CORE)
VDD2
1.6
1.8
2.0
V
4
Input High Voltage on 3.3V tolerant I/O
VIH3
0.7VDD1
VDD1
V
5
Input High Voltage on 5V tolerant I/O pins
VIH5
0.7VDD1
5.5
V
6
Input Low Voltage
VIL
0.3VDD1
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Static Supply Current
Sym
IDD_IO (VDD1 = 3.3V)
IDD_CORE (VDD2 = 1.8V)
2
Power Consumption
Input High Voltage
VIH
3
4
5
6
7
8
9
10
Input Low Voltage
Input Leakage
Input Leakage on Pullup
Input Leakage on Pulldown
Input Pin Capacitance
O
U
T
P
U
T
S
Typ‡
Max
Units
Test Conditions
µA
RESET = 0
mA
All 8 channels active
22
mA
All 8 channels active
56
mW
All 8 channels active
ICC
1
I
N
P
U
T
S
Min
250
IDD_IO
5
IDD_CORE
PC
0.7VDD1
V
VIL
0.3VDD1
V
IIH/IIL
ILU
ILD
10
-55
65
µA
µA
µA
10
pF
-30
30
CI
0.8VDD1
VIN=VSS to VDD1or 5.5V
VIN=VSS
VIN=VDD1
See Note 1
Output High Voltage
VOH
V
IOH = 12 mA
Output Low Voltage
VOL
0.4
V
IOL = 12 mA
High Impedance Leakage
IOZ
10
µA
VIN=VSS to 5.5V
Output Pin Capacitance
CO
10
pF
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V DD1 =3.3V and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
Zarlink Semiconductor Inc.
33
ZL50234
Data Sheet
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
- Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym
Level
Units
1
CMOS Threshold
VTT
0.5VDD1
V
2
CMOS Rise/Fall Threshold Voltage High
VHM
0.7VDD1
V
3
CMOS Rise/Fall Threshold Voltage Low
VLM
0.3VDD1
V
Conditions
† Characteristics are over recommended operating conditions unless otherwise stated
AC Electrical Characteristics† - Frame Pulse and C4i
1
Characteristic
Sym
Min
Frame pulse width (ST-BUS, GCI)
tFPW
20
Typ‡
Max
Units
2*
ns
Notes
tCP-20
2
Frame Pulse Setup time before
C4i falling (ST-BUS or GCI)
tFPS
10
122
150
ns
3
Frame Pulse Hold Time from C4i
falling (ST-BUS or GCI)
tFPH
10
122
150
ns
4
C4i Period
tCP
190
244
300
ns
5
C4i Pulse Width High
tCH
85
150
ns
6
C4i Pulse Width Low
tCL
85
150
ns
7
C4i Rise/Fall Time
tr, tf
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes
Characteristic
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Rin/Sin Set-up Time
tSIS
10
ns
2
Rin/Sin Hold Time
tSIH
10
ns
3
Rout/Sout Delay
- Active to Active
tSOD
60
ns
CL=150pF
4
Output Data Enable (ODE)
Delay
tODE
30
ns
CL=150pF, RL=1K
See Note 1
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing
* Note1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated.
1
2
3
Characteristic
Sym
Min
Typ‡
Max
Units
Master Clock Frequency,
- Fsel = 0
- Fsel = 1
fMCF0
fMCF1
19.0
9.5
20.0
10.0
21.0
10.5
MHz
MHz
Master Clock Low
tMCL
20
ns
Master Clock High
tMCH
20
ns
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing
34
Zarlink Semiconductor Inc.
Notes
ZL50234
Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym
Min
Typ‡
Max
Units
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
0
ns
3
Address setup from DS falling
tADS
0
ns
4
CS hold after DS rising
tCSH
0
ns
5
R/W hold after DS rising
tRWH
0
ns
6
Address hold after DS rising
tADH
0
ns
7
Data delay on read
tDDR
8
Data hold on read
tDHR
3
9
Data setup on write
tDSW
0
ns
10
Data hold on write
tDHW
0
ns
11
Acknowledgment delay
tAKD
12
Acknowledgment hold time
tAKH
13
IRQ delay
tIRD
79
ns
15
ns
80
ns
0
8
ns
20
65
ns
Test Conditions
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V DD1 = 3.3V and for design aid only: not guaranteed and not subject to production testing
tFPW
F0i
VTT
tFPS
tCP
tFPH
tCH
tCL
tr
VHM
VTT
VLM
C4i
tSOD
Rout/Sout
tf
Bit 7, Channel 0
tSIS
Rin/Sin
Bit 6, Channel 0
Bit 5, Channel 0
VTT
tSIH
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
VTT
Figure 12 - ST-BUS Timing at 2.048 Mb/s
Zarlink Semiconductor Inc.
35
ZL50234
Data Sheet
tFPW
F0i
VTT
tFPS
tCP
tFPH
tCH
tCL
tr
VHM
VTT
VLM
C4i
tSOD
Sout/Rout
tf
Bit 0, Channel 0
tSIS
Sin/Rin
Bit 1, Channel 0
Bit 2, Channel 0
VTT
tSIH
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
VTT
Figure 13 - GCI Interface Timing at 2.048 Mb/s
VTT
ODE
tODE
Sout/Rout
HiZ
tODE
Valid Data
HiZ
VTT
Figure 14 - Output Driver Enable (ODE)
tMCH
VTT
MCLK
tMCL
Figure 15 - Master Clock
36
Zarlink Semiconductor Inc.
ZL50234
Data Sheet
VTT
DS
tCSS
tCSH
VTT
CS
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A10
tDDR
tDHR
VTT
VALID READ DATA
D0-D7
READ
tDSW
tDHW
VTT
VALID WRITE DATA
D0-D7
WRITE
tAKD
tAKH
VTT
DTA
tIRD
VTT
IRQ
Figure 16 - Motorola Non-Multiplexed Bus Timing
Zarlink Semiconductor Inc.
37
ZL50234
38
Data Sheet
Zarlink Semiconductor Inc.
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