Features Application Description n A/D conversion with 6-bit resolution n Time base programmable from 50ns to 3.27 ms (at a clock frequency of 20 MHz) n Trigger Modes: Auto, Internal +/-, External +/n 5 discrete trigger levels n Internal SRAM for 128 values n SRAM bypass mode n Shift of base line by adjustable offset n Supply voltage 5 Volts n Bidirectional µC interface n Power-down for analog part n PLCC44 package The Graphic Signal Monitor IC was developed for visualization of the time behavior of electrical signals. Interaction with an external µC makes it possible to achieve the functionality of a one-channel digital storage oscilloscope with additional digital voltmeter function. After the parameters of time basis, trigger level and trigger mode have been loaded into the control register, the recording starts as soon as the trigger condition occurs. This procedure ends when 128 times 6 bit data have been written from the flash A/D converter into the internal SRAM. The small dimensions as well as a minimum of external wiring facilitate both the application in miniaturized measuring devices for service and test area, and placement near the front panels in control panels and switch cabinets. Afterwards, an externally connected microcontroller can read the data and formate it for an LC display or for transmission via an interface. Block Diagram SRAM ADC A_IN Z_IN A + - uC Interface D MUX REFT REF REFB PARITY DIO_0..7 OUT_10 OUT_100 SEL_AC SEL_DC STATUS TRIGGER TIME BASE CONTROL LD-DISPL EN_REC EXT_PWR BP_RAM T_IN CPUCLK WR_TEST TRIG_OUT TRIG_IN SHIFT REG DISP_DATA DISP_CLK 1 Functional Description The input amplifier serves for impedance matching and amplifies the input signal. In order to allow also bipolar input signals to be processed even if there is only one supply voltage, a level shift takes place in the input amplifier. Using an external potentiometer, such shift can be varied into a base line shift. The measuring range can be extended by connection of an external voltage divider. An AC input can be implemented by means of an additional external capacitor. Two special inputs of the integrated circuit can be connected with the external voltage divider; they supply a low current during the measurement pauses. The resulting voltage at the pins indicates the selected measurement range. Two more pins have been provided for detection of the selected signal coupling type. The external AC/DC switch is to tie the pins to ground. The status information about measurement range and coupling type, multiplexed with the measured data, is provided for interpretation at the bidirectional interface. The measured signal is digitized in an analog-to-digital converter operating according to the flash principle. When the measurement is activated, it converts the input signal into a 6-bit digital word at a fixed conversion rate of 20 MHz. The 63 comparators of the flash ADC consist of a differential stage with subsequent latch. For storaging the measured data, the integrated circuit contains an SRAM which is 6 bits wide and 128 values deep. The SRAM Write signal is generated by the Time Base unit by means of a programmable shift register. The time base is freely selectable within the range from 0 16 2 to 2 times the clock period. Connection with a 20-MHz quartz will result in a range from 50ns to 3,27ms. The RAM bypass mode creates more possibilities of application; the values are output directly to the bidirectional interface, not into the RAM. The measurement can be initiated by an external signal or, controlled by the trigger logic, Pin Configuration 39 38 37 36 35 34 33 32 31 30 29 40 41 42 43 44 1 2 3 4 5 6 28 27 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 2 depending on the level of the input signal, in an automatic or edge- and level triggered mode. For this purpose, there is a comparator, the reference level of which can be selected in five discrete stages. The comparator has been provided with a hysteresis for noise suppression. The Control unit coordinates the circuit functions, such as the data exchange via the interface. Measured data and status information are output in parallel. The loading of the time base, trigger level, trigger mode parameters into registers, which is uncritical with regard to time, is done serially via 2 pins of the bidirectional interface. The analog part of the circuit is activated only during the short data recording time, which significantly reduces the total power consumption. For special applications, e. g. for control of an LCD module, a shift register has been implemented. Loading of information into the shift register is parallel, while the output is serial via two pins. Pin Description Pin Name IN/OU T Power Supply Connections 29 VDD 38 VDDA Description Pin Pos. supply voltage, digital Pos. supply voltage, analog Digital Outputs 8 PD 31 CPUCLK O (ub) O 17 3 44 Neg. supply voltage, digital Neg. supply voltage, analog Signal ground 30 36 32 O O O VSS VSSA AGND Name IN/OUT Description WR_TEST TRIG_OUT DISP_CLK Analog Inputs 43 A_IN 42 T_IN 41 Z_IN I I I Analog signal input Trigger signal input Zero-level input 33 DISP_DATA O Data I/Os 20 PARITY bid 28...21 DIO_0...7 bid Digital Inputs 1 OUT_10 2 OUT_100 I (puc) I (puc) Status 1 (10V area switch) Status 2 (100V area switch) Analog Outputs 6 REFT 5 REFB 10 9 34 35 19 SEL_AC SEL_DC N_MODE TRIG_IN EN_REC I (pu) I (pu) I (pu) I I Status 3 (AC operation) Status 4 (DC operation) Control 1 (operating mode) Trigger input Enable Record 4 VED O External Components 12 XOUT 13 XIN 40 CF 18 LD_DISPL I Load Display 39 CZ 16 EXT_PWR I Control 2 (external power) 7 CW 15 BP_RAM I Bypass Ram Mode Test Pins 11 TRESULT 14 TEST pu = Internal Pull-Up ub = Unbuffered output puc = Internal Pull-Up Controlled O O O I (pd) Analog power-down 5 MHz clock (for processor) RAM Write mode active Trigger output 1.25 MHz clock (Display data clock) Display data serial Bid. data pin (parity) Bidirectional data interface Reference voltage (top) Reference voltage (bottom) Internal base potential Crystal output Qrystal input Follower stage, Connection to trim-C Amplifier , Connection to trim-C A/D converter power bypass capacitor Test mode output Test mode input pd= Internal Pull-Down Characteristics (Selection) Maximum Ratings General Supply voltage (VDDA=VDD) Oscillator frequency Operating temperature Current drain Digital Input H-level Input L-level Output H-level (2mA, pin32: 8mA)) Output L-level (-2mA, pin32 -8mA) Analog Part Input voltage Input resistance Input capacitance A/D Converter Resolution Differential non-linearity Integral non-linearity Symbol Min Typ Max Unit VDD fq T IS 4.75 5.0 5.25 20 70 100 V MHz o C mA VIH VIL VOH VOL VDD-0.8 Vis,Vit Ris,Rid Cis,Cit -0.5 100 0 60 0.8 2.4 0.4 radc DNL INL 3 +0.5 V V V V 5 V MΩ pF 0.8 1 Bit LSB LSB 6 Notes for Application Before starting the measurement, the parameters of time base, trigger level and trigger mode are to be serially loaded to DIO(0) (clock) and DIO(1) (data) by the microcontroller. The recording of measured values is prepared by activation of EN_REC. Then, the IC outputs the status of the 4 pins for measurement range and AC/DC coupling to DIO(2 to 5) (parallel), until a High pulse is applied to the LD_DISPL pin. The integrated circuit is now ready to record measured values, which happens as soon as the trigger condition occurs. Subsequently, the microcontroller, by clocking of LD_DISPL, reads out the contents of the SRAM in bit-parallel and byte-serial form at DIO(0 to 5). The measured data and status information taken over are prepared in the external microcontroller in a way that allows to indicate them on an external LC display or to transfer them to a computer, for instance, formatted according to the RS232-Protocol. For digital voltmeter functions, the microprocessor can calculate the average value of all 128 recorded measured values, and, by multiplying them by 0.7, it can determine the approximate effective value. This value can be shown on the display as well. A shift register is available in the integrated circuit for special applications. In the application shown below, it controls an LCD module of 16 x 32 pixels. The microcontroller loads the data available in parallel at DIO (0 to 7) as well as the parity information into the register. The process of loading is controlled by means of the signals EN_REC and LD_DISPL. A start and stop bit are added, then the output takes place at DISP_CLK (data) and DISP_DATA (data). When using the ZM407, it is absolutely necessary to ensure synchronous operation of the system. Therefore, a 5-MHz system clock for an external microcontroller is provided at the CPUCLK pin. Multi-channel recording is possible by cascading of several SCOPE ICs. In this case, one TRIG_OUT output will control several TRIG_IN inputs. Application Circuit SCOPE IC Y-POSITION uController REFT DIO1..7 Z_IN PARITY REFB EN_REC A_IN LD_DISPL RS232 TX RX IN CPUCLK OUT_10 AC/DC OUT_100 DISP_DATA 10V/100V DISP_CLK SEL_AC SEL_DC TRG TRIG_OUT T_IN TRIG_IN 4 LC Display