PSD3XX ZPSD3XX ZPSD3XXV PSD3XXR ZPSD3XXR ZPSD3XXRV Low Cost Field Programmable Microcontroller Peripherals FEATURES SUMMARY ■ Single Supply Voltage: Figure 1. Packages – 5 V±10% for PSD3xx, ZPSD3xx, PSD3xxR, ZPSD3xxR – 2.7 to 5.5 V for ZPSD3xxV, ZPSD3xxRV ■ Up to 1 Mbit of EPROM ■ Up to 16 Kbit SRAM ■ Input Latches ■ Programmable I/O ports ■ Page Logic ■ Programmable Security PLDCC44 (J) CLDCC44 (L) PQFP44 (M) TQFP44 (U) January 2002 1/3 PSD3XX Family PSD3XX ZPSD3XX ZPSD3XXV PSD3XXR ZPSD3XXR ZPSD3XXRV Low Cost Microcontroller Peripherals Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 i Introduction ...........................................................................................................................................................1 Notation ................................................................................................................................................................2 Key Features ........................................................................................................................................................4 PSD3XX Family Feature Summary ......................................................................................................................5 Partial Listing of Microcontrollers Supported ........................................................................................................6 Applications ..........................................................................................................................................................6 ZPSD Background ................................................................................................................................................6 7.1 Integrated Power ManagementTM Operation .............................................................................................7 Operating Modes (MCU Configurations) ............................................................................................................10 Programmable Address Decoder (PAD).............................................................................................................12 I/O Port Functions ...............................................................................................................................................15 10.1 CSIOPORT Registers..............................................................................................................................15 10.2 Port A (PA0-PA7).....................................................................................................................................16 10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode................................................................16 10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode ........................................................17 10.3 Port B (PB0-PB7).....................................................................................................................................18 10.3.1 Port B (PA0-PA7) in Multiplexed Address/Data Mode................................................................18 10.3.2 Port B (PA0-PA7) in Non-Multiplexed Address/Data Mode ........................................................19 10.4 Port C (PC0-PC2) ....................................................................................................................................20 10.5 ALE/AS Input Pin .....................................................................................................................................20 PSD Memory ......................................................................................................................................................21 11.1 EPROM....................................................................................................................................................21 11.2 SRAM (Optional)......................................................................................................................................21 11.3 Page Register (Optional) .........................................................................................................................21 11.4 Programming and Erasure.......................................................................................................................21 Control Signals ...................................................................................................................................................22 12.1 ALE or AS ................................................................................................................................................22 12.2 WR or R/W...............................................................................................................................................22 12.3 RD/E/DS (DS option not available on 3X1 devices) ................................................................................22 12.4 PSEN or PSEN ........................................................................................................................................22 12.5 A19/CSI ...................................................................................................................................................23 12.6 Reset Input ..............................................................................................................................................24 Program/Data Space and the 8031 ....................................................................................................................26 Systems Applications..........................................................................................................................................27 Security Mode .....................................................................................................................................................30 Power Management............................................................................................................................................30 16.1 CSI Input..................................................................................................................................................30 16.2 CMiser Bit ................................................................................................................................................30 16.3 Turbo Bit (ZPSD Only).............................................................................................................................31 16.4 Number of Product Terms in the PAD Logic............................................................................................31 16.5 Composite Frequency of the Input Signals to the PAD Logic..................................................................32 16.6 Loading on I/O Pins .................................................................................................................................33 Calculating Power ...............................................................................................................................................34 PSD3XX Family PSD3XX ZPSD3XX ZPSD3XXV PSD3XXR ZPSD3XXR ZPSD3XXRV Low Cost Microcontroller Peripherals Table of Contents (cont.) 18 19 20 21 22 23 Specifications......................................................................................................................................................37 18.1 Absolute Maximum Ratings .....................................................................................................................37 18.2 Operating Range .....................................................................................................................................37 18.3 Recommended Operating Conditions......................................................................................................37 18.4 Pin Capacitance.......................................................................................................................................37 18.5 AC/DC Characteristics – PSD3XX/ZPSD3XX (All 5 V devices) ..............................................................38 18.6 AC/DC Characteristics – PSD3XXV (3 V devices only)...........................................................................39 18.7 Timing Parameters – PSD3XX/ZPSD3XX (All 5 V devices)....................................................................40 18.8 Timing Parameters – ZPSD3XXV (3 V devices only) ..............................................................................42 18.9 Timing Diagrams for PSD3XX Parts.......................................................................................................44 18.10 AC Testing ...............................................................................................................................................65 Pin Assignments .................................................................................................................................................66 Package Information ...........................................................................................................................................67 Package Drawings ..............................................................................................................................................68 PSD3XX Product Ordering Information ..............................................................................................................72 22.1 PSD3XX Selector Guide..........................................................................................................................72 22.2 Part Number Construction .......................................................................................................................73 22.3 Ordering Information................................................................................................................................73 Data Sheet Revision History ...............................................................................................................................80 ii Programmable Peripheral PSD3XX Family Field-Programmable Microcontroller Peripheral 1.0 Introduction The low cost PSD3XX family integrates high-performance and user-configurable blocks of EPROM, programmable logic, and optional SRAM into one part. The PSD3XX products also provide a powerful microcontroller interface that eliminates the need for external “glue logic”. The part’s integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. The major functional blocks of the PSD3XX include: • Two programmable logic arrays • 256Kb to 1 Mb of EPROM • Optional 16 Kb SRAM • Input latches • Programmable I/O ports • Page logic • Programmable security. The PSD3XX family architecture (Figure 1) can efficiently interface with, and enhance, almost any 8- or 16-bit microcontroller system. This solution provides microcontrollers the following: • Chip-select logic, control logic, and latched address signals that are otherwise implemented discretely • Port expansion (reconstructs lost microcontroller I/O) • Expanded microcontroller address space (up to 16 times) • An EPROM (with security) and optional SRAM • Compatible with 8031-type architectures that use separate Program and Data Space • Interface to shared external resources. 1 PSD3XX Family 1.0 Introduction (cont.) The PSD3XX I/O ports can be used for: • Standard I/O ports • Programmable chip select outputs • Address inputs • Demultiplexed address outputs • A data bus port for non-multiplexed MCU applications • A data bus “repeater” port that shares and arbitrates the local MCU data bus with external devices. Implementing your design has never been easier than with PSDsoft —ST’s software development suite. Using PSDsoft, you can do the following: • Configure your PSD3XX to work with virtually any microcontroller • Specify what you want implemented in the programmable logic using a high-level Hardware Description Language (HDL) • Simulate your design • Download your design to the part using a programmer. 2. Notation For a complete product comparison, refer to Table 1. PSD3XX references the standard version of the PSD3XX family, which are ideal for general-purpose embedded control applications. PSD3XXR SRAM-less version of the PSD3XX. If you don’t require the 16 Kb SRAM or need a larger external SRAM, go with this part to save cost. ZPSD3XX has improved technology that helps reduce current consumption using the Turbo bit. Excellent if you require a 5 V version of the PSD3XX that uses less power. ZPSD3XXR SRAM-less version of the ZPSD3XX. ZPSD3XXV 2.7 V to 5.5 V operation, ideal for very low-power and low-voltage applications. ZPSD3XXRV SRAM-less version of the ZPSD3XXV. Throughout this data sheet, references are made to the PSD3XX. In most cases, these references also cover the entire family. Exceptions will be noted. References, such as “3X1 only” cover all parts that have a 301 or 311 in the part number. Use the following table to determine what references cover which product versions: Reference PSD3XX PSD3XXR ZPSD3XX ZPSD3XXR ZPSD3XXV ZPSD3XXRV PSD3XX PSD X X X X X X PSD3XX only X X Non-ZPSD X X X X X X X X X X ZPSD only ZPSD3XX Non-V versions X X V versions only V suffix ZPSD3XXV only SRAM-less Non-R 2 X X X PSD3XX Family Figure 1. PSD3XX Family Architecture OPTIONAL PAGE LOGIC* P3–P0 AD8–AD15 L A T C H A11–A15 A8–A10 ALE/AS LOGIC IN CSIOPORT A19/CSI A19/CSI ALE/AS AD0–AD7 A16–A18 PAD A ALE/AS RD RD WR WR 13 P.T. PAD B 27 P.T. RESET RESET ES7 ES6 ES5 ES4 ES3 ES2 ES1 ES0 L A T C H 16/8 MUX PROG. PORT EXP. PORT C PC0– PC2 CS8– CS10 CS0– CS7 EPROM 256Kb TO 1Mb PROG. PORT EXP. PORT B D8–D15 PB0– PB7 D8–D15 CSIOPORT D0–D7 RS0 OPTIONAL SRAM 16K BIT ** TRACK MODE SELECTS A0–A7 AD0–AD7/D0–D7 PROG. PORT EXP. PORT A PA0– PA7 ALE/AS PROG. CHIP CONFIGURATION RD/E/DS WR/R/W BHE/PSEN RESET PROG. CONTROL SIGNALS X8, X16 MUX or NON–MUX BUSSES SECURITY MODE A19/CSI **Not available for 3X1 devices. **SRAM not available on “R” versions. 3 PSD3XX Family 3.0 Key Features ❏ Single-chip programmable peripheral for microcontroller-based applications ❏ 256K to 1 Mbit of UV EPROM with the following features: • Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16 • Divided into eight equally-sized mappable blocks for optimized address mapping • As fast as 70 ns access time, which includes address decoding ❏ Optional 16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as quick as 70 ns, including address decoding. ❏ 19 I/O pins that can be individually configured for : • Microcontroller I/O port expansion • Programmable Address decoder (PAD) I/O • Latched address output • Open-drain or CMOS output ❏ Two Programmable Arrays (PAD A and PAD B) replace your PLD or decoder, and have the following features: • Up to 18 Inputs and 24 outputs • 40 Product terms (13 for PAD A and 27 for PAD B) • Ability to decode up to 1 MB of address without paging ❏ Microcontroller logic that eliminates the need for external “glue logic” has the following features: • Ability to interface to multiplexed and non-multiplexed buses • Built-in address latches for multiplexed address/data bus • ALE and Reset polarity are programmable (Reset polarity not programmable on V-versions) • Multiple configurations are possible for interface to many different microcontrollers ❏ Optional built-in page logic expands the MCU address space by up to 16 times ❏ Programmable power management with standby current as low as 1µA for low-voltage version • CMiser bit —programmable option to reduce AC power consumption in memory • Turbo Bit (ZPSD only)—programmable bit to reduce AC and DC power consumption in the PADs. ❏ Track Mode that allows other microcontrollers or host processors to share access to the local data bus ❏ Built-in security locks the device and PAD decoding configuration ❏ Wide Operating Voltage Range • V-versions: 2.7 to 5.5 volts • Others: 4.5 to 5.5 volts ❏ Available in a variety of packaging (44-pin PLDCC, CLDCC, TQFP, and PQFP) ❏ Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC. 4 PSD3XX Family 4.0 PSD3XX Family Feature Summary Use the following table to determine which PSD product will fit your needs. Refer back to this page whenever there is confusion as to which part has what features. Part # PLD Inputs EPROM Size SRAM Size PSD301R PSD311R 14 14 256 Kb 256 Kb PSD302R PSD312R 18 18 512 Kb 512 Kb PSD303R PSD313R 18 18 1 Mb 1 Mb ZPSD301R ZPSD311R 14 14 256 Kb 256 Kb ZPSD302R ZPSD312R 18 18 512 Kb 512 Kb ZPSD303R ZPSD313R 18 18 1 Mb 1 Mb PSD301 PSD311 14 14 256 Kb 256 Kb 16 Kb 16 Kb PSD302 PSD312 18 18 512 Kb 512 Kb 16 Kb 16 Kb PSD303 PSD313 18 18 1 Mb 1 Mb 16 Kb 16 Kb ZPSD301 ZPSD311 14 14 256 Kb 256 Kb 16 Kb 16 Kb ZPSD302 ZPSD312 18 18 512 Kb 512 Kb 16 Kb 16 Kb ZPSD303 ZPSD313 18 18 1 Mb 1 Mb 16 Kb 16 Kb ZPSD301V1 ZPSD311V1 14 14 256 Kb 256 Kb 16 Kb 16 Kb ZPSD302V1 ZPSD312V1 18 18 512 Kb 512 Kb 16 Kb 16 Kb ZPSD303V1 ZPSD313V1 18 18 1 Mb 1 Mb 16 Kb 16 Kb Bus Width Typical Standby Current 5V 5V x8 or x16 x8 50 µA 50 µA X X 5V 5V x8 or x16 x8 50 µA 50 µA X X 5V 5V x8 or x16 x8 50 µA 50 µA Page Reg Voltage Turbo Bit 5V 5V X X x8 or x16 x8 10 µA 10 µA X X 5V 5V X X x8 or x16 x8 10 µA 10 µA X X 5V 5V X X x8 or x16 x8 10 µA 10 µA 5V 5V x8 or x16 x8 50 µA 50 µA X X 5V 5V x8 or x16 x8 50 µA 50 µA X X 5V 5V x8 or x16 x8 50 µA 50 µA 5V 5V X X x8 or x16 x8 10 µA 10 µA X X 5V 5V X X x8 or x16 x8 10 µA 10 µA X X 5V 5V X X x8 or x16 x8 10 µA 10 µA 2.7 V 2.7 V X X x8 or x16 x8 1 µA 1 µA X X 2.7 V 2.7 V X X x8 or x16 x8 1 µA 1 µA X X 2.7 V 2.7 V X X x8 or x16 x8 1 µA 1 µA NOTES: 1. Low power versions of the ZPSD3XX (ZPSD3XXV) can only accept an active-low level Reset input. 5 PSD3XX Family 5.0 Partial Listing of Microcontrollers Supported ❏ Motorola family: 68HC11, 68HC16, M68000/10/20, M68008, M683XX, 68HC05C0 ❏ Intel family: 80C31, 80C51, 80C196/198, 80C186/188 ❏ Philips family: 80C31 and 80C51 based MCUs ❏ Zilog: Z8, Z80, Z180 ❏ National: HPC16000, HPC46400 ❏ Echelon/Motorola/Toshiba: NEURON ® 3150™ Chip 6.0 Applications ❏ Telecommunications: • Cellular phone • Digital PBX • Digital speech • FAX • Digital Signal Processing (DSP) ❏ Portable Industrial Equipment: • Industrial control • Measurement meters • Data recorders ❏ Instrumentation ❏ Medical Instrumentation: • Hearing aids • Monitoring equipment • Diagnostic tools ❏ Computers—notebooks, portable PCs, and palm-top computers: • Peripheral control (fixed disks, laser printers, etc.) • Modem Interface • MCU peripheral interface 7.0 ZPSD Background 6 Portable and battery-powered systems have recently become major embedded control application segments. As a result, the demand for electronic components having extremely low power consumption has increased dramatically. Recognizing this trend, ST developed a new lower power 3XX part, denoted ZPSD3XX. The Z stands for Zero-power because ZPSD products virtually eliminate the DC component of power consumption, reducing it to standby levels. Virtual elimination of the DC component is the basis for the words “Zero-power” in the ZPSD name. ZPSD products also minimize the AC power component when the chip is changing states. The result is a programmable microcontroller peripheral family that replaces discrete circuit components, while drawing less power. PSD3XX Family 7.0 ZPSD Background (cont.) Integrated Power Management TM Operation Upon each address or logic input change to the ZPSD, the device powers up from low power standby for a short time. Then the ZPSD consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. After the new outputs are stable, the ZPSD latches them and automatically reverts back to standby mode. The ICC current flowing during standby mode and during DC operation is identical and is only a few microamperes. The ZPSD automatically reduces its DC current drain to these low levels and does not require controlling by the CSI (Chip Select Input). Disabling the CSI pin unconditionally forces the ZPSD to standby mode independent of other input transitions. The only significant power consumption in the ZPSD occurs during AC operation. The ZPSD contains the first architecture to apply zero power techniques to memory and logic blocks. Figure 2 compares ZPSD zero power operation to the operation of a discrete solution. A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and the generation of an address. The ZPSD detects the address transition and powers up for a short time. The ZPSD then latches the outputs of the PAD, EPROM and SRAM to the new values. After finishing these operations, the ZPSD shuts off its internal power, entering standby mode. The time taken for the entire cycle is less than the ZPSD’s “access time.” The ZPSD will stay in standby mode while its inputs are not changing between bus cycles. In an alternate system implementation using discrete EPROM, SRAM, and other discrete components, the system will consume operating power during the entire bus cycle. This is because the chip select inputs on the memory devices are usually active throughout the entire cycle. The AC power consumption of the ZPSD may be calculated using the composite frequency of the MCU address and control signals, as well as any other logic inputs to the ZPSD. Figure 2. ZPSD Power Operation vs. Discrete Implementation ALE SRAM ACCESS EPROM ACCESS ADDRESS EPROM ACCESS DISCRETE EPROM, SRAM & LOGIC ZPSD ICC ZPSD ZPSD TIME 7 PSD3XX Family Table 2. PSD3XX Pin Descriptions Name BHE/ PSEN WR/VPP or R/W/VPP RD/E/DS A19/CSI Type Description I When the data bus is 8 bits: This pin is for 8031 or compatible MCUs that use PSEN to separate program space from data space. In this case, PSEN is used for reads from the EPROM. Note: if your MCU does not output a PSEN signal, pull up this pin to VCC. When the data bus is 16 bits: This pin is BHE. When low, D8-D15 are read from or written to. Note: in programming mode, this pin is pulsed between VPP and 0 V. I The following control signals can be connected to this port, based on your MCU (and the way you configure the PSD in PSDsoft): 1. WR—active-low write pulse. 2. R/W—active-high read/active-low write input. Note: in programming mode, this pin must be tied to VPP. I I The following control signals can be connected to this port, based on your MCU (and the way you configure the PSD in PSDsoft): 1. RD—active-low read input. 2. E—E clock input. 3. DS—active-low data strobe input (3X2/3X3 devices only) The following control signals can be connected to this port: 1. CSI—Active-low chip select input. If your MCU supports a chip select output, and you want the PSD to save power when not selected, use this pin as a chip select input. 2. If you don’t wish to use the CSI feature, you may use this pin as an additional input (logic or address) to the PAD. A19 can be latched (with ALE/AS), or a transparent logic input. PSD3XX/ZPSD3XX: This pin is user-programmable and can be configured to reset on a high- or low-level input. Reset must be applied for at least 100 ns. Reset ALE/AS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 I I I/O ZPSD3XXV: This pin is not configurable, and the chip will only reset on an active-low level input. Reset must be applied for at least 500 ns, and no operations may take place for an additional 500 ns minimum. (See Figure 8.) If you use an MCU that has a multiplexed bus: Connect ALE or AS to this pin. The polarity of this pin is configurable. The trailing edge of ALE/AS latches all multiplexed address inputs (and BHE where applicable). If you use an MCU that does not have a multiplexed bus: If your MCU uses ALE/AS, connect the signal to this pin. Otherwise, use this pin for a generic logic input to the PAD. (Non-3X1 devices only.) These pins make up Port A. These port pins are configurable, and can have the following functions: (see Figure 5A and 5B) 1. Track AD7-AD0. This feature repeats the MCU address and data bus on all Port A pins. 2. MCU I/O—in this mode, the direction of the pin is defined by its direction bit, which resides in the direction register. 3. Latched address output. 4. CMOS or open-drain output. 5. If your MCU is non-multiplexed: data bus input—connect your data bus (D0-7) to these pins. See Figure 3. Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power. 8 PSD3XX Family Table 2. PSD3XX Pin Descriptions (cont.) Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 Type Description I/O These pins make up Port B. These port pins are configurable, and can have the following functions: (see Figure 6) 1. MCU I/O —in this mode, the direction of the pin is defined by its direction bit, which resides in the direction register. 2. Chip select output —each of PB0-3 has four product terms available per pin, while PB4-7 have 2 product terms each. See Figure 4. 3. CMOS or open-drain. 4. If your MCU is non-multiplexed, and the data bus width is 16 bits: data bus input—connect your data bus (D8-D15) to these pins. See Figure 3. I/O These pins make up Port C. These port pins are configurable, and can have the following functions (see Figure 7): 1. PAD input—when configured as an input, a bit individually becomes an address or a logic input, depending on your PSDsoft design file. When declared as an address, the bit(s) can be latched with ALE/AS. 2. PAD output—when configured as an output (i.e. there is an equation written for it in your PSDsoft design file), there is one product term available to it. I/O I/O If your MCU is multiplexed: These pins are the multiplexed, low-order address/data byte (AD0-AD7). As inputs, address information is latched by the ALE/AS signal and used internally by the PSD. The pins also serve as MCU data bus inputs or outputs, depending on the MCU control signals (RD, WR, etc.). If your MCU is non-multiplexed: These pins are the low-order address inputs (A0-A7) If your MCU is multiplexed with a 16-bit data bus: These pins are the multiplexed, high-order address/data byte (AD8-AD15). As inputs, address information is latched by the ALE/AS signal and used internally the PSD. The pins also serve as MCU data bus inputs or outputs, depending on the MCU control signals (RD, WR, etc.). If your MCU is non-multiplexed or has a 8-bit data bus: These pins are the high-order address inputs (A8-A15). GND P Ground Pin VCC P Supply voltage input. Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power. 9 PSD3XX Family 8.0 Operating Modes (MCU Configurations) The PSD3XX’s four operating modes enable it to interface directly to most 8- and 16-bit microcontrollers with multiplexed and non-multiplexed address/data busses. The 16-bit modes are not available to some devices; see Table 1. The following are the four operating modes available: ❏ ❏ ❏ ❏ Multiplexed 8-bit address/data bus Multiplexed 16-bit address/data bus Non-multiplexed 8-bit data bus Non-multiplexed 16-bit data bus Please read the section below that corresponds to your type of MCU. Then check the appropriate Figure (3A/3B/3C/3D) to determine your pin connections. Table 3 lists the Port connections in tabular form. Multiplexed 8-bit address/data bus (Figure 3A) This mode is used to interface to microcontrollers with a multiplexed 8-bit data bus. Since the low-order address and data are multiplexed together, your MCU will output an ALE or AS signal. The PSD3XX contains a transparent latch to demultiplex the address/data lines internally. All you have to do is connect the ALE/AS signal and select 8-bit multiplexed bus mode in PSDsoft. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable. Multiplexed 16-bit address/data bus (Figure 3B) This mode is used to interface to microcontrollers with a multiplexed 16-bit data bus. Since the low address bytes and data are multiplexed together, your MCU will output an ALE or AS signal. The PSD3XX contains a transparent latch to demultiplex the address/data lines internally. All you have to do is connect the ALE/AS signal and select 8-bit multiplexed bus mode in PSDsoft. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable. Non-multiplexed 8-bit data bus (Figure 3C) This mode is used to interface to microcontrollers with a non-multiplexed 8-bit data bus. Connect the MCU’s address bus to AD0/A0-AD15/A15 on the PSD. Connect the data bus signals of your MCU to Port A of the PSD. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable. Non-multiplexed 16-bit data bus (Figure 3D) This mode is used to interface to microcontrollers with a non-multiplexed 16-bit data bus. Connect the MCU’s address bus to AD0/A0-AD15/A15 on the PSD. Connect the low byte data bus signals of your MCU to Port A, and the high byte data output of your MCU to Port B of the PSD. If your MCU outputs more than 16 bits of address, and you wish to connect them to the PSD, connect A16-A18 to Port C and A19 to A19/CSI, where applicable. For users with multiplexed MCUs that have data multiplexed on address lines other than A0-A7 note: You can still use the PSD3XX, but you will have to connect your data to Port A (and Port B where required), as shown in Figure 3C or 3D. That is, you will be connecting it as if you were using a non-multiplexed MCU. In this case, you must connect the ALE/AS signal so that the address will still be properly latched. This option is not available on the 3X1 versions. 10 PSD3XX Family Figure 3A. Connecting a PSD3XX to an 8-Bit Multiplexed-Bus MCU 8.0 Operating Modes AD0 -AD7 (MCU A8 -A15 PA Configurations) ALE/AS (cont.) Your 8-bit MCU PSEN R/ W or WR RD/E / DS1 A19 / CSI RESET A16-A182 PSD3XX PB PC Figure 3B. Connecting a PSD3XX to a 16-Bit Multiplexed-Bus MCU Your 16-bit MCU AD0 -AD7 AD8 -AD15 ALE/AS BHE/ PSEN R/ W or WR RD/E / DS1 A19 / CSI RESET A16-A182 PA PSD3XX PB PC Figure 3C. Connecting a PSD3XX to an 8-Bit Non-Multiplexed-Bus MCU Your 8-bit MCU D0 -D7 A0-A15 ALE/AS PSEN R/ W or WR RD/E / DS1 A19 / CSI RESET A16-A182 PA PSD3XX PB PC Figure 3D. Connecting a PSD3XX to a 16-Bit Non-Multiplexed-Bus MCU Your 16-bit MCU D0 -D15 A0-A15 ALE/AS BHE / PSEN R/ W or WR RD/E / DS1 A19 / CSI RESET A16-A182 D0 -D7 PA PSD3XX PB D8-D15 PC NOTES: 1. DS is a valid input on 3X2/3X3 and devices only. 2. Connect A16-A18 to Port C if your MCU outputs more than 16 bits of address. 11 PSD3XX Family 8.0 Operating Modes (MCU Configurations) Table 3. Bus and Port Configuration Options Multiplexed Address/Data Non-Multiplexed Address/Data 8-bit Data Bus Port A I/O or low-order address lines or Low-order multiplexed address/data byte D0–D7 data bus byte Port B I/O and/or CS0–CS7 I/O and/or CS0–CS7 AD0/A0–AD7/A7 Low-order multiplexed address/data byte Low-order address bus byte AD8/A8–AD15/A15 High-order address bus byte High-order address bus byte Port A I/O or low-order address lines or low-order multiplexed address/data byte Low-order data bus byte Port B I/O and/or CS0–CS7 High-order data bus byte AD0/A0–AD7/A7 Low-order multiplexed address/data byte Low-order address bus byte AD8/A8–AD15/A15 High-order multiplexed address/data byte High-order address bus byte (cont.) 16-bit Data Bus 9.0 Programmable Address Decoder (PAD) The PSD3XX contains two programmable arrays, referred to as PAD A and PAD B (Figure 4). PAD A is used to generate chip select signals derived from the input address to the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals. PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the decoding to select external devices or as a random logic replacement. PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft based on the designer’s input. The PAD’s non-volatile configuration is stored in a re-programmable CMOS EPROM. Windowed packages are available for erasure by the user. See Table 4 for a list of PAD A and PAD B functions. 12 PSD3XX Family Figure 4. PAD Description P3 P2 P1 P0 ALE or AS RD/E/DS WR or R/W A19 ES0 ES1 ES2 ES3 ES4 8 EPROM BLOCK SELECT LINES PAD A ES5 ES6 ES7 RS0 SRAM BLOCK SELECT* CSIOPORT CSADIN CSADOUT1 CSADOUT2 I/O BASE ADDRESS TRACK MODE CONTROL SIGNALS CS0/PB0 A18 CS1/PB1 A17 A16 A15 CS2/PB2 CS3/PB3 CS4/PB4 A14 CS5/PB5 PAD B A13 CS6/PB6 A12 A11 CS7/PB7 CS8/PC0 CSI CS9/PC1 RESET CS10/PC2 *SRAM no available on “R” versions NOTES: 1. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs become non-active. See Tables 12 and 13. 2. RESET deselects all PAD output signals. See Tables 10 and 11. 3. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively. Either A18 or CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of Port C. Port C pins can be configured as either input or output, individually. 4. P0–P3 are not included on 3X1 devices. 5. DS is not available on 3X1 devices. 13 PSD3XX Family Table 4. PSD3XX PAD A and PAD B Functions Function PAD A and PAD B Inputs A19/CSI When the PSD is configured to use CSI and while CSI is a logic 1, the PAD deselects all of its outputs and enters a power-down mode (see Tables 12 and 13). When the PSD is configured to use A19, this signal is another input to the PAD. A16–A18 These are general purpose inputs from Port C. See Figure 4, Note 3. A11–A15 These are address inputs. P0–P3 RD/E/DS WR or R/W ALE/AS RESET These are inputs from the page register (not available on 3X1 versions). This is the read pulse or strobe input. (DS not available on 3X1 versions). This is the write pulse or R/W select signal. This is the ALE or AS input to the chip. Use to demultiplex address and data. This deselects all outputs from the PAD; it can not be used in product term equations. See Tables 10 and 11. PAD A Outputs ES0–ES7 These are internal chip-selects to the 8 EPROM banks. Each bank can be located on any boundary that is a function of one product term of the PAD address inputs. RS0 This is an internal chip-select to the SRAM. Its base address location is a function of one term of the PAD address inputs. CSIOPORT This internal chip-select selects the I/O ports. It can be placed on any boundary that is a function of one product term of the PAD inputs. See Tables 5A and 5B. CSADIN This internal chip-select, when Port A is configured as a low-order address/data bus in the track mode controls the input direction of Port A. CSADIN is gated externally to the PAD by the internal read signal. When CSADIN and a read operation are active, data presented on Port A flows out of AD0/A0–AD7/A7. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5B. CSADOUT1 This internal chip-select, when Port A is configured as a low-order address/data bus in track mode, controls the output direction of Port A. CSADOUT1 is gated externally to the PAD by the ALE signal. When CSADOUT1 and the ALE signal are active, the address presented on AD0/A0–AD7/A7 flows out of Port A. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5B. CSADOUT2 This internal chip-select, when Port A is configured as a low-order address/data bus in the track mode, controls the output direction of Port A. CSADOUT2 must include the write-cycle control signals as part of its product term. When CSADOUT2 is active, the data presented on AD0/A0–AD7/A7 flows out of Port A. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5B. PAD B Outputs 14 CS0–CS3 These chip-select outputs can be routed through Port B. Each of them is a function of up to four product terms of the PAD inputs. CS4–CS7 These chip-select outputs can be routed through Port B. Each of them is a function of up to two product terms of the PAD inputs. CS8–CS10 These chip-select outputs can be routed through Port C. See Figure 4, Note 3. Each of them is a function of one product term of the PAD inputs. PSD3XX Family 10.0 I/O Port Functions The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications. The next section describes the control registers for the ports. Following that are sections that describe each port. Figures 5 through 7 show the structure of Ports A through C, respectively. Note: any unused input should be connected directly to ground or pulled up to VCC (using a 10KΩ to 100KΩ resistor). 10.1 CSIOPORT Registers Control of the ports is primarily handled through the CSIOPORT registers. There are 24 bytes in the address space, starting at the base address labeled CSIOPORT. Since the PSD3XX uses internal address lines A15-A8 for decoding, the CSIOPORT space will occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to reduce wasted address space by connecting lower order address lines (A7 and below) to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The CSIOPORT space must be defined in your PSDsoft design file. The following tables list the registers located in the CSIOPORT space. 16-Bit Users Note When referring to Table 5B, realize that Ports A and B are still accessible on a byte basis. Note: When accessing Port B on a 16-bit data bus, BHE must be low. Table 5A. CSIOPORT Registers for 8-Bit Data Busses Offset (in hex) from CSIOPORT Base Address Type of Access Allowed Port A Pin Register +2 Read Port A Direction Register +4 Read/Write Port A Data Register +6 Read/Write Port B Pin Register +3 Read Port B Direction Register +5 Read/Write Port B Data Register +7 Read/Write Power Management Register (Note 1) +10 Read/Write Page Register +18 Read/Write Register Name NOTE: 1. ZPSD only. Table 5B. CSIOPORT Registers for 16-Bit Data Busses Offset (in hex) from CSIOPORT Base Address Type of Access Allowed Port A/B Pin Register +2 Read Port A/B Direction Register +4 Read/Write Port A/B Data Register +6 Read/Write Power Management Register (Note 1) +10 Read/Write Page Register +18 Read/Write Register Name NOTE: 1. ZPSD only. 15 PSD3XX Family 10.0 I/O Port Functions (cont.) 10.2 Port A (PA0-PA7) The control registers of Port A are located in CSIOPORT space; see Table 5. 10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode Each pin of Port A can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port A do: Register Name Default Value 0 Value 1 Value Sampled logic level at pin = ‘0’ Sampled logic level at pin = ‘1’ X Port A Direction Register Pin is configured as input Pin is configured as output 0 Port A Data Register Data in DFF = ‘0’ Data in DFF = ‘1’ 0 Port A Pin Register (Note 1) NOTE: 1. Default value is the value after reset. MCU I/O Mode The default configuration of Port A is MCU I/O. In this mode, every pin can be set (at runtime) as an input or output by writing to the respective pin’s direction flip-flop (DIR FF, Figure 5A). As an output, the pin level can be controlled by writing to the respective pin’s data flip-flop (DFF, Figure 5A). The Pin Register can be read to determine logic level of the pin. The contents of the Pin Register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin. Pins can be configured as CMOS or open-drain using ST’s PSDsoft software. Open-drain pins require external pull-up resistors. Latched Address Output Mode Alternatively, any bit(s) of Port A can be configured to output low-order demultiplexed address bus bit. The address is provided by the internal PSD address latch, which latches the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed address bits. This feature can eliminate the need for an external latch (for example: 74LS373) if you have devices that require low-order latched address bits. Although any pin of Port A may output an address signal, the pin is position-dependent. In other words, pin PA0 of Port A may only pass A0, PA1 only A1, and so on. Track Mode Track Mode sets the entire port to track the signals on AD0/A0-AD7/A7, depending on specific address ranges defined by the PAD’s CSADIN, CSADOUT1, and CSADOUT2 signals. This feature lets the user interface the microcontroller to shared external resources without requiring external buffers and decoders. In Track Mode, Port A effectively operates as a bi-directional buffer, allowing external MCUs or host processors to access the local data bus. Keep the following information in mind when setting up Track Mode: ❏ The direction is controlled by: • ALE/AS • RD/E or RD/E/DS (DS on non-3X1 devices only) • WR or R/W • PAD outputs CSADOUT1, CSADOUT2, and CSADIN defined in PSDsoft design. ❏ When CSADOUT1 and ALE/AS are true, the address on AD0/A0-AD7/A7 is output on Port A. Note: carefully check the generation of CSADOUT1 to ensure that it is stable during the ALE/AS pulse. ❏ When CSADOUT2 is active and a write operation is performed, the data on the AD0/A0-AD7/A7 input pins flows out through Port A. ❏ When CSADIN is active and a read operation is performed, the data on Port A flows out through the AD0/A0-AD7/A7 pins. ❏ Port A is tri-stated when none of the above conditions exist. 16 PSD3XX Family 10.0 I/O Port Functions (cont.) 10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode In this mode, Port A becomes the low-order data bus byte of the chip. When reading an internal location, data is presented on Port A pins to the MCU. When writing to an internal location, data present on Port A pins from the MCU is written to the desired location. Figure 5A. Port A Pin Structure I N T E R N A L READ PIN READ DATA WRITE DATA A D D R / D A T A CK PORT A PIN DFF D R ENABLE LATCHED ADDR OUT ALE MUX G LATCH D R ADn/Dn B U S A D 0 / A D 7 CMOS/OD(1) MCU I/O OUT READ DIR D WRITE DIR CK DIR FF R CONTROL RESET NOTE: 1. CMOS/OD determines whether the output is open drain or CMOS. Figure 5B. Port A Track Mode CONTROL DECODER INTERNAL READ WR or R/W I CSADIN RD/E AD0–AD7 PA0 – PA7 INTERNAL ALE ALE or AS O CSADOUT1 AD8– AD15 LATCH A11– A15 PAD CSADOUT2 (1) A16 – A19 NOTE: 1. The expression for CSADOUT2 must include the following write operation cycle signals: For CRRWR = 0, CSADOUT2 must include WR = 0. For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0. 17 PSD3XX Family 10. I/O Port Functions (cont.) 10.3 Port B (PB0-PB7) The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B. 10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode Each pin of Port B can be individually configured. The following table summarizes what the control registers (in CSIOPORT space) for Port B do: Register Name Default Value 0 Value 1 Value Sampled logic level at pin = ‘0’ Sampled logic level at pin = ‘1’ X Port B Direction Register Pin is configured as input Pin is configured as output 0 Port B Data Register Data in DFF = ‘0’ Data in DFF = ‘1’ 0 Port B Pin Register (Note 1) NOTE: 1. Default value is the value after reset. MCU I/O Mode The default configuration of Port B is MCU I/O. In this mode, every pin can be set (at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the pin. The contents of the Pin Register indicate the true state of the PSD driving the pin through the DFF or an external source driving the pin. Pins can be configured as CMOS or open-drain using ST’s PSDsoft software. Open-drain pins require external pull-up resistors. Chip Select Output Alternatively, each bit of Port B can be configured to provide a chip-select output signal from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is not limited to chip selects only; they can be used for generic combinatorial logic as well. Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7 signals is comprised of two product terms. 18 PSD3XX Family 10. I/O Port Functions (cont.) 10.3.2 Port B (PB0-PB7) in 16-bit Multiplexed Address/Data Mode In this mode, Port B becomes the low-order data bus byte to the MCU chip. When reading an internal high-order location, data is presented on Port B pins to the MCU. When writing to an internal high-order location, data present on Port B pins from the MCU is written to the desired location. Figure 6. Port B Pin Structure READ PIN I N T E R N A L I N T E R N A L READ DATA WRITE DATA CMOS/OD (1) MCU I/O OUT CK PORT B PIN DFF C S O U T B U S C S 0 • • • 7 D D A T A R ENABLE Dn MUX B U S CSn D 8 READ DIR • • • D 1 5 RESET D WRITE DIR DIR CK FF R CONTROL NOTE: 1. CMOS/OD determines whether the output is open drain or CMOS. 19 PSD3XX Family 10. I/O Port Functions (cont.) 10.4 Port C (PC0-PC2) Each pin of Port C (Figure 7) can be configured as an input to PAD A and PAD B, or as an output from PAD B. As inputs, the pins are referenced as A16-A18. Although the pins are given this reference, they can be used for any address or logic input. [For example, A8-A10 could be connected to those pins to improve the resolution (boundaries) of CS0-CS7 to 256 bytes.] How they are defined in the PSDsoft design file determines: • Whether they are address or logic inputs • Whether the input is transparent or latched by the trailing edge of ALE/AS. Notes: 1) If the inputs are addresses, they are routed to PAD A and PAD B, and can be used in any or all PAD equations. 2) A logic input is routed to PAD B and can be used for Boolean equations that are implemented in any or all of the CS0-CS10 PAD B outputs. Alternately, PC0-PC2 can become CS8-CS10 outputs, respectively, providing the user with more external chip-select PAD outputs. Each of the signals (CS8-CS10) is comprised of one product term. Figure 7. Port C (PC0-PC2) Pin Structure CS8 / CS9 / C S10 Address In or Chip Select Out From PAD Latched Address Input A16/A17/A18 Q Port C I/O1 (PC0 / P C1/PC2) D En ALE To PAD Logic Input D E M U X Input or Output Set by PSDsoft 2 PSDsoft 2 NOTES: 1. Port C pins can be individually configured as inputs or outputs, but not both. Pins can be individually configured as address or logic and latched or transparent, except for the 3X1 devices, which must be set to all address or all logic. 2. PSDsoft sets this configuration prior to run-time based on your PSDsoft design file. 10.5 ALE/AS Input Pin The ALE/AS pin may be used as a generic logic input signal to the PADs if a non-multiplexed MCU configuration is chosen in PSDsoft. 20 PSD3XX Family 11. PSD Memory The following sections explain the various memory blocks and memory options within the PSD3XX. 11.1 EPROM For all of the PSD3XX devices, the EPROM is built using Zero-power technology. This means that the EPROM powers up only when the address changes. It consumes power for the necessary time to latch data on its outputs. After this, it powers down and remains in Standby Mode until the next address change. This happens automatically, and the designer has to do nothing special. The EPROM is divided into eight equal-sized banks. Each bank can be placed in any address location by programming the PAD. Bank0-Bank7 are selected by PAD A outputs ES0-ES7, respectively. There is one product term for each bank select (ESi). Refer to Table 1 to see the size of the EPROM for each PSD device. 11.2 SRAM (Optional) Like the EPROM, the optional SRAM in the PSD3XX devices is built using Zero-power technology. All PSD3XX parts which do not have an R suffix contain 2 Kbytes of SRAM (Table 1). The SRAM is selected by the RS0 output of the PAD. There is one product term dedicated to RS0. If your design requires a SRAM larger than 2K x 8, then use one of the RAMless (R versions) of the 3XX devices with an external SRAM. The external SRAM can be addressed trhough Port A and all require logic will be taken care of by the PSD3XXR. 11.3 Page Register (Optional) All PSD3XX parts, except 3X1devices, have a four-bit page register. Thus the effective address space of your MCU can be enlarged by a factor of 16. Each bit of the Page Register can be individually read or written. The Page Register is located in CSIOPORT space (at offset 18h); see Table 5. The Page Register is connected to the lowest nibble of the data bus (D3-D0). The outputs of the Page Register, P3-P0, are connected to PAD A, and therefor can be used in any chip select (internal or external) equations. The contents of the page register are reset to zero at power-up and after any chip-level reset. 11.4 Programming and Erasure Programming the device can be done using the following methods: •ST’s main programmer—PSDpro—which is accessible through a parallel port. • ST’s programmer used specifically with the PSD3XX—PEP300. •ST’s discontinued programmer—Magic Pro. • A 3rd party programmer, such as Data I/O. Information for programming the device is available directly from ST. Please contact your local sales representative. Also, check our web site (www.st.com/psm) for information related to 3rd party programmers. Upon delivery from ST or after each erasure (using windowed part), the PSD3XX device has all bits in PAD and EPROM in the HI state (logic 1). The configuration bits are in the LO state (logic 0). To clear all locations of their programmed contents (assuming you have a windowed version), expose the windowed device to an Ultra-Violet (UV) light source. A dosage of 30 W second/cm2 is required for PSD3XX devices, and 40 W second/cm2 for low-voltage (V suffix) devices. This dosage can be obtained with exposure to a wavelength of 2537 Å and intensity of 12000 µW/cm2 for 40 to 45 minutes for the PSD3XX and 55 to 60 minutes for the low-voltage (V suffix) devices. The device should be approximately 1 inch (2.54 cm) from the source, and all filters should be removed from the UV light source prior to erasure. The PSD3XX devices will erase with light sources having wavelengths shorter than 4000 Å. However, the erasure times will be much longer than when using the recommended 2537 Å wavelength. Note: exposure to sunlight will eventually erase the device. If used in such an environment, the package window should be covered with an opaque substance. 21 PSD3XX Family 12.0 Control Signals Consult your MCU data sheet to determine which control signals your MCU generates, and how they operate. This section is intended to show which control signals should be connected to what pins on the PSD3XX. You will then use PSDsoft to configure the PSD3XX, based on the combination of control signals that your MCU outputs, for example RD, WR, and PSEN. The PSD3XX is compatible with the following control signals: • ALE or AS (polarity is programmable) • WR or R/W • RD/E or RD/E/DS (DS for non-3X1 devices only) • BHE or PSEN • A19/CSI • RESET (polarity is programmable except on low voltage versions with the V suffix). 12.1 ALE or AS Connect the ALE or AS signal from your MCU to this pin where applicable, and program the polarity using PSDsoft. The trailing edge (when the signal goes inactive) of ALE or AS latches the address on any pins that have an address input. If you are using a non-multiplexed-bus MCU that does not output an ALE or AS signal, this pin can be used for a generic input to the PAD. Note: if your data is multiplexed with address lines other than A0-A7, connect your address pins to AD0/A0-AD15/A15, and connect your data to Port A (and Port B where applicable), and connect the ALE/AS signal to this pin. 12.2 WR or R/W Your MCU should output a stand-alone write signal (WR) or a multiplexed read/write signal (R/W). In either case, the signal should be connected to this pin. 12.3 RD/E/DS (DS option not available on 3X1 devices) Your MCU should output any one of RD, E (clock), or DS. In any case, connect the appropriate signal to this pin. 12.4 BHE or PSEN ❏ If your MCU does not output either of these signals, tie this pin to Vcc (through a series resistor), and skip to the next signal. ❏ If you use an 8-bit 8031 compatible MCU that outputs a separate signal when accessing program space, such as PSEN, connect it to this pin. You would then use PSDsoft to configure the EPROM in the PSD3XX to respond to PSEN only or PSEN and RD. If you have an 8031 compatible MCU, refer to the “Program/Data Space and the 8031” section for further information. ❏ If you are using a 16-bit MCU, connect the BHE (or similar signal) output to this pin. BHE enables accessing of the upper byte of the data bus. See Table 6 for information on how this signal is used in conjunction with the A0 address line. Table 6. Truth Table for BHE and Address Bit A0 (16-bit MCUs only) 22 BHE A0 Operation 0 0 Whole Word 0 1 Upper Byte From/To Odd Address 1 0 Lower Byte From/To Even Address 1 1 None PSD3XX Family 12.0 Control Signals (cont.) 12.5 A19/CSI This pin is configured using PSDsoft to be either a chip select for the entire PSD device or an additional PAD input. If your MCU can generate a chip-select signal, and you wish to save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic input. ❏ When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD in normal operation. However, when a high is detected on the pin, the PSD enters Power-down Mode. See Tables 7A and 7B for information on signal states during Power-down Mode. See section 16 for details about the reduction of power consumption. ❏ When configured as A19, the pin can be used as an additional input to the PADs. It can be used for address or logic. It can also be ALE/AS dependent or a transparent input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always enabled. Table 7A. Signal States During Power-Down Mode Port AD0–A0/AD15/A15 Port Pins PA0–PA7 Configuration Mode(s) State All Input (Hi-Z) MCU I/O Unchanged Tracking AD0/A0-AD7/A7 Input (Hi-Z) Latched Address Out Logic 1 MCU I/O Port Pins PB0–PB7 Unchanged Chip Select Outputs, CS0–CS7, CMOS Logic 1 Chip Select Outputs, CS0–CS7, Open Drain Port Pins PC0–PC2 Address or Logic Inputs, A16-A18 Hi-Z Input (Hi-Z) Chip Select Outputs, CS8–CS10, CMOS only Logic 1 Table 7B. Internal States During Power-down Component PAD A and PAD B All registers in CSIOPORT address space, including: Internal Signal Internal Signal State During Power-Down CS0–CS10 Logic 1 (inactive) CSADIN, CSADOUT1, CSADOUT2, CSIOPORT, ES0-ES7, RS0 Logic 0 (inactive) N/A ✓ Direction ✓ Data ✓ Page All unchanged ✓ PMR (turbo bit, ZPSD only) NOTE: N/A = Not Applicable 23 PSD3XX Family 12.0 Control Signals 12.6 Reset Input (cont.) Refer to tables 8A and 8B for information on device status during and after reset. This is an asynchronous input to initialize the PSD device. The standard-voltage PSD3XX and ZPSD3XX (non-V) devices require a reset input that is asserted for at least 100 nsec. The PSD will be functional immediately after reset is de-asserted. For these standard-voltage devices, the polarity of the reset input signal is programmable using PSDsoft (active-high or active-low), to match the functionality of your MCU reset. Note: It is not recommended to drive the reset input of the MCU and the reset input of the PSD with a simple RC circuit between power on ground. The input threshold of the MCU and the PSD devices may differ, causing the devices to enter and exit reset at different times because of slow ramping of the signal. This may result in the PSD not being operational when accessed by the MCU. It is recommended to drive both devices actively. A supervisory device or a gate with hysteresis is recommended. For low-voltage ZPSD3XXV devices only, the reset input must be asserted for at least 500 nsec. The ZPSD3XXV will not be functional for an additional 500 nsec after reset is de-asserted (see Figure 8). These low voltage ZPSD3XXV devices must use an active-low polarity signal for reset. Unlike the standard PSDs, the reset polarity for the ZPSD3XXV is not programmable. If your MCU operates with an active high reset, you must invert this signal before driving the ZPSD3XXV reset input. You must design your system to ensure that the PSD comes out of reset and the PSD is active before the MCU makes its first access to PSD memory. Depending on the characteristics and speed of your MCU, a delay between the PSD reset and the MCU reset may be needed. Table 8A. External PSD Signal States During and Just After Reset Port AD0/A0AD15/A15 Port Pins PA0-PA7 Configured Mode of Operation (Note 1) Input (Hi-Z) MCU address and/or data MCU I/O Input (Hi-Z) Input (Hi-Z) Tracking AD0/A0-AD7/A7 Input (Hi-Z) Active Track Mode Logic 0 MCU address Hi-Z MCU address Input (Hi-Z Input (Hi-Z) Logic 1 Per CS equations ZPSD3XXV Hi-Z Per CS equations PSD3XX, ZPSD3XX Hi-Z Per CS equations ZPSD3XXV Hi-Z Per CS equations Input (Hi-Z) Input (Hi-Z) Logic 1 Per CS equations Hi-Z Per CS equations PSD3XX, ZPSD3XX ZPSD3XXV MCU I/O Chip Select Outputs, CS0-CS7, CMOS Chip Select Outputs, CS0-CS7, Open Drain PSD3XX, ZPSD3XX Address or Logic Inputs, A16-A18 Port Pins PC0-PC2 Signal State Just After Reset All Latched Address Out Port Pins PB0-PB7 Signal State During Reset Chip Select Outputs, CS8-CS10, CMOS PSD3XX, ZPSD3XX ZPSD3XXV NOTE: 1. Signal is valid immediately after reset for PSD3XX and ZPSD3XX devices. ZPSD3XXV devices need an additional 500 nsec after reset before signal is valid. 24 PSD3XX Family 12.0 Control Signals Table 8B. Internal PSD Signal States During and Just After Reset (cont.) Component Internal Signal Internal Signal State During Reset Internal Signal State During Power-Down CS0-CS10 Logic 1 (inactive) Per CS Equations PAD A and PAD B CSADIN, CSADOUT1, CSADOUT2, CSIOPORT, ES0-ES7, RS0 Logic 0 (inactive) All registers in CSIOPORT address space, including: ✓ Direction ✓ Data ✓ Page ✓ PMR (turbo bit, ZPSD3XX only) N/A Logic 0 in all bit of Logic 0 until all registers changed by MCU Per equations for each internal signal NOTE: N/A = Not Applicable Figure 8. The Reset Cycle (RESET) (ZPSD3XXV Versions) VIH VIL 500 ns 500 ns RESET LOW RESET HIGH ZPSD3XXV IS OPERATIONAL 25 PSD3XX Family 13.0 Program/Data Space and the 8031 This section only applies to users who have an 8031 or compatible MCU that outputs a signal such as PSEN when accessing program space. If this applies to you, be aware of the following: ❏ The PSD3XX can be configured using PSDsoft such that the EPROM is either 1) accessed by PSEN only (Figure 10); or 2) accessed by PSEN or RD (Figure 9). The default is PSEN only unless changed in PSDsoft. ❏ The SRAM and I/O Ports (including CSIOPORT) can not be placed in program space only. By default, they are in data space only (Figure 10). However, the SRAM may be placed in Program and Data Space, as shown in Figure 9. Figure 9. Combined Address Space CS ADDRESS PAD SRAM* OE INTERNAL RD PSEN OE EPROM CS CS OE I/O PORTS *Not available on “R” versions. Figure 10. 8031-Compatible Separate Code and Data Address Spaces I/O PORTS OE CS INTERNAL RD OE CS ADDRESS PAD SRAM* CS EPROM PSEN *Not available on “R” versions. 26 OE PSD3XX Family 14.0 System Applications In Figure 11, the PSD3XX is configured to interface with Intel’s 80C31, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 80C31 uses signals RD to read from data memory and PSEN to read from code memory. It uses WR to write into the data memory. It also uses active high reset and ALE signals. The rest of the configuration bits, as well as the unconnected signals, are application specific, and thus, user dependent. Figure 11. PSD3XX Interface With Intel’s 80C31 VCC 0.1µF MICROCONTROLLER 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 Reset EA/VP X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31 44 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 38 37 36 35 34 33 32 23 24 25 26 27 28 29 30 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 31 32 33 35 36 37 38 39 RD WR PSEN ALE TXD RXD 17 16 29 30 11 10 22 2 1 13 3 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 21 20 19 18 17 16 15 14 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 11 10 9 8 7 6 5 4 RD WR/VPP BHE/PSEN ALE RESET PC0 PC1 PC2 40 41 42 A19/CSI 43 GND PSD3XX 34 12 NOTE: RESET to the PSD3XX must be the output of a RESET chip or buffer. If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the PSD3XX (shorter than the 80C31 RC RESET) must be provided to avoid a race condition. 27 PSD3XX Family 14.0 System Applications (cont.) In Figure 12, the PSD3XX is configured to interface with Motorola’s 68HC11, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 68HC11 uses E and R/W signals to derive the read and write strobes. It uses the Address Strobe (AS) for the address latch pulse. RESET is an active-low signal. The rest of the configuration bits, as well as the unconnected signals, are specific, and thus, user dependent. Figure 12. PSD3XX Interface With Motorola’s 68HC11 VCC 0.1µF MICROCONTROLLER 20 21 22 23 24 25 PD0 PD1 PD2 PD3 PD4 PD5 43 45 47 49 44 46 48 50 PE0 PE1 PE2 PE3 PD4 PE5 PE6 PE7 34 33 32 31 30 29 28 27 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 52 51 VRH VRL PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 E R/W AS RESET XIRQ IRQ MODB MODA XTAL EXTAL 68HC11 RESET 28 44 9 10 11 12 13 14 15 16 23 24 25 26 27 28 29 30 42 41 40 39 38 37 36 35 31 32 33 35 36 37 38 39 5 22 6 4 17 2 13 3 1 18 19 2 3 VCC AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 E PC0 PC1 PC2 R/W/VPP AS RESET BHE/PSEN A19/CSI GND PSD3XX 34 12 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 PSD3XX Family 14.0 System Applications (cont.) In Figure 13, the PSD3XX is configured to work directly with Intel’s 80C196KB microcontroller, which is a 16-bit address/16-bit data bus processor. The Address and data lines multiplexed. The PSD3XX is configured to use PC0, PC1, PC2, and A19/CSI as logic inputs. These signals are independent of the ALE pulse (latch-transparent). They are used as four general-purpose inputs that take part in the PAD equations. Port A is configured to work in Track Mode, in which (for certain conditions) PA0–PA7 tracks lines AD0/A0–AD7/A7. Port B is configured to generate CS0–CS7. In this example, PB2 serves as a WAIT signal that slows down the 80C196KB during the access of external peripherals. These 8-bit wide peripherals are connected to the shared bus of Port A. The WAIT signal also drives the buswidth input of the microcontroller, so that every external peripheral cycle becomes an 8-bit data bus cycle. PB3 and PB4 are open-drain output signals; thus, they are pulled up externally. Figure 13. PSD3XX Interface With Intel’s 80C196KB +5V +5V 0.1µF 0.1µF ADDRESS/DATA MULTIPLEXED BUS VCC 67 66 NMI RST 3 43 64 14 16 6 5 7 4 11 10 8 9 RxD TxD +5V 0.1µF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 NMI READY BUSWIDTH CDE RESET P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 18 17 15 44 42 39 33 38 P2.0/TXD P2.1/RXD P2.2/EXINT P2.3/T2CLK P2.4/T2RST P2.5/PWM P2.6/ T2 UP/DN P2.7/ T2 CAPTR 24 25 26 27 HSI.0 HSI.1 HSI.2/HSO.4 HSI.3/HSO.5 13 37 12 2 VREF VPP ANGND EA P4.0/AD8 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 CLKOUT BHE / WRH WR / WRL RD ALE /ADV INST HSO.0 HSO.1 HSO.2 HSO.3 VSS 80C196KB 68 VSS 36 AD[0 ..15] AD[0 ..15] 19 20 21 22 23 30 31 32 PORT 1 I/O PINS 60 59 58 57 56 55 54 53 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 52 51 50 49 48 47 46 45 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 65 41 40 61 62 63 28 29 34 35 44 SHARED BUS VCC AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 40 41 42 43 PC0 PC1 PC2 A19/CSI 1 2 22 13 3 BHE /PSEN WR / VPP RD ALE RESET PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 WAIT 4.7KΩ 4.7KΩ +5V GND GND PSD3XX 12 34 ALE FOUR GENERAL PURPOSE INPUTS 29 PSD3XX Family 15.0 Security Mode Security Mode in the PSD3XX locks the contents of PAD A, PAD B, and all the configuration bits. The EPROM, optional SRAM, and I/O contents can be accessed only through the PAD. The Security Mode must be set by PSDsoft prior to run-time. The Security Bit can only be erased on the UV parts using a full-chip erase. If Security Mode is enabled, the contents of the PSD3XX can not be uploaded (copied) on a device programmer. 16.0 Power Management PSDs from all PSD3XX families use Zero-power memory techniques that place memory into Standby Mode between MCU accesses. The memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to Standby. This is done automatically and the designer has to do nothing special to benefit from this feature. In addition to the benefits of Zero-power memory technology, there are ways to gain additional savings. The following factors determine how much current the entire PSD device uses: • Use of CSI (Chip Select Input) • Setting of the CMiser bit • Setting of the Turbo Bit (ZPSD only) • The number of product terms used in the PAD • The composite frequency of the input signals to the PAD • The loading on I/O pins. The total current consumption for the PSD is calculated by summing the currents from memory, PAD logic, and I/O pins, based on your design parameters and the power management options used. 16.1 CSI Input Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire PSD to enter Power-down Mode, independent of any transition on the MCU bus (address and control) or other PSD inputs. During this time, the PSD device draws only standby current (micro-amps). Alternately, driving a logic 0 on the CSI pin returns the PSD to normal operation. See Tables 7A and 7B for information on signal states during Power-down Mode. The CSI pin feature is available only if enabled in the PSDsoft Configuration utility. 16.2 CMiser bit In addition to power savings resulting from the Zero-power technology used in the memory, the CMiser feature saves even more power under certain conditions. Savings are significant when the PSD is configured for an 8-bit data path because the CMiser feature turns off half of the array when memory is being accessed (the memory is divided internally into odd and even arrays). See the DC characteristics table for current usage related to the CMiser bit. You should keep the following in mind when using this bit: • Setting of this bit is accomplished with PSDsoft at the design stage, prior to run-time. • Memory access times are extended by 10 nsec for standard voltage (non-V) devices, and 20 nsec for low voltage (V) devices. • EPROM access: although CMiser offers significant power savings in 8-bit mode (~50%), CMiser contributes no additional power savings when the PSD is configured for 16-bits. • SRAM access: CMiser reduces power consumption of PSDs configured for either 8-bit or 16-bit operation. 30 PSD3XX Family 16. Power Management 16.3 Turbo Bit (ZPSD only) (cont.) Power Management Register (PMR) The turbo bit is controlled by the MCU at run-time and is accessed through bit zero of the Power Management Register (PMR). The PMR is located in CSIOPORT space at offset 10h. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 * * * * * * * 1= OFF 1= OFF 1= OFF 1= OFF 1= OFF 1= OFF 1= OFF Bit 0 Turbo bit 1= OFF *Future Configuration bits are reserved and should be set to one when writing to this register. The default value at reset of all bits in the PMR is logic 0, which means the Turbo feature is enabled. The PAD logic (PAD A and PAD B) of the PSD will operate at full speed and full power. When the Turbo Bit is set to logic 1, the Turbo feature is disabled. When disabled, the PAD logic will draw only standby current (micro-amps) while no PAD inputs change. Whenever there is a transition on any PAD input (including MCU address and control signals), the PAD logic will power up and will generate new outputs, latch those outputs, then go back to Standby Mode. Keep in mind that the signal propagation delay through the PAD logic increases by 10 nsec for non-V devices, and 20 nsec for V devices while in non-turbo mode. Use of the Turbo Bit does not affect the operation or power consumption of memory. Tremendous power savings are possible by setting the Turbo Bit and going into non-turbo mode. This essentially reduces the DC power consumption of the PAD logic to zero. It also reduces the AC power consumption of PAD logic when the composite frequency of all PAD inputs change at a rate less than 40 MHz for non-V devices, and less than 20 MHz for V devices. Use Figures 14 and 15 to calculate AC and DC current usage in the PAD with the Turbo Bit on and off. You will need to know the number of product terms that are used in your design and you will have to calculate the composite frequency of all signals entering the PAD logic. 16.4 Number of Product Terms in the PAD Logic The number of product terms used in your design relates directly to how much current the PADs will draw. Therefore, minimizing this number will be in your best interest if power is a concern for you. Basically, the amount of product terms your design will use is based on the following (see Figure 4): • Each of the EPROM block selects, ES0-ES7 uses one product term (for a total of 8). • The CSIOPORT select uses one product term. • If your part has SRAM (non-R versions), the SRAM select RS0 uses one product term. • The Track Mode control signals (CSADIN, CSADOUT1, and CSADOUT2) each use one product term if you use these signals. • Port B, pins PB0-PB3 are allocated four product terms each if used as outputs. • Port B, pins PB4-PB7 are allocated two product terms each if used as outputs. • Port C, pins PC0-PC2 are allocated one product term each if used as outputs. Given the above product term allocation, keep the following points in mind when calculating the total number of product terms your design will require: 1) The EPROM block selects, CSIOPORT select, and SRAM select will use a product term whether you use these blocks or not. This means you start out with 10 product terms, and go up from there. 2) For Port B, if you use a pin as an output and your logic equation requires only one product term, you still have to include all the available product terms for that pin for power consumption, even though only one product term is specified. For example, if the output equation for pin PB0 uses just one product term, you will have to count PB0 as contributing four product terms to the overall count. With this in mind, you should use Port C for the outputs that only require one product term and PB4-7 for outputs that require two product terms. Use pins PB0-3 if you need outputs requiring more than two product terms or you have run out of outputs. 3) The following PSD functions do not consume product terms: MCU I/O mode, Latched Address Output, and PAD inputs (logic or address). 31 PSD3XX Family 16.0 Power Management (cont.) 16.5 Composite Frequency of the Input Signals to the PAD Logic The composite frequency of the input signals to the PADs is calculated by considering all transitions on any PAD input signal (including the MCU address and control inputs). Once you have calculated the composite frequency and know the number of product terms used, you can determine the total AC current consumption of the PAD by using Figure 14 or Figure 15. From the figures, notice that the DC component (f = 0 MHz) of PAD current is essentially zero when the turbo feature is disabled, and that the AC component increases as frequency increases. When the turbo feature is disabled, the PAD logic can achieve low power consumption by becoming active briefly, only when inputs change. For standard voltage (non-V) devices, the PAD logic will stay active for 25 nsec after it detects a transition on any input. If there are more transitions on any PAD input within the 25 nsec period, these transitions will not add to power consumption because the PAD logic is already active. This effect helps reduce the overall composite frequency value. In other words, narrowly spaced groups of transitions on input signals may count as just one transition when estimating the composite frequency. Note that the “knee” frequency in Figure 14 is 40 MHz, which means that the PAD will consume less power only if the composite frequency of all PAD inputs is less than 40 MHz. When the composite frequency is above 40 MHz, the PAD logic never gets a chance to shut down (inputs are spaced less than 25 nsec) and no power savings can be achieved. Figure 15 is for low-voltage devices in which the “knee” frequency is 20 MHz. Take the following steps to calculate the composite frequency: 1) Determine your highest frequency input for either PAD A or PAD B. 2) Calculate the period of this input and use this period as a basis for determining the composite frequency. 3) Examine the remaining PAD input signals within this base period to determine the number of distinct transitions. 4) Signal transitions that are spaced further than 25 nsec apart count as a distinct transition (50 nsec for low-voltage V devices). Signal transitions spaced closer than 25 nsec count as the same transition. 5) Count up the number of distinct transitions and divide that into the value of the base period. 6) The result is the period of the composite frequency. Divide into one to get the composite frequency value. Unfortunately, this procedure is complicated and usually not deterministic since different inputs may be changing in various cycles. Therefore, we recommend you think of the situation that has the most activity on the inputs to the PLD and use this to calculate the composite frequency. Then you will have a number that represents your best estimate at the worst case scenario. Since this is a complicated process, the following example should help. Example Composite Frequency Calculation Suppose you had the following circuit: 80C31 (12 MHz Crystal) 32 AD0-AD7 A8-A15 ALE RD WR PSEN CSI PSD3XX PA Latched Address Output (LA0-LA7) 3 Inputs: Int, Sel, Rdy PB PC 5 MCU I/O Outputs 3 Chip-Select Outputs PSD3XX Family 16.0 Power Management (cont.) All the inputs shown, except CSI, go to the PAD logic. These signals must be taken into consideration when calculating the composite frequency. Before we make the calculation, let’s establish the following conditions: • The input with the highest frequency is ALE, which is 2 MHz. So our base period is 500 nsec for this example. • Only the address information from the multiplexed signals AD0-AD7 reach the PAD logic because of the internal address latch. Signal transitions from data on AD0-AD7 do not reach the PADs. • The three inputs (Int, Sel, or Rdy) change state very infrequently relative to the 80C31 bus signals. Now, lets assume the following is a snapshot in time of all the input signals during a typical 80C31 bus cycle. We’ll use a code fetch as an example since that happens most often. ONE TYPICAL 80C31 BUS CYCLE (2 MHz, 500 nsec) ALE PSEN 1 ADDR AD0-AD7 DATA 2 A8-A15 INT < 25 nsec SEL 3 RDY FOUR DISTINCT TRANSITIONS The calculation of the composite frequency is as follows: • There are four distinct transitions (first four dotted lines) within the base period of 500 nsec. These first four transitions all count toward the final composite frequency. • The transition at (1) in the diagram does not count as a distinct transition because it is within 25 nsec of a neighboring transition (use 50 nsec for a ZPSD3XXV device). • Transition (2) above does not add to the composite frequency because only the internally latched address signals reach the PADs, the data signal transitions do not. • The transition at (3) just happens to appear in this snapshot, but its frequency is so low that it is not a significant contributor to the overall composite frequency, and will not be used. • Divide the 500 nsec base period by the four (distinct transitions), yielding 125 nsec. 1/125 nsec = 8 MHz. • Use 8 MHz as the composite frequency of PAD inputs when calculating current consumption. (See the next section for a sample current calculation.) 16.6 Loading on I/O pins A final consideration when calculating the current usage for the entire PSD device is the loading on I/O pins. All specifications for PSD current consumption in this document assume zero current flowing through PSD I/O pins (including ADIO). I/O current is dictated by the individual design implementation, and must be calculated by the designer. Be aware that I/O current is a function of loading on the pins and the frequency at which the signals toggle. 33 PSD3XX Family 17. Calculating Power Once you have read the “Power Management” section, you should be able to calculate power. The following is a sample power calculation: Conditions Part Used MCU ALE Clock Frequency Composite ZPLD Input Frequency % EPROM Access % SRAM Access % I/O access %Time CSI is high (standby mode) %Time CSI is low (normal operation mode) # Product terms used (see previous section) Turbo bit CMiser bit MCU Bus Configuration = = = = = = = = = = = = ZPSD3XX (VCC = 5.0 V) 2.0 MHz 8.0 MHz (see example in above section) 80% 15% 5% 90% 10% 13 (13/40 = 33%) OFF (Turbo Mode disabled) ON 8-bit multiplexed bus mode Calculation (Based on Typical AC and DC Currents) ICC total = Istandby x % time CSI is high + [ICC (AC) + ICC (DC)] x % time CSI is low. = Istandby x % time CSI is high + [% EPROM Access x 0.8 mA/MHz x Freq. of ALE + % SRAM x 1.4 mA/MHz x Freq of ALE + ZPLD AC current (Figure 14: 13 PTs, 8 MHz, Non-Turbo)] x % time CSI is low = 10 µA x 0.9 + (0.8 x 0.8 mA/MHz x 2 MHz + 0.15 x 1.4 mA/MHz x 2 MHz + 5.0 mA) x 0.1 = 9.0 µA + (1.28 mA + 0.42 mA + 5.0 mA) x 0.1 = 679 µA, based on the system operating in standby 90% of the time NOTES: 1. 2. 3. 4. 5. 34 Calculation is based on the assumption that IOUT = 0 mA (no I/O pin loading) ICC(DC) is zero for all ZPSD devices operating in non-turbo mode. 13 product terms: 8 for EPROM, 3 for Chip Selects, 1 for SRAM, 1 for CSIOPORT. The 5% I/O access in the conditions section is when the MCU accesses CSIOPORT space. Standby Mode can also be achieved without using the CSI pin. The ZPSD device will automatically go into Standby while no inputs are changing on any pin, and Turbo Mode is disabled. PSD3XX Family 17.0 Calculating Power Figure 14. Typical ICC vs. Frequency for the PAD (VCC = 5 V) (cont.) 45 40 PT Turbo 40 40 PT Non-Turbo 10 PT Turbo 35 10 PT Non-Turbo ICC (mA 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 Composite Frequency at PAD Inputs (MHz) Figure 15. Typical ICC vs. Frequency (VCC = 3 V) 14 40 PT Turbo 40 PT Non-Turbo 12 10 PT Turbo 10 PT Non-Turbo ICC (mA 10 8 6 4 2 0 0 5 10 15 20 25 Composite Frequency at PAD Inputs (MHz) 35 PSD3XX Family Figure 16. IOL vs. VOL (5 V ± 10%) Figure 17. Normalized ICC (DC vs. VCC ) (VCC = 3.0 V) ZPSD3XXV ZPSD3XXV 3.5 35 3.0 30 2.5 ICC 40 IOL (mA) 25 2.0 1.5 20 1.0 15 0.5 10 2.5 3.0 2.7 Temp. = 125°C 3.5 4.0 4.5 ( VCC V) 5.0 5.5 6.0 Temp. = 25°C 5 0 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 VOL (V) Figure 18. Normalized ICC (AC) (VCC = 3.0 V) Figure 19. Normalized Access Time (T6) (VCC = 3.0 V) ZPSD3XXV ZPSD3XXV 2.2 1.1 2.0 1.05 1.0 ACCESS TIME ICC (AC) 1.8 1.6 1.4 1.2 0.95 0.9 0.85 0.8 0.75 1.0 0.7 0.8 0.65 2.5 3.0 2.7 36 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0 2.5 3.0 2.7 3.5 4.0 4.5 VCC (V) 5.0 5.5 6.0 PSD3XX Family 18.0 Specifications 18.1 Absolute Maximum Ratings 1 Symbol Parameter Min Max Unit CERDIP – 65 + 150 °C PLASTIC – 65 + 125 °C Voltage on any Pin With Respect to GND – 0.6 +7 V VPP Programming Supply Voltage With Respect to GND – 0.6 + 14 V VCC Supply Voltage With Respect to GND – 0.6 +7 V TSTG Storage Temperature Condition >2000 ESD Protection V NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 18.2 Operating Range Range Temperature VCC VCC Tolerance Commercial 0° C to +70°C + 3 V1, + 5 V ± 10% Industrial –40° C to +85°C +3 V1, +5V ± 10% NOTES: 1. 3 V version available for ZPSD3XXV devices only. 18.3 Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Unit VCC Supply Voltage ZPSD Versions, All Speeds 4.5 5 5.5 V VCC Supply Voltage ZPSD V Versions Only, All Speeds 2.7 3.0 5.5 V 18.4 Pin Capacitance 1 Symbol Parameter CIN Capacitance (for input pins only) COUT CVPP Conditions Typical 2 Max Unit VIN = 0 V 4 6 pF Capacitance (for input/output pins) VOUT = 0 V 8 12 pF Capacitance (for WR/VPP or R/W/VPP) VPP = 0 V 18 25 pF NOTES: 1. This parameter is only sampled and is not 100% tested. 2. Typical values are for TA = 25°C and nominal supply voltages. 37 PSD3XX Family 18.5 AC/DC Characteristics – PSD3XX/ZPSD3XX (All 5 V devices) Symbol Parameter Conditions Min Typ Max Unit 4.5 5 5.5 V VCC Supply Voltage All Speeds VIH High-Level Input Voltage 4.5 V < VCC > 5.5 V 2 VCC + .1 V VIL Low-Level Input Voltage 4.5 V < VCC > 5.5 V – 0.5 0.8 V VOH Output High Voltage VOL Output Low Voltage (See Figure 16) ISB IOH = – 20 µA, VCC = 4.5 V 4.4 4.49 V IOH = – 2 mA, VCC = 4.5 V 2.4 3.9 V IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V IOL = 8 mA, VCC = 4.5 V 0.15 0.45 V 10 20 µA 50 100 µA ZPSD3XX Standby Supply Current (Notes 1,4) PSD3XX Standby Supply Current ILI Input Leakage Current VSS < VIN > VCC –1 ±.1 1 µA ILO Output Leakage Current .45 < VIN > VCC –10 ±5 10 µA ZPSD3XX Operating Suppy Current ICC (DC) (Note 3) ZPLD Turbo Mode = Off, f = 0 MHz See ISB ZPLD Turbo Mode = On, f = 0 MHz 0.5 1 mA/PT EPROM, f = 0 MHz 0 0 µA SRAM, f = 0 MHz 0 0 µA 0.5 1 mA/PT EPROM, f = 0 MHz 0 0 µA SRAM, f = 0 MHz 0 0 µA See Fig. 14 1.0 mA/MHz CMiser = On and 8-Bit Bus Mode 0.8 2.0 mA/MHz All Other Cases (Note 5) 1.8 4.0 mA/MHz CMiser = On and 8-Bit Bus Mode 1.4 2.7 mA/MHz CMiser = On and 16-Bit Bus Mode 2 4 mA/MHz 3.8 7.5 mA/MHz PLD, f = 0 MHz PSD3XX Operating Supply Current ZPLD AC Base ICC (AC) (Note 3) EPROM Access AC Adder SRAM Access AC Adder CMiser = Off NOTES: 1. 2. 3. 4. 5. 38 CMOS inputs: GND ± 0.3 V or VCC ± 0.3V. TTL inputs: VIL ≤ 0.8 V, VIH ≥ 2.0 V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode. All other cases include CMiser = On and 16-bit bus mode and CMiser = Off and 8- or 16-bit bus mode. µA PSD3XX Family 18.6 AC/DC DC Characteristics – ZPSD3XXV (3 V devices only) Symbol Parameter Conditions VCC Supply Voltage All Speeds VIH High-Level Input Voltage 2.7 V < VCC > 5.5 V VIL Low-Level Input Voltage 2.7 V < VCC > 5.5 V VOH Output High Voltage VOL Output Low Voltage ISB Standby Supply Current VCC = 3.0 V ILI Input Leakage Current VIN = VCC or GND ILO Output Leakage Current VOUT = VCC or GND (Notes 1,4) ICC (DC) (Note 3) Operating Supply Current EPROM Access AC Adder ICC (AC) (Note 3) SRAM Access AC Adder NOTES: 1. 2. 3. 4. 5. Typ 2.7 3 Max Unit 5.5 V .7 VCC VCC + .5 V – 0.5 .3 VCC V IOH = – 20 µA, VCC = 2.7 V 2.6 2.69 V IOH = – 1 mA, VCC = 2.7 V 2.3 2.4 V IOL = 20 µA, VCC = 2.7 V 0.01 0.1 V IOL = 4 mA, VCC = 2.7 V 0.15 0.45 V 1 5 µA –1 ±.1 1 µA –1 .1 1 µA ZPLD Turbo Mode = Off, f = 0 MHz, VCC = 3.0 V See ISB ZPLD Turbo Mode = On, f = 0 MHz, VCC = 3.0 V 0.17 0.35 mA/PT 0 0 µA See Figure 15 (VCC = 3.0 V) See Fig. 15 0.5 mZ/MHz CMiser = On and 8-Bit Bus Mode (VCC = 3.0 V) 0.4 1 mA/MHz All Other Cases (Note 5) (VCC = 3.0 V) 0.9 1.7 mA/MHz CMiser = On and 8-Bit Bus Mode (VCC = 3.0 V) 0.7 1.4 mA/MHz CMiser = On and 16-Bit Bus Mode (VCC = 3.0 V) 1 2 mA/MHz CMiser = Off (VCC = 3.0 V) 1.9 3.8 mA/MHz EPROM, f = 0 MHz, VCC = 3.0 V ZPLD AC Base Min µA CMOS inputs: GND ± 0.3 V or VCC ± 0.3V. TTL inputs: VIL ≤ 0.8 V, VIH ≥ 2.0 V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode. All other cases include CMiser = On and 16-bit bus mode and CMiser = Off and 8- or 16-bit bus mode. 39 PSD3XX Family 18.7 Timing Parameters – PSD3XX/ZPSD3XX (All 5 V devices) -70 Symbol Parameter Min Max Min Max -15 Min Max CMiser Turbo On = Off = Add Add Unit T1 ALE or AS Pulse Width 18 20 40 0 0 ns T2 Address Set-up Time 5 5 12 0 0 ns T3 Address Hold Time 7 8 10 0 0 ns T4 Leading Edge of Read to Data Active 0 0 0 0 0 ns T5 ALE Valid to Data Valid 80 100 160 10 0 ns T6 Address Valid to Data Valid 70 90 150 10 0 ns T7 CSI Active to Data Valid 80 100 160 10 0 ns T8 Leading Edge of Read to Data Valid 20 32 55 0 0 ns Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode 32 32 55 0 0 ns 0 0 ns 0 0 ns T8A T9 Read Data Hold Time T10 Trailing Edge of Read to Data High-Z T11 Trailing Edge of ALE or AS to Leading Edge of Write 0 0 0 0 0 ns T12 RD, E, PSEN, or DS Pulse Width 35 40 60 0 0 ns WR Pulse Width 18 20 35 0 0 ns T13 Trailing Edge of Write or Read to Leading Edge of ALE or AS 5 5 5 0 0 ns T14 Address Valid to Trailing Edge of Write 70 90 150 0 0 ns T15 CSI Active to Trailing Edge of Write 80 100 160 0 0 ns T16 Write Data Set-up Time 18 20 30 0 0 ns T17 Write Data Hold Time 5 5 10 0 0 ns T18 Port to Data Out Valid Propagation Delay 0 0 ns T19 Port Input Hold Time 0 0 ns T20 Trailing Edge of Write to Port Output Valid 50 0 0 ns T21 ADi1 or Control to CSOi2 Valid 6 20 6 25 6 35 0 10 ns T22 ADi1 or Control to CSOi2 Invalid 5 20 5 25 4 35 0 10 ns T12A 0 0 20 0 0 32 25 35 30 0 30 *-90 speed available only on Industrial Temperature versions. 40 -90* 35 0 40 PSD3XX Family 18.7 Timing Parameters – PSD3XX/ZPSD3XX (All 5 V devices) -70 Symbol Parameter Min (cont.) -90* Max Min Max -15 Min Max CMiser Turbo On = Off = Add Add Unit Track Mode Address Propagation Delay: CSADOUT1 Already True 22 22 28 0 0 Latched Address Outputs, Port A 22 22 28 0 0 T23A Track Mode Address Propagation Delay: CSADOUT1 Becomes True During ALE or AS 33 33 50 0 10 ns T24 Track Mode Trailing Edge of ALE or AS to Address High-Z 30 32 35 0 0 ns T25 Track Mode Read Propagation Delay 27 29 35 0 0 ns T26 Track Mode Read Hold Time 29 0 0 ns T27 Track Mode Write Cycle, Data Propagation Delay 30 0 0 ns T28 Track Mode Write Cycle, Write to Data Propagation Delay 6 40 0 10 ns T29 Hold Time of Port A Valid During Write CSOi2 Trailing Edge 2 0 0 ns T30 CSI Active to CSOi2 Active 8 37 9 40 9 50 0 0 ns T31 CSI Inactive to CSOi2 Inactive 8 37 9 40 9 50 0 0 ns T32 Direct PAD Input3 0 10 12 0 0 ns T33 R/W Active to E or DS Start 18 20 30 0 0 ns T34 E or DS End to R/W 18 20 30 0 0 ns T35 AS Inactive to E high 0 0 0 0 0 ns T36 Address to Leading Edge of Write 18 20 25 0 0 ns T23 NOTES: as Hold Time 5 29 11 18 30 29 11 20 8 30 2 9 2 ns 1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C (CS8–CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0–PC2, ALE (or AS). 4. Control signals RD/E/DS or WR or R/W. *-90 speed available only on Industrial Temperature versions. 41 PSD3XX Family 18.8 Timing Parameters – ZPSD3XXV (3 V devices only) -15* Symbol Parameter Max Min -25 Max Min Max CMiser Turbo On = Off = Add Add Unit T1 ALE or AS Pulse Width 40 50 60 0 0 ns T2 Address Set-up Time 12 15 20 0 0 ns T3 Address Hold Time 10 15 20 0 0 ns T4 Leading Edge of Read to Data Active 0 0 0 0 0 ns T5 ALE Valid to Data Valid 170 200 250 20 0 ns T6 Address Valid to Data Valid 150 200 250 20 0 ns T7 CSI Active to Data Valid 160 200 250 20 0 ns T8 Leading Edge of Read to Data Valid 45 50 60 0 0 ns Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode 65 70 80 0 0 ns 0 0 ns 0 0 ns T8A T9 Read Data Hold Time T10 Trailing Edge of Read to Data High-Z T11 Trailing Edge of ALE or AS to Leading Edge of Write 0 0 0 0 0 ns T12 RD, E, PSEN, or DS Pulse Width 60 75 85 0 0 ns WR Pulse Width 35 45 55 0 0 ns T13 Trailing Edge of Write or Read to Leading Edge of ALE or AS 5 5 5 0 0 ns T14 Address Valid to Trailing Edge of Write 150 200 250 0 0 ns T15 CSI Active to Trailing Edge of Write 160 200 250 0 0 ns T16 Write Data Set-up Time 30 40 50 0 0 ns T17 Write Data Hold Time 10 12 15 0 0 ns T18 Port to Data Out Valid Propagation Delay 0 0 ns T19 Port Input Hold Time 0 0 ns T20 Trailing Edge of Write to Port Output Valid 70 0 0 ns T21 ADi1 or Control to CSOi2 Valid 6 50 5 55 5 60 0 20 ns T22 ADi1 4 50 4 55 4 60 0 20 ns T12A or Control to CSOi2 *-15 speed available only on ZPSD311V. 42 Min -20 0 0 45 50 45 0 Invalid 0 55 50 0 50 60 0 60 PSD3XX Family 18.8 Timing Parameters – ZPSD3XXV (3 V devices only) (cont.) -15* Symbol Parameter Min -20 Max Min -25 Max Min Max CMiser Turbo On = Off = Add Add Unit Track Mode Address Propagation Delay: CSADOUT1 Already True 50 60 60 0 0 Latched Address Outputs, Port A 50 60 60 0 0 T23A Track Mode Address Propagation Delay: CSADOUT1 Becomes True During ALE or AS 70 80 90 0 20 ns T24 Track Mode Trailing Edge of ALE or AS to Address High-Z 50 60 60 0 0 ns T25 Track Mode Read Propagation Delay 45 55 60 0 0 ns T26 Track Mode Read Hold Time 70 0 0 ns T27 Track Mode Write Cycle, Data Propagation Delay 60 0 0 ns T28 Track Mode Write Cycle, Write to Data Propagation Delay 8 80 0 20 ns T29 Hold Time of Port A Valid During Write CSOi2 Trailing Edge 2 0 0 ns T30 CSI Active to CSOi2 Active 9 70 9 80 9 90 0 0 ns T31 CSI Inactive to CSOi2 Inactive 9 70 9 80 9 90 0 0 ns T32 Direct PAD Input 3 0 0 0 0 0 ns T33 R/W Active to E or DS Start 30 40 50 0 0 ns T34 E or DS End to R/W 30 40 50 0 0 ns T35 AS Inactive to E high 0 0 0 0 0 ns T36 Address to Leading Edge of Write 30 35 40 0 0 ns T23 NOTES: as Hold Time 10 70 10 45 65 70 10 55 8 75 3 8 3 ns 1. ADi = any address line. 2. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C (CS8–CS10). 3. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0–PC2, ALE (or AS). 4. Control signals RD/E/DS or WR or R/W. *-15 speed available only on ZPSD311V. 43 PSD3XX Family 18.9 Timing Diagrams for all PSD3XX Parts Figure 20. Timing of 8-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 14 6 Multiplexed (2) Inputs 10 6 A0/AD0A7/AD7 Active High ALE DATA VALID ADDRESS A 2 3 DATA IN 14 ADDRESS B 2 9 17 3 16 1 1 11 Active Low ALE 4 13 8 12 RD/E as RD 36 5 BHE/PSEN as PSEN 12A WR/VPP or RW as WR 18 20 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT Any of PA0-PA7 Pins as Address Outputs 23 See referenced notes on page 64. 44 19 13 23 ADDRESS A ADDRESS B PSD3XX Family Figure 21. Timing of 8-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 14 6 Multiplexed (2) Inputs 10 6 A0/AD0A7/AD7 Active High ALE DATA VALID ADDRESS A 2 3 DATA IN 14 ADDRESS B 2 9 17 3 16 1 1 Active Low ALE 4 11 13 8 12 RD/E/DS as RD 5 BHE/PSEN as PSEN 36 12A WR/VPP or RW as WR 18 19 13 20 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT Any of PA0-PA7 Pins as Address Outputs 23 23 ADDRESS A ADDRESS B See referenced notes on page 64 45 PSD3XX Family Figure 22. Timing of 8-Bit Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 14 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 ADDRESS A 2 Active High AS ADDRESS B DATA VALID 3 DATA IN 14 10 2 9 17 3 16 1 Active Low AS 1 35 35 13 4 34 33 34 8 RD/E as E 12 36 5 33 13 12 WR/VPP or R/W as R/W 18 20 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT Any of PA0-PA7 Pins as Address Outputs 23 See referenced notes on page 64. 46 19 23 ADDRESS A ADDRESS B PSD3XX Family Figure 23. Timing of 8-Bit Multiplexed Address/Data Bus Using R/W E or R/W, DS (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 14 6 Multiplexed (2) Inputs 6 A0/AD0A7/AD7 ADDRESS A 2 Active High AS ADDRESS B DATA VALID 3 DATA IN 14 10 2 9 17 3 16 1 Active Low AS 1 35 35 13 4 34 33 34 8 RD/E/DS as E 36 5 12 RD/E/DS as DS 33 12 13 WR/VPP or R/W as R/W 18 19 20 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT Any of PA0-PA7 Pins as Address Outputs 23 23 ADDRESS A ADDRESS B See referenced notes on page 64. 47 PSD3XX Family Figure 24. Timing of 16-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 6 14 Multiplexed (2) Inputs 6 14 10 BHE/PSEN as BHE DATA IN A0/AD0A15/AD15 ADDRESS A 2 Active High ALE ADDRESS B DATA VALID 3 2 9 17 3 4 16 1 1 Active Low ALE 8 11 13 5 12 RD/E as RD 36 13 12A WR/VPP or R/W as WR 18 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT 23 Any of PA0-PA7 Pins as Address Outputs See referenced notes on page 64. 48 20 19 23 ADDRESS A ADDRESS B PSD3XX Family Figure 25. Timing of 16-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 6 14 Multiplexed (2) Inputs 14 6 BHE/PSEN as BHE 10 A0/AD0A15/AD15 ADDRESS A 2 Active High ALE DATA IN ADDRESS B DATA VALID 3 2 9 17 3 16 4 1 1 Active Low ALE 8 11 13 5 12 RD/E/DS as RD 36 13 12A WR/VPP or R/W as WR 18 20 19 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT 23 Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A ADDRESS B See referenced notes on page 64. 49 PSD3XX Family Figure 26. Timing of 16-Bit Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 6 14 Multiplexed (2) Inputs 6 14 10 BHE/PSEN as BHE DATA IN A0/AD0A15/AD15 ADDRESS A 2 Active High AS ADDRESS B DATA VALID 3 2 9 16 1 Active Low AS 1 35 4 35 13 33 34 RD/E as E 34 12 5 WR/VPP or R/W as R/W 33 12 13 8 18 36 19 20 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT 23 Any of PA0-PA7 Pins as Address Outputs See referenced notes on page 64. 50 17 3 23 ADDRESS A ADDRESS B PSD3XX Family Figure 27. Timing of 16-Bit Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 15 32 Direct (1) PAD Input STABLE INPUT STABLE INPUT 6 14 Multiplexed (2) Inputs 14 6 BHE/PSEN as BHE A0/AD0A15/AD15 ADDRESS A 2 Active High AS DATA IN 10 ADDRESS B DATA VALID 3 2 9 17 3 16 1 Active Low AS 1 35 4 33 34 8 RD/E/DS as E 35 13 34 5 12 RD/E/DS as DS 36 33 12 13 WR/VPP or R/W as R/W 18 19 20 Any of PA0-PA7 as I/O Pin INPUT OUTPUT Any of PB0-PB7 as I/O Pin INPUT OUTPUT 23 Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A ADDRESS B See referenced notes on page 64. 51 PSD3XX Family Figure 28. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 14 6 A0/AD0A15/AD15 as A0-A15 STABLE INPUT PC0-PC2, CSI/A19 as Multiplexed Inputs 6 32 14 10 PA0-PA7 DATA IN DATA VALID 2 Active High ALE STABLE INPUT 32 3 2 9 1 17 3 16 1 4 Active Low ALE 8 13 11 12 RD/E as RD 36 13 12A WR/VPP or R/W as WR 5 19 18 Any of PB0-PB7 as I/O Pin See referenced notes on page 64. 52 INPUT 20 OUTPUT PSD3XX Family Figure 29. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 14 6 A0/AD0A15/AD15 as A0-A15 STABLE INPUT STABLE INPUT 32 32 Multiplexed (2) Inputs 6 PA0-PA7 DATA IN DATA VALID 2 Active High ALE 14 10 3 2 9 1 17 3 16 1 4 Active Low ALE 8 13 11 12 RD/E/DS as RD 36 13 12A WR/VPP or R/W as WR 5 19 18 Any of PB0-PB7 as I/O Pin INPUT 20 OUTPUT See referenced notes on page 64. 53 PSD3XX Family Figure 30. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 15 7 Direct (1) PAD Input STABLE INPUT STABLE INPUT 14 6 A0/AD0A15/AD15 as A0-A15 STABLE INPUT STABLE INPUT 32 PC0-PC2, CSI/A19 as Multiplexed Inputs 6 14 10 PA0-PA7 3 2 9 17 3 16 1 1 Active Low ALE DATA IN DATA VALID 2 Active High ALE 32 4 35 13 35 36 34 34 RD/E as E 12 33 33 8 12 13 WR/VPP or R/W as R/W 18 Any of PB0-PB7 as I/O Pin See referenced notes on page 64. 54 19 INPUT 20 OUTPUT PSD3XX Family Figure 31. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 14 6 A0/AD0A15/AD15 as A0-A15 STABLE INPUT STABLE INPUT 32 32 Multiplexed (2) Inputs 6 DATA IN DATA VALID PA0-PA7 2 Active High ALE 14 10 3 2 9 17 3 16 1 1 Active Low ALE 4 35 33 34 8 RD/E/DS as E 36 5 RD/E/DS as DS 35 13 34 12 12 33 13 WR/VPP or R/W as R/W 18 Any of PB0-PB7 as I/O Pin 19 INPUT 20 OUTPUT See referenced notes on page 64. 55 PSD3XX Family Figure 32. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 6 A0/AD0A15/AD15 as A0-A15 14 STABLE INPUT STABLE INPUT 32 32 PC0-PC2, CSI/A19 as Multiplexed Inputs 14 BHE/PSEN as BHE 6 DATA IN PA0-PA7 (Low Byte) DATA VALID 17 9 DATA VALID PB0-PB7 (High Byte) 2 Active High ALE 9 3 2 3 16 10 DATA IN 1 1 4 Active Low ALE 8 13 11 12 RD/E as RD 36 13 12A WR/VPP or R/W as WR See referenced notes on page 64. 56 PSD3XX Family Figure 33. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 6 A0/AD0A15/AD15 as A0-A15 14 STABLE INPUT STABLE INPUT 32 32 Multiplexed (2) Inputs 14 BHE/PSEN as BHE 6 DATA IN DATA VALID PA0-PA7 (Low Byte) 17 9 DATA VALID PB0-PB7 (High Byte) 2 Active High ALE 2 3 3 16 10 DATA IN 1 1 4 Active Low ALE 8 11 13 12 RD/E/DS as RD 36 5 13 12A WR/VPP or R/W as WR See referenced notes on page 64. 57 PSD3XX Family Figure 34. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X1) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 14 6 A0/AD0A15/AD15 as A0-A15 STABLE INPUT STABLE INPUT 32 32 PC0-PC2, CSI/A19 as Multiplexed Inputs 14 BHE/PSEN as BHE 6 DATA IN PA0-PA7 (Low Byte) DATA VALID 9 PB0-PB7 (High Byte) DATA VALID 2 Active High AS DATA IN 10 3 3 1 35 16 17 1 4 Active Low AS 2 35 8 33 13 34 13 36 33 34 RD/E as E 12 WR/VPP or R/W as R/W See referenced notes on page 64. 58 PSD3XX Family Figure 35. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using R/W, E or R/W, DS (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 32 CSI/A19 as CSI 7 Direct (1) PAD Input 15 STABLE INPUT STABLE INPUT 14 6 A0/AD0A15/AD15 as A0-A15 STABLE INPUT STABLE INPUT 32 32 Multiplexed (2) Inputs 14 BHE/PSEN as BHE 6 DATA IN PA0-PA7 (Low Byte) DATA VALID 9 PB0-PB7 (High Byte) DATA VALID 2 Active High AS DATA IN 10 3 16 17 3 1 1 4 Active Low AS 2 35 35 8 33 13 34 13 36 33 34 RD/E/DS as E 12 5 RD/E/DS as DS 12 WR/VPP or R/W as R/W See referenced notes on page 64. 59 PSD3XX Family Figure 36. Chip-Select Output Timing 31 30 A19/CSI as CSI Direct PAD (1) Input INPUT STABLE Multiplexed (2) PAD Inputs 2 ALE (Multiplexed Mode Only) 3 1 or ALE (Multiplexed Mode Only) 21 CSOi (3,8) See referenced notes on page 64. 60 22 PSD3XX Family Figure 37. Port A as AD0–AD7 Timing (Track Mode) Using RD, WR (PSD3X1) READ CYCLE WRITE CYCLE 32 Direct PAD Input (1,4) Multiplexed PAD Inputs (5,7) 32 STABLE INPUT STABLE INPUT 2 2 STABLE INPUT STABLE INPUT 2 A0/AD0A7/AD7 3 25 ADDRESS 2 26 3 WRITTEN DATA ADDRESS DATA VALID 32 ALE 1 1 or ALE 32 4 12 27 RD/E as RD 11 WR/VPP or R/W as WR 24 24 PA0-PA7 ADR OUT 23 12A DATA OUT ADR OUT DATA IN 23 28 29 CSOi (3,6) See referenced notes on page 64. 61 PSD3XX Family Figure 38. Port A as AD0–AD7 Timing (Track Mode) Using RD, WR (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 Direct PAD Input (1,4) Multiplexed PAD Inputs (5,7) 32 STABLE INPUT STABLE INPUT 2 2 STABLE INPUT STABLE INPUT 2 A0/AD0A7/AD7 3 25 ADDRESS 2 26 3 WRITTEN DATA ADDRESS DATA VALID 32 ALE 1 1 or ALE 32 4 12 27 RD/E/DS as RD 11 WR/VPP or R/W as WR ADR OUT 23 CSOi (3,6) See referenced notes on page 64. 62 24 24 PA0-PA7 12A DATA OUT ADR OUT DATA IN 23 28 29 PSD3XX Family Figure 39. Port A as AD0–AD7 Timing (Track Mode) Using R/W, E or R/W, DS (PSD3X1) READ CYCLE WRITE CYCLE 32 Direct PAD Input (1,4) Multiplexed PAD Inputs (5,7) 32 STABLE INPUT STABLE INPUT 2 STABLE INPUT STABLE INPUT 2 A0/AD0A7/AD7 3 25 2 26 DATA VALID ADDRESS 3 WRITTEN DATA ADDRESS 32 AS 1 1 35 or AS 12 35 12 33 33 RD/E as E 34 WR/VPP or R/W as R/W 34 24 PA0-PA7 ADR OUT 23 24 27 DATA OUT ADR OUT DATA IN 23 28 29 CSOi (3,6) See referenced notes on page 64. 63 PSD3XX Family Figure 40. Port A as AD0–AD7 Timing (Track Mode) Using R/W, E or R/W, DS (PSD3X2/3X3) READ CYCLE WRITE CYCLE 32 Direct PAD Input (1,4) Multiplexed PAD Inputs (5,7) 32 STABLE INPUT STABLE INPUT 2 STABLE INPUT STABLE INPUT 2 A0/AD0A7/AD7 3 25 ADDRESS 2 26 3 WRITTEN DATA ADDRESS DATA VALID 32 AS 1 1 35 or AS 12 35 12 33 33 RD/E/DS as E 34 RD/E/DS as DS WR/VPP or R/W as R/W 34 24 PA0-PA7 ADR OUT 23 24 27 DATA OUT ADR OUT DATA IN 23 28 29 CSOi (3,6) Notes for Timing Diagrams 64 1. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0–PC2, ALE in non-multiplexed modes. 2. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): A0/AD0–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2. 3. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C (CS8–CS10). 4. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD input signals, otherwise the address propagation delay is slowed down. 5. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be derived from any combination of direct PAD inputs and multiplexed PAD inputs. 6. The write operation signals are included in the CSOi expression. 7. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in the multiplexed modes: A11/AD11–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2. 8. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset and CSI. PSD3XX Family 18.10 AC Testing Figure 41A. AC Testing Input/Output Waveform (5 V Versions) 3.0V TEST POINT 1.5V 0V Figure 41B. AC Testing Input/Output Waveform (3 V Versions) 0.9 VCC TEST POINT 1.5V 0V Figure 42A. AC Testing Load Circuit (5 V Versions) 2.01 V 195 Ω DEVICE UNDER TEST CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) Figure 42B. AC Testing Load Circuit (3 V Versions) 2.0 V 400 Ω DEVICE UNDER TEST CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) 65 PSD3XX Family 19.0 Pin Assignments 66 Pin Name 44-Pin PLDCC/CLDCC Package 44-Pin PQFP/TQFP Package BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 PC0 41 PC1 42 PC2 43 A19/CSI 44 VCC 7 39 AD15/A15 PB3 8 38 AD14/A14 PB2 9 37 AD13/A13 PB1 10 36 AD12/A12 PB0 11 35 AD11/A11 GND 12 34 GND 33 AD10/A10 ALE or AS 13 AD5/A5 28 34 PC0 AD4/A4 27 AD3/A3 26 AD2/A2 25 37 A19/CSI 35 PC1 AD1/A1 24 38 VCC 44 PB5 36 PC2 RD/E 22 AD0/A0 23 40 WR/VPP or R/W 39 BHE/PSEN 29 AD6/A6 PA0 21 PA4 17 41 RESET 30 AD7/A7 PA1 20 PA5 16 42 PB7 31 AD8/A8 PA2 19 32 AD9/A9 PA6 15 PA3 18 PA7 14 (TOP VIEW) 6 28 GND ALE or AS 7 27 AD10/A10 PA7 8 26 AD9/A9 PA6 9 25 AD8/A8 PA5 10 24 AD7/A7 PA4 11 23 AD6/A6 AD5/A5 22 29 AD11/A11 GND AD4/A4 21 5 AD3/A3 20 30 AD12/A12 PB0 AD2/A2 19 4 AD1/A1 18 31 AD13/A13 PB1 AD0/A0 17 3 RD/E 16 32 AD14/A14 PB2 PA0 15 33 AD15/A15 2 PA1 14 1 PB3 PA2 13 PB4 PA3 12 Figure 44. Drawing M1 – 44 Pin Plastic Quad Flatpack (PQFP) (Package Type M) OR Drawing U1 – 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 1 BHE/PSEN 3 RESET 4 PB7 5 PB6 PB4 43 PB6 Figure 43. Drawing J2 – 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) OR Drawing L4 – 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 6 PB5 20.0 Package Information 2 WR/VPP or R/W PSD3XX Family 67 PSD3XX Family 21.0 Package Drawings Drawing J2 – 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) D D1 3 2 1 44 E1 E C B1 e1 A1 A2 A B D3 E3 D2 E2 Family: Plastic Leaded Chip Carrier Millimeters Symbol Min Max A 4.19 A1 Inches Min Max 4.57 0.165 0.180 2.54 2.79 0.100 0.110 A2 3.76 3.96 0.148 0.156 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 C 0.246 0.262 0.0097 0.0103 D 17.40 17.65 0.685 0.695 D1 16.51 16.61 0.650 0.654 D2 14.99 16.00 0.590 0.630 D3 12.70 Notes Reference 0.500 Notes Reference E 17.40 17.65 0.685 0.695 E1 16.51 16.61 0.650 0.654 E2 14.99 16.00 0.590 0.630 E3 12.70 Reference 0.500 Reference e1 1.27 Reference 0.050 Reference N 44 44 030195R6 68 PSD3XX Family Drawing L4 – 44-Pin Pocketed Ceramic Leaded Chip Carrier (CLDCC) – CERQUAD (Package Type L) D D1 3 2 1 44 E1 View A E Commercial and Industrial packages include the lead pocket on the underside of the package but Military packages do not. B1 C A2 View A e1 B D3 D2 A1 E3 E2 A Family: Ceramic Leaded Chip Carrier – CERQUAD Millimeters Symbol Min Max Inches Notes Min Max A 3.94 4.57 0.155 0.180 A1 2.29 2.92 0.090 0.115 A2 3.05 3.68 0.120 0.145 B 0.43 0.53 0.017 0.021 B1 0.66 0.81 0.026 0.032 C 0.15 0.25 0.006 0.010 D 17.40 17.65 0.685 0.695 D1 16.31 16.66 0.642 0.656 D2 14.73 16.26 0.580 0.640 D3 12.70 Reference 0.500 Notes Reference E 17.40 17.65 0.685 0.695 E1 16.31 16.66 0.642 0.656 E2 14.73 16.26 0.580 0.640 E3 12.70 Reference 0.500 Reference e1 1.27 Reference 0.050 Reference N 44 44 030195R8 69 PSD3XX Family Drawing M1 – 44-Pin Plastic Quad Flatpack (PQFP) (Package Type M) D D1 D3 44 1 2 Index Mark 3 E3 E1 E Standoff: 0.10 mm Min 0.25 mm Max A1 C a A A2 e1 B L Family: Plastic Quad Flatpack (PQFP) Millimeters Symbol Min Max α 0° A – A1 Inches Min Max 7° 0° 7° 2.35 – 0.092 1.075 Notes Reference 0.042 Notes Reference A2 1.95 2.10 0.077 0.083 B 0.30 0.45 0.012 0.018 C 0.13 0.23 0.005 0.009 D 13.20 0.520 D1 10.00 0.394 D3 8.00 E 13.20 0.520 E1 10.00 0.394 E3 8.00 Reference 0.315 Reference e1 0.80 Reference 0.031 Reference L N 0.73 Reference 1.03 44 0.315 0.029 Reference 0.040 44 030195R4 70 PSD3XX Family Drawing U1 – 44-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) D D1 D3 44 1 2 Index Mark 3 E3 E1 E Standoff: 0.05 mm Min A1 C a A A2 e1 B Lead Coplanarity: 0.102 mm Max. L Family: Plastic Thin Quad Flatpack (TQFP) Millimeters Symbol Min Max α 0° A Inches Min Max 8° 0° 8° – 1.60 – 0.063 A1 0.54 0.74 0.021 0.029 A2 1.15 1.55 0.045 0.061 B 0.35 Notes Reference 0.014 Reference C 0.09 0.20 0.004 0.008 D 15.75 16.25 0.620 0.640 D1 13.90 14.10 0.547 0.555 D3 10.00 Reference Notes 0.394 Reference E 15.75 16.25 0.620 0.640 E1 13.90 14.10 0.547 0.555 E3 10.00 Reference 0.394 Reference e1 1.00 Reference 0.039 Reference L N 0.35 0.65 44 0.014 0.026 44 030195R4 71 ST Part # PSD @ 5V ZPSD @ 5V MCU ZPSD @ 2.7 V PLDs/Decoders 8-Bit 16-Bit Interface Inputs Product PLD Data Data Terms Outputs PSD311R ZPSD311R X PSD301R ZPSD301R X PSD312R ZPSD312R X PSD302R ZPSD302R X PSD313R ZPSD313R X PSD303R ZPSD303R X PSD311 ZPSD311 ZPSD311V X PSD301 ZPSD301 ZPSD301V X PSD312 ZPSD312 ZPSD312V X PSD302 ZPSD302 ZPSD302V X PSD313 ZPSD313 ZPSD313V X PSD303 ZPSD303 ZPSD303V X X X X X X X I/O Page Reg. Memory Ports Open Drain EPROM SRAM Other Peripheral Security Mode STD 14 40 11 19 X 256Kb X STD 14 40 11 19 X 256Kb X X X STD 18 40 11 X 19 X 512Kb X X STD 18 40 11 X 19 X 512Kb X X STD 18 40 11 X 19 X 1024Kb X X STD 18 40 11 X 19 X 1024Kb X X STD 14 40 11 19 X 256Kb 16Kb X X STD 14 40 11 19 X 256Kb 16Kb X X STD 18 40 11 X 19 X 512Kb 16Kb X X STD 18 40 11 X 19 X 512Kb 16Kb X X STD 18 40 11 X 19 X 1024Kb 16Kb X X STD 18 40 11 X 19 X 1024Kb 16Kb X X PSD3XX Family 22.0 PSD3XX Ordering Information 72 22.1 PSD3XX Family – Selector Guide PSD3XX Family PSD3XX Ordering Information (cont.) 22.2 Part Number Construction Z PSD 413A2 V -A -20 J I Temperature (Blank = Commercial, I = Industrial, M = Military) Package Type Speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) Revision (Blank = No Revision) Supply Voltage (Blank = 5V, V = 3 Volt) Base Part Number - see Selector Guide PSD (ST Programmable System Device) Fam. Power Down Feature (Blank = Standard, Z = Zero Power Feature) 22.3 Ordering Information Speed (ns) Package Type Operating Temperature Range PSD301-B-70J PSD301-B-70L PSD301-B-70M PSD301-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD301-B-90JI PSD301-B-90LI PSD301-B-90MI PSD301-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial PSD301-B-15J PSD301-B-15L PSD301-B-15M PSD301-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD301R-B-70J PSD301R-B-90JI PSD301R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l Part Number 73 PSD3XX Family PSD3XX Ordering Information (cont.) 74 Ordering Information Speed (ns) Package Type Operating Temperature Range PSD302-B-70J PSD302-B-70L PSD302-B-70M PSD302-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD302-B-90JI PSD302-B-90LI PSD302-B-90MI PSD302-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial PSD302-B-15J PSD302-B-15L PSD302-B-15M PSD302-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD302R-B-70J PSD302R-B-90JI PSD302R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l PSD303-B-70J PSD303-B-70L PSD303-B-70M PSD303-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD303-B-90JI PSD303-B-90LI PSD303-B-90MI PSD303-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial PSD303-B-15J PSD303-B-15L PSD303-B-15M PSD303-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD303R-B-70J PSD303R-B-90JI PSD303R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l PSD311-B-70J PSD311-B-70L PSD311-B-70M PSD311-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD311-B-90JI PSD311-B-90LI PSD311-B-90MI PSD311-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial PSD311-B-15J PSD311-B-15L PSD311-B-15M PSD311-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD311R-B-70J PSD311R-B-90JI PSD311R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l Part Number PSD3XX Family PSD3XX Ordering Information (cont.) Ordering Information Speed (ns) Package Type Operating Temperature Range PSD312-B-70J PSD312-B-70L PSD312-B-70M PSD312-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD312-B-90JI PSD312-B-90LI PSD312-B-90MI PSD312-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial PSD312-B-15J PSD312-B-15L PSD312-B-15M PSD312-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD312R-B-70J PSD312R-B-90JI PSD312R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l PSD313-B-70J PSD313-B-70L PSD313-B-70M PSD313-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD313-B-90JI PSD313-B-90LI PSD313-B-90MI PSD313-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial PSD313-B-15J PSD313-B-15L PSD313-B-15M PSD313-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l PSD313R-B-70J PSD313R-B-90JI PSD313R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l Part Number 75 PSD3XX Family PSD3XX Ordering Information (cont.) 76 Ordering Information Part Number Speed (ns) Package Type Operating Temperature Range ZPSD301-B-70J ZPSD301-B-70L ZPSD301-B-70M ZPSD301-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD301-B-90JI ZPSD301-B-90LI ZPSD301-B-90MI ZPSD301-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial ZPSD301-B-15J ZPSD301-B-15L ZPSD301-B-15M ZPSD301-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD301R-B-70J ZPSD301R-B-90JI ZPSD301R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l ZPSD301V-B-15J ZPSD301V-B-15L ZPSD301V-B-15U 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin TQFP Comm’l Comm’l Comm’l ZPSD301V-B-20J ZPSD301V-B-20JI ZPSD301V-B-20L ZPSD301V-B-20M ZPSD301V-B-20MI ZPSD301V-B-20U ZPSD301V-B-20UI 200 200 200 200 200 200 200 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PQFP 44 Pin TQFP 44 Pin TQFP Comm’l Industrial Comm’l Comm’l Industrial Comm’l Industrial ZPSD301V-B-25J ZPSD301V-B-25L ZPSD301V-B-25M ZPSD301V-B-25U 250 250 250 250 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD302-B-70J ZPSD302-B-70L ZPSD302-B-70M ZPSD302-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD302-B-90JI ZPSD302-B-90LI ZPSD302-B-90MI ZPSD302-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial ZPSD302-B-15J ZPSD302-B-15L ZPSD302-B-15M ZPSD302-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD302R-B-70J ZPSD302R-B-90JI ZPSD302R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l PSD3XX Family PSD3XX Ordering Information (cont.) Ordering Information Part Number Speed (ns) Package Type Operating Temperature Range ZPSD302V-B-20J ZPSD302V-B-20JI ZPSD302V-B-20L ZPSD302V-B-20M ZPSD302V-B-20MI ZPSD302V-B-20U ZPSD302V-B-20UI 200 200 200 200 200 200 200 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PQFP 44 Pin TQFP 44 Pin TQFP Comm’l Industrial Comm’l Comm’l Industrial Comm’l Industrial ZPSD302V-B-25J ZPSD302V-B-25L ZPSD302V-B-25M ZPSD302V-B-25U 250 250 250 250 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD303-B-70J ZPSD303-B-70L ZPSD303-B-70M ZPSD303-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD303-B-90JI ZPSD303-B-90LI ZPSD303-B-90MI ZPSD303-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial ZPSD303-B-15J ZPSD303-B-15L ZPSD303-B-15M ZPSD303-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD303R-B-70J ZPSD303R-B-90JI ZPSD303R-B-15J 70 90 150 44 Pin PLDCC 44 Pin PLDCC 44 Pin PLDCC Comm’l Industrial Comm’l ZPSD303V-B-20J ZPSD303V-B-20JI ZPSD303V-B-20L ZPSD303V-B-20M ZPSD303V-B-20MI ZPSD303V-B-20U ZPSD303V-B-20UI 200 200 200 200 200 200 200 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PQFP 44 Pin TQFP 44 Pin TQFP Comm’l Industrial Comm’l Comm’l Industrial Comm’l Industrial ZPSD303V-B-25J ZPSD303V-B-25L ZPSD303V-B-25M ZPSD303V-B-25U 250 250 250 250 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l 77 PSD3XX Family PSD3XX Ordering Information (cont.) 78 Ordering Information Speed (ns) Package Type Operating Temperature Range ZPSD311-B-70J ZPSD311-B-70L ZPSD311-B-70M ZPSD311-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD311-B-90JI ZPSD311-B-90LI ZPSD311-B-90MI ZPSD311-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial ZPSD311-B-15J ZPSD311-B-15L ZPSD311-B-15M ZPSD311-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD311R-B-70J ZPSD311R-B-70M 70 70 44 Pin PLDCC 44 Pin PQFP Comm’l Comm’l ZPSD311R-B-90JI ZPSD311R-B-90MI 90 90 44 Pin PLDCC 44 Pin PQFP Industrial Industrial ZPSD311R-B-15J ZPSD311R-B-15M 150 150 44 Pin PLDCC 44 Pin PQFP Comm’l Comm’l ZPSD311V-B-15J ZPSD311V-B-15L ZPSD311V-B-15M ZPSD311V-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD311V-B-20J ZPSD311V-B-20JI ZPSD311V-B-20L ZPSD311V-B-20M ZPSD311V-B-20MI ZPSD311V-B-20U ZPSD311V-B-20UI 200 200 200 200 200 200 200 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PQFP 44 Pin TQFP 44 Pin TQFP Comm’l Industrial Comm’l Comm’l Industrial Comm’l Industrial ZPSD311V-B-25J ZPSD311V-B-25L ZPSD311V-B-25M ZPSD311V-B-25U 250 250 250 250 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l Part Number PSD3XX Family PSD3XX Ordering Information (cont.) Ordering Information Part Number Speed (ns) Package Type Operating Temperature Range ZPSD312-B-70J ZPSD312-B-70L ZPSD312-B-70M ZPSD312-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD312-B-90JI ZPSD312-B-90LI ZPSD312-B-90MI ZPSD312-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial ZPSD312-B-15J ZPSD312-B-15L ZPSD312-B-15M ZPSD312-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD312R-B-70J ZPSD312R-B-70M ZPSD312R-B-90JI ZPSD312R-B-90MI ZPSD312R-B-15J ZPSD312R-B-15M 70 70 90 90 150 150 44 Pin PLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PQFP Comm’l Comm’l Industrial Industrial Comm’l Comm’l ZPSD312V-B-20J ZPSD312V-B-20JI ZPSD312V-B-20L ZPSD312V-B-20M ZPSD312V-B-20MI ZPSD312V-B-20U ZPSD312V-B-20UI 200 200 200 200 200 200 200 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PQFP 44 Pin TQFP 44 Pin TQFP Comm’l Industrial Comm’l Comm’l Industrial Comm’l Industrial ZPSD312V-B-25J ZPSD312V-B-25L ZPSD312V-B-25M ZPSD312V-B-25U 250 250 250 250 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD313-B-70J ZPSD313-B-70L ZPSD313-B-70M ZPSD313-B-70U 70 70 70 70 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l ZPSD313-B-90JI ZPSD313-B-90LI ZPSD313-B-90MI ZPSD313-B-90UI 90 90 90 90 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Industrial Industrial Industrial Industrial ZPSD313-B-15J ZPSD313-B-15L ZPSD313-B-15M ZPSD313-B-15U 150 150 150 150 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l 79 PSD3XX Family PSD3XX Ordering Information (cont.) 23. Revisions History 80 Ordering Information Part Number Speed (ns) Package Type Operating Temperature Range ZPSD313R-B-70J ZPSD313R-B-70M ZPSD313R-B-90JI ZPSD313R-B-90MI ZPSD313R-B-15J ZPSD313R-B-15M 70 70 90 90 150 150 44 Pin PLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PQFP 44 Pin PLDCC 44 Pin PQFP Comm’l Comm’l Industrial Industrial Comm’l Comm’l ZPSD313V-B-20J ZPSD313V-B-20JI ZPSD313V-B-20L ZPSD313V-B-20M ZPSD313V-B-20MI ZPSD313V-B-20U ZPSD313V-B-20UI 200 200 200 200 200 200 200 44 Pin PLDCC 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin PQFP 44 Pin TQFP 44 Pin TQFP Comm’l Industrial Comm’l Comm’l Industrial Comm’l Industrial ZPSD313V-B-25J ZPSD313V-B-25L ZPSD313V-B-25M ZPSD313V-B-25U 250 250 250 250 44 Pin PLDCC 44 Pin CLDCC 44 Pin PQFP 44 Pin TQFP Comm’l Comm’l Comm’l Comm’l Date Parts Affected Data Sheet Changes May, 1995 PSD3XX Initial Release May, 1998 ZPSD3XX SRAM-less (R suffix) version added. PQFP package added. May, 1998 PSD3XX PQFP package added, Specifications updated, PSD3XXL discontinued, Some speed grades eliminated. February, 1999 PSD3XXR, ZPSD3XXR Combined Data Sheets Updated Specifications PSD3XX, ZPSD3XX, ZPSD3XXV, PSD3XXR, ZPSD3XXR, ZPSD3XXRV REVISION HISTORY Table 1. Document Revision History Date Rev. May-1995 1.0 Documents written in the WSI format. Initial release May-1998 1.1 ZPSD3XX SRAM-less (R suffix) version added. PQFP package added. PSD3XX PQFP package added, Specifications updated, PSD3XXL discontinued, Some speed grades eliminated. February, 1999 PSD3XXR, ZPSD3XXR Combined Data Sheets Updated Specifications Feb-1999 1.2 PSD3XX ZPSD3XX ZPSD3XXV, PSD3XXR ZPSD3XXR ZPSD3XXRV Combined Data Sheets Updated Specifications 1.3 PSD3XX, ZPSD3XX, ZPSD3XXV, PSD3XXR, ZPSD3XXR, ZPSD3XXRV: Low Cost Field Programmable Microcontroller Peripherals Front page, and back two pages, in ST format, added to the PDF file Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft Express 31-Jan-2002 2/3 Description of Revision PSD3XX, ZPSD3XX, ZPSD3XXV, PSD3XXR, ZPSD3XXR, ZPSD3XXRV Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 3/3