Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 ADC12Jxx00 12-Bit 1.6 or 2.7 GSPS ADCs With Integrated DDC 1 Features 2 Applications • • • • • • • • • 1 • • • • • • • • • • • • Excellent Noise and Linearity up to and beyond FIN = 3 GHz Configurable DDC Decimation Factors from 4 to 32 (Complex Baseband Out) Bypass Mode for Full Nyquist Output Bandwidth Usable Output Bandwidth of 540 MHz at 4x Decimation and 2700 MSPS Usable Output Bandwidth of 320 MHz at 4x Decimation and 1600 MSPS Usable Output Bandwidth of 67.5 MHz at 32x Decimation and 2700 MSPS Usable Output Bandwidth of 40 MHz at 32x Decimation and 1600 MSPS Low Pin-Count JESD204B Subclass 1 Interface Automatically Optimized Output Lane Count Embedded Low Latency Signal Range Indication Low Power Consumption Key Specifications – Max Sampling Rate: 1600 or 2700 MSPS – Min Sampling Rate: 1000 MSPS – DDC Output Word Size: 15-Bit Complex (30 bits total) – Bypass Output Word Size: 12-Bit Offset Binary – Noise Floor: –147.3 dBFS/Hz (ADC12J2700) – Noise Floor: –145 dBFS/Hz (ADC12J1600) – IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS) – FPBW (–3 dB): 3.2 GHz – Peak NPR: 46 dB – Supply Voltages: 1.9 V and 1.2 V – Power Consumption – Bypass (2700 MSPS): 1.8 W – Bypass (1600 MSPS): 1.6 W – Power Down Mode: <50 mW Wireless Infrastructure RF-Sampling Software Defined Radio Wideband Microwave Backhaul Military Communications SIGINT RADAR and LIDAR DOCSIS / Cable Infrastructure Test and Measurement 3 Description The ADC12J1600 and ADC12J2700 devices are wideband sampling and digital tuning devices. Texas Instruments' giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface. A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output. The ADC12J1600 and ADC12J2700 devices are available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADC12J1600 VQFN (68) 10.00 mm × 10.00 mm ADC12J2700 VQFN (68) 10.00 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Bypass — Spectral Response ƒS = 2.7 GHz, FIN = 1897 MHz at –1 dBFS 0 Amplitude (dBFS) -20 -40 -60 -80 -100 0 225 450 675 900 1125 1350 Frequency (MHz) C001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 3 8 Absolute Maximum Ratings ...................................... 8 ESD Ratings.............................................................. 9 Recommended Operating Conditions....................... 9 Thermal Information .................................................. 9 Electrical Characteristics........................................... 9 Timing Requirements .............................................. 16 Internal Characteristics ........................................... 18 Switching Characteristics ........................................ 19 Typical Characteristics ............................................ 20 Detailed Description ............................................ 30 7.1 7.2 7.3 7.4 7.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 30 30 31 49 55 7.6 Register Map........................................................... 57 8 Application and Implementation ........................ 82 8.1 8.2 8.3 8.4 9 Application Information............................................ Typical Application ................................................. Initialization Set-Up ................................................. Dos and Don'ts........................................................ 82 82 86 86 Power Supply Recommendations...................... 87 9.1 Supply Voltage ........................................................ 87 10 Layout................................................................... 87 10.1 Layout Guidelines ................................................. 87 10.2 Layout Example .................................................... 88 10.3 Thermal Management ........................................... 90 11 Device and Documentation Support ................. 90 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 90 92 92 92 92 92 92 12 Mechanical, Packaging, and Orderable Information ........................................................... 92 4 Revision History Changes from Revision B (September 2014) to Revision C Page • Added additional voltage difference parameters to the Absolute Maximum Ratings table .................................................... 8 • Added junction temperature to the Absolute Maximum Ratings table ................................................................................... 8 • Added common mode voltage parameter to the Recommended Operating Conditions table. Changed CLK to SYSREF, and ~SYNC ........................................................................................................................................................... 9 • Changed some of the maximum interleaving offset values for both devices to tighten the levels ...................................... 10 • Deleted the Differential Analog Input Connection image in The Analog Inputs section ...................................................... 31 • Added note about offset adjust in Background Calibration Mode to the Offset Adjust section and I/O offset register tables .................................................................................................................................................................................... 35 • Added the Calibration Cycle Timing for Different Calibration Modes and Options table in the Timing Calibration Mode section ........................................................................................................................................................................ 50 • Changed 0x004-0x005 to RESERVED in the Standard SPI-3.0 Registers summary table................................................. 60 Changes from Revision A (February 2014) to Revision B • 2 Page Changed the device status from Product Preview to Production Data .................................................................................. 1 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 5 Pin Configuration and Functions VBG DNC RSV VA12 Tdiode+ Tdiode± VA19 RSV2 VA19 SCSb SCLK SDI SDO VD12 DS7+/NCO_2b DS7-/NCO_2a VD12 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 NKE Package 68-Pin VQFN With Thermal Pad Top View DS2+ VA12 14 38 DS2± DEVCLK+ 15 37 VD12 DEVCLK± 16 36 DS1+ VA12 17 35 DS1± VD12 39 34 13 33 VD12 VA19 DS0± VNEG 40 DS0+ DS3± 12 32 41 31 11 VD12 DS3+ VA12 SYNC~ VA19 42 30 VD12 10 29 43 VD12 9 VNEG_OUT DS4± VIN± 28 VIN+ 44 27 DS4+ 8 VA19 45 OR_T1 7 26 VD12 VA19 25 VA12 46 VA19 DS5±/NCO_0a 6 OR_T0 47 24 5 23 DS5+/NCO_0b VNEG SYNC~±/TMST± 48 22 4 VA12 VA19 SYNC~+/TMST+ VD12 21 49 20 3 SYSREF± DS6±/NCO_1a VCMO SYSREF+ 50 19 51 2 18 1 RBIAS± VA12 RBIAS+ DS6+/NCO_1b DNC = Make no external connection Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 3 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Pin Functions PIN NAME EQUIVALENT CIRCUIT NO. TYPE DESCRIPTION ANALOG RBIAS+ VA19 1 VBIAS RBIAS– 2 TDIODE– 63 I/O External Bias Resistor Connections External bias resistor terminals. A 3.3 kΩ (±0.1%) resistor should be connected between RBIAS+ and RBIAS–. The RBIAS resistor is used as a reference for internal circuits which affect the linearity of the converter. The value and precision of this resistor should not be compromised. These pins must be isolated from all other signals and grounds. Passive Temperature Diode These pins are the positive (anode) and negative (cathode) diode connections for die temperature measurements. Leave these pins unconnected if they are not used. See the Built-In Temperature Monitor Diode section for more details. O Bandgap Output Voltage This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. Leave this pin unconnected if it is not used in the application. See the The Reference Voltage section for more details. O Common Mode Voltage The voltage output at this pin must be the common-mode input voltage at the VIN+ and VIN– pins when DC coupling is used. This pin is capable of sourcing or sinking 100 μA and can drive a load up to 80 pF. Leave this pin unconnected if it is not used in the application. I Signal Input The differential full-scale input range is determined by the full-scale voltage adjust register. An internal peaking inductor (LPEAK) of 5 nH is included for parasitic compensation. GND TDIODE+ 64 VBG 68 Tdiode+ Tdiode± VA19 VCM VCMO 3 VIN+ 8 GND VA19 VIN+ To T&H+ LPEAK GND 50 20 k VCM VIN– 9 50 VA19 LPEAK VIN± To T&H± GND 4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Pin Functions (continued) PIN NAME EQUIVALENT CIRCUIT NO. TYPE DESCRIPTION DATA DS0– 32 DS0+ 33 DS1– 35 DS1+ 36 DS2– 38 DS2+ 39 DS3– 41 DS3+ 42 DS4– 44 DS4+ 45 DS5–/NCO_0 47 DS5+/NCO_0 48 DS6−/NCO_1 50 DS6+/NCO_1 51 DS7−/NCO_2 53 VD12 VA19 + 50 50 ± O Data CML These pins are the high-speed serialized-data outputs with user-configurable pre-emphasis. These outputs must always be terminated with a 100-Ω differential resistor at the receiver. GND Data VA19 VD12 50 + 50 ± O/I OE DS7+/NCO_2 54 GND DS5–/NCO_0, DS5+/NCO_0, DS6–/NCO_1, DS6+/NCO_1, DS7–/NCO_2 and DS7+/NCO_2: When decimation is enabled, these pins become LVCMOS inputs and allow the host device to select the specific NCO frequency or phase accumulator that is active. In this mode the positive (+) and negative (–) pins should be connected together and both driven. An acceptable alternative is to let one of the pair float while the other pin is driven. Connect these inputs to GND if they are not used in the application. GROUND, RESERVED, DNC — Do Not Connect Do not connect DNC to any circuitry, power, or ground signals. 66 — Reserved Connect to Ground or Leave Unconnected: This reserved pin is a logic input for possible future device versions. It is recommended to connect this pin to ground. Floating this pin is also permissible. 61 — Reserved Connect to Ground Connect this reserved input pin to ground for proper operation. — Ground (GND) The exposed pad on the bottom of the package is the ground return for all supplies. This pad must be connected with multiple vias to the printed circuit board (PCB) ground planes to ensure proper electrical and thermal performance. The exposed center pad on the bottom of the package must be thermally and electrically connected (soldered) to a ground plane to ensure rated performance. O Over-Range Over-range detection status for T0 and T1 thresholds. Leave these pins unconnected if they are not used in the application. DNC 67 RSV RSV2 VA19 GND Thermal Pad LVCMOS OR_T0 OR_T1 25 VA19 26 GND Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 5 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Pin Functions (continued) PIN NAME NO. SCLK 58 EQUIVALENT CIRCUIT TYPE I Serial Interface Clock This pin functions as the serial-interface clock input which clocks the serial data in and out. The Using the Serial Interface section describes the serial interface in more detail. I Serial Data In This pin functions as the serial-interface data input. The Using the Serial Interface section describes the serial interface in more detail. I SYNC~ This pin provides the JESD204B-required synchronizing request input. A logic-low applied to this input initiates a lane alignment sequence. The choice of LVCMOS or differential SYNC~ is selected through bit 6 of the configuration register 0x202h. Connect this input to GND or VA19 if differential SYNC~ input is used. I Serial Chip Select (active low) This pin functions as the serial-interface chip select. The Using the Serial Interface section describes the serial interface in more detail. O Serial Data Out This pin functions as the serial-interface data output. The Using the Serial Interface section describes the serial interface in more detail. I Device Clock Input The differential device clock signal must be AC coupled to these pins. The input signal is sampled on the rising edge of CLK. I SYSREF The differential periodic waveform on these pins synchronizes the device per JESD204B. If JESD204B subclass 1 synchronization is not required and these inputs are not utilized they may be left unconnected. In that case ensure SysRef_Rcvr_En=0 and SysRef_Pr_En=0. I SYNC~/TMST This differential input provides the JESD204B-required synchronizing request input. A differential logic-low applied to these inputs initiates a lane alignment sequence. For differential SYNC~ usage, ensure that SYNC_DIFF_PD = 0 and SYNC_DIFFSEL = 1. When the LVCMOS SYNC~ is selected these inputs can be used as the differential TIMESTAMP input. For TMST usage, ensure that SYNC_DIFF_PD = 0, SYNC_DIFFSEL = 0, and TIME_STAMP_EN = 1. For additional information see the Time Stamp section. These inputs may be left unconnected if they are not used for either the SYNC~ or TIMESTAMP functions. VA19 SDI 57 SYNC~ 30 SCS 59 DESCRIPTION GND VA19 SDO 56 GND DIFFERENTIAL INPUT DEVCLK+ 15 DEVCLK– 16 SYSREF+ 19 SYSREF– 20 SYNC~+/TMST+ 22 VA19 AGND 50 1k V(CM_CLK) VA19 50 SYNC~-/TMST– 23 AGND 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Pin Functions (continued) PIN NAME NO. EQUIVALENT CIRCUIT TYPE DESCRIPTION — Analog 1.2 V power supply pins Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling. — Analog 1.9 V power supply pins Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling. — Digital 1.2 V power supply pins Bypass these pins to ground using one 10-µF capacitor and two 1-µF capacitors for bulk decoupling plus one 0.1-µF capacitor per pin for individual decoupling. I VNEG These pins must be decoupled to ground with a 0.1-µF ceramic capacitor near each pin. These power input pins must be connected to the VNEG_OUT pin with a low resistance path. The connections must be isolated from any noisy digital signals and must also be isolated from the analog input and clock input pins. O VNEG_OUT The voltage on this output can range from –1V to +1V. This pin must be decoupled to ground with a 4.7-µF, low ESL, low ESR multi-layer ceramic chip capacitor and connected to the VNEG input pins. This voltage must be isolated from any noisy digital signals, clocks, and the analog input. POWER 6 11 14 VA12 17 18 21 65 4 7 10 VA19 13 24 27 60 62 28 31 34 37 VD12 40 43 46 49 52 55 5 VNEG VNEG_OUT 12 29 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 7 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings The soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (1) (2) (3) MIN Supply voltage Voltage 1.2-V supply VA12, VD12 1.9-V supply VA19 RF input power, PI Junction temperature, TJ 2.2 V 200 mV On any input pin (except VIN+ or VIN–) –0.15 V(VA19) + 0.15 V 0 2 V |(VIN+) – (VIN–)| (4) 2 |(DEVCLK+) – (DEVCLK–)| 2 |(SYSREF+) – (SYSREF–)| 2 |(~SYNC+) – (~SYNC–)| 1 On VIN+, VIN–, with proper input common mode maintained. FIN ≥ 3 GHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 0 or 1 11.07 On VIN+, VIN–, with proper input common mode maintained. FIN = 1 GHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1 14.95 On VIN+, VIN–, with proper input common mode maintained. FIN ≤ 100 MHz, Z(SOURCE) = 100 Ω, Input_Clamp_EN = 1 20.97 (5) VIN+ or VIN– Power applied. Verified by High Temperature Operation Life testing to 1000 hours. (3) (4) V dBm –25 25 mA –50 50 mA DC 100 mA –40 150 °C –65 150 °C Package (5) (sum of absolute value of all currents forced in or out, not including power supply current) Storage temperature, Tstg (1) (2) V –200 At any pin other than VIN+ or VIN– Input current UNIT 1.4 1.2-V supply difference between VA12 and VD12 On VIN+ or VIN– Voltage difference MAX Reflow temperature profiles are different for lead-free and non-lead-free packages. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The analog inputs are protected as in the following circuit. Input-voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. VA19 To Internal Circuitry I/O GND (5) 8 When the input voltage at any pin (other than VIN+ or VIN–) exceeds the power supply limits (that is, less than GND or greater than VA19), the current at that pin must be limited to 25 mA. The 100-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies. This limit is not placed upon the power pins or thermal pad (GND). Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions All voltages are measured with respect to GND = 0 V, unless otherwise specified. VDD MIN MAX UNIT 1.14 1.26 V 1.8 2 V 1.9 supply ≥ 1.2 supply V V(VCMO) – 0.15 V(VCMO) + 0.15 V 0 V(VA19) V 1.2-V supply: VA12, VD12 Supply voltage 1.9-V supply: VA19 Supply sequence (power-up and power-down) VCMI Analog input common mode voltage VIN+, VIN– voltage (maintaining common mode) DEVCLK±, SYSREF±, ~SYNC± pin voltage range 0 V(VA19) 0.4 2 SYSREF±, ~SYNC± Common Mode 0.64 1.1 V Ambient temperature –40 85 °C 135 °C VID(CLK) Differential DEVCLK±, SYSREF±, ~SYNC± amplitude VCM(CLK) TA TJ Junction temperature V VPP 6.4 Thermal Information ADC12J1x00 THERMAL METRIC (1) NKE (VQFN) UNIT 68 PINS RθJA Thermal resistance, junction-to-ambient 19.8 °C/W RθJCbot Thermal resistance, junction-to-case (bottom) 2.7 °C/W ψJB Characterization parameter, junction-to-board 9.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C. (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE CHARACTERISTICS RES ADC core resolution INL Integral non-linearity DNL Differential non-linearity Resolution with no missing codes 12 TA = 25°C ±2 TA = TMIN to TMAX ±3 TA = 25°C TA = TMIN to TMAX Peak NPR Peak noise power ratio 500-kHz tone spacing from 1 MHz to ƒS / 2−1 MHz, DDC bypass mode 25-MHz wide notch at 320 MHz IMD3 Third-order intermodulation distortion F1 = 2110 MHz at −13 dBFS F2 = 2170 MHz at −13 dBFS (1) (2) bits LSB ±0.25 LSB ±0.3 46 dB –64 dBc To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or more bypass capacitors. Interleave related fixed frequency spurs at ƒS / 4 and ƒS / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The magnitude of these spurs is provided separately. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 9 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DDC BYPASS Mode, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55.1 TA = 25°C SNR Signal-to-noise ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 54.9 TA = TMIN to TMAX 52.5 TA = 25°C, calibration = BG TA = TMIN to TMAX, calibration = BG 54.8 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.5 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 50 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55 TA = 25°C SINAD Signal-to-noise and distortion ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 54.8 TA = TMIN to TMAX 52.3 TA = 25°C, calibration = BG TA = TMIN to TMAX, calibration = BG 54.7 52.4 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 50 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 8.8 TA = 25°C ENOB FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 8.8 TA = TMIN to TMAX 8.4 TA = 25°C, calibration = BG TA = TMIN to TMAX, calibration = BG 8.8 8.4 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 8 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 66.7 TA = 25°C Spurious-free dynamic range Input frequency-dependent interleaving spurs included FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 71.6 TA = TMIN to TMAX 61 TA = 25°C, calibration = BG TA = TMIN to TMAX, calibration = BG ƒS/2 70 65.2 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 58.6 FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –77 TA = TMIN to TMAX –59.5 dBFS TA = 25°C, calibration = BG –74 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/4 Interleaving offset spur at ¼ sampling rate FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –57.5 –70 TA = TMIN to TMAX –54.5 dBFS TA = 25°C, calibration = BG –68 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/2 – FIN Interleaving offset spur at ½ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –53 –78 TA = TMIN to TMAX –62 dBFS TA = 25°C, calibration = BG –76 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/4 + FIN Interleaving offset spur at ¼ sampling rate + input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –61 –76 TA = TMIN to TMAX –61 dBFS TA = 25°C, calibration = BG –71 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/4 – FIN Interleaving offset spur at ¼ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode Submit Documentation Feedback –59 –77 TA = TMIN to TMAX –61.4 dBFS TA = 25°C, calibration = BG TA = TMIN to TMAX, calibration = BG 10 dBFS 59 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C Interleaving offset spur at ½ sampling rate Bits 8.4 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode SFDR dBFS 52.2 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode Effective number of bits, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included dBFS 52.4 –76 –61 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS MIN FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode THD Total harmonic distortion –61 TA = 25°C, calibration = BG –72 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –68 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –68 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –72 FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –79 TA = TMIN to TMAX –62 TA = 25°C, calibration = BG –81 TA = TMIN to TMAX, calibration = BG –76 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –70 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –72 TA = 25°C HD3 Third harmonic distortion dBFS –64 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode dBFS –62 TA = 25°C Second harmonic distortion –75 TA = TMIN to TMAX –63 TA = 25°C, calibration = BG –81 TA = TMIN to TMAX, calibration = BG dBFS –64 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –70 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –76 –147.3 NSD Noise spectral density, average NSD across Nyquist bandwidth UNIT –70 TA = TMIN to TMAX TA = TMIN to TMAX, calibration = BG HD2 MAX –73 TA = 25°C FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TYP dBFS/Hz 50-Ω AC-coupled terminated input 12-bit DDC bypass mode, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz FIN = 600 MHz, –1 dBFS –149.1 dBm/Hz –146.2 dBFS/Hz –148.0 dBm/Hz DDC BYPASS MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55.3 TA = 25°C SNR Signal-to-noise ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 54.9 TA = TMIN to TMAX 52.3 TA = 25°C, calibration = BG 54.8 TA = TMIN to TMAX, calibration = BG FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.5 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 49.8 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55.2 TA = 25°C SINAD Signal-to-noise and distortion ratio, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 54.8 TA = TMIN to TMAX 52.1 TA = 25°C, calibration = BG 54.7 TA = TMIN to TMAX, calibration = BG FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.4 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 49.7 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 8.9 ENOB FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode 8.8 TA = TMIN to TMAX 8.4 TA = 25°C, calibration = BG 8.8 TA = TMIN to TMAX, calibration = BG 8.4 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 8 Product Folder Links: ADC12J1600 ADC12J2700 Bits 8.4 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode Copyright © 2014–2015, Texas Instruments Incorporated dBFS 52 TA = 25°C Effective number of bits, integrated across entire Nyquist bandwidth Input frequency-dependent interleaving spurs included dBFS 52.2 Submit Documentation Feedback 11 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS MIN FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode SFDR Spurious-free dynamic range Input frequency-dependent interleaving spurs included Interleaving offset spur at ½ sampling rate 61.8 TA = 25°C, calibration = BG 71 TA = TMIN to TMAX, calibration = BG 66.7 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 59.8 –77 TA = TMIN to TMAX –59.8 dBFS TA = 25°C, calibration = BG –73 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/4 Interleaving offset spur at ¼ sampling rate FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –57.3 –72 TA = TMIN to TMAX –54.3 dBFS TA = 25°C, calibration = BG –69 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/2 – FIN Interleaving offset spur at ½ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –54 –77 TA = TMIN to TMAX –62 dBFS TA = 25°C, calibration = BG –79 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/4 + FIN Interleaving offset spur at ¼ sampling rate + input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –62 –76 TA = TMIN to TMAX –61.8 dBFS TA = 25°C, calibration = BG –74 TA = TMIN to TMAX, calibration = BG TA = 25°C ƒS/4 – FIN Interleaving offset spur at ¼ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –61 –76 TA = TMIN to TMAX –62 dBFS TA = 25°C, calibration = BG –77 TA = TMIN to TMAX, calibration = BG FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode Total harmonic distortion FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –61 –72 TA = 25°C THD –72 TA = TMIN to TMAX –60.9 TA = 25°C, calibration = BG –71 TA = TMIN to TMAX, calibration = BG –69 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –69 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –79 TA = 25°C HD2 Second harmonic distortion –78 TA = TMIN to TMAX –62 TA = 25°C, calibration = BG –79 TA = TMIN to TMAX, calibration = BG Third harmonic distortion –73 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –70 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –76 FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode –81 TA = TMIN to TMAX –65 TA = 25°C, calibration = BG –76 TA = TMIN to TMAX, calibration = BG 12 dBFS –61 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –72 FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –76 Submit Documentation Feedback dBFS –63 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C HD3 dBFS –61 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode dBFS 60.7 FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode UNIT 74.8 TA = TMIN to TMAX TA = 25°C ƒS/2 MAX 72.9 TA = 25°C FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TYP Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX –145 Noise spectral density, average NSD across Nyquist bandwidth NSD UNIT dBFS/Hz 50-Ω AC-coupled terminated input 12-bit DDC bypass mode, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz FIN = 600 MHz, –1 dBFS –146.8 dBm/Hz –143.9 dBFS/Hz –145.7 dBm/Hz DECIMATE-BY-8 MODE, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz 62.8 Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode FIN = 2400 MHz, –1 dBFS, Decimate-by-8 mode 53.3 Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 62.8 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 53.3 Effective number of bits, integrated across DDC output bandwidth Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 10.1 Spurious-free dynamic range Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/2 Interleaving offset spur at ½ sampling rate (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/4 Interleaving offset spur at ¼ sampling rate (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/2 – FIN Interleaving spur at ½ sampling rate – input frequency (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/4 + FIN Interleaving spur at ¼ sampling rate + input frequency (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/4 – FIN Interleaving spur at ¼ sampling rate – input frequency (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG THD Total harmonic distortion (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode calibration = BG SNR SINAD ENOB SFDR Second harmonic distortion (3) HD2 Third harmonic distortion (3) HD3 Calibration = BG Calibration = BG Calibration = BG FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 62.7 62.7 10.1 dBFS dBFS Bits 8.6 75.9 dBFS 74.7 –73 dBFS –72 –70 dBFS –70 –80 dBFS –79 –73 dBFS –70 –77 dBFS –77 –70 –71 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –65 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –78 Calibration = BG –76 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –67 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –74 Calibration = BG FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –81 dBFS dBFS dBFS –73 DECIMATE-BY-8 MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz SNR SINAD ENOB SFDR ƒS/2 (3) 63.5 Signal-to-noise ratio, integrated across DDC output bandwidth Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 55.8 Signal-to-noise and distortion ratio, integrated across DDC output bandwidth Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 63.5 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 55.8 Effective number of bits, integrated across DDC output bandwidth Interleaving spurs included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 10.3 Spurious-free dynamic range Interleaving Spurs Included FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG Interleaving offset spur at ½ sampling rate (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG Calibration = BG Calibration = BG Calibration = BG FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 63.4 63.4 10.2 dBFS dBFS Bits 9.0 76.2 dBFS 76.7 –73 dBFS –72 Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 13 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS ƒS/4 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode ƒS/2 – FIN Interleaving spur at ½ sampling rate – input frequency (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/4 + FIN Interleaving spur at ¼ sampling rate + input frequency (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG ƒS/4 – FIN Interleaving spur at ¼ sampling rate – input frequency (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG THD Total harmonic distortion (3) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode Calibration = BG Second harmonic distortion (3) HD2 Third harmonic distortion (3) HD3 MIN TYP MAX UNIT –70 Interleaving offset spur at ¼ sampling rate (3) dBFS Calibration = BG –69 –78 dBFS –79 –76 dBFS –77 –77 dBFS –72 –71 –71 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –63 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –77 Calibration = BG dBFS –78 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –65 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –80 Calibration = BG dBFS –77 FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode dBFS –74 DDC CHARACTERISTICS Alias protection (4) Alias protected bandwidth SFDR-DDC (4) Spurious-free dynamic range of digital down-converter (4) 80 dB 80 % of output BW 100 dB Implementation loss (4) 0.5 dB 800 mVPP ANALOG INPUT CHARACTERISTICS Minimum FSR setting (5) Full-scale analog-differential input range VID(VIN) CI(VIN) Analog input capacitance (4) RID(VIN) Differential input resistance 500 Default FSR setting, TA = TMIN to TMAX 650 950 Differential 0.05 Each input pin to ground FPBW 725 Maximum FSR setting (5) pF 1.5 80 95 –3 dB — calibration = BG 2.8 –3 dB — calibration = FG 3.2 DC to 2 GHz 1.2 2 GHz to 4 GHz 3.8 DC to 2 GHz — calibration = BG 1.5 2 GHz to 4 GHz — calibration = BG 4.5 pF 110 Full power bandwidth Ω GHz Gain flatness dB ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG) I(VCMO) = ±100 µA, TA = 25°C V(VCMO) Common-mode output voltage TCVO(VCMO) Common-mode outputvoltage temperature coefficient C(LOAD_VCMO) Maximum VCMO output load capacitance VO(BG) Bandgap reference output voltage I(BG) = ±100 µA, TA = 25°C TCVref(BG) Bandgap reference voltage temperature coefficient TA = TMIN to TMAX, I(BG) = ±100 µA C(LOAD_BG) Maximum bandgap reference output load capacitance (4) (5) 14 1.225 V I(VCMO) = ±100 µA, TA = TMIN to TMAX 1.185 TA = TMIN to TMAX 1.265 -21 ppm/°C 80 pF 1.248 V I(BG) = ±100 µA, TA = TMIN to TMAX 1.195 1.3 0 ppm/°C 80 pF This parameter is specified by design and is not tested in production. This parameter is specified by design, characterization, or both and is not tested in production. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE DIODE CHARACTERISTICS V(TDIODE) Temperature diode voltage slope Offset voltage (approx. 0.77 V) varies with process and must be measured for each part. Offset measurement should be done with PowerDown=1 to minimize device selfheating. 100-µA forward current Device active –1.6 mV/°C 100-µA forward current Device in power-down –1.6 mV/°C CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~/TMST±) VID(CLK) Differential clock input level II(CLK) Input current CI(CLK) RID(CLK) Input capacitance Sine wave clock, TA = TMIN to TMAX 0.4 0.6 2 VPP Square wave clock, TA = TMIN to TMAX 0.4 0.6 2 VPP VI = 0 or VI = VA (4) Differential Each input to ground Differential input resistance TA = 25°C TA = TMIN to TMAX ±1 µA 0.02 pF 1 pF Ω 95 80 110 Ω 330 mV peak CML OUTPUT CHARACTERISTICS (DS0–DS7±) VOD Differential output voltage VO(ofs) Output offset voltage IOS Output short-circuit current ZOD Differential output impedance Assumes ideal 100-Ω load Measured differentially Default pre-emphasis setting 280 305 0.6 Output+ and output– shorted together ±6 Output+ or output– shorted to 0 V 12 V mA Ω 100 LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~) VIH Logic high input voltage See (5) VIL Logic low input voltage See (5) CI Input capacitance (4) (6) Each input to ground 0.83 V 0.4 1 V pF LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1) VOH CMOS H level output IOH = –400 µA (5) VOL CMOS L level output IOH = 400 µA (5) 0.01 0.15 PD = 0, calibration = FG, bypass DDC 457 495 PD = 0, calibration = BG, bypass DDC 557 594 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 557 598 PD = 0, calibration = FG, bypass DDC 245 296 PD = 0, calibration = BG, bypass DDC 261 312 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 270 322 PD = 0, calibration = FG, bypass DDC 330 541 PD = 0, calibration = BG, bypass DDC 341 588 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 366 610 PD = 0, calibration = FG, bypass DDC 1.56 1.94 PD = 0, calibration = BG, bypass DDC 1.78 2.21 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 1.82 2.25 PD = 1 < 50 1.65 1.9 V V POWER SUPPLY CHARACTERISTICS ADC12J2700, ƒ(DEVCLK) = 2.7 GHz I(VA19) I(VA12) I(VD12) PC (6) Analog 1.9-V supply current Analog 1.2-V supply current Digital 1.2-V supply current mA mA mA W Power consumption mW The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately 0.4 pF. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 15 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX PD = 0, calibration = FG, bypass DDC 454 493 PD = 0, calibration = BG, bypass DDC 553 591 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 553 598 PD = 0, calibration = FG, bypass DDC 180 222 PD = 0, calibration = BG, bypass DDC 190 233 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 196 243 PD = 0, calibration = FG, bypass DDC 225 460 PD = 0, calibration = BG, bypass DDC 237 529 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 255 568 PD = 0, calibration = FG, bypass DDC 1.35 1.75 PD = 0, calibration = BG, bypass DDC 1.56 2.04 PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 1.59 2.11 PD = 1 < 50 UNIT ADC12J1600, ƒ(DEVCLK) = 1.6 GHz I(VA19) Analog 1.9-V supply current I(VA12) Analog 1.2-V supply current I(VD12) Digital 1.2-V supply current PC mA mA mA W Power consumption mW 6.6 Timing Requirements MIN NOM MAX UNIT DEVICE (SAMPLING) CLOCK ƒ(DEVCLK) Input DEVCLK frequency td(A) Sampling (aperture) delay t(AJ) Aperture jitter t(LAT) ADC core latency (1) t(LAT_DDC) (1) 16 ADC core and DDC latency (1) Sampling rate is equal to clock input, ADC12J2700 1 2.7 Sampling rate is equal to clock input, ADC12J1600 1 1.6 Input CLK transition to sampling instant GHz 0.64 ns 0.1 ps RMS Decimation = 1, DDR = 1, P54 = 0 64 t(DEVCLK) Decimation = 4, DDR = 1, P54 = 0 292 Decimation = 4, DDR = 1, P54 = 1 284 Decimation = 8, DDR = 0, P54 = 0 384 Decimation = 8, DDR = 0, P54 = 1 368 Decimation = 8, DDR = 1, P54 = 0 392 Decimation = 8, DDR = 1, P54 = 1 368 Decimation = 10, DDR = 0, P54 = 0 386 Decimation = 10, DDR = 1, P54 = 0 386 Decimation = 16, DDR = 0, P54 = 0 608 Decimation = 16, DDR = 0, P54 = 1 560 Decimation = 16, DDR = 1, P54 = 0 608 Decimation = 16, DDR = 1, P54 = 1 560 Decimation = 20, DDR = 0, P54 = 0 568 Decimation = 20, DDR = 1, P54 = 0 568 Decimation = 32, DDR = 0, P54 = 0 1044 Decimation = 32, DDR = 0, P54 = 1 948 Decimation = 32, DDR = 1, P54 = 0 1044 t(DEVCLK) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay). Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Timing Requirements (continued) MIN NOM MAX UNIT JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1) td(LMFC) SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary (1) td(TX) All decimation modes 40 t(DEVCLK) LMFC to frame boundary delay - DDC bypass mode Functional delay from LMFC frame boundary Decimation = 1, DDR = 1, P54 = 0 to beginning of next multi-frame in transmitted data. (2) 52.7 t(DEVCLK) Decimation = 4, DDR = 1, P54 = 0 52.7 Decimation = 4, DDR = 1, P54 = 1 43.9 Decimation = 8, DDR = 0, P54 = 0 60.7 Decimation = 8, DDR = 0, P54 = 1 51.5 Decimation = 8, DDR = 1, P54 = 0 52.7 Decimation = 8, DDR = 1, P54 = 1 43.9 Decimation = 10, DDR = 0, P54 = 0 60.7 LMFC to frame boundary delay - decimation Decimation = 10, DDR = 1, P54 modes Functional delay from LMFC frame boundary Decimation = 16, DDR = 0, P54 to beginning of next multi-frame in Decimation = 16, DDR = 0, P54 transmitted data (2) Decimation = 16, DDR = 1, P54 td(TX) tsu(SYNC~F) th(SYNC~F) =0 52.7 =0 60.7 =1 51.5 =0 52.7 Decimation = 16, DDR = 1, P54 = 1 43.9 Decimation = 20, DDR = 0, P54 = 0 60.7 Decimation = 20, DDR = 1, P54 = 0 52.7 Decimation = 32, DDR = 0, P54 = 0 60.7 Decimation = 32, DDR = 0, P54 = 1 51.5 Decimation = 32, DDR = 1, P54 = 0 52.7 SYNC~ to LMFC setup time (3) Required SYNC~ setup time relative to the internal LMFC boundary. 40 SYNC~ to LMFC hold time (3) Required SYNC~ hold time relative to the internal LMFC boundary. –8 t(SYNC~) SYNC~ assertion time Required SYNC~ assertion time before deassertion to initiate a link resynchronization. td(LMFC) Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary t(ILA) t(DEVCLK) t(DEVCLK) 4 Duration of initial lane alignment sequence Frame clock cycles 40 t(DEVCLK) 4 Multi-frame clock cycles ps SYSREF tsu(SYS) Setup time SYSREF relative to DEVCLK rising edge (4) 40 th(SYS) Hold time SYSREF relative to DEVCLK rising edge (4) 40 t(PH_SYS) SYSREF assertion duration after rising edge event. 8 t(PL_SYS) SYSREF deassertion duration after falling edge event. 8 t(SYS) (2) (3) (4) t(DEVCLK) DDR = 0, P54 = 0 K×F× 10 DDR = 0, P54 = 1 K×F× 8 DDR = 1, P54 = 0 K×F× 5 DDR = 1, P54 = 1 K×F× 4 Period SYSREF± ps t(DEVCLK) t(DEVCLK) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present. This parameter must be met to achieve deterministic alignment of the data frame and NCO phase to other similar devices. If this parameter is not met the device will still function correctly but will not be aligned to other devices. This parameter is specified by design, characterization, or both and is not tested in production. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 17 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Timing Requirements (continued) MIN NOM MAX UNIT 20 MHz SERIAL INTERFACE (REFER TO Figure 2) ƒ(SCK) Serial clock frequency (5) t(PH) Serial clock high time 20 ns t(PL) Serial clock low time 20 ns tsu Serial-data to serial-clock rising setup time (5) 10 ns th Serial-data to serial clock rising hold time (5) 10 ns t(CSS) SCS-to-serial clock rising setup time 10 ns t(CSH) SCS-to-serial clock falling hold time 10 ns t(IAG) Inter-access gap 10 ns (5) This parameter is specified by design and is not tested in production. 6.7 Internal Characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DEVICE (SAMPLING) CLOCK td(A) Sampling (aperture) delay t(AJ) Aperture jitter t(LAT) ADC core latency. See Input CLK transition to sampling instant (1) Decimation = 1, DDR = 1, P54 = 0 0.64 ns 0.1 ps RMS 64 t(DEVCLK) CALIBRATION TIMING CHARACTERISTICS (REFER TO THE CALIBRATION SECTION) t(CAL) Calibration = FG, T_AUTO=1 227 × 106 Calibration = FG, T_AUTO=0 102 × 106 Calibration cycle time t(DEVCLK) JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1) td(LMFC) SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary (1) All decimation modes td(TX) LMFC to Frame Boundary delay - DDC Bypass Mode Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data (2) LMFC to frame boundary delay - decimation modes Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data (2) td(TX) td(LMFC) t(ILA) (1) (2) 18 40 t(DEVCLK) Decimation = 1, DDR = 1, P54 = 0 52.7 t(DEVCLK) Decimation = 4, DDR = 1, P54 = 0 52.7 Decimation = 4, DDR = 1, P54 = 1 43.9 Decimation = 8, DDR = 0, P54 = 0 60.7 Decimation = 8, DDR = 0, P54 = 1 51.5 Decimation = 8, DDR = 1, P54 = 0 52.7 Decimation = 8, DDR = 1, P54 = 1 43.9 Decimation = 10, DDR = 0, P54 = 0 60.7 Decimation = 10, DDR = 1, P54 = 0 52.7 Decimation = 16, DDR = 0, P54 = 0 60.7 Decimation = 16, DDR = 0, P54 = 1 51.5 Decimation = 16, DDR = 1, P54 = 0 52.7 Decimation = 16, DDR = 1, P54 = 1 43.9 Decimation = 20, DDR = 0, P54 = 0 60.7 Decimation = 20, DDR = 1, P54 = 0 52.7 Decimation = 32, DDR = 0, P54 = 0 60.7 Decimation = 32, DDR = 0, P54 = 1 51.5 Decimation = 32, DDR = 1, P54 = 0 52.7 Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary Duration of initial lane alignment sequence t(DEVCLK) 40 t(DEVCLK) 4 Multi-frame clock cycles Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay). The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 6.8 Switching Characteristics Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground mode calibration with timing calibration enabled. Typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL DATA OUTPUTS Serialized output bit rate 1 Serialized output bit rate 10 DDR = 0, P54 = 0 ƒS DDR = 0, P54 = 1 1.25 × ƒS DDR = 1, P54 = 0 2 × ƒS DDR = 1, P54 = 1 2.5 × ƒS Gbps tTLH LH transition time — differential 10% to 90%, 8 Gbps 35 ps tTHL HL transition time — differential 10% to 90%, 8 Gbps 35 ps UI Unit interval 8 Gbps serial rate 125 ps DDJ Data dependent jitter 8 Gbps serial rate 11.3 ps RJ Random Jitter 8 Gbps serial rate 1.4 ps SERIAL INTERFACE t(OZD) SDO tri-state to driven t(ODZ) SDO driven to tri-state t(OD) SDO output delay See Figure 2 SYSREF assertion SYNC~ assertion latched latched 2.5 5 ns 5 ns 20 ns SYNC~ de-assertion latched t(SYNC~) tsu(SYNC~-F) th(-SYNC~-F) SYNC~ t(ILA) Serial Data XXX th(SYS) XXX K28.5 K28.5 ILA td(TX) tsu(SYS) ILA Valid Data td(TX) DEVCLK t(PL-SYS) SYSREF t(PH-SYS) Tx Frame Clk Tx LMFC Boundary td(LMFC) Code Group Synchronization Frame Clock Alignment Initial Frame and Lane Synchronization Data Transmission Figure 1. JESD204 Synchronization st 1 clock th 16 th clock 24 clock SCLK t(CSH) t(PH) t(CSS) t(CSS) t(PL) t(CSH) t(IAG) t(PH) + t(PL) = t(P) = 1 / ¦(SCK) SCS tsu th tsu SDI D7 D1 th D0 Write Command COMMAND FIELD t(OD) SDO Hi-Z D7 t(OZD) D1 D0 Read Command Hi-Z t(ODZ) Figure 2. Serial Interface Timing Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 19 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 6.9 Typical Characteristics Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 10 80 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 9 70 ENOB (Bits) Magnitude (dBFS) 75 65 60 8 7 55 6 50 45 1500 2000 2500 Sampling Rate (MSPS) DDC bypass mode 5 1500 3000 2000 2500 Sampling Rate (MSPS) D120 DDC bypass mode FIN = 608 MHz 1.8 VA19 VA12 VD12 0.5 Supply Current (A) Power Consumption (W) 0.6 1.6 1.4 1.2 0.4 0.3 0.2 1 1500 2000 2500 Sampling Rate (MSPS) DDC bypass mode 0.1 1500 3000 2000 2500 Sampling Rate (MSPS) D124 FIN = 608 MHz DDC bypass mode Figure 5. Power Consumption vs Sampling Rate 3000 D123 FIN = 608 MHz Figure 6. Supply Current vs Sampling Rate 100 80 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 75 70 65 60 55 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 90 Magnitude (dBFS) Magnitude (dBFS) D122 FIN = 608 MHz Figure 4. ENOB vs Sampling Rate Figure 3. SNR, SINAD, SFDR vs Sampling Rate 2 80 70 60 50 50 40 45 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 Input Frequency (MHz) D073 ADC12J2700 DDC bypass mode Figure 7. SNR, SINAD, SFDR vs Input Frequency 20 3000 Submit Documentation Feedback 0 4 8 ADC12J2700 12 16 20 Decimation Factor 24 28 32 D086 FIN = 608 MHz Figure 8. SNR, SINAD, SFDR vs Decimation Setting Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 100 80 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) Magnitude (dBFS) Magnitude (dBFS) 90 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 75 80 70 60 50 70 65 60 55 50 40 0 4 8 12 16 20 Decimation Factor 24 28 45 -10 32 D091 ADC12J2700 FIN = 2483 MHz ADC12J2700 Figure 9. SNR, SINAD, SFDR vs Decimation Setting DDC bypass mode 10 D076 FIN = 608 MHz Figure 10. SNR, SINAD, SFDR vs Supply Voltage 10 80 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 75 9 70 ENOB (Bits) Magnitude (dBFS) -5 0 5 All Supply Voltage Variation from Nominal (%) 65 60 8 7 55 6 50 45 -50 5 -25 0 25 50 Ambient Temperature (°C) ADC12J2700 75 100 0 300 DDC bypass mode FIN = 608 MHz 900 1200 1500 1800 2100 2400 2700 3000 Input Frequency (MHz) D075 ADC12J2700 Figure 11. SNR, SINAD, SFDR vs Temperature DDC bypass mode Figure 12. ENOB vs Input Frequency 11 10 10 9 ENOB (Bits) ENOB (Bits) 600 D079 9 8 8 7 0 4 8 ADC12J2700 12 16 20 Decimation Factor 24 28 32 0 4 8 D088 FIN = 608 MHz Figure 13. ENOB vs Decimation Setting ADC12J2700 12 16 20 Decimation Factor 24 28 32 D093 FIN = 2483 MHz Figure 14. ENOB vs Decimation Setting Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 21 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) 10 10 9 9 ENOB (Bits) ENOB (Bits) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 8 7 6 8 7 6 5 -10 -5 0 5 All Supply Variation from Nominal (%) ADC12J2700 DDC bypass mode 5 -50 10 -25 FIN = 608 MHz ADC12J2700 Figure 15. ENOB vs Supply Voltage 100 D080 DDC bypass mode FIN = 608 MHz THD (dBFS) HD2 (dBFS) HD3 (dBFS) -60 Magnitude (dBFS) Magnitude (dBFS) 75 -50 THD (dBFS) HD2 (dBFS) HD3 (dBFS) -60 -70 -80 -90 -70 -80 -90 -100 0 300 600 -100 -10 900 1200 1500 1800 2100 2400 2700 3000 Input Frequency (MHz) D074 ADC12J2700 DDC bypass mode Figure 17. THD, H2, H3 vs Input Frequency DDC bypass mode 10 D078 FIN = 608 MHz Figure 18. THD, H2, H3 vs Supply Voltage 1.9 THD (dBFS) HD2 (dBFS) HD3 (dBFS) Power Consumption (W) -60 -70 -80 -90 -100 -50 -5 0 5 All Supply Variation from Nominal (%) ADC12J2700 -50 Magnitude (dBFS) 25 50 Temperature (°C) Figure 16. ENOB vs Temperature ADC12J2700 -50 1.8 1.7 1.6 1.5 1.4 -25 ADC12J2700 0 25 50 Temperature (°C) DDC bypass mode 75 Submit Documentation Feedback 100 0 4 8 D081 FIN = 608 MHz Figure 19. THD, H2, H3 vs Temperature 22 0 D077 ADC12J2700 12 16 20 Decimation Factor 24 28 32 D089 FIN = 608 MHz Figure 20. Power Consumption vs Decimation Setting Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 1.8 1.7 Power Consumption (W) Power Consumption (W) 1.8 1.6 1.5 1.4 1.3 -10 -5 0 5 All Supply Voltage Variation from Nominal (%) ADC12J2700 DDC bypass mode 1.6 1.4 1.2 -50 10 FIN = 608 MHz Figure 21. Power Consumption vs Supply Voltage DDC bypass mode 75 100 D084 FIN = 608 MHz Figure 22. Power Consumption vs Temperature 0.6 VA19 VA12 VD12 VA19 VA12 VD12 0.5 Supply Current (A) 0.5 Supply Current (A) 0 25 50 Ambient Temperature (°C) ADC12J2700 0.6 0.4 0.3 0.2 0.4 0.3 0.2 0.1 0 4 8 12 16 20 Decimation Factor 24 28 0.1 -10 32 -5 0 5 All Supply Voltage Variation from Nominal (%) D090 ADC12J2700 FIN = 608 MHz ADC12J2700 Figure 23. Supply Current vs Decimation Setting DDC bypass mode 10 D083 FIN = 608 MHz Figure 24. Supply Current vs Supply Voltage 0.6 80 VA19 VA12 VD12 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 75 Magnitude (dBFS) 0.5 Supply Current (A) -25 D082 0.4 0.3 70 65 60 55 0.2 50 0.1 -50 45 -25 ADC12J2700 0 25 50 Ambient Temperature (°C) DDC bypass mode 75 100 D085 FIN = 608 MHz Figure 25. Supply Current vs Temperature 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 Input Frequency (MHz) D099 ADC12J1600 DDC bypass mode Figure 26. SNR, SINAD, SFDR vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 23 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 100 100 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 90 Magnitude (dBFS) Magnitude (dBFS) 90 80 70 60 50 80 70 60 50 40 40 0 4 8 12 16 20 Decimation Factor 24 28 32 0 4 8 12 16 20 Decimation Factor D112 ADC12J1600 FIN = 608 MHz ADC12J1600 Figure 27. SNR, SINAD, SFDR vs Decimation Setting 24 28 32 D117 FIN = 2483 MHz Figure 28. SNR, SINAD, SFDR vs Decimation Setting 80 80 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 75 SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 75 70 Magnitude (dBFS) Magnitude (dBFS) SNR (dBFS) SINAD (dBFS) SFDR (dBFS) 65 60 55 50 70 65 60 55 50 45 -10 -5 0 5 All Supply Voltage Variation from Nominal (%) ADC12J1600 DDC bypass mode 45 -50 10 -25 0 25 50 Ambient Temperature (°C) D043 D102 FIN = 608 MHz ADC12J1600 Figure 29. SNR, SINAD, SFDR vs Supply Voltage 75 100 D105 DDC bypass mode FIN = 608 MHz Figure 30. SNR, SINAD, SFDR vs Temperature 10 11 ENOB (Bits) ENOB (Bits) 9 8 7 10 9 6 5 8 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 Input Frequency (MHz) D101 ADC12J1600 DDC bypass mode Figure 31. ENOB vs Input Frequency 24 Submit Documentation Feedback 0 4 8 ADC12J1600 12 16 20 Decimation Factor 24 28 32 D114 FIN = 608 MHz Figure 32. ENOB vs Decimation Setting Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 10 10 9 ENOB (Bits) ENOB (Bits) 9 8 7 8 6 7 0 4 8 12 16 20 Decimation Factor 24 28 5 -10 32 -5 0 5 All Supply Variation from Nominal (%) D119 ADC12J1600 FIN = 2483 MHz ADC12J1600 Figure 33. ENOB vs Decimation Setting Figure 34. ENOB vs Supply Voltage Magnitude (dBFS) ENOB (Bits) THD (dBFS) HD2 (dBFS) HD3 (dBFS) -60 9 8 7 -70 -80 -90 6 -100 -25 0 ADC12J1600 25 50 Temperature (°C) 75 0 100 300 DDC bypass mode FIN = 608 MHz 900 1200 1500 1800 2100 2400 2700 3000 Input Frequency (MHz) D100 ADC12J1600 Figure 35. ENOB vs Temperature DDC bypass mode Figure 36. THD, H2, H3 vs Input Frequency -50 THD (dBFS) HD2 (dBFS) HD3 (dBFS) THD (dBFS) HD2 (dBFS) HD3 (dBFS) -60 Magnitude (dBFS) -60 Magnitude (dBFS) 600 D106 -50 -70 -80 -90 -100 -10 D103 FIN = 608 MHz -50 10 5 -50 DDC bypass mode 10 -70 -80 -90 -5 0 5 All Supply Variation from Nominal (%) ADC12J1600 DDC bypass mode 10 -100 -50 -25 D104 FIN = 608 MHz Figure 37. THD, H2, H3 vs Supply Voltage ADC12J1600 0 25 50 Temperature (°C) DDC bypass mode 75 100 D107 FIN = 608 MHz Figure 38. THD, H2, H3 vs Temperature Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 25 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) 1.7 1.6 1.6 1.5 Power Consumption (W) Power Consumption (W) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 1.5 1.4 1.3 1.2 0 4 8 12 16 20 Decimation Factor 24 28 1.4 1.3 1.2 1.1 -10 32 D115 ADC12J1600 FIN = 608 MHz ADC12J1600 Figure 39. Power Consumption vs Decimation Setting Figure 40. Power Consumption vs Supply Voltage Supply Current (A) Power Consumption (W) D108 FIN = 608 MHz VA19 VA12 VD12 0.5 1.4 1.3 0.4 0.3 0.2 1.2 -50 0.1 -25 ADC12J1600 0 25 50 Ambient Temperature (°C) DDC bypass mode 75 100 0 FIN = 608 MHz 8 12 16 20 Decimation Factor ADC12J1600 Figure 41. Power Consumption vs Temperature 24 28 32 D116 FIN = 608 MHz Figure 42. Supply Current vs Decimation Setting 0.6 VA19 VA12 VD12 VA19 VA12 VD12 0.5 Supply Current (A) 0.5 0.4 0.3 0.2 0.1 -10 4 D110 0.6 Supply Current (A) DDC bypass mode 10 0.6 1.5 0.4 0.3 0.2 -5 0 5 All Supply Voltage Variation from Nominal (%) ADC12J1600 DDC bypass mode Submit Documentation Feedback 10 0.1 -50 -25 D109 FIN = 608 MHz Figure 43. Supply Current vs Supply Voltage 26 -5 0 5 All Supply Voltage Variation from Nominal (%) ADC12J1600 0 25 50 Ambient Temperature (°C) DDC bypass mode 75 100 D111 FIN = 608 MHz Figure 44. Supply Current vs Temperature Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 6 6 Corrected for Setup Losses Raw Insertion Loss Curve Fit Corrected for Setup Losses Raw Insertion Loss Curve Fit 3 0 Insertion Loss (dB) Insertion Loss (dB) 3 -3 -6 -9 0 -3 -6 -9 -12 -12 -15 -15 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Input Frequency (MHz) D037 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Input Frequency (MHz) D038 Foreground calibration mode Background calibration mode Figure 45. Insertion Loss vs Input Frequency Figure 46. Insertion Loss vs Input Frequency 4 0.75 0.5 2 INL (LSB) DNL (LSB) 0.25 0 0 -0.25 -2 -0.5 -4 -0.75 0 0 4095 Output Code 4095 Output Code D069 Figure 47. DNL versus Code - ADC12J2700 D070 Figure 48. INL versus Code - ADC12J2700 0.75 4 0.5 2 INL (LSB) DNL (LSB) 0.25 0 0 -0.25 -2 -0.5 -0.75 -4 0 4095 Output Code 0 4095 Output Code D071 Figure 49. DNL versus Code - ADC12J1600 D072 Figure 50. INL versus Code - ADC12J1600 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 27 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 30 0.0025 Filter Response -80dB 0 0 Magnitude (dB) Magnitude (dB) -30 -60 -90 -0.0025 -0.005 -120 -0.0075 -150 -180 -0.01 0 0.1 0.2 0.3 0.4 Normalized to Filter Input Sample Rate 0.5 0 D055 Figure 51. Decimate by 4 - Stopband Response 0.025 0.05 0.075 0.1 Normalized to Filter Input Sample Rate 0.125 D056 Figure 52. Decimate by 4 - Passband Response 30 0.0025 Filter Response -80dB 0 0 Magnitude (dB) Magnitude (dB) -30 -60 -90 -0.0025 -0.005 -120 -0.0075 -150 -180 -0.01 0 0.1 0.2 0.3 0.4 Normalized to Filter Input Sample Rate 0.5 0 D057 Figure 53. Decimate by 8 - Stopband Response 0.01 0.02 0.03 0.04 0.05 Normalized to Filter Input Sample Rate 0.06 D058 Figure 54. Decimate by 8 - Passband Response 30 0.0025 Filter Response -80dB 0 0 Magnitude (dB) Magnitude (dB) -30 -60 -90 -0.0025 -0.005 -120 -0.0075 -150 -180 -0.01 0 0.1 0.2 0.3 0.4 Normalized to Filter Input Sample Rate 0.5 Figure 55. Decimate by 10 - Stopband Response 28 Submit Documentation Feedback D059 0 0.01 0.02 0.03 0.04 Normalized to Filter Input Sample Rate 0.05 D060 Figure 56. Decimate by 10 - Passband Response Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Characteristics (continued) Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) = Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS. 0.0025 30 Filter Response -80dB 0 0 Magnitude (dB) Magnitude (dB) -30 -60 -90 -0.0025 -0.005 -120 -0.0075 -150 -0.01 -180 0 0.1 0.2 0.3 0.4 Normalized to Filter Input Sample Rate 0 0.5 D061 Figure 57. Decimate by 16 - Stopband Response 0.006 0.012 0.018 0.024 Normalized to Filter Input Sample Rate 0.03 D062 Figure 58. Decimate by 16 - Passband Response 30 0.0025 Filter Response -80dB 0 0 Magnitude (dB) Magnitude (dB) -30 -60 -90 -0.0025 -0.005 -120 -0.0075 -150 -180 -0.01 0 0.1 0.2 0.3 0.4 Normalized to Filter Input Sample Rate 0.5 0 D063 Figure 59. Decimate by 20 - Stopband Response 0.005 0.01 0.015 0.02 Normalized to Filter Input Sample Rate 0.025 D064 Figure 60. Decimate by 20 - Passband Response 30 0.0025 Filter Response 0 0 Magnitude (dB) Magnitude (dB) -30 -60 -90 -0.0025 -0.005 -120 -0.0075 -150 -180 -0.01 0 0.1 0.2 0.3 0.4 Normalized to Filter Input Sample Rate 0.5 Figure 61. Decimate by 32 - Stopband Response D065 0 0.003 0.006 0.009 0.012 Normalized to Filter Input Sample Rate 0.015 D066 Figure 62. Decimate by 32 - Passband Response Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 29 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7 Detailed Description 7.1 Overview The ADC12J1600 and ADC12J2700 devices are an ultra-wideband sampling and digital tuning subsystem. The devices combine a very-wideband and high sampling-rate ADC front-end with a configurable digital-down conversion block. This combination provides the necessary features to facilitate the development of flexible software-defined radio products for a wide range of communications applications. The ADC12J1600 and ADC12J2700 devices are based on an ultra high-speed ADC core. The core uses an interleaved calibrated folding and interpolating architecture that results in very high sampling rate, very good dynamic performance, and relatively low-power consumption. This ADC core is followed by a configurable DDC block which is implemented on a small geometry CMOS. The DDC block provides a range of decimation settings that allow the product to work in ultra-wideband, wideband, and more-narrow-band receive systems. The output data from the DDC block is transmitted through a JESD204B-compatible multi-lane serial-output system. This system minimizes the number of data pairs required to convey the output data to the downstream processing circuitry. 7.2 Functional Block Diagram DS7+/NCO_2 DS7±/NCO_2 Buffer VIN+ ADC VIN± DS6+/NCO_1 DDC DS6±/NCO_1 VCM VCMO DS5±/NCO_0 REF JESD204B Interface VBG RBIAS+ RBIAS± DS5+/NCO_0 DDC Bypass DEVCLK+ DEVCLK± VCM CLK Clock Sync SYSREF+ DS4+ DS4± DS3+ DS3± DS2+ DS2± SYSREF± DS1+ SYNC~/TMST+ DS1± SYNC~/TMST± DS0+ SYNC~ DS0± OR_T0 TDIODE+ Overrange Detection OR_T1 TDIODE± SCS Configuration Registers 30 Submit Documentation Feedback SPI Interface SCLK SDI SDO Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Functional Block Diagram (continued) Configurable 32-bit NCO and Mixer Configurable Decimation Filters Filter 15 bit I Complex Baseband Output 12 bit Filter 15 bit Q 90° Oscillator Figure 63. DDC Details Block Diagram 7.3 Feature Description 7.3.1 Signal Acquisition The analog input is sampled on the rising edge of CLK and the digital equivalent of that data is available in the serialized datastream t(LAT) or t(LAT_DDC) input clock cycles later. The ADC12J1600 and ADC12J2700 devices convert as long as the input clock signal is present. The fullydifferential comparator design and the innovative design of the sample-and-hold amplifier, together with calibration, enables very good performance at input frequencies beyond 3 GHz. The ADC12J1600 and ADC12J2700 data is output on a high-speed serial JESD204B interface. 7.3.2 The Analog Inputs A differential input signal must be used to drive the ADC12J1600 and ADC12J2700 devices. Operation with a single-ended signal is not recommended as performance suffers. The input signals can be either be AC coupled or DC coupled. The analog inputs are internally connected to the VCMO bias voltage. When DC-coupled input signals are used, the common mode voltage of the applied signal must meet the device Input common mode requirements. See VCMI in the Recommended Operating Conditions table. The full-scale input range for each converter can be adjusted through the serial interface. See the Full Scale Range Adjust section. The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at sampling ADC inputs is not required. If an amplifier circuit before the ADC is desired, use care when selecting an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used for the application. If gain is not required, a balun (balanced-to-unbalanced transformer) is generally used to provide single ended (SE) to differential conversion. The input impedance of VIN± consists of two 50-Ω resistors in series between the inputs and a capacitance from each of these inputs to ground. A resistance of approximately 20 kΩ exists from the center point of the 50-Ω resistors to the on-chip VCMO providing self-biasing for AC-coupled applications. Performance is good in both DC-coupled mode and AC coupled mode, provided the common-mode voltage at the analog input is within specifications. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 31 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Feature Description (continued) 7.3.2.1 Input Clamp The ADC12J1600 and ADC12J2700 maximum DC input voltage is limited to the range 0 to 2 V to prevent damage to the device. To help maintain these limits, an active input clamping circuit is incorporated which sources or sinks input currents up to ±50 mA. The clamping circuit is enabled by default and is controlled via the Input_Clamp_EN bit (register 0x034, bit 5). The protection provided by this circuit is limited as follows: • Shunt current-clamping is only effective for non-zero source impedances. • At frequencies above 3 GHz the clamping is ineffective because of the finite turn-on and turn-off time of the switch. With these limitations in mind, analysis has been done to determine the allowable input signal levels as a function of input frequency when the Input Clamp is enabled, assuming the source impedance matches the input impedance of the device (100-Ω differential). This information is incorporated in the Absolute Maximum Ratings table. 7.3.2.2 AC Coupled Input Usage The easiest way to accomplish SE-to-differential conversion for AC-coupled signals is with an appropriate balun. C(couple) 50- Source VIN+ R(VIN) 1:2 Balun C(couple) VIN± Figure 64. Single-Ended-to-Differential Signal Conversion With a Balun Figure 64 shows a generic depiction of a SE-to-differential signal conversion using a balun. The circuitry specific to the balun depends on the type of balun selected and the overall board layout. TI recommends that the system designer contact the manufacturer of the selected balun to aid in designing the best performing single-ended to differential conversion circuit using that particular balun. When selecting a balun, understanding the input architecture of the ADC is important. Specific balun parameters must be considered. The balun must match the impedance of the analog source to the on-chip 100-Ω differential input termination of the ADC12J1600 and ADC12J2700 devices. The range of this input termination resistor is described in the Electrical Characteristics table as the specification RID. Also, as a result of the ADC architecture, the phase and amplitude balance are important. The lowest possible phase and amplitude imbalance is desired when selecting a balun. The phase imbalance must be no more than ±2.5° and the amplitude imbalance must be limited to less than 1 dB at the desired input frequency range. Finally, when selecting a balun, the voltage standing-wave ratio (VSWR), bandwidth, and insertion loss of the balun must also be considered. The VSWR aids in determining the overall transmission line termination capability of the balun when interfacing to the ADC input. The insertion loss must be considered so that the signal at the balun output is within the specified input range of the ADC as described in the Electrical Characteristics table as the specification VID. Table 1 lists the recommended baluns for specific signal frequency ranges. Table 1. Balun Recommendations MINIMUM FREQUENCY (MHz) MAXIMUM FREQUENCY (MHz) IMPEDANCE RATIO 32 PART NUMBER MANUFACTURER Mini-Circuits 4.5 3000 1:1 TC1-1-13MA+ 400 3000 1:2 B0430J50100AHF Anaren 30 1800 1:2 ADTL2-18+ Mini-Circuits 10 4000 1:2 TCM2-43X+ Mini-Circuits Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.3.2.3 DC Coupled Input Usage When a DC-coupled signal source is used, the common mode voltage of the applied signal must be within a specified range (VCMI). To achieve this range, the common mode of the driver should be based on the VCMO output provided for this purpose. Full-scale distortion performance degrades as the input common-mode voltage deviates from VCMO. Therefore, maintaining the input common-mode voltage within the VCMI range is important. Table 2 lists the recommended amplifiers for DC-coupled usage or if AC-coupling with gain is required. Table 2. Amplifier Recommendations –3-dB BANDWIDTH (MHz) MIN GAIN (dB) MAX GAIN (dB) GAIN TYPE PART NUMBER 7000 16 2800 0 16 Fixed LMH3401 17 Resistor set 2400 LMH6554 6 26 Digital programmable LMH6881 900 –1.16 38.8 Digital programmable LMH6518 7.3.2.4 Handling Single-Ended Input Signals The ADC12J1600 and ADC12J2700 devices have no provision to adequately process single-ended input signals. The best way to handle single-ended signals is to convert these signals to balanced differential signals before presenting the signals to the ADC. 7.3.3 Clocking The ADC12J1600 and ADC12J2700 devices have a differential clock input, DEVCLK+ and DEVCLK–, that must be driven with an AC-coupled differential clock-signal. The clock inputs are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as shown in Figure 65. C(couple) CLK+ C(couple) CLK± Figure 65. Differential Sample-Clock Connection The differential sample-clock line pair must have a characteristic impedance of 100 Ω and must be terminated at the clock source of that 100-Ω characteristic impedance. The input clock line must be as short and direct as possible. The ADC12J1600 and ADC12J2700 clock input is internally terminated with an untrimmed 100-Ω resistance. Insufficient input clock levels results in poor dynamic performance. Excessively-high input-clock levels can cause a change in the analog-input offset voltage. To avoid these issues, maintain the input clock level within the range specified in the Electrical Characteristics table. The low times and high times of the input clock signal can affect the performance of any ADC. The ADC12J1600 and ADC12J2700 devices feature a duty-cycle clock-correction circuit which maintains performance over temperature. The ADC meets the performance specification when the input clock high times and low times are maintained as specified in the Electrical Characteristics table. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 33 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com High-speed high-performance ADCs such as the ADC12J1600 and ADC12J2700 devices require a very-stable input clock-signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution or ENOB (effective number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. Use Equation 1 to calculate the maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR. VFSR 1 RMStot(J) u (n1) VI(PP) 2 uSuF IN where • • • • • RMStot(J) is the RMS total of all jitter sources in seconds VI(PP) is the peak-to-peak analog input signal VFSR is the full-scale range of the ADC n is the ADC resolution in bits FIN is the maximum input frequency, in Hertz, at the ADC analog input (1) Note that the maximum jitter previously described is the root sum square (RSS) of the jitter from all sources, including that from the clock source, the jitter added by noise coupling at board level and that added internally by the ADC clock circuitry, in addition to any jitter added to the input signal. Because the effective jitter added by the ADC is beyond user control, the best option is to minimize the jitter from the clock source, the sum of the externally-added input clock jitter and the jitter added by any circuitry to the analog signal. Input clock amplitudes above those specified in the Recommended Operating Conditions table can result in increased input-offset voltage. Increased input-offset voltage causes the converter to produce an output code other than the expected 2048 when both input pins are at the same potential. 7.3.4 Over-Range Function To ensure that system-gain management has the quickest-possible response time, a low-latency configurable over-range function is included. The over-range function works by monitoring the raw 12-bit samples exiting the ADC module. The upper 8 bits of the magnitude of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. The following table lists how a raw ADC value is converted to an absolute value for a comparison of the thresholds. ADC SAMPLE (OFFSET BINARY) ADC SAMPLE (2's COMPLEMENT) ABSOLUTE VALUE UPPER 8 BITS USED FOR COMPARISON 1111 1111 1111 (4095) 0111 1111 1111 (+2047) 111 1111 1111 (2047) 1111 1111 (255) 1111 1111 0000 (4080) 0111 1111 0000 (+2032) 111 1111 0000 (2032) 1111 1110 (254) 1000 0000 0000 (2048) 0000 0000 0000 (0) 000 0000 0000 (0) 0000 0000 (0) 0000 0001 0000 (16) 1000 0001 0000 (-2032) 111 1111 0000 (2032) 1111 1110 (254) 0000 0000 0000 (0) 1000 0000 0000 (-2048) 111 1111 1111 (2047) 1111 1111 (255) If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 threshold during the monitoring period, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit is 0. The resulting over-range bits are embedded into the complex output data samples and output on OR_T0 and OR_T1. Table 3 lists the outputs, related data samples, threshold settings and the monitoring period equation. Table 3. Threshold and Monitor Period for Embedded OR Bits (1) 34 EMBEDDED OVER-RANGE OUTPUTS ASSOCIATED THRESHOLD OR_T0 OVR_T0 In-Phase (I) samples OR_T1 OVR_T1 Quadrature (Q) samples ASSOCIATED SAMPLES MONITORING PERIOD (ADC SAMPLES) 2OVR_N (1) OVR_N is the monitoring period register setting. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Table 4. Over-Range Monitoring Period OVR_N MONITORING PERIOD 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set much lower. For example, the OVR_T1 threshold can be set to 64 (−12 dBFS). If the input signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of the signal is above −12 dBFS). The OR_T0 threshold is embedded as the LSB along with the upper 15 bits of every complex I sample. The OR_T1 threshold is embedded as the LSB along with the upper 15 bits of every complex Q sample. 7.3.5 ADC Core Features 7.3.5.1 The Reference Voltage The reference voltage for the ADC12J1600 and ADC12J2700 devices is derived from an internal bandgap reference. A buffered version of the reference voltage is available at the VBG pin for user convenience. This output has an output-current capability of ±100 μA. The VBG output must be buffered if more current is required. No provision exists for the use of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register settings. 7.3.5.2 Common-Mode Voltage Generation The internal reference voltage is used to generate a stable common-mode voltage reference for the analog Inputs and the DEVCLK and SYSREF differential-clock inputs. 7.3.5.3 Bias Current Generation An external bias resistor, in combination with the on-chip voltage reference is used to provide an accurate and stable source of bias currents for internal circuitry. Using an external accurate resistor minimizes variation in device power consumption and performance. 7.3.5.4 Full Scale Range Adjust The ADC input full-scale range can be adjusted through the GAIN_FS register setting (registers 0x022 and 0x023). The adjustment range is approximately 500 mVPP to 950 mVPP. The full-scale range adjustment is useful for matching the input-signal amplitude to the ADC full scale, or to match the full-scale range of multiple ADCs when developing a multi-converter system. 7.3.5.5 Offset Adjust The ADC-input offset voltage can be adjusted through the OFFSET_FS register setting (registers 0x025 and 0x026). The adjustment range is approximately 28 mV to –28 mV differential. NOTE Offset adjust has no effect when background calibration mode is enabled. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 35 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.3.5.6 Power-Down The power-down bit (PD) allows the ADC12J1600 and ADC12J2700 devices to be entirely powered down. The serial data output drivers are disabled when PD is high. When the device returns to normal operation, the JESD204 link must be re-established, and the ADC pipeline and decimation filters contain meaningless information and must be flushed. 7.3.5.7 Built-In Temperature Monitor Diode A built-in thermal monitoring diode junction is made available on the TDIODE+ and TDIODE– pins. This diode facilitates temperature monitoring and characterization of the device in higher ambient temperature environments. While the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline measurement at a known ambient or board temperature with the device in power-down (PD) mode. Recommended monitoring ICs include the LM95233 device and similar remote-diode temperature monitoring products from Texas Instruments. 7.3.6 Digital Down Converter (DDC) The digitized data is the input to the digital down-converter block. This block provides frequency conversion and decimation filtering to allow a specific range of frequencies to be selected and output in the digital data stream. 7.3.6.1 NCO/Mixer The DDC contains a complex numerically-controlled oscillator and a complex mixer. The oscillator generates a complex exponential sequence shown in Equation 2. x[n] = ejωn (2) The frequency (ω) is specified by the a 32-bit register setting. The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down to 0 Hz. 7.3.6.2 NCO Settings 7.3.6.2.1 NCO Frequency Phase Selection Within the DDC, eight different frequency and phase settings are always available for use. Each of the eight settings uses a different phase accumulator within the NCO. Because all eight phase accumulators are continuously running independently, rapid switching between different NCO frequencies is possible allowing rapid tuning of different signals. The specific frequency-phase pair in use is selected through either the NCO_x input pins, or the NCO_SEL configuration bits (register 0x20D, bits 2:0). The CFG_MODE bit (register 0x20C, bit 0) is used to choose whether the input pins or selection bits are used. When the CFG_MODE bit is set to 0, the NCO_x input pins select the active NCO frequency and phase setting. When the CFG_MODE bit is set to 1, the NCO_SEL register settings select the active NCO frequency and phase setting. The frequency for each phase accumulator is programmed independently through the NCO_FREQn (and optionally NCO_RDIV) settings. The phase offset for each accumulator is programmed independently through the NCO_PHASEn register settings. 7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x) When the CFG_MODE bit is set to 0, the state of these three inputs determines the active NCO frequency and phase accumulator settings. 7.3.6.2.3 NCO_SEL Bits (2:0) When the CFG_MODE bit is set to 1, the state of these register bits determines the active NCO frequency and phase accumulator settings. 36 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.3.6.2.4 NCO Frequency Setting (Eight Total) 7.3.6.2.4.1 Basic NCO Frequency-Setting Mode In basic NCO frequency-setting mode, the NCO frequency setting is set by the 32-bit register value, NCO_FREQn (n = preset 0 trough 7, see the NCO Frequency (Preset x) Register section). (n = 0 – 7) ƒ(NCO) = NCO_FREQn × 2–32 × ƒ(DEVCLK) (3) NOTE Changing the register setting after the JESD204B interface is running results in nondeterministic NCO phase. If deterministic phase is required, the JESD204B link must be re-initialized after changing the register setting. See the Multiple ADC Synchronization section. 7.3.6.2.4.2 Rational NCO Frequency Setting Mode In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized, but sometimes an application requires very specific frequencies that fall between two frequency steps. For example with ƒS equal to 2457.6 MHz and a desired ƒ(NCO) equal to 5.02 MHz the value for NCO_FREQ is 8773085.867. Truncating the fractional portion results in an ƒ(NCO) equal to 5.0199995 MHz, which is not the desired frequency. To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at specific frequencies without error. First, select a frequency step size (ƒ(STEP)) that is appropriate for the NCO frequency steps required. The typical value of ƒ(STEP) is 10 kHz. Next, program the NCO_RDIV value according to Equation 4. NCO _ RDIV § ¦(DEVCLK) · ¨ ¸ ¨ ¦(STEP) ¸ © ¹ 128 (4) The result of Equation 4 must be an integer value. If the value is not an integer, adjust either of the parameters until the result in an integer value. For example, select a value of 1920 for NCO_RDIV. NOTE NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are not recommended. Now use Equation 5 to calculate the NCO_FREQ register value. § 225 u N · NCO _ FREQ round u ¨ ¨ NCO _ RDIV ¸¸ © ¹ (5) Alternatively, the following equations can be used: ¦(NCO) N ¦(STEP) (6) § 2 u N · round u ¨ ¨ NCO _ RDIV ¸¸ © ¹ 25 NCO _ FREQ Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 (7) Submit Documentation Feedback 37 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table 5. Common NCO_RDIV Values (For 10-kHz Frequency Steps) ƒ(DEVCLK) (MHz) NCO_RDIV 2457.6 1920 1966.08 1536 1474.56 1152 1228.8 960 7.3.6.2.5 NCO Phase-Offset Setting (Eight Total) The NCO phase-offset setting is set by the 16-bit register value NCO_PHASEn (n = preset 0 trough 7, see the NCO Phase (Preset x) Register section). The value is left-justified into a 32-bit field and then added to the phase accumulator. Use Equation 8 to calculate the phase offset in radians. NCO_PHASEn × 2–16 × 2 × π (8) NOTE Changing the register setting after the JESD204B interface is running results in nondeterministic NCO phase. If deterministic phase is required, the JESD204B link must be re-initialized after changing the register setting. See Multiple ADC Synchronization. 7.3.6.2.6 Programmable DDC Delay The DDC Filter elements incorporate a programmable sample delay. The delay can be programmed from 0 to (decimation setting – 0.5) ADC sample periods. The delay step-size is 0.5 ADC sample periods. The delay settings are programmed through the DDC_DLYn parameter. Table 6. Programmable DDC Delay Range 38 D (Decimation Setting) Min Delay (t(DEVCLK)) Max Delay (t(DEVCLK)) 4 0 3.5 8 0 7.5 10 0 9.5 16 0 15.5 20 0 19.5 32 0 31.5 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.3.6.3 Decimation Filters The decimation filters are arranged to provide a programmable overall decimation of 4, 8, 10, 16, 20, or 32. The input and output of each filter is complex. The output data consists of 15-bit complex baseband information. Table 7 lists the effective output sample rates. Table 7. Output Sample Rates COMPLEX SAMPLE OUTPUT RATE AND RESULTING BANDWIDTH (OUTPUT SAMPLE = 15-BIT I + 15-BIT Q + 2-BIT OR) ƒ(DEVCLK) DECIMATION SETTING OUTPUT RATE (MSPS) ƒ(DEVCLK) = 4000 MHz RAW OUTPUT BANDWIDTH (MHz) ALIAS PROTECTED BANDWIDTH (MHz) OUTPUT RATE (MSPS) RAW OUTPUT BANDWIDTH (MHz) ALIAS PROTECTED BANDWIDTH (MHz) 4 ƒ(DEVCLK) / 4 ƒ(DEVCLK) / 4 0.8 × ƒ(DEVCLK) / 4 1000 1000 800 8 ƒ(DEVCLK) / 8 ƒ(DEVCLK)N / 8 0.8 × ƒ(DEVCLK) / 8 500 500 400 10 ƒ(DEVCLK) / 10 ƒ(DEVCLK) / 10 0.8 × ƒ(DEVCLK) / 10 400 400 320 16 ƒ(DEVCLK) / 16 ƒ(DEVCLK) / 16 0.8 × ƒ(DEVCLK) / 16 250 250 200 20 ƒ(DEVCLK) / 20 ƒ(DEVCLK) / 20 0.8 × ƒ(DEVCLK) / 20 200 200 160 32 ƒ(DEVCLK) / 32 ƒ(DEVCLK) / 32 0.8 × ƒ(DEVCLK) / 32 125 125 100 For maximum efficiency a group of high speed filter blocks are implemented with specific blocks used for each decimation setting. The first table below describes the combination of filter blocks used for each decimation setting. The next table lists the coefficient details and decimation factor of each filter block. Table 8. Decimation Mode Filter Usage Decimation Setting Filter Blocks Used 4 CS19, CS55 8 CS11, CS15, CS55 10 CS11, CS139 16 CS7, CS11, CS15, CS55 20 CS7, CS11, CS139 32 CS7, CS7, CS11, CS15, CS55 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 39 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table 9. Filter Coefficient Details Filter Coefficient Set (Decimation Factor of Filter) CS7 (2) CS11 (2) CS15 (2) CS19 (2) CS55 (2) –65 109 109 –327 –327 22 22 –37 –37 –5 –5 0 0 0 0 0 0 0 0 0 0 –9 –9 577 577 –837 –837 2231 2231 –174 –174 118 118 –9 –9 0 0 0 0 0 0 0 0 –5 –5 4824 4824 –8881 –8881 744 744 –291 –291 0 0 0 0 0 0 0 0 20 20 39742 39742 –2429 –2429 612 612 33 33 0 0 0 0 33 33 10029 10029 –1159 –1159 21 21 0 0 0 0 2031 2031 –54 –54 1024 8192 65536 16384 0 0 –88 –88 –3356 –3356 –89 –89 0 0 –56 –56 5308 5308 0 0 0 0 119 119 –8140 –8140 196 196 0 0 199 199 12284 12284 125 125 0 0 0 0 –18628 –18628 –234 –234 0 0 –385 –385 29455 29455 –393 –393 0 0 –248 –248 –53191 –53191 0 0 0 0 422 422 166059 166059 696 696 711 711 450 450 262144 40 CS139 (5) –65 Submit Documentation Feedback 0 0 –711 –711 –1176 –1176 –1206 –1206 –766 –766 0 0 1139 1139 1893 1893 1949 1949 1244 1244 0 0 –1760 –1760 –2940 –2940 –3044 –3044 –1955 –1955 0 0 2656 2656 4472 4472 4671 4671 3026 3026 0 0 –3993 –3993 –6802 –6802 –7196 –7196 –4730 –4730 0 0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Table 9. Filter Coefficient Details (continued) Filter Coefficient Set (Decimation Factor of Filter) CS7 (2) CS11 (2) CS15 (2) CS19 (2) CS55 (2) CS139 (5) 6159 6159 10707 10707 11593 11593 7825 7825 0 0 –10423 –10423 –18932 –18932 –21629 –21629 –15618 –15618 0 0 24448 24448 52645 52645 78958 78958 97758 97758 104858 7.3.6.4 DDC Output Data The DDC output data consist of 15-bit complex data plus the two over-range threshold-detection control bits. The following table lists the data format: 16-BIT OUTPUT WORD CHANNEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I DDC Output In-Phase (I) 15 bit OR_T0 Q DDC Output Quadrature (Q) 15 bit OR_T1 7.3.6.5 Decimation Settings 7.3.6.5.1 Decimation Factor The decimation setting is adjustable over the following settings: • Bypass — no decimation • Decimate-by-4 • Decimate-by-8 • Decimate-by-10 • Decimate-by-16 • Decimate-by-20 • Decimate-by-32 NOTE Because the output format is complex I+Q, the effective output bandwidth is approximately two-times the value for a real output with the same decimation factor. 7.3.6.5.2 DDC Gain Boost The DDC gain boost (register 0x200, bit 4) provides additional gain through the DDC block. With a setting of 1 the final filter has 6.02-dB gain. With a setting of 0, the final filter has a 0-dB gain. This setting is recommended when the NCO is set near DC. 7.3.7 Data Outputs The data outputs (DSx±) are very high-speed differential outputs and conform to the JESD204B JEDEC standard. A CML (current-mode logic)-type output driver is used for each output pair. Output pre-emphasis is adjustable to compensate for longer PCB-trace lengths. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 41 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.3.7.1 The Digital Outputs The ADC12J1600 and ADC12J2700 output data is transmitted on up to eight high-speed serial-data lanes. The output data from the ADC or DDC is formatted to the eight lanes, 8b10b encoded, and serialized. Up to four different serial output rates are possible depending on the decimation mode setting: 1x, 1.25x, 2x, and 2.5x. In 1x mode, the output serializers run at the same bit rate as the frequency of the applied DEVCLK. In 1.25x mode, the output serializers run at a bit rate that is 1.25-times that of the applied DEVCLK, and so on. For example, for a 1.6-GHz input DEVCLK, the output rates are 1.6 Gbps in 1x mode, 2 Gbps in 1.25x mode, 3.2 Gbps in 2x mode and 4 Gbps in 2.5x mode. 7.3.7.2 JESD204B Interface Features and Settings 7.3.7.2.1 Scrambler Enable Scrambling randomizes the 8b10b encoded data, spreading the frequency content of the data interface. This reduces the peak EMI energy at any given frequency reducing the possibility of feedback to the device inputs impacting performance. The scrambler is disabled by default and is enabled via SCR (register 0x201, bit 7). 7.3.7.2.2 Frames Per Multi-Frame (K-1) The frames per multi-frame (K) setting can be adjusted within constraints that are dependant on the selected decimation (D) and serial rate (DDR) settings. The K-minus-1 (KM1) register setting (register 0x201, bits 6:2) must be one less than the desired K setting. 7.3.7.2.3 DDR The serial rate can be either 1ƒ(CLK) (DDR = 0) or 2ƒ(CLK) (DDR = 1). 7.3.7.2.4 JESD Enable The JESD interface must be disabled (JESD_EN is set to 0) while any of the other JESD parameters are changed. While JESD_EN is set 0 the block is held in reset and the serializers are powered down. The clocks for this section are also gated off to further save power. When the parameters have been set as desired the JESD block can be enabled (JESD_EN is set to 1). 7.3.7.2.5 JESD Test Modes Several different JESD204B test modes are available to assist in link verification and debugging. The list of modes follows. NOTE PRBS test signals are output directly, without 8b10b encoding. • • • • • • • • • • • • 42 Normal operation PRBS7 test mode PRBS15 test mode PRBS23 test mode Ramp test mode Short or long transport-layer test mode D21.5 test mode K28.5 test mode Repeated ILA test mode Modified RPAT test mode Serial-outputs differential 0 test mode Serial-outputs differential 1 test mode Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.3.7.2.6 Configurable Pre-Emphasis The high-speed serial-output drivers incorporate a configurable pre-emphasis feature. This feature allows the output drive waveform to be optimized for different PCB materials and signal transmission distances. The preemphasis setting is adjusted through the serializer pre-emphasis setting in register 0x040, bits 3 to 0. The default setting is 4d. Higher values will increase the pre-emphasis to compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. The pre-emphasis setting should be adjusted to optimize the eye-opening for the hardware configuration and line rates needed. 7.3.7.2.7 Serial Output-Data Formatting Output data is generated by the DDC then formatted according to the selected decimation and output rate settings. When less than the maximum of eight lanes are active, lanes are disabled beginning with the highest numerical lanes. For example when only two lanes are active, lanes 0 and 1 are active, while all higher lanes are inactive. Table 10. Parameter Definitions PARAMETER D DESCRIPTION USER CONFIGURED OR DERIVED STANDARD JESD204B LINK PARAMETER No Decimation factor, determined by DMODE register User DDR Serial line rate: 1 = DDR rate (2x), 0 = SDR rate (1x) User No P54 Enable 5/4 PLL to increase line rate by 1.25x. User No 0 = no PLL (1x), 1 = enable PLL (1.25x) K Number of frames per multiframe User Yes N Bits per sample (before adding control bits and tails bits) Derived Yes CS Control bits per sample Derived Yes N’ Bits per sample (after adding control bits and tail bits). Must be a multiple of 4. Derived Yes L Number of serial lanes Derived Yes F Number of octets (bytes) per frame (per lane) Derived Yes M Number of (logical) converters Derived Yes S Number of samples per converter per frame Derived Yes CF Number of control words per frame Derived Yes HD 1=High density mode (samples may be broken across lanes), 0 = normal mode (samples may not be broken across lanes) Derived Yes KS Legal adjustment step for K, to ensure that the multi-frame clock is a subharmonic of other internal clocks Derived No Table 11. Serial Link Parameters (1) USER SPECIFIED PARAMETERS DERIVED PARAMETERS OTHER INFORMATION DECIMATION FACTOR (D) DDR P54 N CS N’ L F M S 1 1 0 12 0 12 8 8 8 4 1 0 15 1 16 5 4 2 4 1 1 15 1 16 4 2 8 0 0 15 1 16 5 8 0 1 15 1 16 4 8 1 0 15 1 16 8 1 1 15 1 16 10 0 0 15 1 10 1 0 15 1 16 0 0 15 16 0 1 15 (1) (2) KS LEGAL K RANGE BIT RATE / ADC CLOCK (2) 5 2 4-32 2x 5 4 8-32 2x 2 2 2 10-32 2.5x 4 2 5 2 6-32 1x 2 2 2 1 9-32 1.25x 3 8 2 5 2 4-32 2x 2 2 2 1 2 10-32 2.5x 16 4 2 2 2 4 12-32 1x 16 2 2 2 1 8 16-32 2x 1 16 3 8 2 5 1 3-32 1x 1 16 2 2 2 1 1 9-32 1.25x In all modes: HD = 0 and CF = 0 x = times (for example, 2x = 2-times) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 43 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table 11. Serial Link Parameters(1) (continued) USER SPECIFIED PARAMETERS DERIVED PARAMETERS OTHER INFORMATION DECIMATION FACTOR (D) DDR P54 N CS N’ L F M S KS LEGAL K RANGE BIT RATE / ADC CLOCK (2) 16 1 0 15 1 16 2 16 2 5 1 2-32 2x 16 1 1 15 1 16 1 4 2 1 1 5-32 2.5x 20 0 0 15 1 16 2 2 2 1 4 12-32 1x 20 1 0 15 1 16 1 4 2 1 4 8-32 2x 32 0 0 15 1 16 2 16 2 5 1 2-32 1x 32 0 1 15 1 16 1 4 2 1 1 5-32 1.25x 32 1 0 15 1 16 1 32 2 5 1 1-32 2x Output data is formatted in a specific optimized fashion for each decimation and DDR setting combination. For bypass mode (decimation = 1) the 12-bit offset binary values are mapped to the 8-bit characters. For the DDC mode the 16-bit values (15-bit complex data plus 1 bit OR_Tn) are mapped to the 8-bit characters. The following tables list the specific mapping formats. In all mappings the T or tail bits are 0 (zero). Table 12. Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 Lane 0 C0S0 C0S1 C0S2 C0S3 C0S4 T Lane 1 C1S0 C1S1 C1S2 C1S3 C1S4 T Lane 2 C2S0 C2S1 C2S2 C2S3 C2S4 T Lane 3 C3S0 C3S1 C3S2 C3S3 C3S4 T Lane 4 C4S0 C4S1 C4S2 C4S3 C4S4 T Lane 5 C5S0 C5S1 C5S2 C5S3 C5S4 T Lane 6 C6S0 C6S1 C6S2 C6S3 C6S4 T Lane 7 C7S0 C7S1 C7S2 C7S3 C7S4 T Frame n Table 13. Bypass Mode, No Decimation, DDR = 1, P54 = 0, Composite View of Interleaved Converters TIME → CHAR NUMBER 0 1 Lane 0 S0 Lane 1 Lane 2 2 3 4 5 6 7 S8 S16 S24 S32 T S1 S9 S17 S25 S33 T S2 S10 S18 S26 S34 T Lane 3 S3 S11 S19 S27 S35 T Lane 4 S4 S12 S20 S28 S36 T Lane 5 S5 S13 S21 S29 S37 T Lane 6 S6 S14 S22 S30 S38 T Lane 7 S7 S15 S23 S31 S39 T Frame n 44 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Table 14. Decimate-by-4, DDR = 1, P54 = 0, LMF = 5,2,4 TIME → CHAR NUMBER 0 1 2 3 Lane 0 I0 Lane 1 I2 I1 I3 Lane 2 I4 Q0 Lane 3 Q1 Q2 Lane 4 Q3 Q4 Frame n Table 15. Decimate-by-4, DDR = 1, P54 = 1, LMF = 4,2,2 TIME → CHAR NUMBER 0 1 Lane 0 2 I0 3 4 5 I2 I4 Lane 1 I1 I3 I5 Lane 2 Q0 Q2 Q4 Lane 3 Q1 Q3 Q5 Frame n Frame n+1 Frame n+2 Table 16. Decimate-by-8, DDR = 0, P54 = 0, LMF = 5,2,4 TIME → CHAR NUMBER 0 1 2 3 Lane 0 I0 I1 Lane 1 I2 I3 Lane 2 I4 Q0 Lane 3 Q1 Q2 Lane 4 Q3 Q4 Frame n Table 17. Decimate-by-8, DDR = 0, P54 = 1, LMF = 4,2,2 TIME → CHAR NUMBER 0 1 2 3 4 5 Lane 0 I0 I2 Lane 1 I1 I3 I4 I5 Lane 2 Q0 Q2 Q4 Lane 3 Q1 Q3 Q5 Frame n Frame n+1 Frame n+2 Table 18. Decimate-by-8, DDR = 1, P54 = 0, LMF = 3,2,8 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 Lane 0 I0 I1 I2 I3 Lane 1 I4 Q0 Q1 Q2 Lane 2 Q3 Q4 T T Frame n Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 45 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table 19. Decimate-by-8, DDR = 1, P54=1, LMF = 2,2,2 TIME → CHAR NUMBER 0 1 2 3 4 5 Lane 0 I0 I1 I2 Lane 1 Q0 Q1 Q2 Frame n Frame n+1 Frame n+2 Table 20. Decimate-by-10, DDR = 0, P54 = 0, LMF = 4,2,2 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 Lane 0 I0 I2 I4 Lane 1 I1 I3 I5 I7 Lane 2 Q0 Q2 Q4 Q6 Lane 3 I6 Q1 Q3 Q5 Q7 Frame n Frame n+1 Frame n+2 Frame n+3 Table 21. Decimate-by-10, DDR = 1, P54 = 0, LMF = 2,2,2 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 Lane 0 I0 I1 I2 I3 Lane 1 Q0 Q1 Q2 Q3 Frame n Frame n+1 Frame n+2 Frame n+3 Table 22. Decimate-by-16, DDR = 0, P54 = 0, LMF = 3,2,8 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 Lane 0 I0 I1 I2 I3 Lane 1 I4 Q0 Q1 Q2 Lane 2 Q3 Q4 T T Frame n Table 23. Decimate-by-16, DDR = 0, P54 = 1, LMF = 2,2,2 TIME → CHAR NUMBER 0 1 2 3 4 5 Lane 0 I0 I1 I2 Lane 1 Q0 Q1 Q2 Frame n Frame n+1 Frame n+2 Table 24. Decimate-by-16, DDR = 1, P54 = 0, LMF = 2,2,16 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 0 I0 I1 I2 I3 I4 Q0 Q1 Q2 Lane 1 Q3 Q4 T T T T T T Frame n 46 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Table 25. Decimate-by-16, DDR = 1, P54 = 1, LMF = 1,2,4 TIME → CHAR NUMBER 0 1 Lane 0 2 3 I0 4 5 Q0 6 I1 7 8 9 Q1 Frame n 10 11 I2 Q2 Frame n + 1 Frame n + 2 Table 26. Decimate-by-20, DDR = 0, P54 = 0, LMF = 2,2,2 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 Lane 0 I0 I1 I2 I3 Lane 1 Q0 Q1 Q2 Q3 Frame n Frame n+1 Frame n+2 Frame n+3 Table 27. Decimate-by-20, DDR = 1, P54 = 0, LMF = 1,2,2 TIME → CHAR NUMBER 0 1 Lane 0 2 3 I0 4 5 Q0 6 7 I1 Q1 Frame n Frame n + 1 Table 28. Decimate-by-32, DDR = 0, P54 = 0, LMF = 2,2,16 TIME → CHAR NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 0 I0 I1 I2 I3 I4 Q0 Q1 Q2 Lane 1 Q3 Q4 T T T T T T Frame n Table 29. Decimate-by-32, DDR = 0, P54 = 1, LMF = 1,2,4 TIME → CHAR NUMBER 0 1 Lane 0 2 3 I0 4 5 Q0 6 I1 7 8 9 Q1 Frame n 10 11 I2 Q2 Frame n + 1 Frame n + 2 Table 30. Decimate-by-32, DDR = 1, P54 = 0, LMF = 1,2,32 TIME → CHAR NUMBE R Lane 0 0 1 I0 2 3 I1 4 5 I2 6 7 I3 8 9 I4 10 11 Q0 12 13 Q1 14 15 Q2 16 17 Q3 18 19 Q4 20 21 T 22 23 T 24 25 T 26 27 T 28 29 T 30 31 T Frame n The formatted data is 8b10b encoded and output on the serial lanes. The 8b10b encoding provides a number of specific benefits, including: • Standard encoding format. Therefore the IP is readily available in off-the-shelf FPGAs and ASIC building blocks. • Inherent DC balance allows AC coupling of lanes with small on-chip capacitors • Inherent error checking Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 47 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.3.7.2.8 JESD204B Synchronization Features The JESD204B standard defines methods for synchronization and deterministic latency in a multi-converter system. These devices are a JESD204B Subclass 1 device and conforms to the various aspects of link operation as described in section 5.3.3 of the JESD204B standard. The specific signals used to achieve link operation are described briefly in the following sections. 7.3.7.2.9 SYSREF The SYSREF is a periodic signal which is sampled by the device clock, and is used to align the boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of the LMFC internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency as determined by the selected DDC decimation and frames per multi-frame settings. This clock is typically in the range of 10 MHz to 300 MHz. See the Multiple ADC Synchronization section for more details on SYSREF timing requirements. 7.3.7.2.10 SYNC~ SYNC~ is asserted by the receiver to initiate a synchronization event. Single ended and differential SYNC~ inputs are provided. The SYNC_DIFFSEL bit (register 0x202, bit 6) is used to select which input is used. Using the single ended SYNC~ input is recommended, as this frees the differential SYNC~/TMST input pair for use in the Time Stamp function. To assert SYNC~, a logic low is applied. To deassert SYNC~ a logic high is applied. 7.3.7.2.11 Time Stamp When configured through the TIME_STAMP_EN register setting (register 0x050, bit 5), the SYNC~ differential input (pins 22 and 23) can be used as a time-stamp input. The time-stamp feature enables the user to capture the timing of an external trigger event relative to the sampled signal. When enabled, the LSB of the 12-bit ADC digital output captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger must be applied to the differential SYNC~/TMST inputs. The trigger can be asynchronous to the ADC sampling clock and is sampled at approximately the same time as the analog input. 7.3.7.2.12 Code-Group Synchronization Code-group synchronization is achieved using the following process: • The receiver issues a synchronization request through the SYNC~ input • The transmitter issues a stream of K28.5 symbols • The receiver synchronizes and waits for correct reception of at least 4 consecutive K symbols • The receiver deactivates the synchronization request • Upon detecting that the receiver has deactivated the SYNC~ pin, the transmitter continues emitting K symbols until the next LMFC boundary (or optionally a later LMFC boundary) • On the first frame following the selected LMFC boundary the transmitters emit an initial lane-alignment sequence The initial-lane alignment sequence transmitted by the ADC device is defined in additional detail in JESD204B section 5.3.3.5. 7.3.7.2.13 Multiple ADC Synchronization The second function for the SYSREF input is to facilitate the precise synchronization of multiple ADCs in a system. One key challenge is to ensure that this synchronization works is to ensure that the SYSREF inputs are repeatedly captured by the input CLK. Two key elements must occur for the SYSREF inputs to be captured. First, the SYSREF input must be created so that it is synchronous to the input DEVCLK, be an integer subharmonic of the multi-frame (K × t(FRAME)) and a repeatable and fixed-phase offset. When this constraint is achieved, repeatedly capturing SYSREF is easier. To further ease this task, the SYSREF signal is routed through a user-adjustable delay which eases the timing requirements with respect to the input DEVCLK signal. The SYSREF delay RDEL is adjusted through bits 3 through 0 in register 0x032. 48 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 As long as the SYSREF signal has a fixed timing relationship to DEVCLK, the internal delay can be used to maximize the setup and hold times between the internally delayed SYSREF and the internal DEVCLK signal. These timing relationships are listed in the Timing Requirements table. To find the proper delay setting, the RDEL value is adjusted from minimum to maximum while applying SYSREF and monitoring the SysRefDet and Dirty Capture detect bits. The SysRefDet bit is set whenever a rising edge of SYSREF is detected. The Dirty Capture bit is set whenever the setup or hold time between DEVCLK and the delayed SYSREF is insufficient. The SysRefDetClr bit is used to clear the SysRefDet bit. The Clear Dirty Capture bit is used to clear that bit. This procedure should be followed to determine the range of delay settings where a clean SYSREF capture is achieved. The delay value at the center of the clean capture range must be loaded as the final RDEL setting. Table 31 lists a summary of the control bits that are used and the monitor bits that are read. Table 31. SYSREF Capture Control and Status BIT NAME REGISTER ADDRESS REGISTER BIT RDEL 0x032 3:0 FUNCTION Adjust relative delay between DEVCLK and SYSREF SysRefDet 0x031 7 Detect if a SYSREF rising edge has been captured (not self clearing) Dirty Capture 0x031 6 Detect if SYSREF rising edge capture failed setup/hold (not self clearing) SysRefDetClr 0x030 5 Clear SYSREF detection bit Clear Dirty Capture 0x030 4 Clear Dirty Capture detection bit SysRef_Rcvr_En 0x030 7 Enable SYSREF receiver. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section for more information. SysRef_Pr_En 0x030 6 Enable SYSREF processing. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section for more information. One final aspect of multi-device synchronization relates to phase alignment of the NCO phase accumulators when DDC modes are enabled. The NCO phase accumulators are reset during the ILA phase of link startup which means that for multiple ADCs to have NCO phase alignment, all links must be enabled in the same LMFC period. Enabling all links in the same LMFC period requires synchronizing the SYNC~ de-assertion across all data receivers in the system, so that all of the SYNC~ signals are released during the same LMFC period. Using large K values and resulting longer LMFC periods will ease this task, at the expense of potentially higher latency in the receiving device. 7.4 Device Functional Modes 7.4.1 DDC Bypass Mode In DDC bypass mode (decimation = 1) the raw 12 bit data from the ADC is output at the full sampling rate. 7.4.2 DDC Modes In the DDC modes (decimation > 1) complex (I,Q) data is output at a lower sample rate as determined by the decimation factor (4, 8, 10, 16, 20, and 32). 7.4.3 Calibration Calibration adjusts the ADC core to optimize the following device parameters: • ADC core linearity • ADC core-to-core offset matching • ADC core-to-core full-scale range matching • ADC core 4-way interleave timing All calibration processes occur internally. Calibration does not require any external signals to be present and works properly as long as the device is maintained within the values listed in the Recommended Operating Conditions table. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 49 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Device Functional Modes (continued) 7.4.3.1 Foreground Calibration Mode In foreground mode the calibration process interrupts normal ADC operation and no output data is available during this time (the output code is forced to a static value). The calibration process should be repeated if the device temperature changes by more than 20ºC to ensure rated performance is maintained. Foreground calibration is initiated by setting the CAL_SFT bit (register 0x050, bit 3) which is self clearing. The foreground calibration process finishes within t(CAL) number of DEVCLK cycles. The process occurs somewhat longer when the timing calibration mode is enabled. NOTE Initiating a foreground calibration asynchronously resets the calibration control logic and may glitch internal device clocks. Therefore after setting the CAL_SFT bit clearing and then setting JESD_EN is necessary. If resetting the JESD204B link is undesirable for system reasons, background calibration mode may be preferred. 7.4.3.2 Background Calibration Mode In background mode an additional ADC core is powered-up for a total of 5 ADC cores. At any given time, one core is off-line and not used for data conversion. This core is calibrated in the background and then placed online simultaneous with another core going off-line for calibration. This process operates continuously without interrupting data flow in the application and ensures that all cores are optimized in performance regardless of any changes of temperature. The background calibration cycle rate is fixed and is not adjustable by the user. Because of the additional circuitry active in background calibration mode, a slight degradation in performance occurs in comparison to foreground calibration mode at a fixed temperature. As a result of this degradation, using foreground calibration mode is recommended if the expected change in operating temperature is <30°C. Using background calibration mode is recommended if the expected change in operating temperature is >30°C. The exact difference in performance is dependent on the DEVCLK (sampling clock) frequency, and the analog input signal frequency and amplitude. For this reason, device and system performance should be evaluated using both calibration modes before finalizing the choice of calibration mode. To enable the background calibration feature, set the CAL_BCK bit (register 0x057, bit 0) and the CAL_CONT bit (register 0x057, bit 1). The value written to the register 0x057 to enable background calibration is therefore 0x013h. After writing this value to register 0x057, set the CAL_SFT bit in register 0x050 to perform the one-time foreground calibration to begin the process. NOTE The ADC offset-adjust feature has no effect when background calibration mode is enabled. 7.4.4 Timing Calibration Mode The timing calibration process optimizes the matching of sample timing for the 4 internally interleaved converters. This process minimize the presence of any timing related interleaving spurs in the captured spectrum. The timing calibration feature is disabled by default, but using this feature is highly recommended. To enable timing calibration, set the T_AUTO bit (register 0x066, bit 0). When this bit is set, the timing calibration performs each time the CAL_SFT bit is set. 50 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Device Functional Modes (continued) Table 32. Calibration Cycle Timing for Different Calibration Modes and Options CAL_CONT, CAL_BCK T_AUTO LOW_SIG_EN INITIAL ONE-TIME CALIBRATION CAL_SFT 0 → 1 (tDEVCLK) BACKGROUND CALIBRATION CYCLE (1) (ALL CORES) (tDEVCLK) 0 0 0 102 E+6 N/A 0 0 1 64 E+6 N/A 0 1 0 227 E+6 N/A 0 1 1 189 E+6 N/A 1 0 0 127.5 E+6 816 E+6 1 0 1 80 E+6 512 E+6 1 1 0 283.75 E+6 816 E+6 1 1 1 236.25 E+6 512 E+6 (1) N/A = not applicable 7.4.5 Test-Pattern Modes A number of device test modes are available. These modes insert known patterns of information into the device data path for assistance with system debug, development, or characterization. 7.4.5.1 ADC Test-Pattern Mode The 12-bit ADC core has a built-in test-pattern generator. This mode is helpful for verifying the full data link from the ADC to the data receiver when in DDC bypass mode. When the test-pattern mode is enabled, the ADC output data is replaced by a pattern that repeats every two frames. The data sequence is is shown in Table 33 (shown for default settings with foreground calibration mode). Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 51 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Table 33. ADC Test Pattern (1) LANE (CONVERTER ID) (1) SAMPLE NUMBER (SID) 0 1 2 3 4 5 6 7 8 9 0 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 0x000 0xFFF 1 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 0x008 0xFF7 2 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 0x010 0xFEF 3 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 0x020 0xFDF 4 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 0x040 0xFBF 5 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 0x100 0xEFF 6 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 0x200 0xDFF 7 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF 0x400 0xBFF When background-calibration mode is enabled, the pattern values are dynamic because the internal converter banks are output on different lanes during the calibration bank-switching process. Each converter bank has dedicated pattern values as listed in Table 34. Table 34. ADC Bank Pattern Values BANK LOCATION LOW VALUE Lane n 0x000 0xFFF Lane n+4 0x040 0xFBF 0 1 2 3 4 HIGH VALUE Lane n 0x004 0xFFE Lane n+4 0x080 0xF7F Lane n 0x008 0xFF7 Lane n+4 0x100 0xEFF Lane n 0x010 0xFEF Lane n+4 0x200 0xDFF Lane n 0x020 0xFDF Lane n+4 0x400 0xBFF 7.4.5.2 Serializer Test-Mode Details Test modes are enabled by setting the appropriate configuration of the JESD204B_TEST setting (Register 0x202, Bits 3:0). Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer outputs are powered up based on the configuration decimation and DDR settings. The test modes should only be enabled while the JESD204B link is disabled. ADC DDC JESD204B Transport Layer Scrambler JESD204B Link Layer 8b10b Encoder JESD204B TX Active Lanes and Serial Rates Set by D, DDR, and P54 Parameters ADC Test Pattern Enable Long or Short Transport Octet Ramp Test Mode Enable Repeated ILA Modified RPAT Test Mode Enable PRBSn D21.5 K28.5 Serial Outputs High/Low Test Mode Enable Figure 66. Test-Mode Insertion Points 52 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.4.5.3 PRBS Test Modes The PRBS test modes bypass the 8B10B encoder. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150 specification. These bit streams are used with lab test equipment that can selfsynchronize to the bit pattern and therefore the initial phase of the pattern is not defined. The sequences are defined by a recursive equation. For example, the PRBS7 sequence is defined as shown in Equation 9. y[n] = y[n – 6]y[n – 7] where • Bit n is the XOR of bit [n – 6] and bit [n – 7] which are previously transmitted bits (9) Table 35. PBRS Mode Equations PRBS TEST MODE SEQUENCE SEQUENCE LENGTH (bits) PRBS7 y[n] = y[n – 6]y[n – 7] 127 PRBS15 y[n] = y[n – 14]y[n – 15] 32767 PRBS23 y[n] = y[n – 18]y[n – 23] 8388607 The initial phase of the pattern is unique for each lane. 7.4.5.4 Ramp Test Mode In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the input from the formatter is ignored. After the ILA sequence, each lane transmits an identical octet stream that increments from 0x00 to 0xFF and repeats. 7.4.5.5 Short and Long-Transport Test Mode The short-transport test mode is available when the device is operated in DDC bypass mode (decimation = 1). The short transport pattern has a length of one frame. Table 36 lists the formula followed by each sample of the pattern. Table 36. Short Transport Test Pattern Definition BIT 11 10 9 8 7 6 5 ~LID 4 3 2 LID 1 0 SID+1 LID is the lane ID (0 to 7) and SID is the sample number within the frame (0 to 4). The entire pattern has a length of one frame and is listed in Table 37. Table 37. Short Transport Test Pattern LANE (CONVERTER ID) 0 SAMPLE NUMBER (SID) 0 1 2 3 4 0xF01 0xF02 0xF03 0xF04 0xF05 1 0xE11 0xE12 0xE13 0xE14 0xE15 2 0xD21 0xD22 0xD23 0xD24 0xD25 3 0xC31 0xC32 0xC33 0xC34 0xC35 4 0xB41 0xB42 0xB43 0xB44 0xB45 5 0xA51 0xA52 0xA53 0xA54 0xA55 6 0x961 0x962 0x963 0x964 0x965 7 0x871 0x872 0x873 0x874 0x875 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 53 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com The long-transport test mode is available in all DDC modes (decimation > 1). Patterns are generated in accordance with the JESD204B standard and are different for each output format. Table 38 lists one example of the long transport test pattern: Table 38. Long Transport Test Pattern - Decimate-by-4, DDR = 1, P54 = 1, K=10 TIME → CHAR NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Lane 0 0x0003 0x0002 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0003 Lane 1 0x0002 0x0005 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0002 Lane 2 0x0004 0x0002 0x8001 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 Lane 3 0x0004 0x0004 0x8000 0x8001 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0004 Frame n Frame n+1 Frame n+2 Frame n+3 Frame n+4 Frame n+5 Frame n+6 Frame n+7 Frame n+8 Frame n+9 Frame n + 10 If multiple devices are all programmed to the transport layer test mode (while JESD_EN = 0), then JESD_EN is set to 1, and then SYSREF is used to align the LMFC of the devices, the patterns will be aligned to the SYSREF event (within the skew budget of JESD204B). For more details see JESD204B, section 5.1.6.3. 7.4.5.6 D21.5 Test Mode In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s). 7.4.5.7 K28.5 Test Mode In this test mode, the controller transmits a continuous stream of K28.5 characters. 7.4.5.8 Repeated ILA Test Mode In this test mode, the JESD204B link layer operates normally with one exception: when the ILA sequence completes, the sequence repeats indefinitely. Whenever the receiver issues a synchronization request, the transmitter will initiate code group synchronization. Upon completion of code group synchronization, the transmitter will repeatedly transmit the ILA sequence. If there is no active code group synchronization request at the moment the transmitter enters the test mode, the transmitter will behave as if it received one. 7.4.5.9 Modified RPAT Test Mode A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white spectral content for JESD204B compliance and jitter testing. Table 39 lists the pattern before and after 8b10b encoding. Table 39. Modified RPAT Pattern Values 54 OCTET NUMBER Dx.y NOTATION 8-BIT INPUT TO 8b10b ENCODER 0 D30.5 0xBE 1 D23.6 0xD7 2 D3.1 0x23 3 D7.2 0x47 4 D11.3 0x6B 5 D15.4 0x8F 6 D19.5 0xB3 7 D20.0 0x14 8 D30.2 0x5E 9 D27.7 0xFB 10 D21.1 0x35 11 D25.2 0x59 Submit Documentation Feedback 20b OUTPUT OF 8b10b ENCODER (2 CHARACTERS) 0x86BA6 0xC6475 0xD0E8D 0xCA8B4 0x7949E 0xAA665 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.5 Programming 7.5.1 Using the Serial Interface The serial interface is accessed using the following four pins: serial clock (SCLK), serial-data in (SDI), serial-data out (SDO), and serial-interface chip-select (SCS). Registers access is enabled through the SCS pin. SCS This signal must be asserted low to access a register through the serial interface. Setup and hold times with respect to the SCLK must be observed. SCLK Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement. SDI Each register access requires a specific 24-bit pattern at this input. This pattern consists of a readand-write (R/W) bit, register address, and register value. The data is shifted in MSB first. Setup and hold times with respect to the SCLK must be observed (see Figure 2). SDO The SDO signal provides the output data requested by a read command. This output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles. Each register access consists of 24 bits, as shown in Figure 2. The first bit is high for a read and low for a write. The next 15 bits are the address of the register that is to be written to. During write operations, the last 8 bits are the data written to the addressed register. During read operations, the last 8 bits on SDI are ignored, and, during this time, the SDO outputs the data from the addressed register. The serial protocol details are illustrated in Figure 67. Single Register Access SCS 1 8 16 17 24 SCLK Command Field SDI R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 Data Field A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Data Field SDO (read mode) Hi Z D7 D6 D5 D4 D3 D2 D1 D0 Hi Z Figure 67. Serial Interface Protocol - Single Read / Write Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 55 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Programming (continued) 7.5.1.1 Streaming Mode The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends (increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_STATIC bit (register 010h, bit 0). The streaming mode transaction details are shown in Figure 68. Multiple Register Access SCS 8 1 16 17 A0 D7 24 32 25 SCLK Command Field SDI SDO (read mode) R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 Data Field (write mode) A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 Data Field (write mode) D0 D7 D6 D5 D4 Data Field Hi Z D7 D6 D5 D4 D3 D2 D3 D2 D1 D0 Data Field D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Hi Z Figure 68. Serial Interface Protocol - Streaming Read / Write See the Register Map section for detailed information regarding the registers. NOTE The serial interface must not be accessed during calibration of the ADC. Accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. Writing or reading the serial registers also reduces dynamic performance of the ADC for the duration of the register access time. 56 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6 Register Map Several groups of registers provide control and configuration options for this device. Each following register description also shows the power-on reset (POR) state of each control bit. NOTE All multi-byte registers are arranged in little-endian format (the least-significant byte is stored at the lowest address) unless explicitly stated otherwise. Memory Map Address Reset Type Register Standard SPI-3.0 (0x000 to 0x00F) 0x000 0x3C R/W Configuration A Register 0x001 0x002 0x00 R Configuration B Register 0x00 R/W 0x003 0x03 R Chip Type Register 0x004-0x005 Undefined R RESERVED 0x006 0x03 R Chip Version Register 0x007-0x00B Undefined R RESERVED 0x00C-0x00D 0x0451 R Vendor Identification Register 0x00E-0x00F Undefined R RESERVED Device Configuration Register User SPI Configuration (0x010 to 0x01F) 0x010 0x00 R/W 0x011-0x01F Undefined R User SPI Configuration Register RESERVED General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) 0x020 0x9D R/W RESERVED 0x021 0x00 R/W Power-On Reset Register 0x022 0x40 R/W I/O Gain 0 Register 0x023 0x00 R/W I/O Gain 1 Register 0x024 0x00 R/W RESERVED 0x025 0x40 R/W I/O Offset 0 Register 0x026 0x00 R/W I/O Offset 1 Register 0x027 0x06 R/W RESERVED 0x028 0xBA R/W RESERVED 0x029 0xD4 R/W RESERVED 0x02A 0xEA R/W RESERVED 0x02B-0x02F Undefined R RESERVED Clock (0x030 to 0x03F) 0x030 0xC0 R/W Clock Generator Control 0 Register 0x031 0x07 R 0x032 0x80 R/W Clock Generator Control 2 Register 0x033 0xC3 R/W Analog Miscellaneous Register 0x034 0x2F R/W Input Clamp Enable Register 0x035 0xDF R/W RESERVED 0x036 0x00 R/W RESERVED 0x037 0x45 R/W RESERVED 0x038-0x03F Undefined R/W Clock Generator Status Register RESERVED Serializer (0x040 to 0x04F) 0x040 0x04 R/W 0x041-0x04F Undefined R Serializer Configuration Register RESERVED Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 57 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Register Map (continued) Memory Map (continued) Address Reset Type Register ADC Calibration (0x050 to 0x1FF) 0x050 0x06 R/W Calibration Configuration 0 Register 0x051 0xF4 R/W Calibration Configuration 1 Register 0x052 0x00 R/W RESERVED 0x053 0x5C R/W RESERVED 0x054 0x1C R/W RESERVED 0x055 0x92 R/W RESERVED 0x056 0x20 R/W RESERVED 0x057 0x10 R/W Calibration Background Control Register 0x058 0x00 R/W ADC Pattern and Over-Range Enable Register 0x059 0x00 R/W RESERVED 0x05A 0x00 R/W Calibration Vectors Register 0x05B Undefined R Calibration Status Register 0x05C 0x00 R/W RESERVED 0x05D-0x05E Undefined R/W RESERVED 0x05F 0x00 R/W RESERVED 0x060 Undefined R RESERVED 0x061 Undefined R RESERVED 0x062 Undefined R RESERVED 0x063 Undefined R RESERVED 0x064 Undefined R RESERVED 0x065 Undefined R RESERVED 0x066 0x02 R/W Timing Calibration Register 0x067 0x01 R/W RESERVED 0x068 Undefined R RESERVED 0x069 Undefined R RESERVED 0x06A 0x00 R/W RESERVED 0x06B 0x20 R/W RESERVED 0x06C-0x1FF Undefined R RESERVED Digital Down Converter and JESD204B (0x200-0x27F) 0x200 0x10 R/W Digital Down-Converter (DDC) Control 0x201 0x0F R/W JESD204B Control 1 0x202 0x00 R/W JESD204B Control 2 0x203 0x00 R/W JESD204B Device ID (DID) 0x204 0x00 R/W JESD204B Control 3 0x205 Undefined R/W JESD204B and System Status Register 0x206 0xF2 R/W Overrange Threshold 0 0x207 0xAB R/W Overrange Threshold 1 0x208 0x00 R/W Overrange Period 0x209-0x20B 0x00 R/W RESERVED 0x20C 0x00 R/W DDC Configuration Preset Mode 0x20D 0x00 R/W DDC Configuration Preset Select 0x20E-0x20F 0x0000 R/W Rational NCO Reference Divisor 0x210-0x213 0xC0000000 R/W NCO Frequency (Preset 0) 0x214-0x215 0x0000 R/W NCO Phase (Preset 0) PRESET 0 58 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Register Map (continued) Memory Map (continued) Address Reset Type 0x216 0xFF R/W DDC Delay (Preset 0) Register 0x217 0x00 R/W RESERVED PRESET 1 0x218-0x21B 0xC0000000 R/W NCO Frequency (Preset 1) 0x21C-0x21D 0x0000 R/W NCO Phase (Preset 1) 0x21E 0xFF R/W DDC Delay (Preset 1) 0x21F 0x00 R/W RESERVED 0x220-0x223 0xC0000000 R/W NCO Frequency (Preset 2) 0x224-0x225 0x0000 R/W NCO Phase (Preset 2) 0x226 0xFF R/W DDC Delay (Preset 2) 0x227 0x00 R/W RESERVED PRESET 2 PRESET 3 0x228-0x22B 0xC0000000 R/W NCO Frequency (Preset 3) 0x22C-0x22D 0x0000 R/W NCO Phase (Preset 3) 0x22E 0xFF R/W DDC Delay (Preset 3) 0x22F 0x00 R/W RESERVED 0x230-0x233 0xC0000000 R/W NCO Frequency (Preset 4) 0x234-0x235 0x0000 R/W NCO Phase (Preset 4) 0x236 0xFF R/W DDC Delay (Preset 4) 0x237 0x00 R/W RESERVED PRESET 4 PRESET 5 0x238-0x23B 0xC0000000 R/W NCO Frequency (Preset 5) 0x23C-0x23D 0x0000 R/W NCO Phase (Preset 5) 0x23E 0xFF R/W DDC Delay (Preset 5) 0x23F 0x00 R/W RESERVED 0x240-0x243 0xC0000000 R/W NCO Frequency (Preset 6) 0x244-0x245 0x0000 R/W NCO Phase (Preset 6) 0x246 0xFF R/W DDC Delay (Preset 6) 0x247 0x00 R/W RESERVED PRESET 6 PRESET 7 0x248-0x24B 0xC0000000 R/W NCO Frequency (Preset 7) 0x24C-0x24D 0x0000 R/W NCO Phase (Preset 7) 0x24E 0xFF R/W DDC Delay (Preset 7) 0x24F-0x251 0x00 R/W RESERVED 0x252-0x27F Undefined R RESERVED 0x0280-0x7FFF Undefined R RESERVED Reserved Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 59 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1 Register Descriptions 7.6.1.1 Standard SPI-3.0 (0x000 to 0x00F) Table 40. Standard SPI-3.0 Registers Address Reset Acronym Register Name 0x000 0x3C CFGA Configuration A Register Section Go 0x001 0x00 CFGB Configuration B Register Go 0x002 0x00 DEVCFG Device Configuration Register Go 0x003 0x03 CHIP_TYPE Chip Type Register Go 0x004-0x005 0x0000 RESERVED RESERVED Go 0x006 0x03 CHIP_VERSION Chip Version Register Go 0x007-0x00B Undefined RESERVED RESERVED 0x00C-0x00D 0x0451 VENDOR_ID Vendor Identification Register 0x00E-0x00F Undefined RESERVED RESERVED Go 7.6.1.1.1 Configuration A Register (address = 0x000) [reset = 0x3C] All writes to this register must be a palindrome (for example: bits [3:0] are a mirror image of bits [7:4]). If the data is not a palindrome, the entire write is ignored. Figure 69. Configuration A Register (CFGA) 7 SWRST R/W-0 6 RESERVED R/W-0 5 ADDR_ASC R/W-1 4 RESERVED R/W-1 3 RESERVED R/W-1 2 ADDR_ASC R/W-1 1 RESERVED R/W-0 0 SWRST R/W-0 Table 41. CFGA Field Descriptions Bit Field Type Reset Description 7 SWRST R/W 0 Setting this bit causes all registers to be reset to their default state. This bit is self-clearing. 6 RESERVED R/W 0 5 ADDR_ASC R/W 1 This bit is NOT reset by a soft reset (SWRST) 0 : descend – decrement address while streaming (address wraps from 0x0000 to 0x7FFF) 1 : ascend – increment address while streaming (address wraps from 0x7FFF to 0x0000) (default) 4 RESERVED R/W 1 Always returns 1 3 RESERVED R/W 2 ADDR_ASC R/W 1 RESERVED R/W 1100 Palindrome bits bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, bit 0 = bit 7 0 SWRST R/W 7.6.1.1.2 Configuration B Register (address = 0x001) [reset = 0x00] Figure 70. Configuration B Register (CFGB) 7 6 5 4 3 2 1 0 RESERVED R - 0x00h Table 42. CFGB Field Descriptions 60 Bit Field Type Reset 7:0 RESERVED R 0000 0000 Submit Documentation Feedback Description Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.1.3 Device Configuration Register (address = 0x002) [reset = 0x00] Figure 71. Device Configuration Register (DEVCFG) 7 6 5 4 3 2 1 RESERVED R/W-000000 0 MODE R/W-00 Table 43. DEVCFG Field Descriptions Bit Field Type Reset 7-2 RESERVED R/W 0000 00 1-0 MODE R/W 00 Description SPI 3.0 specification has 1 as low power functional mode and 2 as low power fast resume. This chip does not support these modes. 0: Normal Operation – full power and full performance (default) 1: Normal Operation – full power and full performance (default) 2: Power Down – Everything powered down 3: Power Down – Everything powered down 7.6.1.1.4 Chip Type Register (address = 0x003) [reset = 0x03] Figure 72. Chip Type Register (CHIP_TYPE) 7 6 5 4 3 2 RESERVED R-0000 1 0 CHIP_TYPE R-0011 Table 44. CHIP_TYPE Field Descriptions Bit Field Type Reset 7-4 RESERVED R 0000 3-0 CHIP_TYPE R 0011 Description Always returns 0x3, indicating that the part is a high speed ADC. 7.6.1.1.5 Chip Version Register (address = 0x006) [reset = 0x03] Figure 73. Chip Version Register (CHIP_VERSION) 7 6 5 4 3 CHIP_VERSION R-0000 0011 2 1 0 Table 45. CHIP_VERSION Field Descriptions Bit Field Type Reset 7-0 CHIP_VERSION R 0000 0011 Chip version, returns 0x03 Description Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 61 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451] Figure 74. Vendor Identification Register (VENDOR_ID) 15 14 13 12 11 10 9 8 3 2 1 0 VENDOR_ID R-0x04h 7 6 5 4 VENDOR_ID R-0x51h Table 46. VENDOR_ID Field Descriptions Bit 15-0 Field Type Reset Description VENDOR_ID R 0x0451h Always returns 0x0451 (TI Vendor ID) 7.6.1.2 User SPI Configuration (0x010 to 0x01F) Table 47. User SPI Configuration Registers Address Reset Acronym Register Name 0x010 0x00 USR0 User SPI Configuration Register Section 0x011-0x01F Undefined RESERVED RESERVED Go 7.6.1.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00] Figure 75. User SPI Configuration Register (USR0) 7 6 5 4 RESERVED R/W-0000 000 3 2 1 0 ADDR_STATIC R/W-0 Table 48. USR0 Field Descriptions Bit Field Type Reset 7-1 RESERVED R/W 0000 000 ADDR_STATIC R/W 0 0 62 Submit Documentation Feedback Description 0 : Use ADDR_ASC bit to define what happens to address during streaming (default). 1 : Address stays static throughout streaming operation. Useful for reading/writing calibration vector information at CAL_VECTOR register. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) Table 49. General Analog, Bias, Band Gap, and Track and Hold Registers Address Reset Acronym Register Name 0x020 0x9D RESERVED RESERVED Section 0x021 0x00 POR Power-On Reset Register Go 0x022 0x40 IO_GAIN_0 I/O Gain 0 Register Go 0x023 0x00 IO_GAIN_1 I/O Gain 1 Register Go 0x024 0x00 RESERVED RESERVED 0x025 0x40 IO_OFFSET_0 I/O Offset 0 Register Go 0x026 0x00 IO_OFFSET_1 I/O Offset 1 Register Go 0x027 0x06 RESERVED RESERVED 0x028 0xBA RESERVED RESERVED 0x029 0xD4 RESERVED RESERVED 0x02A 0xAA RESERVED RESERVED 0x02B-0x02F Undefined RESERVED RESERVED 7.6.1.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00] Figure 76. Power-On Reset Register (POR) 7 6 5 4 RESERVED R/W-0000 000 3 2 1 0 SPI_RES R/W-0 Table 50. POR Field Descriptions Bit Field Type Reset 7-1 RESERVED R/W 0000 000 SPI_RES R/W 0 0 Description Reset all digital. Emulates a power on reset (not self-clearing). Write a 0 and then write a 1 to emulate a reset. Transition from 0—>1 initiates reset. Default: 0 7.6.1.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40] Figure 77. I/O Gain 0 Register (IO_GAIN_0) 7 RESERVED R/W-0 6 GAIN_FS[14] R/W-1 5 GAIN_FS[13] R/W-0 4 GAIN_FS[12] R/W-0 3 GAIN_FS[11] R/W-0 2 GAIN_FS[10] R/W-0 1 GAIN_FS[9] R/W-0 0 GAIN_FS[8] R/W-0 Table 51. IO_GAIN_0 Field Descriptions Bit 7 6-0 Field Type Reset RESERVED R/W 0 GAIN_FS[14:8] R/W 100 0000 Description MSB Bits for GAIN_FS[14:0]. (See the IO_GAIN_1 description in General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 63 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00] Figure 78. IO_GAIN_1 Register (IO_GAIN_1) 7 GAIN_FS[7] R/W-0 6 GAIN_FS[6] R/W-0 5 GAIN_FS[5] R/W-0 4 GAIN_FS[4] R/W-0 3 GAIN_FS[3] R/W-0 2 GAIN_FS[2] R/W-0 1 GAIN_FS[1] R/W-0 0 GAIN_FS[0] R/W-0 Table 52. IO_GAIN_1 Field Descriptions Bit Field Type Reset 7-0 GAIN_FS[7:0] R/W 0000 0000 LSB bits for GAIN_FS[14:0] GAIN_FS[14:0] Value 0x0000 500 mVp-p 0x4000 725 mVp-p (default) 0x7FFF 950 mVp-p Description 7.6.1.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40] Figure 79. I/O Offset 0 Register (IO_OFFSET_0) 7 RESERVED R/W-0 6 OFFSET_FS[1 4] R/W-1 5 OFFSET_FS[1 3] R/W-0 4 OFFSET_FS[1 2] R/W-0 3 OFFSET_FS[1 1] R/W-0 2 OFFSET_FS[1 0] R/W-0 1 0 OFFSET_FS[9] OFFSET_FS[8] R/W-0 R/W-0 Table 53. IO_OFFSET_0 Field Descriptions Bit 7 6-0 Field Type Reset RESERVED R/W 0 OFFSET_FS[14:8] R/W 100 0000 Description MSB Bits for OFFSET_FS[14:0]. The ADC offset adjust feature has no effect when Background Calibration Mode is enabled. (See IO_OFFSET_1 description in the General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F) section). 7.6.1.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00] Figure 80. I/O Offset 1 Register (IO_OFFSET_1) 7 6 5 4 3 2 1 0 OFFSET_FS[7] OFFSET_FS[6] OFFSET_FS[5] OFFSET_FS[4] OFFSET_FS[3] OFFSET_FS[2] OFFSET_FS[1] OFFSET_FS[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 54. IO_OFFSET_1 Field Descriptions 64 Bit Field Type Reset 7-0 OFFSET_FS[7:0] R/W 0000 0000 LSB bits for OFFSET_FS[14:0]. OFFSET_FS[14:0] adjusts the offset of the entire ADC (all banks are impacted). OFFSET_FS[14:0] Value 0x0000 –28-mV offset 0x4000 no offset (default) 0x7FFF 28-mV offset The ADC offset adjust feature has no effect when Background Calibration Mode is enabled. Submit Documentation Feedback Description Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.4 Clock (0x030 to 0x03F) Table 55. Clock Registers Address Reset Acronym Register Name 0x030 0xC0 CLKGEN_0 Clock Generator Control 0 Register Section Go 0x031 0x07 CLKGEN_1 Clock Generator Status Register Go 0x032 0x80 CLKGEN_2 Clock Generator Control 2 Register Go 0x033 0xC3 ANA_MISC Analog Miscellaneous Register Go 0x034 0x2F IN_CL_EN Clamp Enable Register Go 0x035 0xDF RESERVED RESERVED 0x036 0x00 RESERVED RESERVED 0x037 0x45 RESERVED RESERVED 0x038-0x03F Undefined RESERVED RESERVED 7.6.1.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0] Figure 81. Clock Generator Control 0 Register (CLKGEN_0) 7 SysRef_Rcvr_E n R/W-1 6 SysRef_Pr_En 5 SysRefDetClr R/W-1 R/W-0 4 Clear Dirty Capture R/W-0 3 RESERVED R/W-0 2 1 0 DC_LVPECL_C DC_LVPECL_S DC_LVPECL_T LK_en YSREF_en S_en R/W-0 R/W-0 R/W-0 Table 56. CLKGEN_0 Field Descriptions Bit Field Type Reset Description 7 SysRef_Rcvr_En R/W 1 Default: 1 0 : SYSREF receiver is disabled. 1 : SYSREF receiver is enabled (default) 6 SysRef_Pr_En R/W 1 To power down the SYSREF receiver, clear this bit first, then clear SysRef_Rcvr_En. To power up the SYSREF receiver, set SysRef_Rcvr_En first, then set this bit. Default: 1 0 : SYSREF Processor is disabled. 1 : SYSREF Processor is enabled (default) 5 SysRefDetClr R/W 0 Default: 0 Write a 1 and then a 0 to clear the SysRefDet status bit. 4 Clear Dirty Capture R/W 0 Default: 0 Write a 1 and then a 0 to clear the DC status bit. 3 RESERVED R/W 0 Default: 0 2 DC_LVPECL_CLK_en R/W 0 Default: 0 Set this bit if DEVCLK is a DC-coupled LVPECL signal through a 50-Ω resistor. 1 DC_LVPECL_SYSREF_en R/W 0 Default: 0 Set this bit if SYSREF is a DC-coupled LVPECL signal through a 50-Ω resistor. 0 DC_LVPECL_TS_en R/W 0 Default: 0 Set this bit if TimeStamp is a DC-coupled LVPECL signal through a 50-Ω resistor. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 65 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07] Figure 82. Clock Generator Status Register (CLKGEN_1) 7 SysRefDet R-0 6 Dirty Capture R-0 5 4 3 2 1 0 RESERVED R-00 0111 Table 57. CLKGEN_1 Field Descriptions Bit Field Type Reset Description 7 SysRefDet R 0 When high, indicates that a SYSREF rising edge was detected. To clear this bit, write SysRefDetClr to 1 and then back to 0. 6 Dirty Capture R 0 When high, indicates that a SYSREF rising edge occurred very close to the device clock edge, and setup or hold is not ensured (dirty capture). To clear this bit, write CDC to1 and then back to 0. NOTE: When sweeping the timing on SYSREF, it may jump across the clock edge without triggering this bit. The REALIGNED status bit must be used to detect this (see the JESD_STATUS register description in Digital Down Converter and JESD204B (0x200-0x27F)) 5-0 RESERVED R 00 0111 Reserved register. Always returns 000111b 7.6.1.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80] Figure 83. Clock Generator Control 2 Register (CLKGEN_2) 7 6 5 4 3 2 RESERVED R/W-1000 1 0 RDEL R/W-0000 Table 58. CLKGEN_2 Field Descriptions 66 Bit Field Type Reset Description 7-4 RESERVED R/W 1000 Default: 1000b 3-0 RDEL R/W 0000 Adjusts the delay of the SYSREF input signal with respect to DEVCLK. Each step delays SYSREF by 20 ps (nominal) Default: 0 Range: 0 to 15 decimal Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3] Figure 84. Analog Miscellaneous Register (ANA_MISC) 7 6 5 RESERVED R/W-1100 0 4 3 2 SYNC_DIFF_PD R/W-0 1 0 RESERVED R/W-11 Table 59. ANA_MISC Field Descriptions Bit Field Type Reset 7-3 RESERVED R/W 1100 0 SYNC_DIFF_PD R/W 0 Set this bit to power down the differential SYNC~± inputs for the JESD204B interface. The SYNC~± inputs can also serve as the TimeStamp input receiver for the TimeStamp function. The receiver must be powered up to support the time stamp or differential SYNC~. Default: 0b RESERVED R/W 11 Default: 11b 2 1-0 Description 7.6.1.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F] Figure 85. Input Clamp Enable Register (IN_CL_EN) 7 6 RESERVED R/W-00 5 INPUT_CLAMP_EN R/W-1 4 3 2 RESERVED R/W-0 1111 1 0 Table 60. IN_CL_EN Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00 Default: 00b INPUT_CLAMP_EN R/W 1 Set this bit to enable the analog input active clamping circuit. Enabled by default. Default: 1b RESERVED R/W 0 1111 Default: 01111b 5 4-0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 67 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.5 Serializer (0x040 to 0x04F) Table 61. Serializer Registers Address Reset Acronym Register Name 0x040 0x04 SER_CFG Serializer Configuration Register Section 0x041-0x04F Undefined RESERVED RESERVED Go 7.6.1.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04] Figure 86. Serializer configuration Register (SER_CFG) 7 6 5 4 3 RESERVED R/W-0000 2 1 SERIALIZER PRE-EMPHASIS R/W-0100 0 Table 62. SER_CFG Field Descriptions 68 Bit Field Type Reset 7-4 RESERVED R/W 0000 3-0 SERIALIZER PRE-EMPHASIS R/W 0100 Submit Documentation Feedback Description Control bits for the pre-emphasis strength of the serializer output driver. Pre-emphasis is required to compensate the low pass behavior of the PCB trace. Default: 4d Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.6 ADC Calibration (0x050 to 0x1FF) Table 63. ADC Calibration Registers Address Reset Acronym Register Name 0x050 0x06 CAL_CFG0 Calibration Configuration 0 Register Section Go 0x051 0xF4 CAL_CFG1 Calibration Configuration 1 Register Go 0x052 0x00 RESERVED RESERVED 0x053 0x5C RESERVED RESERVED 0x054 0x1C RESERVED RESERVED 0x055 0x92 RESERVED RESERVED 0x056 0x20 RESERVED RESERVED 0x057 0x10 CAL_BACK Calibration Background Control Register Go 0x058 0x00 ADC_PAT_OVR_EN ADC Pattern and Over-Range Enable Register Go 0x059 0x00 RESERVED RESERVED 0x05A 0x00 CAL_VECTOR Calibration Vectors Register Go 0x05B Undefined CAL_STAT Calibration Status Register Go 0x05C 0x00 RESERVED RESERVED 0x05D-0x05E Undefined RESERVED RESERVED 0x05F 0x00 RESERVED RESERVED 0x060 Undefined RESERVED RESERVED 0x061 Undefined RESERVED RESERVED 0x062 Undefined RESERVED RESERVED 0x063 Undefined RESERVED RESERVED 0x064 Undefined RESERVED RESERVED 0x065 Undefined RESERVED RESERVED 0x066 0x02 T_CAL Timing Calibration Register 0x067 0x01 RESERVED RESERVED 0x068 Undefined RESERVED RESERVED 0x069 Undefined RESERVED RESERVED 0x06A 0x00 RESERVED RESERVED 0x06B 0x20 RESERVED RESERVED 0x06C-0x1FF Undefined RESERVED RESERVED Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Go Submit Documentation Feedback 69 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06] Figure 87. Calibration Configuration 0 Register (CAL_CFG0) 7 6 RESERVED R/W-00 5 TIME_STAMP_EN R/W-0 4 CALIBRATION_READ_WRITE_EN R/W-0 3 CAL_SFT R/W-0 2 1 RESERVED R/W-110 0 Table 64. CAL_CFG0 Field Descriptions (1) Bit Field Type Reset 7- RESERVED R/W 00 Description 5 TIME_STAMP_EN R/W 0 Enables the capture of the external time stamp signal to allow tracking of input signal. Default: 0 4 CALIBRATION_READ_WRITE_EN R/W 0 Enables the scan register to read or write calibration vectors at register 0x05A. Default: 0 3 CAL_SFT (1) R/W 0 Software calibration bit. Set bit to initiate foreground calibration. This bit is self-clearing. This bit resets the calibration state machine. Most calibration SPI registers are not synchronized to the calibration clock. Changing them may corrupt the calibration state machine. Always set CAL_SFT AFTER making any changes to the calibration registers. 2-0 RESERVED R/W 110 Default: 110 IMPORTANT NOTE: Setting CAL_SFT can glitch internal state machines. The JESD_EN bit must be cleared and then set after setting CAL_SFT. 7.6.1.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4] Figure 88. Calibration Configuration 1 Register (CAL_CFG1) 7 RESERVED R/W-1 6 5 LOW_SIG_EN R/W-111 4 3 2 1 0 RESERVED R/W-0100 Table 65. CAL_CFG1 Field Descriptions Bit Field Type Reset RESERVED R/W 1 6-4 LOW_SIG_EN R/W 111 3-0 RESERVED R/W 0100 7 70 Submit Documentation Feedback Description Controls signal range optimization for calibration processes. 111: Calibration is optimized for lower amplitude input signals (< –10dBFS). 000: Calibration is optimized for large (-1dBFS) input signals. Default: 111 but recommend 000 for large input signals. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10] Figure 89. Calibration Background Control Register (CAL_BACK) 7 6 5 4 3 2 1 CAL_CONT R/W-0 RESERVED R/W-0001 00 0 CAL_BCK R/W-0 Table 66. CAL_BACK Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0001 00 Set to 0001 00b 1 CAL_CONT R/W 0 CAL_CONT is the only calibration register bit that can be modified while background calibration is ongoing. This bit must be set to 0 before modifying any of the other bits. 0 : Pause or stop background calibration sequence. 1 : Start background calibration sequence. 0 CAL_BCK R/W 0 Background calibration mode enabled. When pausing background calibration leave this bit set, only change CAL_CONT to 0. If CAL_BCK is set to 0 after background calibration has been operation the calibration processes may stop in an incomplete condition. Set CAL_SFT to perform a foreground calibration 7.6.1.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00] Figure 90. ADC Pattern and Over-Range Enable Register (ADC_PAT_OVR_EN) 7 6 5 RESERVED R/W-0000 0 4 3 2 ADC_PAT_EN R/W-0 1 OR_EN R/W-0 0 RESERVED R/W-0 1 0 Table 67. ADC_PAT_OVR_EN Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0000 0 Set to 00000b 2 ADC_PAT_EN R/W 0 Enable ADC test pattern 1 OR_EN R/W 0 Enable over-range output 0 RESERVED R/W 0 Set to 0 7.6.1.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00] Figure 91. Calibration Vectors Register (CAL_VECTOR) 7 6 5 4 3 2 CAL_DATA R/W-0000 0000 Table 68. CAL_VECTOR Field Descriptions Bit Field Type Reset 7-0 CAL_DATA R/W 0000 0000 Repeated reads of this register outputs all the calibration register values for analysis if the CALIBRATION_READ_WRITE_EN bit is set. Repeated writes of this register inputs all the calibration register values for configuration if the CAL_RD_EN bit is set. Description Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 71 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.6.6 Calibration Status Register (address = 0x05B) [reset = undefined] Figure 92. Calibration Status Register (CAL_STAT) 7 6 5 4 RESERVED R-0000 10 3 2 1 CAL_CONT_OFF R-X 0 FIRST_CAL_DONE R-X Table 69. CAL_STAT Field Descriptions Bit Field Type Reset 7-2 RESERVED R 0000 10XX Description 1 CAL_CONT_OFF R X After clearing CAL_CONT, calibration does not stop immediately. Use this register to confirm it has stopped before changing calibration settings. 0: Indicates calibration is running (foreground or background) 1: Indicates that calibration is finished or stopped because CAL_CONT = 0 0 FIRST_CAL_DONE R X Indicates first calibration sequence has been done and ADC is operational. 7.6.1.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02] Figure 93. Timing Calibration Register (T_CAL) 7 6 5 4 RESERVED R/W-0000 001 3 2 1 0 T_AUTO R/W-0 Table 70. CAL_STAT Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0000 001 Set to 0000001b T_AUTO R/W 0 Set to enable automatic timing optimization. Timing calibration will occur once CAL_SFT is set. 0 72 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7 Digital Down Converter and JESD204B (0x200-0x27F) Table 71. Digital Down Converter and JESD204B Registers Address Reset Acronym Register Name 0x200 0x10 DDC_CTRL1 Digital Down-Converter (DDC) Control Section Go 0x201 0x0F JESD_CTRL1 JESD204B Control 1 Go 0x202 0x00 JESD_CTRL2 JESD204B Control 2 Go 0x203 0x00 JESD_DID JESD204B Device ID (DID) Go 0x204 0x00 JESD_CTRL3 JESD204B Control 3 Go 0x205 Undefined JESD_STATUS JESD204B and System Status Register Go 0x206 0xF2 OVR_T0 Overrange Threshold 0 Go 0x207 0xAB OVR_T1 Overrange Threshold 1 Go 0x208 0x00 OVR_N Overrange Period Go 0x209-0x20B 0x00 RESERVED RESERVED 0x20C 0x00 NCO_MODE DDC Configuration Preset Mode Go 0x20D 0x00 NCO_SEL DDC Configuration Preset Select Go 0x20E-0x20F 0x0000 NCO_RDIV Rational NCO Reference Divisor Go 0x210-0x213 0xC0000000 NCO_FREQ0 NCO Frequency (Preset 0) Go 0x214-0x215 0x0000 NCO_PHASE0 NCO Phase (Preset 0) Go 0x216 0xFF DDC_DLY0 DDC Delay (Preset 0) Go 0x217 0x00 RESERVED RESERVED NCO_FREQ1 NCO Frequency (Preset 1) Go NCO_PHASE1 NCO Phase (Preset 1) Go Go 0x218-0x21B 0xC0000000 0x21C-0x21D 0x0000 0x21E 0xFF DDC_DLY1 DDC Delay (Preset 1) 0x21F 0x00 RESERVED RESERVED 0x220-0x223 0xC0000000 NCO_FREQ2 NCO Frequency (Preset 2) Go 0x224-0x225 0x0000 NCO_PHASE2 NCO Phase (Preset 2) Go 0x226 0xFF DDC_DLY2 DDC Delay (Preset 2) Go 0x227 0x00 RESERVED RESERVED NCO_FREQ3 NCO Frequency (Preset 3) Go NCO_PHASE3 NCO Phase (Preset 3) Go Go 0x228-0x22B 0xC0000000 0x22C-0x22D 0x0000 0x22E 0xFF DDC_DLY3 DDC Delay (Preset 3) 0x22F 0x00 RESERVED RESERVED 0x230-0x233 0xC0000000 NCO_FREQ4 NCO Frequency (Preset 4) Go 0x234-0x235 0x0000 NCO_PHASE4 NCO Phase (Preset 4) Go 0x236 0xFF DDC_DLY4 DDC Delay (Preset 4) Go 0x237 0x00 RESERVED RESERVED NCO_FREQ5 NCO Frequency (Preset 5) Go NCO_PHASE5 NCO Phase (Preset 5) Go Go 0x238-0x23B 0xC0000000 0x23C-0x23D 0x0000 0x23E 0xFF DDC_DLY5 DDC Delay (Preset 5) 0x23F 0x00 RESERVED RESERVED 0x240-0x243 0xC0000000 NCO_FREQ6 NCO Frequency (Preset 6) Go 0x244-0x245 0x0000 NCO_PHASE6 NCO Phase (Preset 6) Go 0x246 0xFF DDC_DLY6 DDC Delay (Preset 6) Go 0x247 0x00 RESERVED RESERVED NCO_FREQ7 NCO Frequency (Preset 7) Go NCO_PHASE7 NCO Phase (Preset 7) Go Go 0x248-0x24B 0xC0000000 0x24C-0x24D 0x0000 0x24E 0xFF DDC_DLY7 DDC Delay (Preset 7) 0x24F-0x251 0x00 RESERVED RESERVED 0x252-0x27F Undefined RESERVED RESERVED Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 73 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.7.1 Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10] Figure 94. Digital Down-Converter (DDC) Control Register (DDC_CTRL1) 7 RESERVED 6 5 SFORMAT R/W-00 R/W-0 4 DDC GAIN BOOST R/W-1 3 2 1 0 DMODE R/W-0000 Table 72. DDC_CTRL1 Field Descriptions Bit Field Type Reset 7-6 RESERVED R/W 00 5 SFORMAT R/W 0 Output sample format for bypass mode: 0 : Offset binary (default) 1 : Signed 2s complement (1) 4 DDC GAIN BOOST R/W 1 0 : Final filter has 0-dB gain (recommended when NCO is set near DC). 1 : Final filter has 6.02-dB gain (default) DMODE (2) R/W 0000 0 : Bypass mode (12-bit output, decimate-by-1, DDC off) (default) 1 : Reserved 2 : decimate-by-4 3 : decimate-by-8 4 : decimate-by-10 5 : decimate-by-16 6 : decimate-by-20 7 : decimate-by-32 8..15 : RESERVED 3-0 (1) (2) Description Decimated modes always output in signed 2s complement. The DMODE setting must only be changed when JESD_EN is 0. 7.6.1.7.2 JESD204B Control 1 Register (address = 0x201) [reset = 0x0F] Figure 95. JESD204B Control 1 Register (JESD_CTRL1) 7 SCR R/W-0 6 5 4 K_Minus_1 R/W-000 11 3 2 1 DDR R/W-1 0 JESD_EN R/W-1 Table 73. JESD_CTRL1 Field Descriptions Bit Field Type Reset Description 7 SCR R/W 0 0 : Scrambler disabled (default) 1 : Scrambler enabled K_Minus_1 R/W 000 11 K is the number of frames per multiframe, and K – 1 is programmed here. Default: K = 4, K_Minus_1 = 3. Depending on the decimation (D) and serial rate (DDR), there are constraints on the legal values of K. 1 DDR R/W 1 0 : SDR serial rate (ƒ(BIT) = ƒS) 1 : DDR serial rate (ƒ(BIT) = 2ƒS) (default) 0 JESD_EN (1) R/W 1 0 : Block disabled 1 : Normal operation (default) 6-2 (1) 74 Before altering any parameters in the JESD_CTRL1 register, you must set JESD_EN to 0. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7.3 JESD204B Control 2 Register (address = 0x202) [reset = 0x00] Figure 96. JESD204B Control 2 Register (JESD_CTRL2) 7 P54 R/W-0 6 SYNC_DIFFSEL R/W-0 5 4 RESERVED R/W-00 3 2 1 JESD204B_TEST R/W-0000 0 Table 74. JESD_CTRL2 Field Descriptions Bit Field Type Reset Description 7 P54 R/W 0 0 : Disable 5/4 PLL. Serial bit rate is 1x or 2x based on DDR parameter. 1 : Enable 5/4 PLL. Serial bit rate is 1.25x or 2.5x based on DDR parameter. 6 SYNC_DIFFSEL R/W 0 0 : Use SYNC_SE_N input for SYNC_N function 1 : Use SYNC_DIFF_N input for SYNC_N function R/W 00 Set to 00b R/W 0000 See 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS15 test mode 3 : PRBS23 test mode 4 : Ramp test mode 5 : Short and long transport layer test mode 6 : D21.5 test mode 7 : K28.5 test mode 8 : Repeated ILA test mode 9 : Modified RPAT test mode 10: Serial outputs held low 11: Serial outputs held high 12 through 15 : RESERVED 5-4 RESERVED 3-0 (1) JESD204B_TEST (1) The JESD_CTRL2 register must only be changed when JESD_EN is 0. 7.6.1.7.4 JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00] Figure 97. JESD204B Device ID (DID) Register (JESD_DID) 7 6 5 4 3 2 1 0 JESD_DID R/W-0000 0000 Table 75. JESD_DID Field Descriptions Bit 7-0 (1) Field JESD_DID (1) Type Reset Description R/W 0000 0000 Specifies the DID value that is transmitted during the second multiframe of the JESD204B ILA. The DID setting must only be changed when JESD_EN is 0. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 75 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.7.5 JESD204B Control 3 Register (address = 0x204) [reset = 0x00] Figure 98. JESD204B Control 3 Register (JESD_CTRL3) 7 6 5 4 3 2 1 0 RESERVED R/W-0000 00 FCHAR R/W-00 Table 76. JESD_CTRL3 Field Descriptions (1) Bit Field Type Reset 7-2 RESERVED R/W 0000 00 1-0 FCHAR (1) R/W 00 Description Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically according to JESD204B Section 5.3.3.4. When using a JESD204B receiver, always use FCHAR=0. When using a general purpose 8-b or 10-b receiver, the K28.7 character can cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers realign to the false comma. To avoid this, program FCHAR to 1 or 2. 0 : Use K28.7 (default) (JESD204B compliant) 1 : Use K28.1 (not JESD204B compliant) 2 : Use K28.5 (not JESD204B compliant) 3 : Reserved The JESD_CTRL3 register must only be changed when JESD_EN is 0. 7.6.1.7.6 JESD204B and System Status Register (address = 0x205) [reset = Undefined] See the JESD204B Synchronization Features section for more details. Figure 99. JESD204B and System Status Register (JESD_STATUS) 7 RESERVED R/W-0 6 LINK_UP R/W-0 5 SYNC_STATUS R/W-X 4 REALIGNED R/W-X 3 ALIGNED R/W-0 2 PLL_LOCKED R/W-0 1 0 RESERVED R/W-00 Table 77. JESD_STATUS Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0 Always returns 0 6 LINK_UP R/W 0 When set, indicates that the JESD204B link is in the DATA_ENC state. 5 SYNC_STATUS R/W X Returns the state of the JESD204B SYNC~ signal (SYNC_SE_N or SYNC_DIFF_N). 0 : SYNC~ asserted 1 : SYNC~ deasserted 4 REALIGNED R/W X When high, indicates that the div8 clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit clears it. 3 ALIGNED R/W 0 When high, indicates that the multiframe clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit clears it. 2 PLL_LOCKED R/W 0 When high, indicates that the PLL is locked. RESERVED R/W 0 Always returns 0 1-0 76 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7.7 Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2] Figure 100. Overrange Threshold 0 Register (OVR_T0) 7 6 5 4 3 2 1 0 OVR_T0 R/W-1111 0010 Table 78. OVR_T0 Field Descriptions Bit Field Type Reset 7-0 OVR_T0 R/W 1111 0010 Over-range threshold 0. This parameter defines the absolute sample level that causes control bit 0 to be set. Control bit 0 is attached to the DDC I output samples. The detection level in dBFS (peak) is 20log10(OVR_T0 / 256) Default: 0xF2 = 242 → –0.5 dBFS Description 7.6.1.7.8 Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB] Figure 101. Overrange Threshold 1 Register (OVR_T1) 7 6 5 4 3 2 1 0 OVR_T1 R/W-1010 1011 Table 79. OVR_T1 Field Descriptions Bit Field Type Reset Description 7-0 OVR_T1 R/W 1010 1011 Overrange threshold 1. This parameter defines the absolute sample level that causes control bit 1 to be set. Control bit 1 is attached to the DDC Q output samples. The detection level in dBFS (peak) is 20log10(OVR_T1 / 256) Default: 0xAB = 171 → –3.5 dBFS 7.6.1.7.9 Overrange Period Register (address = 0x208) [reset = 0x00] Figure 102. Overrange Period Register (OVR_N) 7 6 5 RESERVED R/W-0000 0 4 3 2 1 OVR_N R/W-000 0 Table 80. OVR_N Field Descriptions (1) Bit Field Type Reset 7-3 RESERVED R/W 0000 0 2-0 OVR_N (1) R/W 000 Description This bit adjusts the monitoring period for the OVR[1:0] output bits. The period is scaled by 2OVR_N. Incrementing this field doubles the monitoring period. Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 77 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00] Figure 103. DDC Configuration Preset Mode Register (NCO_MODE) 7 6 5 4 RESERVED R/W-0000 000 3 2 1 0 CFG_MODE R/W-0 Table 81. NCO_MODE Field Descriptions Bit Field Type Reset 7-1 RESERVED R/W 0000 000 0 CFG_MODE R/W 0 Description The NCO frequency and phase are set by the NCO_FREQx and NCO_PHASEx registers, where x is the configuration preset (0 through 7). The DDC delay setting is defined by the DDC_DLYx register. 0 : Use NCO_[2:0] input pins to select the active DDC and NCO configuration preset. 1 : Use the NCO_SEL register to select the active DDC and NCO configuration preset. 7.6.1.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00] Figure 104. DDC Configuration Preset Select Register (NCO_SEL) 7 6 5 RESERVED R/W-0000 0 4 3 2 1 NCO_SEL R/W-000 0 Table 82. NCO_SEL Field Descriptions 78 Bit Field Type Reset 7-3 RESERVED R/W 0000 0 2-0 NCO_SEL R/W 000 Submit Documentation Feedback Description When NCO_MODE = 1, this register is used to select the active configuration preset. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000] Figure 105. Rational NCO Reference Divisor Register (NCO_RDIV) 15 14 13 12 11 10 9 8 3 2 1 0 NCO_RDIV R/W-0x00h 7 6 5 4 NCO_RDIV R/W-0x00h Table 83. NCO_RDIV Field Descriptions Bit 15-0 Field Type Reset Description NCO_RDIV R/W 0x0000h Sometimes the 32-bit NCO frequency word does not provide the desired frequency step size and can only approximate the desired frequency. This results in a frequency error. Use this register to eliminate the frequency error. Use this equation to compute the proper value to program: NCO_RDIV = ƒS / ƒ(STEP) / 128 where • • ƒS is the ADC sample rate ƒ(STEP) is the desired NCO frequency step size (10) For example, if ƒS= 3072 MHz, and ƒ(STEP) = 10 KHz then: NCO_RDIV = 3072 MHz / 10 KHz / 128 = 2400 (11) Any combination of ƒS and ƒ(STEP) that results in a fractional value for NCO_RDIV is not supported. Values of NCO_RDIV larger than 8192 can degrade the NCO’s SFDR performance and are not recommended. This register is used for all configuration presets. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 79 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 7.6.1.7.13 NCO Frequency (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 106. NCO Frequency (Preset x) Register (NCO_FREQ_x) 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NCO_FREQ_x R/W-0xC0h 23 22 21 20 NCO_FREQ_x R/W-0x00h 15 14 13 12 NCO_FREQ_x R/W-0x00h 7 6 5 4 NCO_FREQ_x R/W-0x00h Table 84. NCO_FREQ_x Field Descriptions Bit 31-0 Field Type Reset Description NCO_FREQ_x R/W 0xC00000 00h Changing this register after the JESD204B interface is running results in non-deterministic NCO phase. If deterministic phase is required, the JESD204B interface must be re-initialized after changing this register. The NCO frequency (ƒ(NCO)) is: ƒ(NCO) = NCO_FREQ_x × 2–32 × ƒS where • • ƒS is the sampling frequency of the ADC NCO_FREQ_x is the integer value of this register (12) This register can be interpreted as signed or unsigned. Use this equation to determine the value to program: NCO_FREQ_x = 232 × ƒ(NCO) / ƒS (13) If the equation does not result in an integer value, you must choose an alternate frequency step (ƒ(STEP) ) and program the NCO_RDIV register. Then use one of the following equations to compute NCO_FREQ_x: NCO_FREQ_x = round(232 × ƒ(NCO) / ƒS) NCO_FREQ_x = round(225 × ƒ(NCO) / ƒ(STEP) / NCO_RDIV) 80 Submit Documentation Feedback (14) (15) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 7.6.1.7.14 NCO Phase (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 107. NCO Phase (Preset) Register (NCO_PHASE_x) 15 14 13 12 11 NCO_PHASE_x R/W-0x00h 10 9 8 7 6 5 4 2 1 0 3 NCO_PHASE_x R/W-0x00h Table 85. NCO_PHASE_x Field Descriptions Bit 15-0 Field Type Reset Description NCO_PHASE_x R/W 0x0000h This value is MSB-justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is NCO_PHASE_x × 2–16 × 2π (16) This register can be interpreted as signed or unsigned. 7.6.1.7.15 DDC Delay (Preset x) Register (address = see Table 71) [reset = see Table 71] Figure 108. DDC Delay (Preset) Register (DDC_DLY_x) 7 6 5 4 3 2 1 0 DDC_DLY_x R/W-0xFFh Table 86. DDC_DLY_x Field Descriptions Bit Field Type Reset Description 7-0 DDC_DLY_x R/W 0xFFh DDC delay for configuration preset 0 This register provides fine adjustments to the DDC group delay. The step size is one half of an ADC sample period (t(DEVCLK) / 2). This is equivalent to Equation 17. tO / (2 × D) where • • tO is the DDC output sample period D is the decimation factor (17) The legal range for this register is 0 to 2D-1. Illegal values result in undefined behavior. Example: When D = 8, the legal register range is 0 to 15. The step size is tO / 16 and the maximum delay is 15 × tO / 16. Programming this register to 0xFF (the default value) powers down and bypasses the fractional delay filter which reduces the DDC latency by 34 ADC sample periods (as compared to the 0 setting). Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 81 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ADC12J1600 and ADC12J2700 devices are a wideband sampling and digital tuning device. The ADC input captures input signals from DC to greater than 3 GHz. The DDC performs digital-down conversion and programmable decimation filtering, and outputs complex (15 bit I and 15 bit Q) data. In DDC Bypass Mode (Decimation = 1) the raw 12 bit ADC data is also available. The resulting output data is output on the JESD204B data interface for capture by the downstream capture or processing device. Most frequency-domain applications benefit from DDC capability to select the desired frequency band and provide only the necessary bandwidth of output data, minimizing the required number of data signals. Time domain applications generally require the raw 12-bit ADC output data provided by the DDC bypass feature. 8.2 Typical Application 8.2.1 RF Sampling Receiver An RF Sampling Receiver is used to directly sample a signal in the RF frequency range and provide the data for the captured signal to downstream processing. The wide input bandwidth, high sampling rate, and DDC features of the ADC12J1600 and ADC12J2700 make them ideally suited for this application. SPI Master Over-Range Logic FPGA 1:2 Balun 4.7 nF BPF L Lanes ADC Limiter Diode JESD204B Receiver SYNC~ SYSREF DEVCLK 4.7 nF JESD204B Clock Generator Data Processing and Storage SYSREF and FPGA CLKs Figure 109. Simplified Schematic 82 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Typical Application (continued) 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 87. Table 87. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Signal center frequency 2500 MHz Signal bandwidth 100 MHz Signal nominal amplitude –7 dBm Signal maximum amplitude 6 dBm Minimum SINAD (in bandwidth of interest) 48 dBc Minimum SFDR (in bandwidth of interest) 60 dBc 8.2.1.2 Detailed Design Procedure Use the following steps to design the RF receiver: • Use the signal-center frequency and signal bandwidth to select an appropriate sampling rate (DEVCLK frequency) and decimate factor (x / 4 to x / 32). • Select the sampling rate so that the band of interest is completely within a Nyquist zone. • Select the sampling rate so that the band of interest is away from any harmonics or interleaving tones. • Use a frequency planning tool, such as the ADC harmonic calculator (see the Development Support section). • Select the decimation factor that provides the highest factor possible with an adequate alias-protected output bandwidth to capture the frequency bandwidth of interest. • Select other system components to provide the needed signal frequency range and DEVCLK rate. • See Table 1 for recommended balun components. • Select bandpass filters and limiter components based on the requirement to attenuate unwanted signals outside the band of interest (blockers) and to prevent large signals from damaging the ADC inputs. See the Absolute Maximum Ratings table. The LMK048xx JESD204B clocking devices can provide the DEVCLK clock and other system clocks for ƒ(DEVCLK) < 3101 MHz. For DEVCLK frequencies up to 4 GHz the consider using the LMX2581 and TRF3765 devices as the DEVCLK source. Use the LMK048xx device to provide the JESD204B clocks. For additional device information, see the Related Documentation section. 8.2.1.3 Application Curves The following curves show an RF signal at 2497.97 MHz captured at a sample rate of 1600 MSPS. Figure 110 shows the spectrum for the full Nyquist band. Figure 111 shows the spectrum for the output data in decimate-by32 mode with ƒ(NCO) equal to 700 MHz. Figure 111 shows the ability to provide only the spectrum of interest in the decimated output data. Figure 111 also shows how proper selection of the sampling rate can ensure interleaving tones are outside the band of interest and outside the decimated frequency range. Lastly, Figure 111 shows the reduction in the noise floor provided by the processing gain of decimation. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 83 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 0 0 -20 Magnitude (dBFS) Magnitude (dBFS) -25 -50 -75 -100 -40 -60 -80 -100 -125 0 80 160 240 320 400 480 560 Frequency (MHz) DDC Bypass Mode FIN = 2497.97 MHz at –1 dBFS 640 720 -120 -25 800 -12.5 D095 ƒS = 1600 MSPS 0 Frequency (MHz) ƒS = 1600 MSPS FIN = 2497.97 MHz at –1 dBFS Figure 110. Spectrum — DDC Bypass Mode 12.5 25 D094 ƒ(NCO) = 2500 MHz Figure 111. Spectrum — Decimate-by-32 8.2.2 Oscilloscope The ADC12J1600 and ADC12J2700 devices are equally well-suited for high-speed time-domain applications such as oscilloscopes. The following typical application is for a generic high-speed oscilloscope. Adjustable gain is provided by the front-end resistor ladder and selection mux, and the gain adjustments of the LMH6518 device. Additional gain fine-tuning can be achieved using the full-scale range adjustment features of the ADC. MEMORY MEMORY MEMORY DISPLAY Display Interface Memory Interface SPI Master 1 nF 900 k 8 Lanes 90 k ADC MUX SYNC~ JFET LNA 10 k DEVCLK 50 JESD204 Receiver Data Processing / Storage VCMO SYSREF Hi-Z 50-Switch Over-Range Logic LMH6518 Output Amp SYSREF and FPGA CLKs JESD204 Clock Generator LMH6518 Aux Amp Trigger Logic Gain Control + LMH7220 DAC101C085 DAC Figure 112. Simplified Schematic for an Oscilloscope 84 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 8.2.2.1 Design Requirements For this design example, use the parameters listed in Table 88. Table 88. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Maximum sample rate 1600 MSPS Maximum input frequency 1500 MHz 1-dB flat-frequency range 0 to 1000 MHz Signal maximum amplitude 6 dBm Signal minimum amplitude 48 dBc Maximum capture depth 1 million points 8.2.2.2 Detailed Design Procedure Use the following primary steps to design a 12-bit oscilloscope: • Select the desired sampling rate based on the maximum sampling-rate requirement. • Select the input path components (LNA, amplifier, and other components) based on the maximum input frequency and 1-dB flat-frequency range requirements. • Set the attenuation range steps based on the required minimum and maximum values for the signal amplitude. • Select the memory size based on the resolution of the ADC output (12 bits) and the required maximum number of sample points. 8.2.2.3 Application Curves 4000 0 3200 -20 Magnitude (dBFS) Magnitude (LSB) The following curves show the time-domain sample data for a 150-MHz input signal at –1 dBFS, sampled at 1600 MSPS using the ADC12J1600 device. Figure 113 shows the raw time-domain data. Figure 114 shows the spectrum of the captured signal which shows the additional capability of a 12-bit ADC oscilloscope to provide basic spectrum-analysis functions with reasonable performance. 2400 1600 -40 -60 -80 800 -100 0 0 8 16 24 Sample Number (n) FIN = 147.97 MHz at –1 dBFS 32 40 0 80 160 D097 ƒS = 1600 MSPS Figure 113. Raw Time-Domain Data 240 320 400 480 560 Frequency (MHz) FIN = 147.97 MHz at –1 dBFS 640 720 800 D098 ƒS = 1600 MSPS Figure 114. Captured Signal Spectrum Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 85 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 8.3 Initialization Set-Up 8.3.1 JESD204B Startup Sequence The JESD204B interface requires a specific startup and alignment sequence. The general order of that sequence is listed in the following steps. 1. Power up or reset the ADC12J1600 and ADC12J2700 devices. 2. Program JESD_EN = 0 to shut down the link and enable configuration changes. 3. Program DECIMATE, SCRAM_EN, KM1 and DDR to the desired settings. 4. Configure the device calibration settings as desired, and initiate a calibration (set CAL_SFT = 1). 5. Program JESD_EN = 1 to enable the link. 6. Apply at least one SYSREF rising edge to establish the LMFC phase. 7. Assert SYNC~ from the data receiver to initiate link communications. 8. After the JESD204B receiver has established code group synchronization, SYNC~ is de-asserted and the ILA process begins. 9. Immediately following the end of the ILA sequence normal data output begins. NOTE If deterministic latency is not required this step can be omitted. 8.4 Dos and Don'ts 8.4.1 Common Application Pitfalls Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, an input must not go more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits even on a transient basis can cause faulty, or erratic, operation and can impair device reliability. High-speed digital circuits exhibiting undershoot that goes more than a volt below ground is common. To control overshoot, the impedance of high-speed lines must be controlled and these lines must be terminated in the characteristic impedance. Care must be taken not to overdrive the inputs of the ADC12J1600 and ADC12J2700 devices. Such practice can lead to conversion inaccuracies and even to device damage. Incorrect analog input common-mode voltage in the DC-coupled mode. As described in the The Analog Inputs and DC Coupled Input Usage sections, the input common-mode voltage (VCMI) must remain the specified range as referenced to the VCMO pin, which has a variability with temperature that must also be tracked. Distortion performance is degraded if the input common mode voltage is outside the specified VCMI range. Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier to drive the ADC12J1600 and ADC12J2700 devices because many high-speed amplifiers have higher distortion than the ADC12J1600 and ADC12J2700 devices which results in overall system performance degradation. Driving the clock input with an excessively high level signal. The ADC input clock level must not exceed the level described in the Recommended Operating Conditions table because the input offset can change if these levels are exceeded. Inadequate input clock levels. As described in the Using the Serial Interface section, insufficient input clock levels can result in poor performance. Excessive input-clock levels can result in the introduction of an input offset. Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having other signals coupled to the input clock signal trace. These pitfalls cause the sampling interval to vary which causes excessive output noise and a reduction in SNR performance. Failure to provide adequate heat removal. As described in the Thermal Management section, providing adequate heat removal is important to ensure device reliability. Adequate heat removal is primarily provided by properly connecting the thermal pad to the circuit board ground planes. Multiple vias should be arranged in a grid pattern in the area of the thermal pad. These vias will connect the topside pad to the internal ground planes and to a copper pour area on the opposite side of the printed circuit board. 86 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 9 Power Supply Recommendations Data-converter-based systems draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A 10-µF capacitor must be placed within one inch (2.5 cm) of the device power pins for each supply voltage. A 0.1-µF capacitor must be placed as close as possible to each supply pin, preferably within 0.5 cm. Leadless chip capacitors are preferred due to their low-lead inductance. As is the case with all high-speed converters, the ADC12J1600 and ADC12J2700 devices must be assumed to have little power-supply noise-rejection. Any power supply used for digital circuitry in a system where a large amount of digital power is consumed must not be used to supply power to the ADC12J1600 and ADC12J2700 devices. If not a dedicated supply, the ADC supplies must be the same supply used for other analog circuitry. 9.1 Supply Voltage The ADC12J1600 and ADC12J2700 devices are specified to operate with nominal supply voltages of 1.9 V (VA19) and 1.2 V (VA12, VD12). For detailed information regarding the operating voltage minimums and maximums see the Recommended Operating Conditions table. During power-up the voltage on all 1.9-V supplies must always be equal to or greater than the voltage on the 1.2V supplies. Similarly, during power-down, the voltage on the 1.2-V supplies must always be lower than or equal to that of the 1.9-V supplies. In general, supplying all 1.9-V buses from a single regulator, and all 1.2-V buses from a single regulator is the easiest method to ensure that the 1.9-V supplies are greater than the 1.2-V supplies. If the 1.2-V buses are generated from separate regulators, they must rise and fall together (within 200 mV). The voltage on a pin, including a transient basis, must not have a voltage that is in excess of the supply voltage or below ground by more than 150 mV. A pin voltage that is higher than the supply or that is below ground can be a problem during startup and shutdown of power. Ensure that the supplies to circuits driving any of the input pins, analog or digital, do not rise faster than the voltage at the ADC12J1600 and ADC12J2700 power pins. The values in the Absolute Maximum Ratings table must be strictly observed including during power up and power down. A power supply that produces a voltage spike at power turnon, turnoff, or both can destroy the ADC12J1600 and ADC12J2700 devices. Many linear regulators produce output spiking at power on unless there is a minimum load provided. Active devices draw very little current until the supply voltages reach a few hundred millivolts. The result can be a turn-on spike that destroys the ADC12J1600 and ADC12J2700 devices, unless a minimum load is provided for the supply. A 100-Ω resistor at the regulator output provides a minimum output current during power up to ensure that no turn-on spiking occurs. Whether a linear or switching regulator is used, TI recommends using a soft-start circuit to prevent overshoot of the supply. 10 Layout 10.1 Layout Guidelines Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Each ground layer should be a single unified ground plane, rather than splitting the ground planes into analog and digital areas. Because digital switching transients are composed largely of high frequency components, the skin effect dictates that the total ground-plane copper weight has little effect upon the logic-generated noise. Total surface area is more important than the total ground-plane volume. Coupling between the typically-noisy digital circuitry and the sensitive analog circuitry can lead to poor performance that can be impossible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High-power digital components must not be located on or near any linear component or power-supply trace or plane that services analog or mixed-signal components because the resulting common return current path could cause fluctuation in the analog input ground return of the ADC which causes excessive noise in the conversion result. In general, assume that analog and digital lines must cross each other at 90° to avoid digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The input clock lines must be isolated from all other lines, both analog and digital. The generally-accepted 90° crossing must be avoided because even a same amount of coupling causes problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 87 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com Layout Guidelines (continued) Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques available including distance isolation, orientation planning to prevent field coupling of components like inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at 90° angles to minimize crosstalk. Isolation of the analog input is important because of the low-level drive required of the ADC12J1600 and ADC12J2700 devices. Quality analog input signal and clock signal path layout is required for full dynamic performance. Symmetry of the differential signal paths and discrete components in the path is mandatory and symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements of the input and clock signal paths necessitate using differential routing with controlled impedances and minimizing signal path stubs (including vias) when possible. Layout of the high-speed serial-data lines is of particular importance. These traces must be routed as tightly coupled 100-Ω differential pairs, with minimal vias. When vias must be used, care must be taken to implement control-impedance vias (that is, 50-Ω) with adjacent ground vias for image current control. 10.2 Layout Example The following examples show layout-example plots (top and bottom layers only). Figure 117 shows a typical stackup for a 10 layer board. VBG DNC RSV VA12 TDIODE+ TDIODE± VA19 RSV2 VA19 SCS SCLK SDI SDO VD12 DS7+/NCO_2 DS7-/NCO_2 VD12 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 RBIAS+ 1 51 RBIAS± 2 50 DS6±/NCO_1 VCMO 3 49 VD12 VA19 4 48 DS5+/NCO_0 VNEG 5 VA12 6 VA19 7 VIN+ Power supply decoupling capacitors near VIN and DEVCLK are located on opposite side of board to minimize noise coupling. 8 VIN± 9 VA19 10 VA12 11 VNEG 12 47 DS5±/NCO_0 46 VD12 45 DS4+ 44 DS4± 43 VD12 42 DS3+ 41 DS3± 40 VD12 39 DS2+ DS1± 34 VD12 33 DS0+ 32 DS0± 31 VD12 SYNC~ VNEG_OUT VD12 VA19 OR_T1 OR_T0 VA19 SYNC~±/TMST± SYNC~+/TMST+ VA12 30 35 29 DS1+ VA12 17 28 36 27 16 26 VD12 DEVCLK± 25 37 24 15 23 DS2± DEVCLK+ 22 38 21 14 20 VA12 18 13 VA12 DEVCLK path B selected if capacitors installed here. DS6+/NCO_1 VA19 19 Straight analog input path with minimal adjacent circuitry. Power supply decoupling capacitors very close to power pins. SYSREF± Balun transformer for SE to differential conversion. Large bulk decoupling capacitor near device. SYSREF+ Single ended VIN path via balun selected if capacitors installed here. AC coupling capacitors on serial output pairs. Straight DEVCLK path with minimal adjacent circuitry. GND reference vias near where high speed signals transition to inner layer. Figure 115. ADC12J1600 and ADC12J2700 Layout Example 1 — Top Side 88 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Layout Example (continued) Additional decoupling capacitors near device. Optional differential VIN path selected if capacitors or resistors installed here. VBG DNC RSV VA12 TDIODE+ TDIODE± VA19 RSV2 VA19 SCS SCLK SDI SDO VD12 DS7+/NCO_2 DS7-/NCO_2 VD12 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 RBIAS resistor near to RBIAS+ and RBIAS- pins. RBIAS+ 1 51 RBIAS± 2 50 DS6±/NCO_1 VCMO 3 49 VD12 VA19 4 48 DS5+/NCO_0 VNEG 5 VA12 6 VA19 Decoupling capacitors power pins near VIN and DEVCLK on this side of board. 7 VIN+ 8 VIN± 9 VA19 10 VA12 11 VNEG 12 47 DS5±/NCO_0 46 VD12 45 DS4+ 44 DS4± 43 VD12 42 DS3+ 41 DS3± 28 29 30 31 32 33 34 VD12 VNEG_OUT SYNC~ VD12 DS0± DS0+ VD12 27 26 OR_T1 VA19 25 DS1± OR_T0 35 24 DS1+ VA12 17 VA19 36 23 16 SYNC~±/TMST± VD12 DEVCLK± 22 37 21 15 VA12 DS2± DEVCLK+ SYNC~+/TMST+ 38 20 14 19 DS2+ VA12 18 39 VA12 VD12 13 SYSREF± 40 VA19 SYSREF+ DEVCLK path A selected if capacitors installed here. DS6+/NCO_1 Larger bulk decoupling capacitors on this side of board, near device. Figure 116. ADC12J1600 and ADC12J2700 Layout Example 2 — Bottom Side L1 ± SIG 0.0040'' L2 ± GND 0.0067'' L3 ± SIG 0.0060'' L4 ± GND 0.0041'' L5 ± PWR 0.0060'' 0.0578'' L6 ± SIG 0.0067'' L7 ± GND 0.0040'' L8 ± SIG 0.0073'' L9 ± GND 0.0040'' L10 ± SIG 1/2 oz. Copper on L1, L3, L6, L8, L10 1 oz. Copper on L2, L4, L5, L7, L9 100 Differential Signaling on SIG Layers Low loss dielectric adjacent very high speed trace layers Finished thickness 0.0620" including plating and solder mask Figure 117. ADC12J1600 and ADC12J2700 Typical Stackup — 10 Layer Board Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 89 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 10.3 Thermal Management The ADC12J1600 and ADC12J2700 devices are capable of impressive speeds and performance at low power levels for speed. However, the power consumption is still high enough to require attention to thermal management. The VQFN package has a primary-heat transfer path through the center pad on the bottom of the package. The thermal resistance of this path is provided as RθJCbot. For reliability reasons, the die temperature must be kept to a maximum of 135°C which is the ambient temperature (TA) plus the ADC power consumption multiplied by the net junction-to-ambient thermal resistance (RθJA). Maintaining this temperature is not a problem if the ambient temperature is kept to a maximum of 85°C as specified in the Recommended Operating Conditions table and the center ground pad on the bottom of the package is thermally connected to a large-enough copper area of the PC board. The package of the ADC12J1600 and ADC12J2700 devices have a center pad that provides the primary heatremoval path as well as excellent electrical grounding to the PCB. Recommended land pattern and solder paste examples are provided in the Mechanical, Packaging, and Orderable Information section. The center-pad vias shown must be connected to internal ground planes to remove the maximum amount of heat from the package, as well as to ensure best product parametric performance. If needed to further reduce junction temperature, TI recommends to build a simple heat sink into the PCB which occurs by including a copper area of about 1 to 2 cm2 on the opposite side of the PCB. This copper area can be plated or solder-coated to prevent corrosion, but should not have a conformal coating which would provide thermal insulation. Thermal vias will be used to connect these top and bottom copper areas and internal ground planes. These thermal vias act as heat pipes to carry the thermal energy from the device side of the board to the opposite side of the board where the heat can be more effectively dissipated. 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support For the ADC Harmonic Calculator, got to http://www.ti.com/tool/adc-harmonic-calc. 11.1.3 Device Nomenclature Aperture (sampling) Delay is the amount of delay, measured from the sampling edge of the clock input, after which the signal present at the input pin is sampled inside the device. Aperture Jitter (t(AJ)) is the variation in aperture delay from sample to sample. Aperture jitter appears as input noise. Clock Duty Cycle is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period. Full Power Bandwidth (FPBW) is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below the low frequency value for a full scale input. Interleaving Spurs are frequency domain (FFT) artifacts resulting from non-idealities in the multi-bank interleaved architecture of the ADC. Offset errors between banks result in fixed spurs at ƒS / 4 and ƒS / 2. Gain and timing errors result in input-signal-dependent spurs at ƒS / 4 ± FIN and ƒS / 2 ± FIN. Intermodulation Distortion (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. IMD is defined as the ratio of the power in the second-order and third-order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. 90 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 ADC12J1600, ADC12J2700 www.ti.com SLAS969C – JANUARY 2014 – REVISED JULY 2015 Device Support (continued) Least Significant Bit (LSB ) is the bit that has the smallest value or weight of all bits. This value is calculated with Equation 18. VFS(dif) / 2n where • • VFS(dif) is the differential full-scale amplitude of VI as set by the FSR input (pin 14) n is the ADC resolution in bits, which is 12 for the ADC12J1600 and ADC12J2700 devices (18) CML Differential Output Voltage (VOD) is the absolute value of the difference between the positive and negative outputs. Each output is measured with respect to Ground. VD+ VD VOD VD+ VOS VD GND VOD = | VD+ - VD- | CML Output Signal Levels CML Output Offset Voltage (VO(ofs)) is the midpoint between the D+ and D– pins output voltage. Equation 19 is an example of VOS. [(VD+) + ( VD–)] / 2 (19) Most Significant Bit (MSB) is the bit that has the largest value or weight. The value of the MSB is one half of full scale. Overrange Recovery Time is the time required after the differential input voltages goes from ±1.2 V to 0 V for the converter to recover and make a conversion with its rated accuracy. Other Spurs is the sum of all higher harmonics (fourth and above), interleaving spurs, and any other fixed or input-dependent spurs. Data Delay (Latency) is the number of input clock cycles between initiation of conversion and when related data is present at the serializer output. Spurious-free Dynamic Range (SFDR) is the difference, expressed in dB, between the RMS values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC. Total Harmonic Distortion (THD) is the ratio expressed in dB, of the RMS total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated with Equation 20. THD = 20 x log A 2 +... +A 2 f2 f10 A f12 where • • A(f1) is the RMS power of the fundamental (output) frequency A(f2) through A(f10) are the RMS power of the first nine harmonic frequencies in the output spectrum (20) Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency detected at the output and the power in the second harmonic level at the output. Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in the third harmonic level at the output. Word Error Rate is the probability of error and is defined as the probable number of errors per unit of time divided by the number of words seen in that amount of time. A Word Error Rate of 10–18 corresponds to a statistical error in one conversion about every four years. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 Submit Documentation Feedback 91 ADC12J1600, ADC12J2700 SLAS969C – JANUARY 2014 – REVISED JULY 2015 www.ti.com 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • LMH3401 7-GHz, Ultra-Wideband, Fixed-Gain, Fully-Differential Amplifier, SBOS695 • LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs, SNAS605 • LMX2581 Wideband Frequency Synthesizer with Integrated VCO, SNAS601 • TRF3765 Integer-N/Fractional-N PLL with Integrated VCO, SLWS230 11.3 Related Links Below are direct links to information available to accelerate design activity. Categories include technical information, community resources, design information, and quick access to sample or purchase once you have made a decision. Parts Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADC12J1600 Click here Click here Click here Click here Click here ADC12J2700 Click here Click here Click here Click here Click here 11.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 92 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC12J1600 ADC12J2700 PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC12J1600NKE ACTIVE VQFN NKE 68 168 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 ADC12J1600 ADC12J1600NKER ACTIVE VQFN NKE 68 2000 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 ADC12J1600 ADC12J1600NKET ACTIVE VQFN NKE 68 250 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 ADC12J1600 ADC12J2700NKE ACTIVE VQFN NKE 68 168 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 ADC12J2700 ADC12J2700NKER ACTIVE VQFN NKE 68 2000 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 ADC12J2700 ADC12J2700NKET ACTIVE VQFN NKE 68 250 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 ADC12J2700 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE OUTLINE NKE0068A VQFN - 0.9 mm max height SCALE 1.700 PLASTIC QUAD FLATPACK - NO LEAD 10.1 9.9 B A PIN 1 ID 10.1 9.9 0.9 MAX C SEATING PLANE 7.7 0.1 4X (45 X0.42) 18 34 17 35 SYMM 4X 8 1 64X 0.5 0.1 C 0.05 0.00 (0.2) 51 52 68 PIN 1 ID (OPTIONAL) SYMM 68X 0.7 0.5 68X 0.3 0.2 0.1 0.05 C A C B 4214820/A 12/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NKE0068A VQFN - 0.9 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 7.7) SYMM 68X (0.8) (1.19) TYP 52 68 68X (0.25) 1 51 (1.19) TYP 64X (0.5) SYMM (9.6) ( 0.2) TYP VIA 35 17 34 18 (9.6) LAND PATTERN EXAMPLE SCALE:8X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4214820/A 12/2014 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN NKE0068A VQFN - 0.9 mm max height PLASTIC QUAD FLATPACK - NO LEAD (9.6) (1.19) TYP 68X (0.8) 68 36X ( 0.99) 52 68X (0.25) 1 51 (1.19) TYP 64X (0.5) SYMM (9.6) METAL TYP 35 17 18 34 SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 60% PRINTED SOLDER COVERAGE BY AREA SCALE:8X 4214820/A 12/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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