ESD8106 Transient Voltage Suppressors Low Capacitance ESD Protection for USB 3.0 Interface http://onsemi.com The ESD8106 transient voltage suppressor is specifically designed to protect USB 3.0 interfaces by integrating two Superspeed pairs, D+ and D− lines into a single protection product. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines. 14 1 6D = Specific Device Code M = Date Code G = Pb−Free Package • Low Capacitance (0.35 pF Max, I/O to GND) • Protection for the Following IEC Standards: • • 6DM G UDFN14 CASE 517CQ Features IEC 61000−4−2 Level 4 UL Flammability Rating of 94 V−0 These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MARKING DIAGRAM PIN CONFIGURATION I/O I/O I/O I/O GND I/O I/O 14 13 12 11 10 9 8 1 2 3 4 5 6 7 N/C N/C N/C N/C Typical Applications • USB 3.0 *N/C MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD ESD ±15 ±15 kV kV IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. N/C GND *Pins 1−7 should be connected to opposite pin with PCB trace in order to maintain a flow−thru routing scheme. ORDERING INFORMATION Device Package Shipping ESD8106MUTAG UDFN14 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 1 1 Publication Order Number: ESD8106/D ESD8106 Pin 8 Pin 9 Pin 11 Pin 12 Pin 13 Pin 14 Pins 5, 10 Note: Common GND – Only minimum of 1 GND connection required = Figure 1. Pin Schematic ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol Parameter IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR IPP RDYN Working Peak Reverse Voltage VCL VBR VRWM Maximum Reverse Leakage Current @ VRWM VBR IT Breakdown Voltage @ IT VCL RDYN Test Current RDYN V IR IT Dynamic Resistance *See Application Note AND8308/D for detailed explanations of datasheet parameters. IPP Uni−Directional TVS ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Reverse Leakage Current Symbol VRWM VBR IR Dynamic Resistance RDYN Junction Capacitance CJ Conditions Min Typ I/O Pin to GND IT = 1 mA, I/O Pin to GND 4.0 (Note 1) 0.45 VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 1 MHz between I/O Pins VR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins and GND 0.30 0.10 0.37 1. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 2 Unit 3.3 V 1.0 mA 5.0 VRWM = 3.3 V, I/O Pin to GND http://onsemi.com Max V W 0.35 0.20 0.47 pF ESD8106 20 10 8 TLP CURRENT (A) 16 14 6 12 10 4 8 6 2 4 EQUIVALENT VIEC (kV) 18 2 0 0 2 4 6 8 10 12 14 VC, VOLTAGE (V) 16 18 0 20 Figure 2. TLP I−V Curve NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 3. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 4 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and high to interpret them please see AND9007/D. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 3. Simplified Schematic of a Typical TLP System Figure 4. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms http://onsemi.com 3 ESD8106 TBD TBD Without ESD With ESD8106 Figure 5. USB 3.0 Eye Diagram with and without ESD8106. 5.0 Gb/s, 400 mVPP Interface Data Rate (Gb/s) Fundamental Frequency (GHz) 3rd Harmonic Frequency (GHz) USB 3.0 5 2.5 (m1) 7.5 (m2) Figure 6. ESD8106 Insertion Loss http://onsemi.com 4 ESD8106 Insertion Loss (dB) m1 = 0.100 m2 = 0.580 ESD8106 USB 3.0 Type A Connector StdA_SSTX+ Vbus StdA_SSTX− ESD8106 D− GND_DRAIN D+ StdA_SSRX+ GND StdA_SSRX− Figure 7. Recommended USB 3.0 Layout Diagram • Make sure to use differential design methodology and PCB Layout Guidelines Steps must be taken for proper placement and signal trace routing of the ESD protection device in order to ensure the maximum ESD survivability and signal integrity for the application. Such steps are listed below. • Place the ESD protection device as close as possible to the I/O connector to reduce the ESD path to ground and improve the protection performance. ♦ In USB 3.0 applications, the ESD protection device should be placed between the AC coupling capacitors and the I/O connector on the TX differential lanes as shown in Figure 8. impedance matching of all high speed signal traces. ♦ Use curved traces when possible to avoid unwanted reflections. ♦ Keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ♦ Place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. Figure 8. USB 3.0 Connection Diagram http://onsemi.com 5 ESD8106 ESD Protection Device Technology ON Semiconductor’s portfolio contains three main technologies for low capacitance ESD protection device which are highlighted below and in Figure 9. • ESD7000 series: Zener diode based technology. This technology has a higher breakdown voltage (VBR) limiting it to protecting chipsets with larger geometries. • ESD8000 series: Silicon controlled rectifier (SCR) type technology. The key advatange for this technology is a low holding voltage (VH) which produces a deeper snapback that results in lower voltage over high • currents as shown in the TLP results in Figure 10. This technology provides optimized protection for chipsets with small geometries against thermal failures resulting in chipset damage (also known as “hard failures”). ESD8100 series: Low voltage punch through (LVPT) technology. The key advatange for this technology is a very low turn-on voltage as shown in Figure 11. This technology provides optimized protection for chipsets with small geometries against recoverable failures due to voltage peaks (also known as “soft failures”). Figure 9. ON Semiconductor’s Low-cap ESD Technology Portfolio 10 20 18 TLP Current (A) 14 6 12 10 4 8 ESD8006 6 ESD8106 4 2 ESD7016 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 Vc (V) Figure 10. High Current, TLP, IV Characteristic of Each Technology http://onsemi.com 6 0 26 Equivalent VIEC (kV) 8 16 ESD8106 1.00E−01 1.00E−02 ESD8006 1.00E−03 ESD8106 1.00E−04 ESD7016 I (A) 1.00E−05 1.00E−06 1.00E−07 1.00E−08 1.00E−09 1.00E−10 1.00E−11 0 1 2 3 4 5 6 7 V (V) Figure 11. Low Current, DC, IV Characteristic of Each Technology http://onsemi.com 7 8 ESD8106 PACKAGE DIMENSIONS UDFN14, 3.5x1.35, 0.5P CASE 517CQ ISSUE O PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C É É L1 E DETAIL A OPTIONAL TERMINAL CONSTRUCTIONS TOP VIEW A DETAIL B 0.10 C 14X (A3) A1 C SIDE VIEW 2X 1 L2 b2 7 14X MOLD CMPD DETAIL B SEATING PLANE OPTIONAL CONSTRUCTION 8 e BOTTOM VIEW 12X 14X 0.62 0.25 b 0.10 C A B 0.05 C MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 0.35 0.45 3.50 BSC 1.35 BSC 0.50 BSC 0.30 0.50 0.00 0.15 0.20 REF RECOMMENDED SOLDERING FOOTPRINT* L 11X 14 DIM A A1 A3 b b2 D E e L L1 L2 ÉÉÉ ÉÉÉ ÇÇÇ EXPOSED Cu 0.08 C DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 MM FROM THE TERMINAL TIP. L L A B D 1.55 NOTE 3 1 3X 0.45 0.50 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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