TI1 DPA02257RGBR 6-a output, d-cap mode, synchronous step-down, integrated-fet converter for ddr memory termination Datasheet

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TPS53317
SLUSAK4D – JUNE 2011 – REVISED JULY 2015
TPS53317 6-A Output, D-CAP+ Mode, Synchronous Step-Down,
Integrated-FET Converter for DDR Memory Termination
1 Features
3 Description
•
The TPS53317 device is a FET-integrated
synchronous buck regulator designed mainly for DDR
termination. It can provide a regulated output at ½
VDDQ with both sink and source capability. The
TPS53317 device employs D-CAP+™ mode
operation that provides ease of use, low external
component count and fast transient response. The
device can also be used for other point-of-load (POL)
regulation applications requiring up to 6 A. In
addition, the device supports full, 6-A, output sinking
current capability with tight voltage regulation.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
TI proprietary Integrated MOSFET and Packaging
Technology
Supports DDR Memory Termination with up to 6-A
Continuous Output Source or Sink Current
External Tracking
Minimum External Components Count
1-V to 6-V Conversion Voltage
D-CAP+™ Mode Architecture
Supports All MLCC Output Capacitors and
SP/POSCAP
Selectable SKIP Mode or Forced CCM
Optimized Efficiency at Light and Heavy Loads
Selectable 600-kHz or 1-MHz Switching
Frequency
Selectable Overcurrent Limit (OCL)
Overvoltage, Over-Temperature and Hiccup
Undervoltage Protection
Adjustable Output Voltage from 0.6 V to 2 V
3.5 mm × 4 mm, 20-Pin VQFN Package
The device features two switching frequency settings
(600 kHz and 1 MHz), integrated droop support,
external tracking capability, pre-bias startup, output
soft discharge, integrated bootstrap switch, power
good function, V5IN pin UVLO protection, and
supports both ceramic and SP/POSCAP capacitors. It
supports input voltages up to 6.0 V, and output
voltages adjustable from 0.6 V to 2.0 V.
The TPS53317 device is available in the 3.5 mm × 4
mm, 20-pin, VQFN package (Green RoHs compliant
and Pb free) with TI proprietary Integrated MOSFET
and packaging technology and is specified from
–40°C to 85°C.
2 Applications
•
•
•
Device Information(1)
Memory Termination Regulator for DDR, DDR2,
DDR3, DDR3L, and DDR4
VTT Termination
Low-Voltage Applications for 1-V to 6-V Input
Rails
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS53317
VQFN (20)
3.50 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
DDR VDDQ IN
EN
VIN
TPS53317 BST
EN
SW
COMP
VREF
REFIN
PGOOD
VTT
PGOOD
PGND
VOUT
MODE
5VIN
V5IN
GND
PowerPAD
UDG-11105
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53317
SLUSAK4D – JUNE 2011 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ............................................... 20
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2013) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added "SW (transient 20 ns and E = 5 µJ)" specification in Absolute Maximum Ratings table ............................................ 5
•
Added Figure 41 .................................................................................................................................................................. 26
Changes from Revision B (MAY 2012) to Revision C
Page
•
Added clarity to Pin Configuration and Functions table ......................................................................................................... 4
•
Added clarity to Internal soft-start delay time and soft-start time test conditions in Electrical Characteristics table.............. 7
•
Added Figure 17, Figure 19 and Figure 20 in Power Sequences section............................................................................ 13
•
Added clarity to Output Overvoltage Protection (OVP) section............................................................................................ 15
•
Changed minimum valley OCL from "is 6 A or 4 A" to "is 7.6 A or 5.4 A" in Overcurrent Limit section. ............................. 15
•
Changed "the absolute value of the negative OCL set point is typically -6.5 A or -4.5 A" to "the typical value of the
negative OCL set point is –9.3 A or –6.5 A" in Negative OCL section................................................................................. 16
•
Added clarity to Layout Guidelines section. ......................................................................................................................... 26
Changes from Revision A (JULY 2011) to Revision B
Page
•
Added Memory Termination bullet in APPLICATIONS .......................................................................................................... 1
•
Added clarity to ...................................................................................................................................................................... 1
•
Added updates to Table 1 .................................................................................................................................................... 19
2
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Changes from Original (JUNE 2011) to Revision A
Page
•
Changed from "SKIP and Forced CCM" to "SKIP or Forced CCM" in FEATURES............................................................... 1
•
Changed from "600-kHz and 1-MHz Switching" to "600-kHz or 1-MHz Switching" in FEATURES ....................................... 1
•
Added clarity to Simplified Application drawing ...................................................................................................................... 1
•
Changed from "fSW = 600 kHz" to " fSW = 1 MHz" for tON(min) in EC table ............................................................................... 7
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5 Pin Configuration and Functions
PGOOD
MODE
EN
20
19
18
17
BST
V5IN
RGB Package
20-Pin VFQN
Top View
PGND
1
16
15
SW
PGND
2
14
SW
PGND
3
13
SW
VIN
4
12
Exposed
Thermal Pad 11
SW
8
9
10
COMP
REFIN
VOUT
SW
7
VREF
5
6
GND
VIN
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
16
I
Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between
this pin and the SW pin. A series boot resistor is optional.
COMP
8
O
Connect an R-C-C network between this pin and VREF for loop compensation.
EN
17
I
Enable pin (3.3-V logic compatible).
GND
6
–
Analog ground.
MODE
18
I
Allows selection of different operation modes. (See Table 1)
G
Power ground.
BST
1
PGND
2
3
PGOOD
19
O
Open drain power good output. Connect pullup resistor.
REFIN
9
I
External tracking reference input. Apply voltage between 0.6 V to 2.0 V. For non-tracking mode,
connect REFIN to VREF via resistor divider.
11
12
SW
13
I/O
Switching node output.
14
15
V5IN
20
4
VIN
5
I
5-V power supply for analog circuits and gate drive.
I
Power supply input pin.
VOUT
10
I
Output voltage monitor input pin.
VREF
7
O
2.0-V reference output. Connect a 0.22-µF ceramic capacitor to GND.
(1)
4
I = Input, O = Output, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage range
Output voltage range
(1)
MIN
MAX
BST (with respect to SW), V5IN, VIN
–0.3
7
BST
–0.3
14
EN
–0.3
7
MODE, REFIN
–0.3
3.6
VOUT
–1
3.6
SW
–2
7
SW (transient 20 ns and E = 5 µJ)
–3
V
COMP, VREF
–0.3
3.6
PGOOD
–0.3
7
PGND
–0.3
0.3
–40
150
˚C
300
˚C
150
˚C
Operating junction temperature, TJ
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature, Tstg
(1)
UNIT
–55
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
BST (with respect to SW), EN, VIN
Input voltage range
Output voltage range
NOM
–0.1
MAX
V5IN
4.5
6.5
BST
–0.1
13.5
SW
–1.0
6.5
VOUT, MODE, REFIN
–0.1
3.5
COMP
–0.1
VREF
UNIT
6.5
3.5
2
PGOOD
–0.1
6.5
PGND
–0.1
0.1
Operating temperature range, TA
-40
85
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V
V
°C
5
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SLUSAK4D – JUNE 2011 – REVISED JULY 2015
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6.4 Thermal Information
TPS53317
THERMAL METRIC (1)
RGB (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
35.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.6
°C/W
RθJB
Junction-to-board thermal resistance
12.4
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
12.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO
IVINSD
VIN shutdown current
EN = 'LO'
VV5IN
V5IN supply voltage
V5IN voltage range
IV5IN
V5IN supply current
EN =’HI’, V5IN supply current, fSW
= 600 kHz
IV5INSD
V5IN shutdown current
EN = ‘LO’, V5IN shutdown current
VV5UVLO
V5IN UVLO
Ramp up; EN = 'HI'
VV5UVHYS
V5IN UVLO hysteresis
Falling hysteresis
VVREFUVLO
REF UVLO (1)
Rising edge of VREF, EN = 'HI'
VVREFUVHYS
REF UVLO hysteresis (1)
VPOR5VFILT
Reset
OVP latch is reset by V5IN falling
below the reset threshold
4.5
4.20
0.02
5
µA
5.0
6.5
V
1.1
2
mA
0.2
7.0
µA
4.37
4.50
440
V
mV
1.8
V
100
mV
1.5
2.3
3.1
VREFIN = 1 V, No droop
–1%
0%
1%
VREFIN = 0.6 V, No droop
–1%
0%
1%
IVREF = 0 µA
1.98
2.00
2.02
IVREF = 50 µA
1.975
2.000
2.025
V
VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER
VOUTTOL
Output voltage accuracy
VVREF
VREF
IREFSNK
VREF sink current
gM
Transconductance
VCM
Common mode input voltage range (1)
0
2
V
VDM
Differential mode input voltage
0
80
mV
ICOMPSNK
COMP pin maximum sinking current
VCOMP = 2 V, (VREFIN - VOUT) = 80
mV
ICOMPSRC
COMP pin maximum sourcing current
VCOMP = 2 V
VOFFSET
Input offset voltage
TA = 25°C
RDSCH
Output voltage discharge resistance
f–3dbVL
–3dB Frequency (1)
VVREF = 2.05 V
2.5
V
mA
1.00
mS
80
µA
-80
µA
0
mV
Ω
42
4.5
6.0
7.5
MHz
43
53
57
mV/A
CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVERCURRENT AND ZERO CROSSING
Gain from the current of the lowside FET to PWM comparator
when PWM = "OFF"
ACSINT
Internal current sense gain
IOCL
Positive overcurrent limit (valley)
7.6
IOCL(neg)
Negative overcurrent limit (valley)
–9.3
VZXOFF
Zero crossing comp internal offset
0
(1)
6
A
A
mV
Ensured by design, not production tested.
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Electrical Characteristics (continued)
over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN
VPGDLL
PGOOD deassert to lower
(PGOOD → Low)
VPGHYSHL
PGOOD high hysteresis
VPGDLH
PGOOD de-assert to higher
(PGOOD → Low)
VPGHYSHH
PGOOD high hysteresis
Measured at the VOUT pin wrt/
VREFIN
84%
8%
Measured at the VOUT pin wrt/
VREFIN
116%
-8%
VINMINPG
Minimum VIN voltage for valid PGOOD
Measured at the VIN pin with a 2mA sink current on PGOOD pin.
V5IN is grounded here. (2)
VOVP
OVP threshold
Measured at the VOUT pin wrt/
VREFIN
VUVP
UVP threshold
Measured at the VOUT pin wrt/
VREFIN, device latches OFF, begins
soft-stop
THSD
Thermal shutdown (1)
Latch off controller, attempt softstop.
THSD(hys)
Thermal Shutdown hysteresis (1)
Controller re-starts after
temperature has dropped
0.9
1.3
1.5
117%
120%
123%
65%
68%
71%
V
145
°C
10
°C
DRIVERS: BOOT STRAP SWITCH
RDSONBST
Internal BST switch on-resistance
IBST = 10 mA, TA = 25°C
10
Ω
IBSTLK
Internal BST switch leakage current
VBST = 14 V, VSW = 7 V
1
µA
TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS
tONESHOTC
PWM one-shot (1)
VVIN = 5 V, VVOUT = 1.05 V, fSW = 1
MHz
210
VVIN = 5 V, VVOUT = 1.05 V, fSW =
600 kHz
310
ns
tMIN(off)
Minimum OFF time
VVIN = 5 V, VVOUT = 1.05 V, fSW = 1
MHz, DRVL on,
SW = PGND, VVOUT < VREFIN
270
ns
tINT(SS)
Soft-start time
From VOUT ramp starting to VOUT
=95%, default setting
1.6
ms
tINT(SSDLY)
Internal soft-start delay time
From VVREF = 2 V to VOUT is ready
to ramp up
260
µs
tPGDDLY
PGOOD startup delay time
At external tracking, the time from
VOUT is ready to ramp up
8
ms
tPGDPDLYH
PGOOD high propagation delay time
50 mV over drive, rising edge
tPGDPDLYL
PGOOD low propagation delay time
50 mV over drive, falling edge
10
µs
OVP delay time
Time from the VOUT pin out of
+20% of REFIN to OVP fault
10
µs
tOVPDLY
tUVDLYEN
tUVPDLY
Undervoltage fault enable delay
UVP delay time
0.8
1
Time from EN_INT going high to
undervoltage fault is ready
2
External tracking from VOUT ramp
starts
8
1.2
ms
ms
Time from the VOUT pin out of
–32% of REFIN to UVP fault
256
µs
LOGIC PINS: I/O VOLTAGE AND CURRENT
VPGDPD
PGOOD pull-down voltage
PGOOD low impedance, ISINK = 4
mA, VV5IN = 4.5 V
IPGDLKG
PGOOD leakage current
PGOOD high impedance, forced to
5.5 V
VENH
EN logic high
EN, VCCP logic
VENL
EN logic low
EN, VCCP logic
IEN
EN input current
(2)
–1
0
0.3
V
1
µA
2
V
0.5
V
1
µA
If V5IN is higher than 1.5 V, PGOOD is valid regardless of the voltage applied at VIN. This is based on bench testing.
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Electrical Characteristics (continued)
over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VMODETH
MODE threshold voltage (3)
IMODE
MODE current
(3)
MIN
TYP
MAX
Threshold 1
80
130
180
Threshold 2
200
250
300
Threshold 3
370
420
470
Threshold 4
1.765
1.800
1.850
15
UNIT
mV
V
µA
See Table 1 for descriptions of MODE parameters.
6.6 Typical Characteristics
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
Characterization data tested using the TPS53317EVM-750 where the external tracking input sets the output voltage and
operates in non-droop mode. See SLUU642 for detailed configuration.
75
70
Ambient Temp TA
65
60
±40ƒC
0°C
25°C
60°C
85°C
VIN = 1.2 V
VOUT = 0.6 V
fSW = 600 kHz PWM
55
50
0
1
2
3
4
5
Output Current (A)
75
70
60
VIN = 1.5 V
VOUT = 0.75 V
fSW = 600 kHz PWM
55
50
0
6
90
85
85
80
80
Efficiency (%)
Efficiency (%)
90
75
Ambient Temp TA
±40ƒC
0°C
VIN = 2.5 V
25°C
VOUT = 0.6 V
60°C
fSW = 600 kHz PWM
85°C
55
50
0
1
2
3
4
5
Output Current (A)
4
5
6
C004
75
70
60
VIN = 2.5 V
VOUT = 0.75 V
fSW = 600 kHz PWM
55
50
6
Ambient Temp TA
±40ƒC
0°C
25°C
60°C
85°C
65
0
C002
Figure 3. Efficiency vs. Output Current
8
3
Figure 2. Efficiency vs. Output Current
95
60
2
Output Current (A)
Figure 1. Efficiency vs. Output Current
65
1
C001
95
70
Ambient Temp TA
±40ƒC
0°C
25°C
60°C
85°C
65
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1
2
3
4
5
Output Current (A)
6
C005
Figure 4. Efficiency vs. Output Current
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Typical Characteristics (continued)
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
Characterization data tested using the TPS53317EVM-750 where the external tracking input sets the output voltage and
operates in non-droop mode. See SLUU642 for detailed configuration.
75
70
Ambient Temp TA
65
60
±40ƒC
0°C
25°C
60°C
85°C
VIN = 3.3 V
VOUT = 0.6 V
fSW = 600 kHz PWM
55
50
0
1
2
3
4
5
75
70
60
55
50
6
Output Current (A)
Ambient Temp TA
±40ƒC
0°C
VIN = 3.3 V
25°C
VOUT = 0.75 V
60°C
fSW = 600 kHz PWM
85°C
65
0
1
Figure 5. Efficiency vs. Output Current
0.610
0.608
VIN = 1.2 V
fSW = 600 kHz PWM
0.758
Output Voltage (V)
Output Voltage (V)
0.602
0.600
Ambient Temp TA
0.598
±40ƒC
0°C
25°C
60°C
85°C
0.596
0.594
0.592
0.590
±6
±4
±2
0
2
4
5
6
C006
VIN = 1.5 V
fSW = 600 kHz PWM
0.754
0.752
0.750
Ambient Temp TA
±40ƒC
0°C
25°C
60°C
85°C
0.748
0.746
0.744
0.742
0.740
6
Output Current (A)
±6
±4
±2
0
2
4
Output Current (A)
C007
Figure 7. Load Regulation
6
C010
Figure 8. Load Regulation
0.760
VIN = 2.5 V
fSW = 600 kHz PWM
0.758
VIN = 2.5 V
fSW = 600 kHz PWM
0.756
Output Voltage (V)
0.606
Output Voltage (V)
4
0.756
0.604
0.608
3
Figure 6. Efficiency vs. Output Current
0.760
0.606
0.610
2
Output Current (A)
C003
0.604
0.602
0.600
Ambient Temp TA
0.598
±40ƒC
0°C
25°C
60°C
85°C
0.596
0.594
0.592
0.590
±6
±4
±2
0
2
Output Current (A)
4
0.754
0.752
0.750
Ambient Temp TA
±40ƒC
0°C
25°C
60°C
85°C
0.748
0.746
0.744
0.742
0.740
6
±6
C008
Figure 9. Load Regulation
±4
±2
0
2
4
Output Current (A)
6
C011
Figure 10. Load Regulation
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Typical Characteristics (continued)
Characterization data tested using the TPS53317EVM-750 where the external tracking input sets the output voltage and
operates in non-droop mode. See SLUU642 for detailed configuration.
0.610
0.608
0.760
VIN = 3.3 V
fSW = 600 kHz PWM
0.756
Output Voltage (V)
0.606
Output Voltage (V)
VIN = 3.3 V
fSW = 600 kHz PWM
0.758
0.604
0.602
0.600
Ambient Temp TA
0.598
±40ƒC
0°C
25°C
60°C
85°C
0.596
0.594
0.592
0.590
±6
±4
±2
0
2
4
0.754
0.752
0.750
±40ƒC
0°C
25°C
60°C
85°C
0.746
0.744
0.742
0.740
6
Output Current (A)
Ambient Temp TA
0.748
±6
±4
90
0.758
85
0.756
80
75
70
65
50
Skip Mode, fSW = 600 kHz
Skip Mode, fSW =1 MHz
PWM Mode, fSW = 600 kHz
PWM Mode, fSW = 1 MHz
0
1
2
3
4
Output Current (A)
VIN = 1.5 V
2
4
6
C012
Figure 12. Load Regulation
0.760
Output Voltage (V)
Efficiency (%)
Figure 11. Load Regulation
55
0
Output Current (A)
95
60
±2
C009
5
0.754
0.752
0.750
0.748
0.746
Skip Mode, fSW = 600 kHz
Skip Mode, fSW =1 MHz
PWM Mode, fSW = 600 kHz
PWM Mode, fSW = 1 MHz
0.744
0.742
0.740
6
0
1
2
G001
VOUT = 0.75 V
3
4
Output Current (A)
VIN = 1.5 V
Figure 13. Efficiency vs Output Current
5
6
G001
VOUT = 0.75 V
Figure 14. Load Regulation
95
90
Efficiency (%)
85
80
75
70
65
VIN
60
1.8 V
2.5 V
3.3 V
TA = 25ƒC
VOUT = 0.9 V
fSW = 600 kHz PWM
55
50
0
1
2
3
4
5
Output Current (A)
6
C013
Figure 15. Efficiency vs. Output Current
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7 Detailed Description
7.1 Overview
The TPS53317 device is a D-CAP+™ mode adaptive on-time converter. Integrated high-side and low-side FETs
support a maximum of 6-A DC output current. The converter automatically operates in discontinuous conduction
mode (DCM) to optimize light-load efficiency. Multiple switching frequencies are provided to enable optimization
of the power train for the cost, size and efficiency requirements of the design (see Table 1).
In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to
maintain a nearly constant frequency during steady-state conditions. In conventional constant on-time converters,
each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS53317 device,
the cycle begins when the current feedback reaches an error voltage level which is the amplified difference
between the reference voltage and the feedback voltage.
7.2 Functional Block Diagram
TPS53317
VREFIN ±32%
VREFIN + 16%
+
UV
19 PGOOD
+
Delay
+
+
OV
VREFIN ± 16%
GND
VREFIN +20%
COMP
REFIN
8
VS
Amplifier
UVP
OVP
+
+
9
Ramp
Comp
VREF
On-Time
Selection
16 BST
PWM
7
DRVH
Internal Voltage
Reference
VOUT 10
18 MODE
+
SS
DAC
EN 17
Control Logic
x On/Off Time
x Minimum On/Off
x SKIP/FPWM
x OCL/OVP/UVP
x Discharge
15 PA
Current Sense
Amplifier
+
R
VIN
XCON
13 SW
14 SW
GND
Current
Sense
5
12 SW
tON
OneShot
OC
SW
VIN
11 SW
8R
+
PGND
4
15 SW
20 V5IN
ZC
DRVL
+
ZC Threshold
Modulation
GND
Pad
6
Discharge
PGND
1
PGND
2
PGND
3
PGND
UDG-11106
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7.3 Feature Description
7.3.1 PWM Operation
Referring to Figure 16, in steady state, continuous conduction mode, the converter operates in the following way.
Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (VCS) is higher
than the error amplifier output (VCOMP). VCS falls until it hits VCOMP, which contains a component of the output
ripple voltage. VCS is not directly accessible by measuring signals on pins of TPS53317 device. The PWM
comparator senses where the two waveforms cross and triggers the on-time generator.
Current
Feedback
Voltage (V)
VCS
VCOMP
VREF
tON
t
Time (ms)
UDG-10187
Figure 16. D-CAP+™ Mode Basic Waveforms
The current feedback is an amplified and filtered version of the voltage between PGND and SW during low-side
FET on-time. The device also provides a single-ended differential voltage (VOUT) feedback to increase the system
accuracy and reduce the dependence of circuit performance on layout.
7.3.2 PWM Frequency and Adaptive On-Time Control
In general, the on-time (at the SW node) can be estimated by Equation 1.
V
1
tON = OUT ´
VIN
fSW
where
•
fSW is the frequency selected by the connection of the MODE pin
(1)
The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value.
Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in Table 1.
7.3.3 Light-Load Power Saving Features
The TPS53317 device has an automatic pulse-skipping mode to provide excellent efficiency over a wide load
range. The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver.
This saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off,
the converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses
as well.
The device also provides a special light-load power saving feature, called ripple reduction. Essentially, it reduces
the on-time in SKIP mode to effectively reduce the output voltage ripple associated with using an all MLCC
capacitor output power stage design.
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Feature Description (continued)
7.3.4 Power Sequences
7.3.4.1 Non-Tracking Startup
The TPS53317 device can be configured for non-tracking application. When non-tracking is configured, output
voltage is regulated to the REFIN voltage which taps off the voltage dividers from the 2-V reference voltage.
Either the EN pin or the V5IN pin can be used to start up the device. The device uses internal voltage servo DAC
to provide a 1.6-ms soft-start time during soft-start initialization. (See Figure 18.)
In a non-tracking application, the output voltage is determined by the resistive divider between the VREF pin and
the REFIN pin.
R2
VOUT = VREF ´
(2)
R1 + R2
.
.
TPS53317
VREF
7
R1
REFIN
9
R2
Figure 17. Non-Tracking Configuration
EN AND
V5IN
VREF
400 µs typical
REFIN
Internal soft-start delay time
260 µs typical
±5%
VOUT
Fixed
1.6 ms
soft-start
PGOOD
Power good window,
+16%
+8%
reference to REFIN
±8%
±16%
PGOOD
Delay
1.0 ms
Tme
Figure 18. Non-Tracking Startup Timing
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Feature Description (continued)
7.3.4.2 Tracking Startup
The TPS53317 device can also be configured for tracking application. When tracking configuration is desired,
output voltage is also regulated to the REFIN voltage which comes from an external power source. In order for
the device to differentiate between a non-tracking configuration or a tracking configuration, there is a minimum
delay time of 260 µs required between the time when VREF reaches 2 V to the time when the REFIN pin voltage
can be applied, in order for the device to track properly (see Figure 21). The valid REFIN voltage range is
between 0.6 V and 2 V.
In a tracking application, the output voltage should be one half of the VDDQ voltage. VDDQ can be VIN or it can
be an additional voltage rail. Thus, R1= R2 both in Figure 19 and Figure 20.
1
VOUT = ´ VVDDQ
(3)
2
TPS53317
TPS53317
VIN
4
VIN
5
VDDQ
VIN
4
VIN
5
REFIN
9
R1
REFIN
R1
9
Figure 19. Tracking Configuration 1
VREF
VDDQ
R2
R2
EN AND
V5IN
VIN
Figure 20. Tracking Configuration 2
400 µs typical
VOUT is ready to ramp up
(REFIN can be applied)
600 mV
REFIN
260 µs
minimum
Loop
Determined
Operation
Forced
CCM
Operation
VOUT
PGOOD
600 mV
PGOOD
startup
Delay
8.0 ms
PGOOD Propagation
Delay 1.0 ms
Figure 21. Tracking Startup Timing
Select PWM mode for an application that requires external tracking, because the output voltage can not be
decreased during a no-load condition when the device operates in SKIP mode.
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Feature Description (continued)
7.3.5 Protection Features
The TPS53317 device offers many features to protect the converter power train as well as the system
electronics.
7.3.5.1 5-V Undervoltage Protection (UVLO)
The TPS53317 device continuously monitors the voltage on the V5IN pin to ensure that the voltage level is high
enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The
converter starts with approximately 4.3 V and has a nominal 440 mV of hysteresis. If the 5-V UVLO limit is
reached, the converter transitions the phase node into an off function, and the converter remains in the off state
until the device is reset by cycling the 5-V supply until the 5-V POR is reached (2.3-V nominal). The power input
does not have a UVLO function.
7.3.5.2 Power Good Signals
The TPS53317 device has one open-drain power good (PGOOD) pin. During startup, there is a 1-ms power
good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low or an undervoltage
condition on V5IN or any other fault is detected.
7.3.5.3 Output Overvoltage Protection (OVP)
In addition to the power good function described above, the TPS53317 device has additional OVP and UVP
thresholds and protection circuits.
An OVP condition is detected when the output voltage is approximately 120% × VREFIN. In this case, the
converter de-asserts the PGOOD signals and performs the overvoltage protection function. During OVP, the lowside FET is always on before triggering a negative overcurrent. When a negative OC is also tripped, the low-side
FET is no longer continuously on, and pulsed signals are generated to limit the negative inductor current. When
the VOUT pin voltage drops below 400 mV, the low-side FET turns off and the converter latches off. The
converter remains in the off state until the device is reset by cycling the 5-V supply until the 5-V POR is reached
(2.3-V nominal) or when the EN pin is toggled off and on.
7.3.5.4 Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described in the Overcurrent
Protection and Overcurrent Limit sections. If the output voltage drops below 68% of VREFIN, after approximately a
250-µs delay, the device stops switching and enters hiccup mode. After a hiccup waiting time, a restart is
attempted. If the fault condition is not cleared, hiccup mode operation may continue indefinitely.
7.3.5.5 Overcurrent Protection
Both positive and negative overcurrent protection are provided in the TPS53317 device.
• Overcurrent Limit (OCL)
• Negative OCL
7.3.5.5.1 Overcurrent Limit
If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current
drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The device uses a valley current
limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The typical
valley OCL threshold is 7.6 A or 5.4 A (depending on mode selection). The average output current limit
calculation is shown in Equation 4.
During the overcurrent protection event, the output voltage droops if the duty cycle cannot satisfy output voltage
requirements and continues to droop until the UVP limit is reached. Then, the converter de-asserts the PGOOD
pin, and then enters hiccup mode after a 250-µs delay. The converter remains in hiccup mode until the fault is
cleared.
1
IOCL(dc ) = IOCL(valley ) + ´ IP-P
2
(4)
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Feature Description (continued)
7.3.5.5.2 Negative OCL
The negative OCL circuit acts when the converter is sinking current from the output capacitor(s). The converter
continues to act in a valley mode, the typical value of the negative OCL set point is –9.3 A or –6.5 A (depending
on mode selection).
7.3.6 Thermal Protection
The TPS53317 device has an internal temperature sensor. When the temperature reaches a nominal 145°C, the
device shuts down until the temperature decreases by approximately 10°C, when the converter restarts.
7.4 Device Functional Modes
7.4.1 Non-Droop Configuration
The TPS53317 device can be configured as a non-droop solution. The benefit of a non-droop approach is that
load regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is
recommended. For the Intel system agent application, non-droop is recommended as the standard configuration.
The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and
the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the
phase delay at unity gain cross over frequency of the converter.
The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the
value of the capacitor (CC) can be calculated by knowing where the zero location is desired. The capacitor CP is
optional, but recommended. Its appropriate capacitance value can be calculated using the desired pole location.
Figure 22 shows the basic implementation of the non-droop mode using the device
CP
RC
CC
VIN
COMP
VREF
VOUT
gMV = 1 mS
VSLEW
+
+
±
RDS(on)
SW
+
+
gMC= 1 mS
Driver
RLOAD
8 k:
+
±
LOUT
ESR
PWM
Comparator
ROUT
COUT
VREF
Figure 22. Non-Droop Mode Basic Implementation
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Device Functional Modes (continued)
Figure 23 shows shows the load regulation using non-droop configuration.
Figure 24 shows the transient response of the device using non-droop configuration, where COUT = 3 x 47 µF.
The applied step load is from 0 A to 2 A.
0.85
0.83
Output Voltage (V)
0.81
0.79
0.77
0.75
0.73
0.71
0.69
0.67
0.65
Non−Droop Configuration
1
2
VIN = 1.5 V
3
4
Output Current (A)
5
6
VOUT = 0.75 V
CH 2: VOUT
(20 mV/div)
Figure 23. Load Regulation (Non-Droop Configuration)
CH 4: IOUT
(1 A/div)
CH 3: SW
(1 V/div)
Figure 24. Non-Droop Configuration Transient Response
7.4.2 Droop Configuration
The terminology for droop is the same as load line or voltage positioning as defined in the Intel CPU VCORE
specification. Based on the actual tolerance requirement of the application, load-line set points can be defined to
maximize either cost savings (by reducing output capacitors) or power reduction benefits.
Accurate droop voltage response is provided by the finite gain of the droop amplifier. The equation for droop
voltage is shown in Equation 5.
´I
A
VDROOP = CSINT OUT
RDROOP ´ gM
where
•
•
•
•
•
low-side on-resistance is used as the current sensing element
ACSINT is a constant, which nominally is 53 mV/A.
IOUT is the DC current of the inductor, or the load current
RDROOP is the value of resistor from the COMP pin to the VREF pin
gM is the transconductance of the droop amplifier with nominal value of 1 mS
Equation 6 can be used to easily derive RDROOP for any load line slope/droop design target.
V
A CSINT
A CSINT
\ RDROOP =
RLOAD _ LINE = DROOP =
IOUT
RDROOP ´ gM
RLOAD _ LINE ´ gM
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(6)
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Device Functional Modes (continued)
Figure 25 shows the basic implementation of the droop mode using the TPS53317 device.
RDROOP
VIN
COMP
VREF
VOUT
gMV = 1 mS
VSLEW
+
+
±
RDS(on)
SW
+
+
gMC= 1 mS
Driver
RLOAD
8 k:
+
±
LOUT
ESR
PWM
Comparator
ROUT
COUT
VREF
Figure 25. DROOP Mode Basic Implementation
The droop (voltage positioning) method was originally recommended to reduce the number of external output
capacitors required. The effective transient voltage range is increased because of the active voltage positioning
(see Figure 26).
Load insertion
IOUT
Load release
Droop
VOUT setpoint at 0 A
Maximum transient voltage
= (5%±1%) x 2 = 8% x VOUT
VOUT setpoint at 6 A
NonDroop
Maximum overshoot voltage =(5%±1%) x 1 = 4% x VOUT
VOUT setpoint at 0 A
Maximum undershoot voltage =(5%±1%) x 1 = 4% x VOUT
Figure 26. DROOP vs Non-DROOP in Transient Voltage Window
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Device Functional Modes (continued)
In applications where the DC and the AC tolerances are not separated, (meaning that there is no strict DC
tolerance requirement) the droop method can be used.
Table 1. Mode Definitions
MODE
MODE
RESISTANCE (kΩ)
LIGHT-LOAD
POWER SAVING
MODE
SWITCHING
FREQUENCY
(fSW)
OVERCURRENT
LIMIT (OCL)
VALLEY (A)
1
0
600 kHz
7.6
2
12
600 kHz
5.4
3
22
1 MHz
5.4
4
33
1 MHz
7.6
5
47
600 kHz
7.6
6
68
600 kHz
5.4
1 MHz
5.4
1 MHz
7.6
7
100
8
OPEN
SKIP
PWM
Figure 27 shows the load regulation of the 1.5-V rail using an RDROOP value of 6.8 kΩ.
Figure 28 shows the transient response of the TPS53317 device using droop configuration and COUT = 3 × 47
µF. The applied step load is from 0 A to 2 A.
0.85
0.83
Output Voltage (V)
0.81
0.79
0.77
0.75
0.73
0.71
0.69
0.67
0.65
Droop Configuration
0
1
VIN = 1.5 V
2
3
4
Output Current (A)
5
6
VOUT = 0.75 V
CH 2: VOUT
(20 mV/div)
Figure 27. Load Regulation (Droop Configuration)
CH 4: IOUT
(1 A/div)
CH 3: SW
(1 V/div)
Figure 28. Droop Configuration Transient Response
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS53317 device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It
can provide a regulated output at ½ VDDQ with both sink and source capability. The device employs D-CAP+
mode operation that provides ease-of-use, low external component count and fast transient response.
8.2 Typical Applications
8.2.1 DDR4 SDRAM Application
This DDR4 application requires a tight load tolerance, fast transient response, and sinking current capability, the
design uses a non-droop PWM configuration.
R1
100 NŸ
R2
68 NŸ
5V
C5
2.2 µF
20
PGND
19
V5IN
C4
C3
22 PF 22 PF
C2
22 PF
C1
22 PF
VIN
18
PGOOD MODE
17
16
EN
BST
C6
0.1PF
1
PGND
SW 15
2
PGND
SW 14
3
PGND
4
VIN
SW 12
5
VIN
SW 11
7
8
C22
1PF
R6
3.9 NŸ
C21
2.2 nF
9
10
VOUT
C7 C8
C9
C10 C11 C12
1 PF 22 PF 22 PF 22 PF 22 PF 22 PF
C13 C14 C15 C16 C17 C18
22 PF 22 PF 22 PF 22 PF 22 PF 22 PF
VREF COMP REFIN VOUT
6
AGND
L1
0.25 PH
SW 13
TPS53317
GND
R7
0 Ÿ
R8
0 Ÿ
EN
R3
10 Ÿ
VIN
C20
33 pF
R4
60.4 NŸ
C19
10 nF
C23
0.1 PF
R5
60.4 NŸ
Figure 29. DDR4 SDRAM Application
8.2.1.1 Design Requirements
• Input voltage : VIN = 1.2 V
• Output voltage: VOUT = 0.6 V
• Maximum load step size of 3 A @ slew rate 7 A/µs (–1.5 A to 1.5 A)
• DC +AC + Ripple voltage regulation limit at sense point: ±42 mV (0.642 V overshoot, 0.558 V undershoot)
• Maximum load: IMAX = 2.5 A
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Step 1. Determine Configuration
Because this DDR4 application requires a tight load tolerance, fast transient response, and sinking current
capability, the design uses a non-droop PWM configuration. Choose 600-kHz switching frequency due to the
duty cycle and minimim off-time of the device, and set an overcurrent (OC) valley limit of 5.4 A due to the
maximum load requirement of 2.5 A. Referring to Table 1 select an RMODE value of 68 kΩ.
8.2.1.2.2 Step 2. Select Inductor
Smaller inductor values have better transient performance but higher ripple and lower efficiency. High values
have the opposite characteristics. It is common practice to limit the ripple current to 30% to 50% of the maximum
current. Choose 50% to allow use of a smaller inductor for faster transient performance.
+2F2 = 2.5 # × 0.5 = 1.25 #
1
.=
× 8176 × (1 F &)
B59 × +2F2
(7)
where
•
D = duty cycle
(8)
Because this device operates in DCAP+ mode, the frequency and duty cycle vary based on the input voltage, the
output voltage and load. With a 2.5-A load, a 1.2-V input voltage and 0.60 V output voltage, fSW is experimentally
measured at approximately 800 kHz and duty cycle of 0.55. Therefore L is calculated as shown in Equation 10.
.=
1
× 0.68 × 0.45 = 0.270 µ*
(800 G*V × 1.25 #)
(9)
Choose the closest standard value, 0.25 µH.
8.2.1.2.3 Step 3. Determine Output Capacitance
Use Equation 10 to calculate the output capacitance for a desired maximum overshoot.
%176 :IEJ ;,15 =
2
+176
×.
2 × 8176 × 815
where
•
•
•
•
COUT(min),OS is the minimum output capacitance for a desired overshoot
ΔIOUT is the maximum output current change in the application
VOUT = desired output voltage
VOS is the desired output voltage change due to overshoot
(10)
Choose a value of 30 mV to account for normal output voltage ripple.
%176 :IEJ ;,15 =
:3 A;2 × 0.25 µ*
= 62.5 µ(
2 × 0.6 8 × 0.03 8
(11)
Use Equation 12 to calculate the necessary output capacitance for a desired maximum undershoot.
%176 :IEJ ;,75
8176
2
+176
×.×@ 8
× P59 + P/+0 :KBB ; A
+0
=
8 F 8176
× P59 F P/+0:KBB; A
2 × 8176 × 875 × @ +0
8+0
where
•
•
•
•
COUT(min),US is the minimum output capacitance for a desired undershoot
VUS is the desired output voltage change due to overshoot
tSW is the period of switch node
tMIN(off) is the minimum off-time (270 ns)
(12)
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Typical Applications (continued)
Again, choose 30 mV to account for normal output voltage ripple.
%176 :IEJ ;,75
0.6 8
1
:3 A;2 × 0.25 µ* × @
×
+ 270 JOA
1.2
8
800
G*V
=
= 157.6 µ(
1.2 8 F 0.6 8
1
2 × 0.6 8 × 0.03 8 × @
×
F
270
JOA
1.2 8
800 G*V
(13)
The undershoot requirements determine, so there must be a minimum of 157.6 µF. Because this is a DDR
application where size is also a consideration, this design uses only ceramic capacitors. To account for voltage
de-rating of capacitors and provide additional margin, this design includes eleven 22-µF output capacitors.
8.2.1.2.4 Step 4. Input Capacitance
This design requires sufficient input capacitance to filter the input current from the host source. Use Equation 14
to calculate the necessary input capacitance.
%+0:IEJ ; = +KQP ×
& × (1 F &)
8+0(2F2) × B59
where
ΔVIN(P-P) is the desired input voltage ripple (typically 1% of the input voltage)
•
%+0:IEJ ;
0.55 × (1 F 0.55)
= 64.45 µ(
= 2.5 # ×
12 mV × 800 G*V
(14)
(15)
As with the output capacitance selection, this design accounts for voltage de-rating of capacitors and provides
additional margin, using four 22-µF input capacitors.
8.2.1.2.5 Step 5. Compensation Network
In order to achieve stable operation, the crossover frequency should be less than 1/5 of the switching frequency.
B%1 =
1
4%
g/
×
×
= 80 G*V
2è %176 45
where
•
RS = 53 mΩ
(16)
Account for capacitor de-rating here and set the value of COUT to 160 µF, so that Equation 17 is true.
4% =
B%1 × 45 × 2è × %176 80 G*V × 53 I3 × 2è × 160 ä(
=
= 4.26 G3
C/
1 I5
(17)
Choose an RC value of 3.9 kΩ. Determine CC by choosing the value of the zero created by RC and CC. Using the
relationship described in Equation 18.
B%1
1
=
2è × 4% × %%
5
BV =
(18)
Equation 18 yields a CC value of 2.55 nF. Choose the closest common capacitor value of 2.2 nF. To determine a
value for CP, first consider the relationship described in Equation 19.
1
BL =
•
% × %2
2è × 4% × %
%% + %2
N
1
2è × 4% × %2
CC >> CP
(19)
Because CC >> CP , set the pole to be two times the switching frequency as described in Equation 20.
1
%2 2è × 4% × 2B59
=
1
= 25.5 L(
2è × 3.9 G3 × 2 × 800 G*V
(20)
To boost the gain margin, set CP to 33 pF.
22
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Typical Applications (continued)
TPS53317
RC
VREF
7
CP
CC
COMP
8
Figure 30. Compensation Network Circuit
8.2.1.2.6 Peripheral Component Selection
As described in Table 1, connect a 0.22-µF capacitor from the VREF pin to GND and connect a 0.1-µF bootstrap
capacitor from the SW pin to the BST pin. Because the PGOOD pin is open drain, connect a pullup resistor
between it and the 5-V rail.
8.2.1.3 Application Curves
95
90
VOUT
(20 mV/div)
80
75
70
65
Design Example
VIN = 1.2 V
VOUT = 0.6 V
fSW = 600 kHz PWM
60
55
50
0.0
0.5
1.0
1.5
2.0
IOUT
2.5
Output Current (A)
(1 A/div)
C018
Figure 31. Efficiency
60
50
40
120
40
120
30
80
30
80
20
40
20
40
10
0
10
0
0
±10
±20
fCO = 86.66 kHz
Phase Margin = 63.3ƒ
Gain Margin = 19.58 dB
±80
Mag
Phase
±30
±40
±40
1k
10k
100k
1M
Frequency (Hz)
Magnitude (dB)
60
160
IOUT = 0 A
fSW = 600 kHz PWM
Phase (ƒ)
200
VIN = 1.2 V
VOUT = 0.6 V
50
Magnitude (dB)
Figure 32. Load Transient
0
±10
±120
±20
±160
±30
±200
±40
VIN = 1.2 V
VOUT = 0.6 V
200
IOUT = 2.5 A
fSW = 600 kHz PWM
160
±40
fCO = 89.83 kHz
Phase Margin = 64.7ƒ
Gain Margin = 17.32 dB
±80
±120
Mag
Phase
1k
C014
Figure 33. Bode Plot, No Load
Phase (ƒ)
Efficiency (%)
85
±160
10k
100k
1M
±200
Frequency (Hz)
C015
Figure 34. Bode Plot, Full Load
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850
0.610
830
0.608
810
0.606
Output Voltage (V)
Switching Frequency (kHz)
Typical Applications (continued)
790
770
750
730
710
690
650
±2.5 ±2.0 ±1.5 ±1.0 ±0.5
0.0
0.5
1.0
1.5
2.0
0.600
0.598
0.596
Design Example
VIN = 1.2 V
fSW = 600 kHz PWM
0.592
0.590
±2.5 ±2.0 ±1.5 ±1.0 ±0.5
2.5
Output Current (A)
0.602
0.594
Design Example
VIN = 1.2 V
fSW = 600 kHz PWM
670
0.604
0.0
0.5
1.0
Output Current (A)
C020
Figure 35. Switching Frequency vs. Load
1.5
2.0
2.5
C019
Figure 36. Load Regulation
8.2.2 DDR3 SDRAM Application
R1
100 NŸ
R2
68 NŸ
5V
C5
2.2 µF
20
PGND
19
V5IN
C4
C3
22 PF 22 PF
C2
22 PF
C1
22 PF
VIN
R8
0 Ÿ
EN
18
PGOOD MODE
17
16
EN
BST
C6
0.1PF
1
PGND
SW 15
2
PGND
SW 14
3
PGND
4
VIN
SW 12
5
VIN
SW 11
GND
R7
0 Ÿ
C13 C14 C15 C16 C17 C18
22 PF 22 PF 22 PF 22 PF 22 PF 22 PF
VREF COMP REFIN VOUT
6
AGND
C7 C8
C9
C10 C11 C12
1 PF 22 PF 22 PF 22 PF 22 PF 22 PF
SW 13
TPS53317
VOUT
L1
0.25 PH
7
8
C22
1PF
R6
3.9 NŸ
C21
2.2 nF
9
10
R3
10 Ÿ
VIN
C20
33 pF
R4
60.4 NŸ
C19
10 nF
C23
0.1 PF
R5
60.4 NŸ
Figure 37. Typical Application Schematic, DDR3
8.2.2.1 Design Requirements
• VIN = 1.5 V
• VOUT = 0.75 V
24
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Typical Applications (continued)
8.2.3 Non-Tracking Point-of-Load (POL) Application
R1
100 NŸ
R2
47 NŸ
5-V VIN
C5
2.2 µF
20
PGND
19
V5IN
C4
C3
22 PF 22 PF
C2
22 PF
C1
22 PF
VIN
R8
2 Ÿ
EN
18
PGOOD MODE
C6
0.1PF
17
16
EN
BST
1
PGND
SW 15
2
PGND
SW 14
3
PGND
4
VIN
SW 12
5
VIN
SW 11
R7
0 Ÿ
C7 C8
C9
C10 C11 C12
1 PF 22 PF 22 PF 22 PF 22 PF 22 PF
C13 C14 C15 C16 C17 C18
22 PF 22 PF 22 PF 22 PF 22 PF 22 PF
VREF COMP REFIN VOUT
6
7
8
9
10
R3
10 Ÿ
C22
1PF
AGND
VOUT
SW 13
TPS53317
GND
L1
0.25 PH
C19
10 nF
R6
3.9 NŸ
C20
33 pF
R4
150 NŸ
C23
0.1 PF
R5
100 NŸ
C21
2.2 nF
Figure 38. Typical Application Schematic, Non-Tracking Point-of-Load (POL)
8.2.3.1 Design Requirements
• VIN = 3.3 V
• VOUT = 1.2 V
8.2.3.2 Application Curves
50
40
120
40
120
30
80
30
80
20
40
20
40
10
0
10
0
Magnitude (dB)
0
±10
±20
fCO = 89.36 kHz
Phase Margin = 66.54ƒ
Gain Margin = 15.58 dB
±80
Mag
Phase
±30
±40
±40
1k
10k
100k
Frequency (Hz)
1M
Magnitude (dB)
60
160
IOUT = 0 A
fSW = 600 kHz PWM
Phase (ƒ)
200
VIN = 3.3 V
VOUT = 1.2 V
50
0
±10
±120
±20
±160
±30
±200
±40
VIN = 3.3 V
VOUT = 1.2 V
200
IOUT = 6 A
fSW = 600 kHz PWM
160
±40
fCO = 95.05 kHz
Phase Margin = 65.83ƒ
Gain Margin = 14.18 dB
±80
±120
Mag
Phase
1k
C016
Figure 39. Bode Plot No Load
Phase (ƒ)
60
±160
10k
100k
1M
±200
Frequency (Hz)
C017
Figure 40. Bode Plot Full Load
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9 Power Supply Recommendations
This device operates from an input voltage supply between 1 V and 6 V. This device requires a separate 5-V
power supply for analog circuits and gate drive. Use the proper bypass capacitors for both the input supply and
the 5-V supply in order to filter noise and to ensure proper device operation.
10 Layout
10.1 Layout Guidelines
Stable power supply operation depends on proper layout. Follow these guidelines for an optimized PCB layout.
• Connect PGND pins to the thermal pad underneath the device. Use four vias to connect the thermal pad to
internal ground planes.
• Place VIN, V5IN and VREF decoupling capacitors as close to the device as possible.
• Use wide traces for the VIN, PGND and SW pins. These nodes carry high current and also serve as heat
sinks.
• Place feedback and compensation components as close to the device as possible.
• Place COMP and VOUT analog signal traces away from noisy signals (SW, BST).
• The GND pin should connect to the PGND in only one place, through a via or a 0-Ω resistor.
BST
EN
SW
PGND
SW
PGND
VIN
SW
PGND
VOUT
SW
REFIN
VIN
COMP
VOUT
SW
Thermal Pad
GND
VIN
MODE
PGND
VREF
PGND
PGOOD
V5IN
10.2 Layout Example
VIN
Figure 41. TPS53317 Board Layout
26
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SLUSAK4D – JUNE 2011 – REVISED JULY 2015
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
D-CAP+, D-CAP+, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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27
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DPA02257RGBR
ACTIVE
VQFN
RGB
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
53317
HPA01188RGBR
ACTIVE
VQFN
RGB
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
53317
TPS53317RGBR
ACTIVE
VQFN
RGB
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
53317
TPS53317RGBT
ACTIVE
VQFN
RGB
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
53317
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DPA02257RGBR
VQFN
RGB
20
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
DPA02257RGBR
VQFN
RGB
20
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
TPS53317RGBR
VQFN
RGB
20
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
TPS53317RGBR
VQFN
RGB
20
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
TPS53317RGBT
VQFN
RGB
20
250
180.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DPA02257RGBR
VQFN
RGB
20
3000
367.0
367.0
35.0
DPA02257RGBR
VQFN
RGB
20
3000
367.0
367.0
35.0
TPS53317RGBR
VQFN
RGB
20
3000
367.0
367.0
35.0
TPS53317RGBR
VQFN
RGB
20
3000
552.0
367.0
36.0
TPS53317RGBT
VQFN
RGB
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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