Cypress CY7C1384D-166AXI 18-mbit (512 k ã 32) pipelined sram Datasheet

CY7C1384D
18-Mbit (512 K × 32) Pipelined SRAM
18-Mbit (512 K × 32) Pipelined SRAM
Features
Functional Description
■
Supports bus operation up to 166 MHz
■
Available speed grades are 166 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V or 3.3 V I/O power supply
■
Fast clock-to-output times
❐ 3.4 ns (for 166 MHz device)
■
Provides high performance 3-1-1-1 access rate
Intel
Pentium®
■
User selectable burst counter supporting
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1384D is available in JEDEC-standard Pb-free 100-pin
TQFP
■
ZZ sleep mode option
The CY7C1384D SRAM integrates 524,288 × 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE1),
depth-expansion chip enables (CE2 and CE3), burst control
inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Truth Table on page 7 for further details). Write
cycles can be one to two or four bytes wide as controlled by the
byte write control inputs. GW when active LOW causes all bytes
to be written.
The CY7C1384D operates from a +3.3 V core power supply
while all outputs operate with a +2.5 or +3.3 V power supply. All
inputs
and
outputs
are
JEDEC-standard
and
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
166 MHz
Unit
Maximum Access Time
Description
3.4
ns
Maximum Operating Current
275
mA
Maximum CMOS Standby Current
70
mA
Cypress Semiconductor Corporation
Document Number: 001-74017 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 4, 2016
CY7C1384D
Logic Block Diagram – CY7C1384D
Document Number: 001-74017 Rev. *C
Page 2 of 20
CY7C1384D
Contents
Pin Configurations ........................................................... 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Single Write Accesses Initiated by ADSP ................... 5
Single Write Accesses Initiated by ADSC ................... 5
Burst Sequences ......................................................... 5
Sleep Mode ................................................................. 6
Interleaved Burst Address Table
(MODE = Floating or VDD) ................................................. 6
Linear Burst Address Table (MODE = GND) ............... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Truth Table for Read/Write .............................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
Document Number: 001-74017 Rev. *C
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 3 of 20
CY7C1384D
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable)
CY7C1384D (512 K × 32)
Document Number: 001-74017 Rev. *C
Page 4 of 20
CY7C1384D
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.4 ns (166 MHz device).
CY7C1384D supports secondary cache in systems using a
linear or interleaved burst sequence. The interleaved burst order
supports Pentium and i486 processors. The linear burst
sequence suits processors that use a linear burst sequence. The
burst order is user selectable, and is determined by sampling the
MODE input. Accesses can be initiated with either the processor
address strobe (ADSP) or the controller address strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is enabled to propagate to the input of the
output registers. At the rising edge of the next clock, the data is
enabled to propagate through the output register and onto the
data bus within 3.4 ns (166 MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state; its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1,
CE2, and CE3 are all asserted active. The address presented to
A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
Document Number: 001-74017 Rev. *C
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
CY7C1384D provides byte write capability that is described in
the write cycle descriptions table. Asserting the byte write enable
input (BWE) with the selected byte write (BWX) input, selectively
writes to only the desired bytes. Bytes not selected during a byte
write operation remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
CY7C1384D is a common I/O device, the output enable (OE)
must be deserted HIGH before presenting data to the DQs
inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, and CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BWX) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
CY7C1384D is a common I/O device, the output enable (OE)
must be deserted HIGH before presenting data to the DQs
inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE.
Burst Sequences
CY7C1384D provides a two-bit wraparound counter, fed by
A1:A0, that implements an interleaved or a linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Page 5 of 20
CY7C1384D
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-74017 Rev. *C
Page 6 of 20
CY7C1384D
Truth Table
The Truth Table for this data sheet follows. [1, 2, 3, 4, 5]
Operation
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-state
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
L–H Tri-state
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-state
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-state
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-state
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-state
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-state
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-state
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
Q
Notes
1. X = Don't Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-74017 Rev. *C
Page 7 of 20
CY7C1384D
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1384D follows. [6, 7]
Function (CY7C1384D)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA)
H
L
H
H
H
L
Write Byte B – (DQB)
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes
6. X = Don't Care, H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-74017 Rev. *C
Page 8 of 20
CY7C1384D
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
DC Voltage Applied to Outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
Ambient
Temperature
Range
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Industrial
–40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [8, 9]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[8]
Test Conditions
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input Current of MODE
Input LOW Voltage
[8]
Input Current of ZZ
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
IOZ
Output Leakage Current
GND  VI  VDDQ, Output Disabled
–5
5
A
IDD
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
6.0-ns cycle,
166 MHz
–
275
mA
ISB1
Automatic CE Power Down
Current – TTL Inputs
VDD = Max, Device Deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
6.0-ns cycle,
166 MHz
–
140
mA
ISB2
Automatic CE Power Down
Current – CMOS Inputs
VDD = Max, Device Deselected, All speeds
VIN  0.3 V or VIN > VDDQ – 0.3 V,
f=0
–
70
mA
ISB3
Automatic CE Power Down
Current – CMOS Inputs
VDD = Max, Device Deselected, 6.0-ns cycle,
VIN  0.3 V or VIN > VDDQ – 0.3 V, 166 MHz
f = fMAX = 1/tCYC
–
125
mA
ISB4
Automatic CE Power Down
Current – TTL Inputs
VDD = Max, Device Deselected,
VIN  VIH or VIN  VIL, f = 0
–
80
mA
All speeds
Notes
8. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
9. TPower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-74017 Rev. *C
Page 9 of 20
CY7C1384D
Capacitance
Parameter [10]
Description
Test Conditions
100-pin TQFP
Package
Unit
CIN
Input Capacitance
5
pF
CCLK
Clock Input Capacitance
5
pF
CIO
Input/Output Capacitance
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
28.66
°C/W
4.08
°C/W
TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 351 
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
OUTPUT
RL = 50 
Z0 = 50 
VT = 1.25 V
(a)
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
 1 ns
(b)
GND
5 pF
90%
10%
90%
 1 ns
R = 1667 
2.5 V
OUTPUT
ALL INPUT PULSES
VDDQ
R = 1538 
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
10. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-74017 Rev. *C
Page 10 of 20
CY7C1384D
Switching Characteristics
Over the Operating Range
Parameter [11, 12]
Description
166 MHz
Unit
Min
Max
VDD(typical) to the first access [13]
1
–
ms
tCYC
Clock cycle time
6
–
ns
tCH
Clock HIGH
2.2
–
ns
tCL
Clock LOW
2.2
–
ns
tPOWER
Clock
Output Times
tCO
Data output valid after CLK rise
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
ns
1.3
–
ns
–
3.4
ns
–
3.4
ns
0
–
ns
–
3.4
ns
[14, 15, 16]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [14, 15, 16]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[14, 15, 16]
OE HIGH to output high Z
[14, 15, 16]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
11. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
12. Test conditions shown in (a) of Figure 2 on page 10 unless otherwise noted.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 10. Transition is measured ±200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document Number: 001-74017 Rev. *C
Page 11 of 20
CY7C1384D
Switching Waveforms
Figure 3. Read Cycle Timing [17]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-74017 Rev. *C
Page 12 of 20
CY7C1384D
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [18, 19]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-74017 Rev. *C
Page 13 of 20
CY7C1384D
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [20, 21, 22]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
tOEHZ
D(A3)
D(A5)
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
22. GW is HIGH.
Document Number: 001-74017 Rev. *C
Page 14 of 20
CY7C1384D
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [23, 24]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
23. Device must be deselected when entering ZZ mode. See Truth Table on page 7 for all possible signal conditions to deselect the device.
24. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-74017 Rev. *C
Page 15 of 20
CY7C1384D
Ordering Information
The below table lists the key package features and ordering codes. The table contains only the parts that are currently available. If
you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Speed
(MHz)
166
Package
Diagram
Ordering Code
CY7C1384D-166AXI
Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Industrial
Ordering Code Definitions
CY 7
C
1384
D - 166
A
X
I
Temperature Range:
I = Industrial
Pb-free
Package Type:
A = 100-pin TQFP
Frequency Range: 166 MHz
Die Revision:
D  90 nm
Part Identifier:
1384 = SCD, 512 K × 32 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-74017 Rev. *C
Page 16 of 20
CY7C1384D
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-74017 Rev. *C
Page 17 of 20
CY7C1384D
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
I/O
Input/Output
µA
microampere
JEDEC
Joint Electron Devices Engineering Council
mA
milliampere
OE
Output Enable
mm
millimeter
SRAM
Static Random Access Memory
ms
millisecond
TQFP
Thin Quad Flat Pack
mV
millivolt
TTL
Transistor-Transistor Logic
ns
nanosecond
Document Number: 001-74017 Rev. *C
Symbol
Unit of Measure

ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 18 of 20
CY7C1384D
Document History Page
Document Title: CY7C1384D, 18-Mbit (512 K × 32) Pipelined SRAM
Document Number: 001-74017
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
3489511
01/10/2012
NJY
*A
3607309
05/03/2012
PRIT
Changed status from Preliminary to Final.
*B
4573182
11/18/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*C
5071495
01/04/2016
PRIT
Updated to new template.
Completing Sunset Review.
Document Number: 001-74017 Rev. *C
Description of Change
New data sheet
Page 19 of 20
CY7C1384D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-74017 Rev. *C
Revised January 4, 2016
All products and company names mentioned in this document may be the trademarks of their respective holders.
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