AN2031 APPLICATION NOTE STA308-508 EVALUATION BOARD DESCRIPTION 1 DESCRIPTION The STA308A is a single chip solution for digital audio processing and control in multi-channel application. It provides output capabilities for DDX (Direct Digital Amplification). In conjunction with DDX power device, it provides high quality, high efficiency, all digital amplification. STA508 is a monolithic quad half bridge stage in Multipower BCD technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability. This device is particularly designed to make the Output stage of a stereo DDX amplifier capable to deliver 80 + 80W @THD = 10% at Vcc = 35V output power on 8Ω load. In single BTL configuration, is also capable to deliver a peak of 160W@THD = 10% at Vcc = 35V on 4Ω load (t<= 1sec). 2 STA308-508// EVALUATION BOARD DESCRIPTION In this board it is possible to solder STA308 or STA308A device how digital audio processor. There are three jumpers (JP2, JP3, JP6) to select the correct device. The board has one S/PDIF input (electrical single ended and optical). In this board it is possible to use two different powers (10V to 35V on J2) and logic (5V on J1) stages or only one supply (10V to 35V on J2) for both stages. This feature is possible setting JP1 in EXT-SEL or INT-SEL respectively. U6 and U7 are configured to drive 3 or 2 ohm (over 250W) on the channel. 2.1 SUPPLY VOLTAGE, REGULATORS The STA308-508// board uses 5V, 3.3V power regulation for logic circuitry and 10<Vcc<35 for power section of STA508 device. It is possible to apply only one power supply and to extract the logic power supply utilizing the L4971D step down device 2.2 S/PDIF INPUT INTERFACE The STA308A controller's data interface is serial I2S for input. The STA308-508//-EVB input accommodates coaxial or optical S/PDIF digital audio interfaces using a digital audio receiver IC. Jumper JP5 may select either input. S/PDIF interfaces (STA120D) will support sample rates from 32KHz to 96KHz Optical S/PDIF receiver IC is SHARP GP1F31R. 2.3 DIGITAL SIGNAL PROCESSING The STA308A converts pulse code modulated, PCM, digital audio input signals into PulseWidth Modulated PWM. This signal enters in the same time in the two STA508 ICs and the exit signal is at high level of power. The STA308A has two independent volume control registers AN2031/0705 Rev. 1 1/12 AN2031 APPLICATION NOTE that have an adjustment range from +48dB to -78dB in 0.5dB increments. In addition, the mater volume is adjustable from 0dB to -127dB in 0.5dB steps. Tone control registers boost or cut the treble and bass by +/-12dB, in 2dB steps. EQ filters are IIR biquads configurable by programmable coefficients. 2.4 POWER OUTPUT The power level signals are applied to passive two-pole low pass filter, and provide low distortion audio power to the load. The output filter functions to prevent unwanted high frequency switching signals from reaching the load. Filter designs for 2Ω. Peak voltage on power pins must not exceed 35V. Snubber networks are employed to protect the output MOSFETs from inductive transients, which can reach levels higher than the supply voltage. Output snubber filter values are R18/C66 and R14/C53. The other critical components for device reliability are C47, C51, C58, C63 (1uF) and C48, C52, C59, C64 (100nF); these bypass capacitors from Vcc and power GND pins of STA508. These capacitors must be X7R Ceramic or Tantalum SMD construction and must be located as close as possible to the device pins. The STA508 shuts down when it reaches 150°C. 2.5 JUMPERS CONNECTOR The STA308-508//-EVB provides some jumpers to configure the board. 2.5.1 JUMPERS: JP1: (INT-SEL-EXT): short on EXT-SEL to use different power supplies; short on INT-SEL to use only one power supply; JP2: (2.5A): short (with solder tin) if STA308 IC is solder on the board. If there is the STA308A this jumper could be opened; JP3: (2.5A): short (with solder tin) if STA308 IC is solder on the board. If there is the STA308A this jumper could be opened; JP4: short this jumper to use two different power supply; JP5: (OPTIC- SPDIF -ELEC): short the central pin with ELEC pin to use Electric S/PDIF; short the central pin with OPTIC pin to use the optical S/PDIF. JP6: short (with solder tin) 3.3A and center if STA308A IC is solder on the board. If there is the STA308A this jumper could be short on 3.3V and center JP7: this pin must be open. 2.5.2 CONNECTORS: J1: Logic supply (5V) J2: Power Supply (10V to 35V) J3: Male 20 pin connector for plug control board J4: RCA connector electric S/PDIF J5: Optical S/PDIF SHARP GP1F31R J6: Connector for output load A 2/12 AN2031 APPLICATION NOTE 3 CONFIGURE STA308A-508//-EVB WITH LPT INTERFACE 1) 2) 3) 4) 5) 6) 7) Plug the LPT Interface on the board utilizing J3 of STA308A-508//-EVB and J2 of LPT Interface; Connect PC parallel port to the LPT board using a parallel cable; Select S/PDIF Input mode (electric or optical) with JP5; Connect logic supply (+5V) on J1 and power supply [10V..35V] on J2; Connect output load on J6; 6Turn on the board; Run STA308A-508PControlPanel.exe on the PC. 3.1 Configuring GUI Software: 1) Go to "Registers" page on GUI. 2) Click "AutoFind LPT" button. It appears the number of LPT port (0x278 or 0x378); 3) Click "Reset" button 4) Click "Power Up" button 5) Click "Test Board I/O". If "passed" it is OK. If "failed", then perform manual board-reset by pressing SW1 button and try again. If still "failed" then make sure connections are OK. 6) Go to "Control" page on GUI. 7) Click "Ext Amp Power Up" to enable the output power. 8) Increase "ALL" master volume control. 4 PERFORMANCES 4.1 THD+Noise Ratio versus Output Power at different input power supply Input frequency: 1KHz; Output load: 4Ω; Blue: 15V; Cyan: 20V; Green: 25V; Yellow: 30V; Red: 35V; Magenta: 37V Figure 1. Audio Precision 10 5 2 1 0.5 % 0.2 0.1 0.05 0.02 0.01 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 200 W 3/12 AN2031 APPLICATION NOTE 4.2 THD+Noise Ratio versus Output Power at different input power supply Input frequency: 1KHz; Output load: 2.67Ω; Blue: 15V; Cyan: 20V; Green: 25V; Yellow: 30V; Red: 35V; Magenta: 37V Figure 2. Audio Precision 10 5 2 1 0.5 % 0.2 0.1 0.05 0.02 0.01 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 300 W 4.3 THD+Noise Ratio versus Output Power at different input power supply Input frequency: 1KHz; Output load: 2Ω; Blue: 15V; Cyan: 20V; Green: 25V; Yellow: 30V; Red: 35V; Magenta: 37V Figure 3. Audio Precision 10 5 2 1 0.5 % 0.2 0.1 0.05 0.02 0.01 100m 4/12 200m 500m 1 2 5 W 10 20 50 100 300 AN2031 APPLICATION NOTE 4.4 THD+Noise Ratio versus frequency at different output power Input power supply: 25V; Output load: 4Ω; Blue: 0dB; Cyan: -10dB; Green: -20dB; Figure 4. Audio Precision 1 0.5 0.2 0.1 % 0.05 0.02 0.01 20 50 100 200 1k 500 2k 5k 10k 20k Hz 5 SCHEMATIC AND LAYOUT 5.1 Schematic Figure 5. Power Section J1 2 JP1 1 5V SEL Ext Sel Int +5V R1 1 2 3 10K 5V L1 C1 Vcc 220u 3V3 LD1086DT33 C9 JP4 C10 L4971D 220n 50V +30V 100n C12 22n C11 2.2n 2V5 2A5 OUT FERRITE 2 2 IN L3 JP2 JP3 2A5 2V5 1 1 + 1 3 C2 + 100u 10V C3 330u 10V + C7 100n C4 10u 10V C5 100n R4 4.7K FERRITE L4 LD1086DT25 U3 3 IN FERRITE GND C8 10u 50V R2 2.7K D1 1 R3 9.1K + 8 7 6 5 4 3 2 1 SMS160 C6 100n 8 7 6 5 4 3 2 1 1 2 9 U1 10 11 12 13 14 15 16 2 3 1 9 10 11 12 13 14 15 16 JUMPER Pwr GND 2 1 LCL GND U2 J2 3A3 100n L2 2 GND Logic C14 100n OUT L5 2 + C13 10u 10V C15 100n FERRITE C16 100n L6 Vicino all'STA308 5/12 AN2031 APPLICATION NOTE Figure 6. Connection Section 3V3 R5 10K J3 SCL R2 0 SDA 33 RESET 1 EAPD JP7 2 TP4 1 PWDN TP5 TP6 TP7 TP8 TP9 SW1 C17 1n BUTTON 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TP1 TP2 TP3 TH_W TP10 3V3 5V Test Pointer Test Pointer Test Pointer Test Pointer Test Pointer Test Pointer Test Pointer Test Pointer Test Pointer Test Pointer CON20 Figure 7. S/P DIF Section U4 1 2 5V L7 C1 8 100n 3 3V3 FE RRITE J4 GP1F31R +VS GND DATA C1 9 1 2 3 RCA JACK 5 6 100n C2 1 JP 5 SPDT/SM 1 2 OPT 3 ELEC J5 4 7 9 11 Cc/F0 SDA TA Cb/E2 ERF Ca/E1 M1 C0/E0 M0 VA+ AGND RXP FILT RXN MCK FS YNC C2 4 12 M2 SCK 13 R9 Ce/F2 DGND 10 100n VERF Cd/F1 VD+ 8 100n C 14 M3 CS1 2/FCK SEL U CBL 82 27 26 25 24 Non S aldare D2 DATA SPDIF R6 560 3V3 23 22 C2 0 21 100n 3A3 20 19 330 BICKI SPDIF R1 1 0 3V3 R1 2 NON S aldare R7 C22 15n XTI SP DIF 18 C2 3 470n 17 16 15 3V3 R1 0 NON saldare STA12 0 LRCKI SPDIF 6/12 28 R8 0 AN2031 APPLICATION NOTE Figure 8. STA308A Section 3V3 2V5 C25 C26 100n 100n 2V5 3V3 C27 100n C28 100n EAPD PWM1A PWM1B C29 100n 2V5 C31 100n 3V3 C33 100n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DATA SPDIF LRCKI SPDIF BICKI SPDIF C35 100n U5 STA308 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2V5 C30 100n C32 100n 3V3 2V5 C34 100n C36 100n 3V3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RESET OUT2A OUT2B Vdd GND Vdd3 OUT3A OUT3B OUT4A OUT4B OUT5A OUT5B Vdd GND Vdd3 OUT6A OUT6B TP11 TP12 PWM2A PWM2B NUOVO 1 3A3 JP6 PWR PLL SDA SCL XTI SPDIF 2 JUMPER SOLDER C37 100n 3V3 C38 2A5 R13 3.3K C42 1n 100n 3V3 100n C39 C40 100p 3 2V5 MVO TEST_MODE Vdd3 GND Vdd SDI_78 SDI_56 SDI_34 SDI_12 LRCKI BICKI Vdd3 GND Vdd RESET PLL_BYPASS SA SDA SCL XTI FILTER_PLL VddA GNDA Vdd3 CKO UT Vdd GND Vdd3 OUT8B OUT8A OUT7B OUT7A 3V3 PWDN SDO _78 SDO _56 Vdd GND Vdd3 SDO _34 SDO _12 LRCKO BICKO Vdd GND Vdd3 EAPD OUT1A OUT1B 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWDN 2V5 C41 100n PWR PLL 7/12 AN2031 APPLICATION NOTE Figure 9. STA508 Section U7 C54 C55 TH_W500 100n PWM2A TH_W 3V3 100n R15 PWM2B 10K FT500 D4 R16 C60 1N4148 10k EAPD EAPD5 00 100n TP14 3V3 C61 C62 100n 100n 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VccSig GND Sub VccSig OUT2B Vss OUT2B Vss Vcc2B IN2B GND2B IN2A GND2A IN1B Vcc2A IN1A OUT2A TH_WARN OUT2A FAULT OUT1B TRISTATE OUT1B PWRDN Vcc1B CONFIG GND1B Ibias GND1A Vdd Vcc1A Vdd OUT1A GNDReg OUT1A GNDClean NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Vcc OUT1A C56 100n OUT1A OUT1B OUT1B C58 C59 1u 100n C63 C64 1u 100n C57 1000u 50V + STA50 5 U6 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 C43 C44 100n 100n PWM2A PWM2B TH_W500 FT500 D3 1N4148 EAPD5 00 TP13 3V3 C49 C50 100n 100n VccSig GND Sub VccSig OUT2B Vss OUT2B Vss Vcc2B IN2B GND2B IN2A GND2A IN1B Vcc2A IN1A OUT2A TH_WARN OUT2A FAULT OUT1B TRISTATE OUT1B PWRDN Vcc1B CONFIG GND1B Ibias GND1A Vdd Vcc1A Vdd OUT1A GNDReg OUT1A GNDClean NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Vcc OUT1A_ C45 100n OUT1A_ OUT1B_ C47 C48 1u 100n OUT1B_ C51 C52 1u 100n + C46 1000u 50V STA50 5 Figure 10. Output Filter Section L10 OUT1A OUT1A_ L8 22u OUTA 505 22u OUTA 505 C65 100n C66 330p C53 330p C68 100n R14 20 C71 100n OUTB 505 L9 6.2 R19 R18 20 OUT1B_ C73 100n 22u OUT1B C69 J6 C70 1nF 63V 1uF 63V 1 2 CON2 6.2 C72 1n OUTB 505 L11 8/12 C67 1n R17 22u AN2031 APPLICATION NOTE 5.2 Layout Figure 11. Component Layer Figure 12. Solder Layer 9/12 AN2031 APPLICATION NOTE Figure 13. Serigraphy 10/12 AN2031 APPLICATION NOTE Table 1. Revision History Date Revision July 2005 1 Description of Changes First Issue 11/12 AN2031 APPLICATION NOTE The present note which is for guidance only, aims at providing customers with information regarding their products in order for them to save time. As a result, STMicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products. 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