TI1 DLPC3478 Display and light controller Datasheet

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DLPC3478
DLPS111 – MARCH 2018
DLPC3478 Display and Light Controller
1 Features
•
•
Display and Light Controller for DLP3010 (.3
720p) TRP DMD
Display Features:
– Supports Input Image Sizes Up to 720p
– Input Frame Rates to 120 Hz (2D and 3D)
– 24-Bit, Input Pixel Interface Support
– Parallel or BT656, Interface Protocols
– Pixel Clock Up to 150 MHz
– Image Processing - IntelliBright™ Algorithms,
Image Resizing, 1D Keystone, CCA,
Programmable Degamma
Light Control Features:
– Pattern Display Optimized for Machine Vision
and Digital Exposure
– Flexible Internal (1D) and External (2D)
Pattern Streaming Modes
– Programmable Exposure Times
– High Speed Pattern Rates Up to 2880 Hz
(1-bit) and 360 Hz (8-bit)
– Programmable 2D Static Patterns via Splash
– Internal Pattern Streaming Mode Enables
Simplified System Design
– Eliminates Video Interface Requirement
– Store >1000 Patterns in Flash Memory
– Flexible Trigger Signals for Camera/Sensor
Synchronization
– One Configurable Input Trigger
– Two Configurable Output Triggers
System Features:
– I2C Control of Device Configuration
– Programmable Splash Screens
– Programmable LED Current Control
– Auto DMD Parking at Power Down
2 Applications
•
•
•
•
•
•
Battery Powered Mobile Accessory HD Projector
Embedded Projection (Notebooks, Laptops,
Tablets, Hot Spots)
3D Depth Capture: 3D Camera, 3D
Reconstruction, AR/VR, Dental Scanner
3D Machine Vision: Robotics, Metrology, In-line
Inspection (AOI)
3D Biometrics: Facial and Finger Print
Recognition
Light Exposure: 3D Printers, Laser Marking
3 Description
The DLPC3478 display and light controller supports
reliable operation of the DLP3010 digital micromirror
device (DMD) for video display and light control
applications. The DLPC3478 controller provides a
convenient interface between user electronics and
the DMD to display video and steer light patterns with
high speed, precision, and efficiency.
Device Information
PART NUMBER
DLPC3478
PACKAGE
NFBGA (201)
(1)
BODY SIZE (NOM)
13.00 × 13.00 mm2
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Standalone System
PROJ_ON
Supports internal SPI Flash
patterns storage
GPIO_8 (Normal Park)
SPI_0
HOST_IRQ
SPI_1
DLPC3478
eDRAM
I2C
DLPA3000
VLED
SPI(4)
Current Sense
LED_SEL(2)
1.8 V
VSPI
3DR
VIO
VCORE
TSTPT
GPIO
GPIO
TRIG_OUT1
TRIG_OUT2
PAT_READY
1.1 V
1.1-V
Reg
Illumination
Optics
L3
BIAS, RST, OFS
3
Focus motor position sensor
Included in DLP® Chip Set
Non-DLP components
Monochrome/RGB
Illumination
Illuminator
SYSPWR
Parallel I/F 28
TRIG_IN
1.8 V
1.1 V
Focus stepper motor
PROJ_ON
Sub-LVDS DATA (18)
CTRL
WVGA
DLP3010
DDR DMD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
•
1
•
DLPC3478
DLPS111 – MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
8.2 Functional Block Diagram ....................................... 31
8.3 Feature Description................................................. 31
8.4 Serial Flash Interface .............................................. 38
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 14
9
9.1 Application Information............................................ 48
9.2 Typical Application ................................................. 48
10 Power Supply Recommendations ..................... 51
6.1
6.2
6.3
6.4
6.5
ADVANCE INFORMATION
Absolute Maximum Ratings .................................... 14
ESD Ratings............................................................ 14
Recommended Operating Conditions..................... 15
Thermal Information ................................................ 15
Electrical Characteristics over Recommended
Operating Conditions .............................................. 16
6.6 Electrical Characteristics......................................... 17
6.7 High-Speed Sub-LVDS Electrical Characteristics... 20
6.8 Low-Speed SDR Electrical Characteristics............. 21
6.9 System Oscillators Timing Requirements ............... 22
6.10 Power-Up and Reset Timing Requirements ......... 22
6.11 Parallel Interface Frame Timing Requirements .... 23
6.12 Parallel Interface General Timing Requirements .. 24
6.13 BT656 Interface General Timing Requirements ... 25
6.14 Flash Interface Timing Requirements ................... 26
7
10.1
10.2
10.3
10.4
10.5
System Power-Up and Power-Down Sequence ... 51
DLPC3478 Power-Up Initialization Sequence ...... 53
DMD Fast PARK Control (PARKZ) ....................... 54
Hot Plug Usage ..................................................... 54
Maximum Signal Transition Time.......................... 54
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
11.2 Layout Example .................................................... 60
11.3 Thermal Considerations ........................................ 60
12 Device and Documentation Support ................. 61
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information ................ 27
7.1 HOST_IRQ Usage Model ....................................... 27
7.2 Input Source............................................................ 28
8
Application and Implementation ........................ 48
Device Support ....................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
61
63
63
63
63
63
Detailed Description ............................................ 30
13 Mechanical, Packaging, and Orderable
Information ........................................................... 63
8.1 Overview ................................................................. 30
13.1 Package Option Addendum .................................. 64
4 Revision History
2
DATE
REVISION
NOTES
March 2018
*
Initial release.
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DLPS111 – MARCH 2018
5 Pin Configuration and Functions
ADVANCE INFORMATION
ZEZ Package
201-Pin NFBGA
Bottom View
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DLPS111 – MARCH 2018
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1
ADVANCE INFORMATION
4
2
3
4
5
6
7
8
9
10
11
12
A
DMD_LS_C DMD_LS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
CMP_OUT
P
LK
DATA
DATAH_P DATAG_P
DATAF_P
DATAE_P
DATAD_P
DATAC_P
DATAB_P
DATAA_P
B
DMD_DEN_ DMD_LS_R DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_CLK_ DMD_HS_W DMD_HS_W DMD_HS_W DMD_HS_W
N
ARSTZ
DATA
DATAH_N DATAG_N
DATAF_N
DATAE_N
DATAD_N
DATAC_N
DATAB_N
DATAA_N
SPI0_DIN
13
14
SPI0_CLK
15
SPI0_CSZ0 CMP_PWM
SPI0_DOUT LED_SEL_1 LED_SEL_0
C
DD3P
DD3N
VDDLP12
VSS
VDD
VSS
VCC
VSS
VCC
HWTEST_E
N
RESETZ
SPI0_CSZ1
PARKZ
GPIO_00
GPIO_01
D
DD2P
DD2N
VDD
VCC
VDD
VSS
VDD
VSS
VDD
VSS
VCC_FLSH
VDD
VDD
GPIO_02
GPIO_03
E
DCLKP
DCLKN
VDD
VSS
VCC
VSS
GPIO_04
GPIO_05
F
DD1P
DD1N
RREF
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VDD
GPIO_06
GPIO_07
G
DD0P
DD0N
VSS_PLLM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIO_08
GPIO_09
H
PLL_REFCL
VDD_PLLM VSS_PLLD
K_I
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
GPIO_10
GPIO_11
J
PLL_REFCL
VDD_PLLD
K_O
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VSS
GPIO_12
GPIO_13
VSS
VSS
VSS
VSS
VSS
VSS
VCC
GPIO_14
GPIO_15
VDD
VDD
GPIO_16
GPIO_17
VSS
JTAGTMS1
GPIO_18
GPIO_19
JTAGTDO1
TSTPT_6
TSTPT_7
K
PDATA_1
PDATA_0
VDD
VSS
L
PDATA_3
PDATA_2
VSS
VDD
M
PDATA_5
PDATA_4
VCC_INTF
VSS
N
PDATA_7
PDATA_6
VCC_INTF
P
VSYNC_WE
DATEN_CM
D
PCLK
PDATA_11
R
PDATA_8
PDATA_9
PDATA_10
PDATA_12
VSS
VDD
VCC_INTF
VSS
VDD
VDD
3DR
VCC_INTF
HOST_IRQ
IIC0_SDA
IIC0_SCL
PDATA_13
PDATA_15
PDATA_17
PDATA_19
PDATA_21
PDATA_23
PDATA_14
PDATA_16
PDATA_18
PDATA_20
PDATA_22
IIC1_SDA
PDM_CVS_
HSYNC_CS
TE
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VCC
JTAGTMS2 JTAGTDO2
JTAGTRSTZ
JTAGTCK
JTAGTDI
TSTPT_4
TSTPT_5
IIC1_SCL
TSTPT_0
TSTPT_1
TSTPT_2
TSTPT_3
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DLPS111 – MARCH 2018
Pin Functions – Board Level Test, Debug, and Initialization
NAME
HWTEST_EN
NUMBER
C10
I/O
DESCRIPTION
I6
Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal
operation.
PARKZ
C13
I6
DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to
enable normal operation. Set PARKZ high prior to releasing RESETZ (that is, prior to the lowto-high transition on the RESETZ input). Set PARKZ low for a minimum of 32 µs before any
power is removed from the DLPC3478 such that the fast DMD PARK operation can be
completed. Note for PARKZ, use fast PARK control only when loss of power is eminent and
beyond the control of the host processor (for example, when the external power source has
been disconnected or the battery has dropped below a minimum level). The longest lifetime of
the DMD may not be achieved with the fast PARK operation. The longest lifetime is achieved
with a normal PARK operation. Because of this, PARKZ is typically used in conjunction with a
normal PARK request control input through GPIO_08. The difference being that when the host
sets PROJ_ON low, which connects to both GPIO_08 and the DLPA200x or DLPA3000 PMIC
chip, the takes much longer than 32 µs to park the mirrors. The DLPA200x or DLPA3000 holds
on all power supplies, and keep RESETZ high, until the longer mirror parking has completed.
This longer mirror parking time, of up to 500 µs, ensures the longest DMD lifetime and
reliability.
The DLPA200x or DLPA3000 monitors power to the and detects an eminent power loss
condition and drives the PARKZ signal accordingly.
Reserved
P12
I6
TI internal use. Leave unconnected.
Reserved
P13
I6
TI internal use. Leave unconnected.
Reserved
N13 (1)
O1
TI internal use. Leave unconnected.
Reserved
(1)
O1
TI internal use. Leave unconnected.
Reserved
M13
I6
TI internal use. Leave unconnected.
Reserved
N11
I6
TI internal use. Leave unconnected.
Reserved
P11
I6
TI internal use
This pin must be tied to ground, through an external 8-kΩ, or less, resistor for normal operation.
Failure to tie this pin low during normal operation causes startup and initialization problems.
I6
power-on reset (active low input) (hysteresis buffer). Self-configuration starts when a low-to-high
transition is detected on RESETZ. All ASIC power and clocks must be stable before this reset is
de-asserted. Note that the following signals become tri-stated while RESETZ is asserted:
SPI0_CLK, SPI0_DOUT, SPI0_CSZ0,
SPI0_CSZ1, and GPIO(19:00)
External pullups or downs (as appropriate) are typically added to all tri-stated output signals
listed (including bidirectional signals to be configured as outputs) to avoid floating ASIC outputs
during reset if connected to devices on the PCB that can malfunction. For SPI, at a minimum,
any chip selects connected to the devices typically have a pullup.
Unused bidirectional signals can be functionally configured as outputs to avoid floating ASIC
inputs after RESETZ is set high.
The following signals are forced to a logic low state while RESETZ is asserted and
corresponding I/O power is applied:
LED_SEL_0, LED_SEL_1 and DMD_DEN_ARSTZ
No signals operate in active state while RESETZ is asserted.
Note that no I2C activity is permitted for a minimum of 500 ms after RESETZ (and PARKZ) are
set high.
RESETZ
TSTPT_0
N12
C11
R12
B1
Test pin 0 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ, and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode.
Without external pullup
Feeds TMSEL(0)
(1)
(2)
(3)
(2)
With external pullup (3)
Feeds TMSEL(0)
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,
then this I/O can be left open or unconnected for normal operation. If operation does not call for an external pullup, but there is external
logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.
External pullup resistor must be 8 kΩ, or less, for pins with internal pullup or down resistors.
If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor,
then the TSTPT I/O can be left open/ unconnected for normal operation. If operation does not call for an external pullup, but there is
external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a
logic low.
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PIN
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DLPS111 – MARCH 2018
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Pin Functions – Board Level Test, Debug, and Initialization (continued)
PIN
NAME
NUMBER
TSTPT_1
R13
I/O
B1
DESCRIPTION
Test pin 1 (includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode.
Without external pullup (2)
Feeds TMSEL(1)
TSTPT_2
R14
B1
Test pin 2 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Note: Do not apply an external pullup component to this pin to avoid putting the in a test mode.
Without external pullup (2)
Feeds TMSEL(2)
TSTPT_3
R15
With external pullup (3)
Feeds TMSEL(1)
With external pullup (3)
Feeds TMSEL(2)
ADVANCE INFORMATION
B1
Test pin 3 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for for test output. Leave open for normal use.
TSTPT_4
P14
B1
Test pin 4 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Reserved for TRIG_OUT_1 signal (Output).
TSTPT_5
P15
B1
Test pin 5 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open or unconnected for normal use.
B1
Test pin 6 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
Alternative use: none. External logic shall not unintentionally pull this pin high to avoid putting
the in a test mode.
B1
Test pin 7 (Includes weak internal pulldown) – tri-stated while RESETZ is asserted low.
Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of
RESETZ and then driven as an output.
Normal use: reserved for test output. Leave open for normal use.
TSTPT_6
TSTPT_7
6
N14
N15
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DLPS111 – MARCH 2018
Pin Functions – Parallel Port Input Data and Control (1) (2)
PIN
DESCRIPTION
I/O
NAME
NUMBER
PCLK
P3
I11
Pixel clock (3)
Pixel clock (3)
PDM_CVS_TE
N4
B5
Parallel data mask (4)
Unused (5)
VSYNC_WE
P1
I11
Vsync (6)
Unused (5)
I11
(6)
HSYNC_CS
N5
DATAEN_CMD
P2
I11
PARALLEL RGB MODE
Hsync
Data Valid
BT656 INTERFACE MODE
Unused (5)
(6)
Unused (5)
(TYPICAL RGB 888)
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
K2
K1
L2
L1
M2
M1
N2
N1
PDATA_8
PDATA_9
PDATA_10
PDATA_11
PDATA_12
PDATA_13
PDATA_14
PDATA_15
R1
R2
R3
P4
R4
P5
R5
P6
PDATA_16
PDATA_17
PDATA_18
PDATA_19
PDATA_20
PDATA_21
PDATA_22
PDATA_23
R6
P7
R7
P8
R8
P9
R9
P10
I11
Blue (bit weight 1)
Blue (bit weight 2)
Blue (bit weight 4)
Blue (bit weight 8)
Blue (bit weight 16)
Blue (bit weight 32)
Blue (bit weight 64)
Blue (bit weight 128)
BT656_Data
BT656_Data
BT656_Data
BT656_Data
BT656_Data
BT656_Data
BT656_Data
BT656_Data
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
I11
Green (bit weight 1)
Green (bit weight 2)
Green (bit weight 4)
Green (bit weight 8)
Green (bit weight 16)
Green (bit weight 32)
Green (bit weight 64)
Green (bit weight 128)
Unused
(TYPICAL RGB 888)
3DR
(1)
(2)
(3)
(4)
(5)
(6)
I11
Red (bit weight 1)
Red (bit weight 2)
Red (bit weight 4)
Red (bit weight 8)
Red (bit weight 16)
Red (bit weight 32)
Red (bit weight 64)
Red (bit weight 128)
Unused
3D reference
•
For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the
host when a 3D command is not provided. Must transition in the middle of each frame
(no closer than 1 ms to the active edge of VSYNC)
•
For light control applications: Reserved for trigger in signal (Input). Applicable in Internal
Pattern Streaming Mode only.
•
If a 3D or light control application are not being used (i.e. 3DR input is not being used),
then this input is typically pulled low through an external resister (8 kΩ or less).
N6
PDATA(23:0) bus mapping is pixel format and source mode dependent. See later sections for details.
PDM_CVS_TE is optional for parallel interface operation. Ground unused inputs or pull down to ground through an external resistor (8
kΩ or less).
Pixel clock capture edge is software programmable.
The parallel data mask signal input is optional for parallel interface operations. Ground unused inputs or pull down to ground through an
external resistor (8 kΩ or less).
Ground unused inputs or pull down to ground through an external resistor (8 kΩ or less).
VSYNC, HSYNC, and DATAEN polarity is software programmable.
Pin Functions – DMD Reset and Bias Control
PIN
NAME
NUMBER
I/O
DESCRIPTION
DMD_DEN_ARSTZ
B1
O2
DMD driver enable (active high)/ DMD reset (active low). Assuming the
corresponding I/O power is supplied, this signal is driven low after the DMD is
parked and before power is removed from the DMD. If the 1.8-V power to the is
independent of the 1.8-V power to the DMD, then TI recommends a weak, external
pulldown resistor to hold the signal low in the event power is inactive while DMD
power is applied.
DMD_LS_CLK
A1
O3
DMD, low speed interface clock
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(TYPICAL RGB 888)
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DLPS111 – MARCH 2018
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Pin Functions – DMD Reset and Bias Control (continued)
PIN
NAME
I/O
NUMBER
DESCRIPTION
DMD_LS_WDATA
A2
O3
DMD, low speed serial write data
DMD_LS_RDATA
B2
I6
DMD, low speed serial read data
Pin Functions – DMD Sub-LVDS Interface
PIN
NAME
NUMBER
I/O
DESCRIPTION
ADVANCE INFORMATION
DMD_HS_CLK_P
DMD_HS_CLK_N
A7
B7
O4
DMD high speed interface
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
A3
B3
A4
B4
A5
B5
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11
O4
DMD high speed interface lanes, write data bits: (The true numbering and
application of the DMD_HS_DATA pins are software configuration dependent)
8
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DLPS111 – MARCH 2018
PIN
NAME
NUMBER
I/O
DESCRIPTION
CMP_OUT
A12
I6
Successive approximation ADC comparator output ( Input). Assumes a successive approximation ADC
is implemented with a WPC light sensor and/or a thermistor feeding one input of an external
comparator and the other side of the comparator is driven from the ASIC’s CMP_PWM pin. Typically
pulled-down to ground if this function is not used. (hysteresis buffer)
CMP_PWM
A15
O1
Successive approximation comparator pulse-duration modulation (output). Supplies a PWM signal to
drive the successive approximation ADC comparator used in WPC light-to-voltage sensor applications.
Leave unconnected if this function is not used.
O9
Host interrupt (output)
HOST_IRQ indicates when the auto-initialization is in progress and most importantly when it
completes.
The tri-states this output during reset and assumes that an external pullup is in place to drive this
signal to its inactive state.
HOST_IRQ
(2)
N8
IIC0_SCL
N10
B7
I2C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis): An external pullup is
required. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF
(which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply
voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH
specification of the slave I2C input buffers).
Reserved
R11
B8
TI internal use. TI recommends an external pullup resistor.
IIC0_SDA
N9
B7
I2C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): An external pullup is
required. The slave I2C port is the control port of ASIC. The slave I2C I/Os are 3.6-V tolerant (high-voltinput tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups
must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup
supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers).
Reserved
R10
B8
TI internal use. TI recommends an external pullup resistor.
LED enable select. Controlled by programmable DMD sequence
Timing
LED_SEL(1:0)
00
01
10
11
Enabled LED
DLPA200x / DLPA3000 application
None
Red
Green
Blue
LED_SEL_0
B15
O1
LED_SEL_1
B14
O1
These signals are driven low when RESETZ is asserted and the corresponding I/O power is supplied
and continues throughout the auto-initialization process. A weak, external pulldown resistor is still
recommended to ensure that the LEDs are disabled when I/O power is not applied.
SPI0_CLK
A13
O13
Synchronous serial port 0, clock
SPI0_CSZ0
A14
O13
SPI port 1, chip select 0 (active low output)
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during
ASIC reset assertion.
SPI0_CSZ1
C12
O13
SPI port 1, chip select 1 (active low output)
TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during
ASIC reset assertion.
SPI0_DIN
B12
I12
Synchronous serial port 0, receive data in
SPI0_DOUT
B13
O13
Synchronous serial port 0, transmit data out
(1)
(2)
External pullup resistor must be 8 kΩ or less.
For more information about usage, see HOST_IRQ Usage Model.
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Pin Functions – Peripheral Interface (1)
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DLPS111 – MARCH 2018
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Pin Functions – GPIO Peripheral Interface (1)
PIN
NAME
NUMBER
GPIO_19
GPIO_18
GPIO_17
ADVANCE INFORMATION
GPIO_16
M15
M14
L15
L14
I/O
DESCRIPTION (2)
B1
General purpose I/O 19 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
2. MTR_SENSE, Motor Sense (Input): For Focus Motor control applications, this GPIO must be
configured as an input to the fed from the focus motor position sensor.
3. KEYPAD_4 (input): keypad applications
B1
General purpose I/O 18 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input)
2. KEYPAD_3 (input): keypad applications
B1
General purpose I/O 17 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
2. KEYPAD_2 (input): keypad applications
B1
General purpose I/O 16 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
2. KEYPAD_1 (input): keypad applications
GPIO_15
K15
B1
General purpose I/O 15 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
2. KEYPAD_0 (input): keypad applications
GPIO_14
K14
B1
General purpose I/O 14 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 13 (hysteresis buffer). Options:
1. CAL_PWR (output): Intended to feed the calibration control of the successive approximation ADC
light sensor.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 12 (hysteresis buffer). Options:
1. (Output) power enable control for LABB light sensor.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 11 (hysteresis buffer). Options:
1. (Output): thermistor power enable.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General Purpose I/O 10 (hysteresis buffer). Options:
1. RC_CHARGE (output): Intended to feed the RC charge circuit of the successive approximation ADC
used to control the light sensor comparator.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 09 (hysteresis buffer). Options:
1. LS_PWR (active high output): Intended to feed the power control signal of the successive
approximation ADC light sensor.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_09
(1)
(2)
10
J15
J14
H15
H14
G15
GPIO signals must be configured through software for input, output, bidirectional, or open-drain. Some GPIO have one or more
alternative use modes, which are also software configurable. The reset default for all GPIO is as an input signal. An external pullup is
required for each signal configured as open-drain.
general purpose I/O. These GPIO are software configurable.
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PIN
NAME
NUMBER
GPIO_08
I/O
DESCRIPTION (2)
B1
General purpose I/O 08 (hysteresis buffer). Options:
1. (All) Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A
logic low on this signal causes the to ASIC to PARK the DMD, but it does not power down the DMD
(the DLPA200x performs that function). The minimum high time is 200 ms. The minimum low time is
also 200 ms.
B1
General purpose I/O 07 (hysteresis buffer). Options:
1. (Output): LABB output sample and hold sensor control signal.
2. Light Control: Reserved for TRIG_OUT_2 signal (Output).
3. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
G14
GPIO_07
F15
GPIO_06
F14
B1
General purpose I/O 06 (hysteresis buffer). Option:
1. Light Control: Reserved for pattern ready signal (Output). Applicable in Internal Pattern Streaming
Mode only.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_05
E15
B1
General purpose I/O 05 (hysteresis buffer). Options:
1. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 04 (hysteresis buffer). Options:
1. 3D glasses control (output): intended to be used to control the shutters on 3D glasses (Left = 1, Right
= 0).
2. SPI1_CSZ1 (active-low output): optional SPI1 chip select 1 signal. An external pullup resistor is
required to deactivate this signal during reset and auto-initialization processes.
3. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 03 (hysteresis buffer). Options:
1. SPI1_CSZ0 (active low output): Optional SPI1 chip select 0 signal. An external pullup resistor is
required to deactivate this signal during reset and auto-initialization processes.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 02 (hysteresis buffer). Options:
1. SPI1_DOUT (output): Optional SPI1 data output signal.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 01 (hysteresis buffer). Options:
1. SPI1_CLK (output): Optional SPI1 clock signal.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
B1
General purpose I/O 00 (hysteresis buffer). Options:
1. SPI1_DIN (input): Optional SPI1 data input signal.
2. Optional GPIO. Configure as a logic zero GPIO output and leave unconnected if not used (otherwise
this pin requires an external pullup or pulldown component to avoid a floating GPIO input).
GPIO_04
E14
GPIO_03
D15
GPIO_02
D14
GPIO_01
C15
GPIO_00
C14
Pin Functions – Clock and PLL Support
PIN
NAME
NUMBER
I/O
DESCRIPTION
PLL_REFCLK_I
H1
I11
Reference clock crystal input. If the application uses an external oscillator instead of a crystal,
use this pin as the oscillator input.
PLL_REFCLK_O
J1
O5
Reference clock crystal return. If the application uses an external oscillator instead of a crystal,
leave this pin unconnected (floating with no added capacitive load).
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ADVANCE INFORMATION
Pin Functions – GPIO Peripheral Interface(1) (continued)
DLPC3478
DLPS111 – MARCH 2018
www.ti.com
Pin Functions – Power and Ground (1)
PIN
NAME
I/O
NUMBER
DESCRIPTION
ADVANCE INFORMATION
VDD
C5, D5, D7, D12, J4, J12, K3, L4, L12, M6,
M9, D9, D13, F13, H13, L13, M10, D3, E3
PWR
Core power 1.1 V (main 1.1 V)
VDDLP12
C3
PWR
Reserved
VSS
Common to all package types
C4, D6, D8, D10, E4, E13, F4, G4, G12, H4,
H12, J3, J13, K4, K12, L3, M4, M5, M8, M12,
G13, C6, C8
Only available on
F6, F7, F8, F9, F10, G6, G7, G8, G9, G10,
H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6,
K7, K8, K9, K10
GND
Core ground (eDRAM, I/O ground, thermal ground)
VCC18
C7, C9, D4, E12, F12, K13, M11
PWR
All 1.8-V I/O power:
(1.8-V power supply for all I/O other than the host or parallel
interface and the SPI flash interface. This includes RESETZ,
PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins)
VCC_INTF
M3, M7, N3, N7
PWR
Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0,
PDATA, video syncs, and HOST_IRQ pins)
VCC_FLSH
D11
PWR
Flash interface I/O power:1.8 to 3.3 V
(Dedicated SPI0 power pin)
VDD_PLLM
H2
PWR
MCG PLL 1.1-V power
VSS_PLLM
G3
RTN
MCG PLL return
VDD_PLLD
J2
PWR
DCG PLL 1.1-V power
VSS_PLLD
H3
RTN
DCG PLL return
(1)
12
The only power sequencing restrictions are:
(a) The VDD supply typically ramps up with a 1-ms minimum rise time.
(b) The reverse is needed at power down.
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Table 1. I/O Type Subscript Definition
I/O
SUBSCRIPT
DESCRIPTION
SUPPLY REFERENCE
ESD STRUCTURE
1
1.8 LVCMOS I/O buffer with 8-mA drive
Vcc18
ESD diode to GND and supply rail
2
1.8 LVCMOS I/O buffer with 4-mA drive
Vcc18
ESD diode to GND and supply rail
3
1.8 LVCMOS I/O buffer with 24-mA drive
Vcc18
ESD diode to GND and supply rail
4
1.8 sub-LVDS output with 4-mA drive
Vcc18
ESD diode to GND and supply rail
5
1.8, 2.5, 3.3 LVCMOS with 4-mA drive
Vcc_INTF
ESD diode to GND and supply rail
6
1.8 LVCMOS input
Vcc18
ESD diode to GND and supply rail
7
1.8-, 2.5-, 3.3-V I2C with 3-mA drive
Vcc_INTF
ESD diode to GND and supply rail
2
1.8-V I C with 3-mA drive
Vcc18
ESD diode to GND and supply rail
9
1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive
Vcc_INTF
ESD diode to GND and supply rail
11
1.8, 2.5, 3.3 LVCMOS input
Vcc_INTF
ESD diode to GND and supply rail
12
1.8-, 2.5-, 3.3-V LVCMOS input
Vcc_FLSH
ESD diode to GND and supply rail
13
1.8-, 2.5-, 3.3-V LVCMOS with 8-mA drive
Vcc_FLSH
ESD diode to GND and supply rail
ADVANCE INFORMATION
8
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DLPC3478
DLPS111 – MARCH 2018
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
MIN
MAX
UNIT
V(VDD) (core)
–0.3
1.21
V
V(VDDLP12) (core)
–0.3
1.32
V
Power + sub-LVDS
–0.3
1.96
V
Host I/O power
–0.3
3.60
If 1.8-V power used
–0.3
1.99
If 2.5-V power used
–0.3
2.75
If 3.3-V power used
–0.3
3.60
Flash I/O power
–0.3
3.60
If 1.8-V power used
–0.3
1.96
If 2.5-V power used
–0.3
2.72
If 3.3-V power used
SUPPLY VOLTAGE (2) (3)
V(VCC_INTF)
V(VCC_FLSH)
V
V
ADVANCE INFORMATION
–0.3
3.58
V(VDD_PLLM) (MCG PLL)
–0.3
1.21
V
V(VDD_PLLD) (1DCG PLL)
–0.3
1.21
V
GENERAL
TJ
Operating junction temperature
–30
125
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended
operating conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Overlap currents, if allowed to continue flowing unchecked, not only increase total power dissipation in a circuit, but degrade the circuit
reliability, thus shortening its usual operating life.
6.2 ESD Ratings
VALUE
V(ESD) (1)
(1)
(2)
(3)
14
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3)
±500
UNIT
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
NOM
MAX
UNIT
Core power 1.1 V (main 1.1 V)
±5% tolerance
1.045
1.1
1.155
V
V(VDDLP12)
Reserved
±5% tolerance
See (1) (2)
1.045
1.10
1.155
V
V(VCC18)
All 1.8-V I/O power:
(1.8-V power supply for all I/O other than the host or
parallel interface and the SPI flash interface. This
includes RESETZ, PARKZ LED_SEL, CMP, GPIO,
IIC1, TSTPT, and JTAG pins.)
±8.5% tolerance
1.64
1.8
1.96
V
Host or parallel interface I/O power: 1.8 to 3.3 V
(includes IIC0, PDATA, video syncs, and HOST_IRQ
pins)
1.64
1.8
1.96
V(VCC_INTF)
±8.5% tolerance
See (3)
2.28
2.5
2.72
3.02
3.3
3.58
1.64
1.8
1.96
Flash interface I/O power:1.8 to 3.3 V
±8.5% tolerance
See (3)
2.28
2.5
2.72
3.02
3.3
3.58
V(VCC_FLSH)
V
V
V(VDD_PLLM)
MCG PLL 1.1-V power
±9.1% tolerance
See (4)
1.025
1.1
1.155
V
V(VDD_PLLD)
DCG PLL 1.1-V power
±9.1% tolerance
See (4)
1.025
1.1
1.155
V
TA
Operating ambient temperature range (5)
–30
85
°C
TJ
Operating junction temperature
–30
105
°C
(1)
(2)
(3)
(4)
(5)
It is recommended that VDDLP12 rail is tied to the VDD rail.
If the VDDLP12 is fed from a separate (from VDD) supply, the VDDLP12 power must sequence ON after the 1.1V core supply and must
sequence OFF before the 1.1V core supply.
These supplies have multiple valid ranges.
These I/O supply ranges are wider to facilitate additional filtering.
The operating ambient temperature range assumes 0 forced air flow, a JEDEC JESD51 junction-to-ambient thermal resistance value at
0 forced air flow (RθJA at 0 m/s), a JEDEC JESD51 standard test card and environment, along with min and max estimated power
dissipation across process, voltage, and temperature. Thermal conditions vary by application, which affects the value of RθJA. Thus,
maximum operating ambient temperature varies by application.
(a) Ta_min = Tj_min – (Pd_min × RθJA) = –30°C – (0.0W × 30.3°C/W) = –30°C
(b) Ta_max = Tj_max – (Pd_max × RθJA) = +105°C – (0.348W × 30.3°C/W) = +94.4°C
6.4 Thermal Information
DLPC3478
THERMAL METRIC (1)
ZEZ (NFBGA)
UNIT
201 PINS
RθJC
Junction-to-case thermal resistance
10.1
°C/W
(2)
28.8
°C/W
at 1 m/s of forced airflow (2)
25.3
°C/W
at 2 m/s of forced airflow (2)
24.4
°C/W
.23
°C/W
at 0 m/s of forced airflow
RθJA
ψJT (3)
(1)
(2)
(3)
Junction-to-air thermal
resistance
Temperature variance from junction to package top center
temperature, per unit power dissipation
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Thermal coefficients abide by JEDEC Standard 51. RθJA is the thermal resistance of the package as measured using a JEDEC defined
standard test PCB. This JEDEC test PCB is not necessarily representative of the DLPC3478 PCB and thus the reported thermal
resistance may not be accurate in the actual product application. Although the actual thermal resistance may be different , it is the best
information available during the design phase to estimate thermal performance.
Example: (0.5 W) × (0.2 C/W) ≈ 1.00°C temperature rise.
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ADVANCE INFORMATION
V(VDD)
MIN
DLPC3478
DLPS111 – MARCH 2018
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6.5 Electrical Characteristics over Recommended Operating Conditions
TEST CONDITIONS (5) (6)
PARAMETER
V(VDD) +
V(VDDLP12)
Core current 1.1 V (main 1.1 V)
V(VDD_PLLM)
MCG PLL 1.1 V current
V(VDD_PLLD)
DCG PLL 1.1 V current
V(VDD) +
Core Current 1.1 V + MCG PLL 1.1 V
V(VDD_PLLM)
current + DCG PLL 1.1 V current
+ V(VDD_PLLD)
V(VCC18)
Main 1.8 V I/O current: 1.8 V power
supply for all I/O other than the host or
parallel interface and the SPI flash
interface.
TYP (7)
MAX (8)
IDLE disabled, 720p, 60 Hz
161
334
IDLE disabled, 720p, 120 Hz
185
368
IDLE disabled, 720p, 60 Hz
4
7
IDLE disabled, 720p, 120 Hz
4
7
IDLE disabled, 720p, 60 Hz
4
7
IDLE disabled, 720p, 120 Hz
4
7
IDLE disabled, 720p, 60 Hz
169
348
IDLE disabled, 720p, 120 Hz
193
382
IDLE disabled, 720p, 60 Hz
13
18
ADVANCE INFORMATION
SPACE
IDLE disabled, 720p, 120 Hz
V(VCC_INTF)
Host or parallel interface I/O current:
1.8 to 3.3 V ( includes IIC0, PDATA,
video syncs, and HOST_IRQ pins)
V(VCC_FLSH)
Flash interface I/O current: 1.8 to 3.3 V
V(VCC18) +
V(VCC_INTF) +
V(VCC_FLSH)
Main 1.8 V I/O current + VCC_INTF
current + VCC_FLSH current
16
MIN
UNIT
mA
mA
mA
mA
mA
This includes sub-LVDS DMD I/O ,
RESETZ, PARKZ, LED_SEL, CMP,
GPIO, IIC1, TSTPT and JTAG pins
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1) (2) (3) (4)
13
18
IDLE disabled, 720p, 60 Hz
2
3
IDLE disabled, 720p, 120 Hz
4
6
IDLE disabled, 720p, 60 Hz
1
1.5
IDLE disabled, 720p, 120 Hz
1
1.5
IDLE disabled, 720p, 60 Hz
16
22.5
IDLE disabled, 720p, 120 Hz
18
25.5
SPACE
mA
mA
mA
Assumes 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT or HVT cells
Programmable host and flash I/O are at minimum voltage (that is 1.8 V) for this typical scenario.
Max currents column use typical motion video as the input. The typical currents column uses SMPTE color bars as the input.
Some applications (that is, high-resolution 3D) may be forced to use 1-oz copper to manage ASIC package heat.
Input image is 1280 × 720 (720p) 24-bits on the parallel interface at the frame rate shown with a 0.3-inch 720p DMD.
In normal operation while displaying an image with CAIC enabled.
Assumes typical case power PVT condition = nominal process, typical voltage, typical temperature (55°C junction). 720p resolution.
Assumes worse case power PVT condition = corner process, high voltage, high temperature (105°C junction), 720p resolution.
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DLPS111 – MARCH 2018
6.6 Electrical Characteristics (1) (2)
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
2
MIN
0.7 × VCC_INTF
1.17
3.6
1.8-V LVTTL (I/O type 1, 6)
identified below: (2)
CMP_OUT; PARKZ; RESETZ;
GPIO 0 →19
1.3
3.6
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
1.7
3.6
3.3-V LVTTL (I/O type 5, 9, 11,
12, 13)
2
3.6
I2C buffer (I/O type 7)
–0.5
0.3 × VCC_INTF
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
–0.3
0.63
1.8-V LVTTL (I/O type 1, 6)
identified below: (2)
CMP_OUT; PARKZ; RESETZ;
GPIO_00 through GPIO_19
–0.3
0.5
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
–0.3
0.7
3.3-V LVTTL (I/O type 5, 9, 11,
12, 13)
–0.3
0.8
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
VIH
Low-level
input
threshold
voltage
VIL
VCM
Steady-state
1.8 sub-LVDS (DMD high speed)
common
(I/O type 4)
mode voltage
ǀVODǀ
Differential
output
magnitude
VOH
High-level
output
voltage
0.8
1.8 sub-LVDS (DMD high speed)
(I/O type 4)
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
1.35
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
1.7
3.3-V LVTTL (I/O type 5, 9, 11,
12, 13)
2.4
2
I C buffer (I/O type 7)
V
V
mV
mV
V
VCC_INTF > 2 V
0.4
VCC_INTF < 2 V
0.2 × VCC_INTF
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
0.45
2.5 V LVTTL (I/O type 5, 9, 11,
12, 13)
0.7
3.3 V LVTTL (I/O type 5, 9, 11,
12, 13)
0.4
1.8 sub-LVDS – DMD high
speed (I/O type 4)
(1)
(2)
(3)
1
UNIT
1
I2C buffer (I/O type 7)
VOL
0.9
200
1.8 sub-LVDS – DMD high
speed (I/O type 4)
Low-level
output
voltage
MAX
(1)
I C buffer (I/O type 7)
High-level
input
threshold
voltage
TYP
ADVANCE INFORMATION
PARAMETER (3)
V
0.8
I/O is high voltage tolerant; that is, if VCC = 1.8 V, the input is 3.3-V tolerant, and if VCC = 3.3 V, the input is 5-V tolerant.
ASIC pins: CMP_OUT; PARKZ; RESETZ; GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V I/O.
The number inside each parenthesis for the I/O refers to the type defined in Table 1.
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Electrical Characteristics(1)(2) (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER (3)
IOH
High-level
output
current
TEST CONDITIONS
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
4 mA
2
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
8 mA
3.5
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
24 mA
10.6
2.5-V LVTTL (I/O type 5)
4 mA
5.4
2.5-V LVTTL (I/O type 9, 13)
8 mA
10.8
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
24 mA
28.7
3.3-V LVTTL (I/O type 5 )
4 mA
7.8
3.3-V LVTTL (I/O type 9, 13)
8 mA
15
I2C buffer (I/O type 7)
ADVANCE INFORMATION
IOL
IOZ
Low-level
output
current
Highimpedance
leakage
current
MIN
Input
capacitance
(including
package)
UNIT
mA
3
4 mA
2.3
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
8 mA
4.6
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
24 mA
13.9
2.5-V LVTTL (I/O type 5)
4 mA
5.2
2.5-V LVTTL (I/O type 9, 13)
8 mA
10.4
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
24 mA
31.1
3.3-V LVTTL (I/O type 5 )
4 mA
4.4
3.3-V LVTTL (I/O type 9, 13)
8 mA
8.9
I2C buffer (I/O type 7)
0.1 × VCC_INTF < VI
< 0.9 × VCC_INTF
–10
10
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
–10
10
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
–10
10
3.3-V LVTTL (I/O type 5, 9, 11,
12, 13)
–10
10
mA
µA
5
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
2.6
3.5
2.5-V LVTTL (I/O type 5, 9, 11,
12, 13)
2.6
3.5
3.3-V LVTTL (I/O type 5, 9, 11,
12, 13)
2.6
3.5
1.8 sub-LVDS – DMD high
speed (I/O type 4)
18
MAX
1.8-V LVTTL (I/O type 1, 2, 3, 5,
6, 8, 9, 11, 12, 13)
I2C buffer (I/O type 7)
CI
TYP
pF
3
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Table 2. Internal Pullup and Pulldown Characteristics (1) (2)
INTERNAL PULLUP AND PULLDOWN RESISTOR
CHARACTERISTICS
Weak pullup resistance
Weak pulldown resistance
MIN
MAX
UNIT
3.3 V
29
63
kΩ
2.5 V
38
90
kΩ
1.8 V
56
148
kΩ
3.3 V
30
72
kΩ
2.5 V
36
101
kΩ
1.8 V
52
167
kΩ
The resistance is dependent on the supply voltage level applied to the I/O.
An external 8-kΩ pullup or pulldown (if needed) would work for any voltage condition to correctly pull enough to override any associated
internal pullups or pulldowns.
ADVANCE INFORMATION
(1)
(2)
VCCIO
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6.7 High-Speed Sub-LVDS Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
0.8
0.9
1.0
V
75
mV
10
mV
VCM
Steady-state common mode voltage
VCM (Δpp) (1)
VCM change peak-to-peak (during switching)
VCM (Δss) (1)
VCM change steady state
|VOD| (2)
Differential output voltage magnitude
VOD (Δ)
VOD change (between logic states)
VOH
Single-ended output voltage high
1.00
V
VOL
Single-ended output voltage low
0.80
V
tR
(2)
–10
200
–10
mV
10
mV
Differential output rise time
250
tF (2)
Differential output fall time
250
ps
tMAX
Max switching rate
1200
Mbps
DCout
Output duty cycle
45%
50%
55%
Txterm (1)
Internal differential termination
80
100
120
Txload
100-Ω differential PCB trace
(50-Ω transmission lines)
0.5
6
ps
Ω
inches
ADVANCE INFORMATION
Vcm
Vcm(ûss)
(1)
(2)
Vcm(ûpp)
Definition of VCM changes:
\
Note that VOD is the differential voltage swing measured across a 100-Ω termination resistance connected directly between the
transmitter differential pins. |VOD| is the magnitude of this voltage swing relative to 0. Rise and fall times are defined for the differential
80%
tF
tR
+ Vod
|Vod|
Vod
0V
|Vod|
20%
- Vod
Differential Output Signal
VOD signal as follows:
20
(Note Vcm is removed when the signals are viewed differentially)
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6.8 Low-Speed SDR Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ID
TEST CONDITIONS
MIN
MAX
UNIT
1.64
1.96
V
Operating voltage
VCC18 (all signal groups)
DC input high voltage
VIHD(DC)
Signal group 1
All
0.7 × VCC18
VCC18 + 0.5
V
DC input low voltage (1)
VILD(DC)
Signal group 1
All
–0.50
0.3 × VCC18
V
AC input high voltage (2)
VIHD(AC)
Signal group 1
All
0.8 × VCC18
VCC18 + 0.5
V
AC input low voltage
VILD(AC)
Signal group 1
All
–0.5
0.2 × VCC18
V
Signal group 1
1
3.0
Signal group 2
0.25
Signal group 3
0.5
Slew rate
V/ns
VILD(AC) min applies to undershoot.
VIHD(AC) max applies to overshoot.
Signal group 1 output slew rate for rising edge is measured between VILD(DC) to VIHD(AC).
Signal group 1 output slew rate for falling edge is measured between VIHD(DC) to VILD(AC).
Signal group 1: See Figure 1.
Signal groups 2 and 3 output slew rate for rising edge is measured between VILD(AC) to VIHD(AC).
ADVANCE INFORMATION
(1)
(2)
(3)
(4)
(5)
(6)
(3) (4) (5) (6)
Figure 1. Low Speed (LS) I/O Input Thresholds
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6.9 System Oscillators Timing Requirements (1)
MIN
MAX
UNIT
ƒclock
Clock frequency, MOSC (2)
24-MHz oscillator
23.998
24.002
MHz
tc
Cycle time, MOSC (2)
24-MHz oscillator
41.670
41.663
ns
tw(H)
Pulse duration (3), MOSC, high
50% to 50% reference points (signal)
40 tc%
tw(L)
Pulse duration (3), MOSC, low
50% to 50% reference points (signal)
40 tc%
tt
Transition time (3), MOSC, tt = tƒ / tr
20% to 80% reference points (signal)
tjp
Long-term, peak-to-peak, period jitter (3), MOSC
(that is the deviation in period from ideal period due solely to high frequency jitter)
(1)
(2)
(3)
10
ns
2%
The I/O pin TSTPT_6 must be left open for 24 MHz timing to work properly inside the DLPC3478.
The frequency accuracy for MOSC is ±200 PPM. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.) The
MOSC input cannot support spread spectrum clock spreading.
Applies only when driven through an external digital oscillator.
tw(H)
MOSC
tt
tt
tc
tw(L)
50%
50%
80%
80%
20%
20%
50%
ADVANCE INFORMATION
Figure 2. System Oscillators
6.10 Power-Up and Reset Timing Requirements
NUMBER
(1)
MIN
1
tw(L)
Pulse duration, inactive low, RESETZ 50% to 50% reference points (signal)
2
tt
Transition time, RESETZ (1), tt = tƒ / tr
MAX
1.25
UNIT
µs
20% to 80% reference points (signal)
0.5
µs
For more information on RESETZ, see Pin Configuration and Functions.
DC Power
Supplies
tt
80%
50%
20%
RESETZ
tw(L)
tt
80%
50%
20%
80%
50%
20%
80%
50%
20%
tw(L)
tw(L)
Figure 3. Power-Up and Power-Down RESETZ Timing
22
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6.11 Parallel Interface Frame Timing Requirements
MAX
UNIT
Pulse duration – VSYNC_WE high
50% reference points
1
lines
tp_vbp
Vertical back porch (VBP) – time from the leading edge of
50% reference points
VSYNC_WE to the leading edge HSYNC_CS for the first active
line (see (1))
2
lines
tp_vƒp
Vertical front porch (VFP) – time from the leading edge of the
HSYNC_CS following the last active line in a frame to the
leading edge of VSYNC_WE (see (1))
50% reference points
1
lines
tp_tvb
Total vertical blanking – time from the leading edge of
HSYNC_CS following the last active line of one frame to the
leading edge of HSYNC_CS for the first active line in the next
frame. (This is equal to the sum of VBP (tp_vbp) + VFP (tp_vfp).)
50% reference points
(1)
lines
tp_hsw
Pulse duration – HSYNC_CS high
50% reference points
4
tp_hbp
Horizontal back porch – time from rising edge of HSYNC_CS
to rising edge of DATAEN_CMD
50% reference points
4
PCLKs
tp_hfp
Horizontal front porch – time from falling edge of
DATAEN_CMD to rising edge of HSYNC_CS
50% reference points
8
PCLKs
tp_thb
Total horizontal blanking – sum of horizontal front and back
porches
50% reference points
(2)
PCLKs
(1)
(2)
See
See
128
PCLKs
The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [8 × Max(1, Source_ALPF/ DMD_ALPF)] lines
where:
(a) SOURCE_ALPF = Input source active lines per frame
(b) DMD_ALPF = Actual DMD used lines per frame supported
The maximum line rate for a given source (which is a function of resolution and orientation) drives total horizontal blanking. Use this
equation: tp_thb = Roundup[(1000 × ƒclock)/ LR] – APPL
where:
(a) ƒclock = Pixel clock rate in MHz
(b) LR = Line rate in kHz
(c) APPL is the number of active pixels per (horizontal) line.
(d) If tp_thb is calculated to be less than tp_hbp + tp_hfp then the pixel clock rate is too low or the line rate is too high, and one or both
must be adjusted.
1 Frame
tp_vsw
VSYNC_WE
(This diagram assumes the VSYNC
active edge is the rising edge)
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
1 Line
tp_hsw
HSYNC_CS
tp_hbp
(This diagram assumes the HSYNC
active edge is the rising edge)
tp_hfp
DATAEN_CMD
P0
PDATA(23/15:0)
P1
P2
P3
P
n-2
P
n-1
Pn
PCLK
Figure 4. Parallel Interface Frame Timing
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ADVANCE INFORMATION
MIN
tp_vsw
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6.12 Parallel Interface General Timing Requirements (1)
MIN
MAX
UNIT
1.0
150.0
MHz
6.66
1000
ns
ƒclock
Clock frequency, PCLK
tp_clkper
Clock period, PCLK
50% reference points
tp_clkjit
Clock jitter, PCLK
Max ƒclock
tp_wh
Pulse duration low, PCLK
50% reference points
2.43
ns
tp_wl
Pulse duration high, PCLK
50% reference points
2.43
ns
tp_su
Setup time – HSYNC_CS, DATEN_CMD,
PDATA(23:0) valid before the active edge of PCLK
50% reference points
0.9
ns
tp_h
Hold time – HSYNC_CS, DATEN_CMD,
PDATA(23:0) valid after the active edge of PCLK
50% reference points
0.9
ns
tt
Transition time – all signals
20% to 80% reference
points
0.2
(1)
(2)
see
(2)
see
(2)
2.0
ns
The active (capture) edge of PCLK for HSYNC_CS, DATEN_CMD and PDATA(23:0) is software programmable, but defaults to the
rising edge.
Clock jitter (in ns) calculation: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met during clock jitter.
tp_clkper
ADVANCE INFORMATION
tp_wh
tp_wl
PCLK
tp_su
tp_h
Figure 5. Parallel Interface General Timing
24
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6.13 BT656 Interface General Timing Requirements (1)
The DLPC3478 ASIC input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITUR BT.656 specification for detailed interface timing requirements.
MIN
MAX
UNIT
1.0
33.5
MHz
1,000
ns
ƒclock
Clock frequency, PCLK
tp_clkper
Clock period, PCLK
50% reference points
tp_clkjit
Clock jitter, PCLK
Max ƒclock
tp_wh
Pulse duration low, PCLK
50% reference points
10.0
ns
tp_wl
Pulse duration high, PCLK
50% reference points
10.0
ns
tp_su
Setup time – PDATA(7:0) before the active edge of
PCLK
50% reference points
3.0
ns
tp_h
Hold time – PDATA(7:0) after the active edge of
PCLK
50% reference points
0.9
ns
tt
Transition time – all signals
20% to 80% reference points
0.2
(2)
(2)
See
(2)
3.0
ns
The BT.656 interface accepts 8-bits per color, 4:2:2 YCb/Cr data encoded per the industry standard through PDATA(7:0) on the active
edge of PCLK (that is programmable). See Figure 6.
Clock jitter calculation: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met during clock jitter.
BT.656 Bus Mode t YCrCb 4:2:2 Source
PDATA(23:0) t BT.656 Mapping
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
n/a
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
PDATA(7:0) of the Input Pixel data bus
Bus Assignment Mapping
n/a
n/a
A.
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Data bit mapping on the pins of the ASIC
BT.656 data bits map to the DLPC3478 PDATA bus as shown.
Figure 6. DLPC3478 PDATA Bus – BT.656 Interface Mode Bit Mapping
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ADVANCE INFORMATION
(1)
29.85
See
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6.14 Flash Interface Timing Requirements (1) (2)
The DLPC3478 ASIC flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The
DLPC3478 can support 1- to 16-Mb flash memories.
MIN
MAX
UNIT
1.42
36.0
MHz
50% reference points
704
27.7
ns
50% reference points
352
Pulse duration high, SPI_CLK
50% reference points
352
tt
Transition time – all signals
20% to 80% reference
points
0.2
tp_su
Setup time – SPI_DIN valid before SPI_CLK falling
edge
50% reference points
10.0
tp_h
Hold time – SPI_DIN valid after SPI_CLK falling edge
50% reference points
0.0
tp_clqv
SPI_CLK clock falling edge to output valid time –
SPI_DOUT and SPI_CSZ
50% reference points
tp_clqx
SPI_CLK clock falling edge output hold time –
SPI_DOUT and SPI_CSZ
50% reference points
ƒclock
Clock frequency, SPI_CLK
See
tp_clkper
Clock period, SPI_CLK
tp_wh
Pulse duration low, SPI_CLK
tp_wl
ADVANCE INFORMATION
(1)
(2)
(3)
(3)
–3.0
ns
ns
3.0
ns
ns
ns
1.0
ns
3.0
ns
Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3478 does
transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI
devices with long clock-to-Q timing. DLPC3478 hold capture timing has been set to facilitate reliable operation with standard external
SPI protocol devices.
With the above output timing, DLPC3478 provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the rising
edge of SPI_CLK.
This range includes the 200 ppm of the external oscillator (but no jitter).
tclkper
SPI_CLK
(ASIC Output)
twh
twl
tp_su
tp_h
SPI_DIN
(ASIC Inputs)
tp_clqv
SPI_DOUT, SPI_CS(1:0)
(ASIC Outputs)
tp_clqx
Figure 7. Flash Interface Timing
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7 Parameter Measurement Information
7.1 HOST_IRQ Usage Model
•
•
•
While reset is applied, HOST_IRQ resets to tri-state (an external pullup pulls the line high).
HOST_IRQ remains in tri-state (pulled high externally) until the microprocessor boot completes. While the
signal is pulled high, this indicates that the ASIC is performing boot-up and auto-initialization.
As soon as possible after boot-up, the microprocessor drives HOST_IRQ to a logic-high state to indicate that
the ASIC is continuing to perform auto-initialization (no real state change occurs on the external signal)
Upon completion of auto-initialization, software sets HOST_IRQ to a logic low state to indicate the completion
of auto-initialization. (At the falling edge, the system enters the INIT_DONE state.)
The 500-ms maximum period from the rising edge of RESETZ to the falling edge of HOST_IRQ may become
longer than 500 ms if many commands are added to the autoinit batch file in flash which automatically runs at
power up.
RESETZ
500 ms (max)
HOST_IRQ
(with external pullup)
(INIT_BUSY)
ADVANCE INFORMATION
•
•
0 ms (min)
t1 t2
t1 is the first falling edge of HOST_IRQ, At this point the auto-initiation sequence is complete.
t2 is where HOST_IRQ goes low. Ensure that I2C interface to the device does not begin until this point (within 500 ms
of the release of RESETZ)
Figure 8. Host IRQ Timing
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7.2 Input Source
Table 3. Supported Input Source Ranges (1) (2) (3) (4)
SOURCE RESOLUTION RANGE (6)
INTERFACE
HORIZONTAL
FRAME RATE
RANGE
VERTICAL
Landscape
Portrait
Landscape
Portrait
24 max
2D only
320 to 1280
200 to 800
200 to 800
320 to 1280
10 to 122 Hz
24 max
3D only
320 to 1280
200 to 720
200 to 720
320 to 1280
98 to 102 Hz
118 to 122 Hz
See
(8)
2D only
720
n/a
240
n/a
60 ±2 Hz
See
(8)
2D only
720
n/a
288
n/a
50 ±2 Hz
BT.656-PAL
ADVANCE INFORMATION
(7)
(8)
IMAGE TYPE
Parallel
(7)
(6)
(5)
Parallel
BT.656-NTSC
(1)
(2)
(3)
(4)
(5)
BITS / PIXEL
(7)
The user must stay within specifications for all source interface parameters such as max clock rate and max line rate.
The max DMD size for all rows in the table is 1280 × 720.
To achieve the ranges stated, the composer-created firmware used must be defined to support the source parameters used.
These interfaces are supported with the DMD sequencer sync mode command (3Bh) set to auto.
Bits / Pixel does not necessarily equal the number of data pins used on the DLPC3478. Fewer pins are used if multiple clocks are used
per pixel transfer.
By using an I2C command, portrait image inputs can be rotated on the DMD by minus 90 degrees so that the image is displayed in
landscape format.
All parameters in this row follow the BT.656 standard. The image format is always landscape.
BT.656 uses 16-bit 4:2:2 YCr/Cb.
7.2.1 Input Source - Frame Rates and 3-D Display Orientation
For 3D sources on the parallel interface, images must be frame sequential (L, R, L, ...) when input to the
DLPC3478. Any processing required to unpack 3D images and to convert them to frame sequential must be
done by external electronics prior to inputting the images to the DLPC3478. Each 3D source frame input must
contain a single eye frame of data separated by a VSYNC where an eye frame contains image data for a single
left or right eye. The signal 3DR input to the DLPC3478 tells whether the input frame is for the left eye or right
eye.
Each DMD frame displays at the same rate as the input interface frame rate. Typical timing for a 50-Hz or 60-Hz
3D HDMI source frame, the input interface of the DLPC3478, and the DMD is shown in Figure 9. GPIO_04 is
optionally sent to a transmitter on the system PCB for wirelessly transmitting a sync signal to 3D glasses. The
glasses are then in phase with the DMD images being displayed. Alternately, 3-D Glasses Operation shows how
DLP Link pulses can be used instead.
Figure 9. DLPC3478 L/R Frame and Signal Timing
28
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7.2.2 Parallel Interface Supports Six Data Transfer Formats
• 24-bit RGB888 or 24-bit YCrCb888 on a 24 data wire interface
• 18-bit RGB666 or 18-bit YCrCb666 on a 18 data wire interface
• 16-bit RGB565 or 16-bit YCrCb565 on a 16 data wire interface
• 16-bit YCrCb 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)
• 8-bit RGB888 or 8-bit YCrCb888 serial (1 color per clock input; 3 clocks per displayed pixel)
– On an 8 wire interface
• 8-bit YCrCb 4:2:2 serial (1 color per clock input; 2 clocks per displayed pixel)
– On an 8 wire interface
PDATA Bus – Parallel Interface Bit Mapping Modes shows the required PDATA(23:0) bus mapping for these six
data transfer formats.
7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
23
Red / Cr
Blue / Cb
0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ADVANCE INFORMATION
ASIC Input
Mapping
Green / Y
ASIC Internal Re7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Mapping
Red / Cr
Green / Y
Blue / Cb
Figure 10. RGB-888 / YCrCb-888 I/O Mapping
23
Input
ASIC Input
Mapping
Input
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0
Input
7 6 5 4 3 2 1 0
ASIC Internal Re7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Mapping
Red / Cr
Green / Y
Blue / Cb
Figure 11. RGB-666 / YCrCb-666 I/O Mapping
23
Input
ASIC Input
Mapping
Input
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0
Input
7 6 5 4 3 2 1 0
ASIC Internal Re7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Mapping
Red / Cr
Green / Y
Blue / Cb
Figure 12. RGB-565 / YCrCb-565 I/O Mapping
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23
Cr / Cb
ASIC Input
Mapping
Y
N/A
0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ASIC Internal Re7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Mapping
Cr/Cb
Y
n/a
Figure 13. 16-Bit YCrCb-880 I/O Mapping
[Input 1 single color pixel per clock t Contiguous]
23
Red / Cr
ASIC Input
Mapping
Green / Y
Blue / Cb
0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Input Order must be R->G->B
ADVANCE INFORMATION
First Input Clock
Second Input Clock
Third Input Clock
ASIC Internal Re7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Mapping
Red / Cr
Green / Y
Blue / Cb
[Output 1 full pixel per clock t Non-Contiguous]
Figure 14. 8-Bit RGB-888 or YCrCb-888 I/O Mapping
[Input 1 single Y/Cr-Cb pixel per clock t Contiguous]
23
Cr/Cb
ASIC Input
Mapping
Y
Blue / Cb
0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 77 66 55 44 33 22 11 0
Input Order must be Cr/Cb ->Y
First Input Clock
Second Input Clock
ASIC Internal Re7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Mapping
Cr/Cb
Y
7 6 5 4 3 2 1 0
Blue / Cb
[Output 1 full pixel per clock t Non-Contiguous]
Figure 15. 8-Bit Serial YCrCb-422 I/O Mapping
8 Detailed Description
8.1 Overview
The DLPC3478 controller is one component of a device set that comprises of the DLPC3478 controller, the
DLP3010 (.3 720p) DMD, and the DLPA200x/DLPA300x PMIC/LED driver. All three components of the device
set must be used together for reliable operation of the DLP3010 (.3 720p) DMD. The DLPC3478 controller
provides a convenient interface between user electronics and the DMD to display data and steer light patterns
with high speed, precision, and efficiency.
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8.2 Functional Block Diagram
Parallel Video
CPU
BT656 Port
/5
/24
Test
Pattern
Generator
Input
Control
Processing
Video Processing
x
x
x
x
x
x
Splash
Screen
Chroma Interpolation
Color Space Conversion
Brightness Enhancement
Dynamic Scaling
Gamma Correction
Image Format Processing
x
x
x
x
x
Contrast Adjust
Color Correction
CAIC Processing
Blue Noise STM
Power Saving Operations
DLP® Subsystem
Display Formatting
SRAM (Frame Memory)
DMD_HS_CLK(LVDS)
Arm Cortex -M3
Processor
128 KB I/D Memory
JTAG
I2C_0
SPI_0
DMD_HS_DATA(A)(LVDS)
®
Real Time
Control System
DMD_HS_DATA(B)(LVDS)
DMD_HS_DATA(C)(LVDS)
DMD Interface
SPI_1
I2C_1
WPC Control
LED Control
Other options
/20
GPIO
DMD_HS_DATA(D)(LVDS)
DMD_HS_DATA(E)(LVDS)
DMD_HS_DATA(F)(LVDS)
Clocks and Reset
Generation
DMD_HS_DATA(G)(LVDS)
DMD_HS_DATA(H)(LVDS)
DMD_LS_CLK
DMD_LS_WDATA
DMD_LS_RDATA
DMD_DEN_ARSTZ
Clock (Crystal)
Reset Control
8.3 Feature Description
8.3.1 Pattern Display
Pattern display is one of the key capabilities of the DLPC3478 display and light controller. When the DLPC3478
controller is configured for pattern display, video processing functions can be bypassed to allow for accurate
pattern display. For user flexibility and simple system design the DLPC3478 controller supports both external
pattern and internal pattern streaming modes. In external pattern streaming mode, patterns are sent to the
DLPC3478 controller over parallel interface. In internal pattern streaming mode, 1D patterns are pre-loaded in
flash memory and a host command is sent to DLPC3478 controller to display the patterns. Internal pattern mode
allows for a simple system design by eliminating the need for any external processor to generate and sent 1D
patterns to the DLPC3478 controller.
The DLPC3478 controller outputs two configurable Trigger Out and one Trigger In signal to synchronize patterns
with a camera, sensor, or other peripherals.
Table 4. Pattern Display Signals
SIGNAL NAME
TRIG_OUT_1
DESCRIPTION
External Pattern Mode: Active during each input frame.
Internal Pattern Mode: Active during a predefined group of patterns.
TRIG_OUT_2
Active during display of each pattern.
TRIG_In
Active in Internal Pattern Display mode only. Trigger In signal is used to advance to next patterns in
internal pattern mode.
8.3.1.1 External Pattern Mode
External pattern mode supports 8-bit and 1-bit monochrome or RGB patterns.
8.3.1.1.1 8-bit Monochrome Patterns
In 8-bit external pattern mode, the DLPC3478 controller supports up to 120-Hz input frame rate (VSYNC). In this
mode, the 24-bit input data sent over the parallel interface can be configured as a combination of 1 (8-bits), 2
(16-bits), or 3 (24-bits) 8-bit patterns. Equation 1 calculates the maximum pattern rate for 8-bit pattern.
150 Hz × 3 = 450 Hz
where
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•
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the maximum allowed input frame rate is 150 Hz
(1)
The DLPC3478 controller firmware allows for the following user programmability.
• Exposure time: Time during which a pattern is displayed
• Dark time: Time during which no pattern is displayed and the illumination in OFF
• Number of 8-bit patterns within a frame: 1, 2 or 3
• Illuminator that is ON for each 8-bit pattern
• TRIG_OUT_1 and TRIG_OUT_2 signal configuration and delay
Figure 16 shows a configuration with 3 × 8-bit patterns
VSYNC
[Frame N+1] PDATA 23:0
Parallel Input
33%
Displayed Pattern
ADVANCE INFORMATION
[Frame N]
PDATA 23:16
Illuminator
Trigger Out 1
(Frame Trigger)
Trigger Out 2
(Sub-frame Trigger)
BLUE LED
[Frame N+2] PDATA 23:0
33%
33%
33%
33%
33%
[Frame N]
PDATA 15:8
[Frame N]
PDATA 7:0
[Frame N+1]
PDATA 23:16
[Frame N+1]
PDATA 15:8
[Frame N+1]
PDATA 7:0
BLUE LED
BLUE LED
BLUE LED
BLUE LED
BLUE LED
tD2
tD2
tD1
tD1
tD2
tD2
tD2
tD2
tD1 is the configurable delay for the frame trigger
tD2 is the configurable delay for the sub-frame trigger
Figure 16. 3 × 8-bit (Blue) Pattern Configurations
•
•
•
•
•
3 × 8-bit patterns are displayed within each input VSYNC. Sum of dark time and exposure time for the three
patterns is always same.
Dark time is configured as zero and exposure time for each pattern is 33% of input frame time. Total
exposure time and dark time must be equal to input frame time.
Blue LED is configured to be ON for the patterns. TRIG_OUT_1. TRIG_OUT_1 is configured as edge type
and active high polarity.
TRIG_OUT_1 is configured as edge type and active high polarity.TRIG_OUT_1 delay (tD1) is configured with
respect to input VSYNC and is set once per input frame. TRIG_OUT_2.
TRIG_OUT_2 is also configured as edge type and active high polarity. TRIG_OUT_2 delay (tD2) is configured
with reference to the start of the pattern and is set once per pattern within a frame.
Figure 17 shows a configuration with 2 × 8-bit patterns
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VSYNC
[Frame N+1] PDATA 23:0
Parallel Input
10%
40%
[Frame N]
PDATA 23:16
40%
[Frame N]
PDATA 15:8
RED LED
Illuminator
Trigger Out 1
(Frame Trigger)
10%
40%
[Frame N+1]
PDATA 23:16
RED LED
10%
40%
[Frame N+1]
PDATA 15:8
RED LED
RED LED
tD1
tD1
Trigger Out 2
(Sub-frame Trigger)
10%
tD2
tD2
tD2
tD2
Figure 17. 2 × 8-bit (Red) Pattern Configurations
•
•
•
•
•
2 × 8-bit patterns are displayed within each input VSYNC.
Pattern is configured for 10% dark time and 90% exposure time for each pattern. Sum of exposure time and
dark time for each pattern is 50% of input frame time. Total exposure time and dark time must be equal to
input frame time.
Red LED is configured to be ON for the patterns.
TRIG_OUT_1. TRIG_OUT_1 is configured as edge type and active high polarity. TRIG_OUT_1 delay (tD1) is
configured with respect to input VSYNC and is set once per input frame. TRIG_OUT_2.
TRIG_OUT_2 is also configured as edge type and active high polarity. TRIG_OUT_2 delay (tD2) is
configured with reference to start of the pattern and is set once per pattern within a frame.
Figure 18 shows a configuration with 1 × 8-bit patterns
VSYNC
[Frame N+1] PDATA 23:0
Parallel Input
Displayed Pattern
[Frame N] PDATA 23:16
90%
10%
Trigger Out 2
(Sub-frame Trigger)
[Frame N+1] PDATA 23:16
90%
10%
GREEN LED
Illuminator
Trigger Out 1
(Frame Trigger)
[Frame N+2] PDATA 23:0
tD1
GREEN LED
tD1
tD2
tD2
Figure 18. 1 × 8-bit (Green) Pattern Configurations
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ADVANCE INFORMATION
Displayed Pattern
[Frame N+2] PDATA 23:0
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•
•
•
•
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1 × 8-bit pattern is displayed within input VSYNC
Pattern is configured for 10% dark time and 90% exposure time.
Green LED is configured to be ON for the patterns.
TRIG_OUT_1. TRIG_OUT_1 is configured as edge type and active high polarity. TRIG_OUT_1 delay (tD1) is
configured with respect to input VSYNC and is set once per input frame.
TRIG_OUT_2. TRIG_OUT_2 is also configured as edge type and active high polarity. TRIG_OUT_2 delay
(tD2) is configured with reference to start of the pattern and is set once per pattern within a frame.
•
8.3.1.1.2 1-Bit Monochrome Patterns
Similar to the 8-bit external pattern mode, the maximum supported input frame for 1-bit external pattern mode is
150 Hz. In 1-bit pattern mode each of the 24-bit inputs are treated as a separate binary pattern resulting in a
maximum of 24 patterns. The maximum pattern rate for each 1-bit pattern is 2 kHz.
ADVANCE INFORMATION
The DLPC3478 controller firmware allows for the following user programmability:
• Exposure time: Time during which a pattern is displayed.
• Dark time: Time during which no pattern is displayed and the illumination in OFF.
• Number of 1-bit patterns within a frame- Up to maximum of 24.
• Illuminator: Illuminator that is ON for each 1-bit pattern. User defined illuminator is auto selected for all the
patterns within a frame. User cannot select different illuminator for different 1-bit patterns within a frame.
• TRIG_OUT_1 and TRIG_OUT_2 signal configuration and delay.
Figure 19 shows a configuration with 24 × 1-bit patterns
VSYNC
[Frame N+1] PDATA 23:0
Parallel Input
tDark
tDark
tExposure
tDark
[Frame N+2] PDATA 23:0
tExposure tDark tExposure tDark tExposure
tDark
tExposure
Displayed Pattern
Pat 0
Pat 1
Pat 23
Pat 0
Pat 1
Pat 23
Illuminator
Blue
LED
Blue
LED
Blue
LED
Blue
LED
Blue
LED
Blue
LED
tD1
tD1
Trigger Out 1
(Set Trigger)
Trigger Out 2
(Pattern Trigger)
tD2
tD2
tD2
tD2
tD2
tD2
Figure 19. 1 × 24-bit (Blue) Pattern Configurations
•
•
•
•
•
34
24x8-bit patterns are displayed within input VSYNC.
All 24 patterns are configured for tDark dark time and tExposure exposure time. The sum of dark time and
exposure time for the 24 patterns is always the same.
Blue LED is configured to be ON for each pattern.
TRIG_OUT_1. TRIG_OUT_1 is configured as edge type and active high polarity. TRIG_OUT_1 delay (tD1) is
configured with reference to input VSYNC and is set once per input frame. TRIG_OUT_2.
TRIG_OUT_2 is also configured as edge type and active high polarity. TRIG_OUT_2 delay (tD2) is configured
with reference to start of the pattern and is set once per pattern within a frame.
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8.3.1.2 Internal Pattern Mode
ADVANCE INFORMATION
Column of Data
There are two key differences between internal and external pattern mode:
• Internal pattern mode only supports 1D patterns i.e the pattern data is same across the entire row or column
of the DMD (Figure 19, Figure 20).
• Internal pattern mode enables user to design a simple system by eliminating need of an external processor to
generate and send patterns every frame. In internal pattern mode one row or one column patterns are preloaded in the flash memory and a command is send to DLPC3478 controller to display the patterns.
Implementation details on how to create patterns, save patterns in Flash memory and load patterns from flash
memory into the DLPC3478 controller’s internal memory are described in SW Programmers Guide.
Copy to every column on the DMD
Figure 20. Column Replication
Copy to every line on the DMD
Line of Data
Figure 21. Row Replication
Internal pattern mode further provides two configurations to trigger the display of patterns, free running mode,
(shown in Figure 22) and trigger in mode (shown in Figure 23).
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8.3.1.2.1 Free Running Mode
In free running mode the DLPC3478 controller generates an internal synchronization signal to display pre-stored
patterns. User sends an I2C command to instruct DLPC3478 controller to start download of the 1D patterns from
flash memory into DLPC3478 controller’s internal memory and displaying of the 1D patterns.
Internally
Generated
VSync
Pattern Data
Pattern Data
tDark
Pattern
Display
Illuminator
ADVANCE INFORMATION
Trigger Out 1
(Set Trigger)
Trigger Out 2
(Pattern Trigger)
tExposure
Pattern Data
tExposure
tExposure
tExposure
Pat 0 tDark Pat 1
Pat N tDark Pat 0 tDark Pat 1
Blue
LED
Blue
LED
Blue
LED
tD1
tD2
tExposure
Blue
LED
tExposure
tDark
Blue
LED
Pat
M
Blue
LED
tD1
tD2
tD2
tD2
tD2
tD2
Figure 22. Free Running Mode
•
•
•
•
Multiple 1D patterns are displayed within internally generated sync signal. tExposure (exposure time) and tDark
(dark time) is same for all the 1D patterns within one internally generated sync signal.
Blue LED is configured to be ON for each pattern.
TRIG_OUT_1 delay (tD1) is configured with reference to internally generated VSync signal. TRIG_OUT_1 is
set once within internally generated synchronization signal.
TRIG_OUT_2 delay (tD2) is configured with reference to start of the pattern. TRIG_OUT_2 is set once for
each 1D pattern.
8.3.1.2.2
Trigger In Mode
Trigger In mode provides higher level of control to the user for displaying patterns. In this mode, user controls
when to display the pattern by sending an external trigger signal to the DLPC470 controller. The DLPC3478
controller outputs a Pattern Ready signal to let the user know when DLPC3478 controller is ready to accept the
external trigger signal.
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Pattern Ready
(Output)
Trigger In
(External)
Load
Pattern Data
Pattern Data
tDark
Pattern Display
Illuminator
tExposure
Pattern Data
tDark
tDark
tExposure
tDark
tExposure
tDark
tExposure
tExposure
tDark
Pat
0
Pat
1
Pat
N
Pat 0
Pat 1
Pat M
Blue
LED
Blue
LED
Blue
LED
Blue LED
Blue LED
BLUE LED
tD1
tD1
Trigger Out 2
(Pattern Trigger)
tD2
tD2
tD2
tD2
tD2
tD2
Figure 23. Trigger In Mode
•
•
•
•
•
DLPC3478 controller sets the Pattern Ready signal high to denote that the DLPC3478 controller is ready to
accept Trigger In signal.
User sends the external trigger signal to the DLPC3478 controller to start displaying next pattern with
predefined TExposure (exposure time) and TDark (dark time).
Blue LED is configured to be ON for each pattern.
TRIG_OUT_1 delay (tD1) is configured with reference to external trigger signal. TRIG_OUT_1 is set once
when Pattern Ready signal is high.
TRIG_OUT_2 delay (tD2) is configured with reference to external trigger signal. TRIG_OUT_2 is set once for
each 1D pattern.
8.3.2 Interface Timing Requirements
This section defines the timing requirements for the external interfaces for the DLPC3478 ASIC.
8.3.2.1 Parallel Interface
The parallel interface complies with standard graphics interface protocol, which includes a vertical sync signal
(VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data
bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are
programmable. Figure 4 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is
optional in that the DLPC3478 provides auto-framing parameters that can be programmed to define the data
valid window based on pixel and line counting relative to the horizontal and vertical syncs.
In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows
periodic frame updates to be stopped without losing the displayed image. When PDM_CVS_TE is active, it acts
as a data mask and does not allow the source image to be propagated to the display. A programmable PDM
polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE
active high. If this function is not desired, tie the XXX to a logic low on the PCB. The device allows
PDM_CVS_TE to change only during vertical blanking.
NOTE
VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display
sequencer stops and causes the LEDs to be turned off.
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Trigger Out 1
(Set Trigger)
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8.4 Serial Flash Interface
DLPC3478 device uses an external SPI serial flash memory device for configuration support. The minimum
required size is dependent on the desired minimum number of sequences, CMT tables, and splash options while
the maximum supported is 16 Mb.
For access to flash, the DLPC3478 device uses a single SPI interface operating at a programmable frequency
complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to
180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz.
Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz,
25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.
The device supports two independent SPI chip selects; however, the flash must be connected to SPI chip select
zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select zero
(SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control to
an auto-initialization routine within program memory. The device asserts the HOST_IRQ output signal high while
auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only after autoinitialization is complete is the device ready to receive commands through I2C.
The device supports any flash device that is compatible with the modes of operation, features, and performance
as defined in Table 5 and Table 6.
ADVANCE INFORMATION
Table 5. SPI Flash Required Features or Modes of Operation
FEATURE
DLPC3478 REQUIREMENT
SPI interface width
Single
SPI protocol
SPI mode 0
Fast READ addressing
Auto-incrementing
Programming mode
Page mode
Page size
256 B
Sector size
4 KB sector
Block size
any
Block protection bits
0 = Disabled
Status register bit(0)
Write in progress (WIP) {also called flash busy}
Status register bit(1)
Write enable latch (WEN)
Status register bits(6:2)
A value of 0 disables programming protection
Status register bit(7)
Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)
The device supports only single-byte status register R/W command execution, and thus may not be
compatible with flash devices that contain an expansion status byte. However, as long as expansion status
byte is considered optional in the byte 3 position and any write protection control in this expansion status
byte defaults to unprotected, then the device shares compatibility with the DLPC3478 device.
To support flash devices with program protection defaults of either enabled or disabled, the DLPC3478 device
always assumes the device default is enabled and goes through the process of disabling protection as part of the
boot-up process. This process consists of:
• A write enable (WREN) instruction executed to request write enable, followed by
• A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable
latch (WEL) bit
• After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes
0 to all 8-bits (this disables all programming protection)
Prior to each program or erase instruction, the DLPC3478 issues:
• A write enable (WREN) instruction to request write enable, followed by
• A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
• After the write enable latch (WEL) bit is set, the program or erase instruction is executed
• Note the flash automatically clears the write enable status after each program and erase instruction
The specific instruction OpCode and timing compatibility requirements are listed in Table 8 and Table 7. Note
however that the device does not read the flash electronic signature ID and thus cannot automatically adapt
protocol and clock rate based on the ID.
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Table 6. SPI Flash Instruction OpCode and Access Profile Compatibility Requirements
(1)
(2)
SPI FLASH COMMAND
FIRST BYTE
(OPCODE)
SECOND
BYTE
THIRD BYTE
FOURTH BYTE
FIFTH BYTE
SIXTH BYTE
Fast READ (1 Output)
0x0B
ADDRS(0)
ADDRS(1)
ADDRS(2)
dummy
DATA(0) (1)
Read status
0x05
n/a
n/a
STATUS(0)
Write status
0x01
STATUS(0)
Write enable
0x06
Page program
0x02
ADDRS(0)
ADDRS(1)
ADDRS(2)
Sector erase (4KB)
0x20
ADDRS(0)
ADDRS(1)
ADDRS(2)
Chip erase
0xC7
(2)
DATA(0) (1)
Only the first data byte is show, data continues
DLPC3478 device does not support access to a second/ expansion Write Status byte
The specific and timing compatibility requirements for a DLPC3478 device compatible flash are listed in Table 7
and Table 8.
Table 7. SPI Flash Key Timing Parameter Compatibility Requirements (1) (2)
SYMBOL
ALTERNATE SYMBOL
FR
ƒC
≤1.42
MHz
Chip select high time (also called chip select deselect
time)
tSHSL
tCSH
≤200
ns
Output hold time
tCLQX
tHO
≥0
Clock low to output valid time
tCLQV
tV
Data in set-up time
tDVCH
tDSU
≤5
ns
Data in hold time
tCHDX
tDH
≤5
ns
(1)
(2)
MIN
MAX
UNIT
ns
≤ 11
ns
The timing values are related to the specification of the flash device itself, not the DLPC3478 device .
The DLPC3478 device does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins are
typically tied to a logic high on the PCB through an external pullup.
The DLPC3478 device supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied
with the corresponding voltage. Table 8 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices
supported by DLPC3478 device .
Table 8. Compatible SPI Flash Device Options (1)
DVT (3)
DENSITY (Mb)
(2)
VENDOR
PART NUMBER
PACKAGE SIZE
1.8-V COMPATIBLE DEVICES
Yes
4 Mb
Winbond
W25Q40BWUXIG
2 × 3 mm USON
Yes
4 Mb
Macronix
MX25U4033EBAI-12G
1.43 × 1.94 mm WLCSP
Yes
8 Mb
Macronix
MX25U8033EBAI-12G
1.68 × 1.99 mm WLCSP
2.5- OR 3.3-V COMPATIBLE DEVICES
Yes
16 Mb
Winbond
W25Q16CLZPIG
5 × 6 mm WSON
Yes
32 Mb
Winbond
W25Q32FVSSIG
5.2 x 7.9 mm SOIC
8.4.1 Serial Flash Programming
Note that the flash can be programmed through the DLPC3478 device over I2C or by driving the SPI pins of the
flash directly while the DLPC3478 device I/O are tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be
tri-stated by holding RESETZ in a logic low state while power is applied to the DLPC3478 device . The
SPI0_CSZ1 signal is not tri-stated by this same action.
(1)
(2)
(3)
The flash supply voltage must match VCC_FLSH on the DLPC3478 device. Special attention needs to be paid when ordering devices to
be sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.
Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be
DLPC3478 device compatible.
All of these flash devices appear compatible with the DLPC3478 device , but only those marked with yes in the DVT column have been
validated on the EVM reference design. Those marked with no can be used at the ODM’s own risk.
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SPI FLASH TIMING PARAMETER
Access frequency (all commands)
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8.4.2 SPI Signal Routing
The DLPC3478 device supports two SPI slave devices on the SPI0 interface, specifically, a serial flash and the
DLPA200x. This requires routing associated SPI signals to two locations while attempting to operate up to 36
MHz. Take special care to ensure that reflections do not compromise signal integrity. Follow these
recommendations.
• Split the SPI0_CLK PCB signal trace from the DLPC3478 source to each slave device into separate routes as
close to the DLPC3478 device as possible. Ensure that the SPI0_CLK trace length to each device are equal
in total length.
• Split the SPI0_DOUT PCB signal trace from the DLPC3478 device source to each slave device into separate
routes as close to the DLPC3478 device as possible. Ensure that the SPI0_DOUT trace length to each device
are equal in total length (use the same strategy as listed for SPI0_CLK).
• Ensure the SPI0_DIN PCB signal trace from each slave device to the point where they intersect on the return
to the DLPC3478 device are equal in length and as short as possible. Ensure that each slave device shares a
common trace back to the DLPC3478 device.
• SPI0_CSZ0 and SPI0_CSZ1 need no special treatment because they are dedicated signals and drive only
one device.
8.4.3 I2C Interface Performance
ADVANCE INFORMATION
Both DLPC3478 I2C interface ports support 100-kHz baud rate. By definition, I2C transactions operate at the
speed of the slowest device on the bus, thus there is no requirement to match the speed grade of all devices in
the system.
8.4.4 Content-Adaptive Illumination Control
Content-adaptive illumination control (CAIC) is an image processing algorithm that takes advantage of the fact
that in common real-world image content most pixels in the images are well below full scale for the for the R, G,
and B digital channels being input to the DLPC3478 device . As a result of this the average picture level (APL)
for the overall image is also well below full scale, and the system’s dynamic range for the collective set of pixel
values is not fully utilized. CAIC takes advantage of this headroom between the source image APL and the top of
the available dynamic range of the display system.
CAIC evaluates images frame by frame and derives three unique digital gains, one for each of the R, G, and B
color channels. During CAIC image processing, each gain is applied to all pixels in the associated color channel.
CAIC derives each color channel’s gain that is applied to all pixels in that channel so that the pixels as a group
collectively shift upward and as close to full scale as possible. To prevent any image quality degradation, the
gains are set at the point where just a few pixels in each color channel are clipped. Figure 24 and Figure 25
show an example of the application of CAIC for one color channel.
Figure 24. Input Pixels Example
40
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Figure 25. Displayed Pixels After CAIC Processing
Figure 25 shows the gain that is applied to a color processing channel inside the device. CAIC also adjusts the
power for the R, G, and B LED. For each color channel of an individual frame, CAIC determines the optimal
combination of digital gain and LED power. The decision regarding how much digital gain to apply to a color
channel and how much to adjust the LED power for that color is heavily influenced by the software command
settings sent to the device for configuring CAIC.
As CAIC applies a digital gain to each color channel independently, and adjusts each LED’s power
independently, CAIC also makes sure that the resulting color balance in the final image matches the target color
balance for the projector system. Thus, the effective displayed white point of images is held constant by CAIC
from frame to frame.
Because the R, G, and B channels can be gained up by CAIC inside the device, the LED power can be turned
down for any color channel until the brightness of the color on the screen is unchanged. Thus, CAIC can achieve
an overall LED power reduction while maintaining the same overall image brightness as if CAIC was not used.
Figure 26 shows an example of LED power reduction by CAIC for an image where the R and B LEDs can be
turned down in power.
CAIC can alternatively be used to increase the overall brightness of an image while holding the total power for all
LEDs constant. In summary, when CAIC is enabled CAIC can operate in one of two distinct modes:
• Power Reduction Mode – holds overall image brightness constant while reducing LED power
• Enhanced Brightness Mode – holds overall LED power constant while enhancing image brightness
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ADVANCE INFORMATION
Figure 26. CAIC Power Reduction Mode (for Constant Brightness)
8.4.5 Local Area Brightness Boost
Local area brightness boost (LABB), is an image processing algorithm that adaptively gains up regions of an
image that are dim relative to the average picture level. Some regions of the image have significant gain applied,
and some regions have little or no gain applied. LABB evaluates images frame by frame and derives the local
area gains to be used uniquely for each image. Because many images have a net overall boost in gain even if
some areas of the image get no gain, the overall perceived brightness of the image is boosted.
Figure 27 shows a split screen example of the impact of the LABB algorithm for an image that includes dark
areas.
Figure 27. Boosting Brightness in Local Areas of an Image
LABB works best when the decision about the strength of gains used is determined by ambient light conditions.
For this reason, there is an option to add an ambient light sensor which can be read by the DLPC3478 device
during each frame. Based on the sensor readings, LABB applies higher gains for bright rooms to help overcome
any washing out of images. LABB applies lower gains in dark rooms to prevent over-punching of images.
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8.4.6 3-D Glasses Operation
For supporting 3D glasses, the DLPC3478 device-based chip set outputs sync information to synchronize the
Left eye/Right eye shuttering in the glasses with the displayed DMD image frames.
Two different types of glasses are often used to achieve synchronization. One relies on an infrared (IR)
transmitter on the system PCB to send an IR sync signal to an IR receiver in the glasses. In this case device
output signal GPIO_04 can be used to cause the IR transmitter to send an IR sync signal to the glasses. The
timing for signal GPIO_04 is shown in Figure 9.
For generating the DLP Link sync information, one light pulse per DMD frame is outputted from the projection
lens while the glasses have both shutters closed. To achieve this, the device signals the DLPA2000 device or
DLPA2005 device when to enable the illumination source (typically LEDs or lasers) so that an encoded light
pulse is output once per DMD frame. Because the shutters in the glasses are both off when the DLP Link pulse
is sent, the projector illumination source is also disabled except when the device sends light to create the DLP
Link pulse. Figure 28 and Figure 29 show the timing for the light pulses for DLP Link 3D operation.
Figure 28. Controller L/R Frame and Signal Timing for DLP Link
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The second type of glasses relies on sync information that is encoded into the light being outputted from the
projection lens. This is referred to as the DLP Link approach for 3D, and many 3D glasses from different
suppliers have been built using this method. This demonstrates that the DLP Link method can work reliable. The
advantage of the DLP Link approach is that it takes advantage of existing projector hardware to transmit the sync
information to the glasses. This can save cost, size and power in the projector.
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DLPS111 – MARCH 2018
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Pulse position changes
on alternate subframes
Both
shutters
off
Video
A
B
Next
shutter
on
A
Video
D
C
E
NOTE: The period between DLPLink pulses alternates between the subframe period =D and the subframe period -D,
where D is the delta period.
Figure 29. 3D DLP Link Pulse Timing
Table 9. 3D Link Nominal Timing Table
ADVANCE INFORMATION
HDMI Source
Reference
3D DMD SEQUENCE RATE
(Hz)
A
B
C
D
E
23.6
94.5
25
500
628
128
>2000
24.0
96
25
500
628
128
>2000
49.0
98
25
500
628
128
>2000
50.0
100
25
500
628
128
>2000
51.0
102
25
500
628
128
>2000
59.0
118
25
500
628
128
>2000
60.0
120
25
500
628
128
>2000
61.0
122
25
500
628
128
>2000
8.4.7 DMD (Sub-LVDS) Interface
The DLPC3478 ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum
clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz.
The device sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not all
output data lanes are needed as DMD display resolutions decrease in size. With internal software selection, the
device also supports a limited number of DMD interface swap configurations that can help board layout by
remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 10 shows
the four options available for the DLP3010 (.3 720p) DMD specifically.
Table 10. DLP3010 (.3720p) DMD – ASIC to 8-Lane DMD Pin Mapping Options
DLPC3478 ASIC 8 LANE DMD ROUTING OPTIONS
44
OPTION 1
Swap Control = x0
OPTION 2
Swap Control = x2
DMD PINS
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_E_P
HS_WDATA_E_N
Input DATA_p_0
Input DATA_n_0
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_F_P
HS_WDATA_F_N
Input DATA_p_1
Input DATA_n_1
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_G_P
HS_WDATA_G_N
Input DATA_p_2
Input DATA_n_2
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_H_P
HS_WDATA_H_N
Input DATA_p_3
Input DATA_n_3
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_A_P
HS_WDATA_A_N
Input DATA_p_4
Input DATA_n_4
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_B_P
HS_WDATA_B_N
Input DATA_p_5
Input DATA_n_5
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Table 10. DLP3010 (.3720p) DMD – ASIC to 8-Lane DMD Pin Mapping Options (continued)
DLPC3478 ASIC 8 LANE DMD ROUTING OPTIONS
OPTION 1
Swap Control = x0
OPTION 2
Swap Control = x2
DMD PINS
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_C_P
HS_WDATA_C_N
Input DATA_p_6
Input DATA_n_6
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_D_P
HS_WDATA_D_N
Input DATA_p_7
Input DATA_n_7
The DLPC3478 device contains a test point output port, TSTPT_(7:0), which provides selected system calibration
support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs
when reset is released. The state of these signals is sampled upon the release of system reset and the captured
value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown
resistor, thus external pullups must be used to modify the default test configuration. The default configuration
(x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated to reduce switching activity during normal
operation. For maximum flexibility, an option to jumper to an external pullup is recommended for TSTPT_(2:0).
Pullups on TSTPT_(6:3) are used to configure the ASIC for a specific mode or option. TI does not recommend
adding pullups to TSTPT_(7:3) because this has adverse affects for normal operation. This external pullup value
is sampled only during a 0-to-1 transition on the RESETZ input, thus changing the configuration after reset is
released and has no effect until the next time reset is asserted and released. Table 11 defines the test mode
selection for one programmable scenario defined by TSTPT(2:0).
Table 11. Test Mode Selection Scenario Defined by TSTPT(2:0) (1)
NO SWITCHING ACTIVITY
CLOCK DEBUG OUTPUT
x000
x010
TSTPT(0)
HI-Z
60 MHz
TSTPT(1)
HI-Z
30 MHz
TSTPT(2)
HI-Z
0.7 to 22.5 MHz
TSTPT(3)
HI-Z
HIGH
TSTPT(4)
HI-Z
LOW
TSTPT(5)
HI-Z
HIGH
TSTPT(6)
HI-Z
HIGH
TSTPT(7)
HI-Z
7.5 MHz
TSTPT(2:0) CAPTURE VALUE
(1)
These are only the default output selections. Software can reprogram the selection at any time.
8.4.9 DMD Interface Considerations
The sub-LVDS HS interface waveform quality and timing on the DLPC3478 device ASIC is dependent on the
total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,
and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires
attention to many factors.
As an example, DMD interface system timing margin can be calculated as follows:
Setup Margin = (DLPC3478 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
Hold-time Margin = (DLPC3478 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)
(2)
where PCB SI degradation is signal integrity degradation due to PCB affects which includes such things as
Simultaneously Switching Output (SSO) noise, cross-talk and Inter-symbol Interference (ISI) noise.
(3)
The data sheets for the DMD devices include I/O timing parameters and DMD I/O timing parameters. Similarly,
PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation
is a more complicated adjustment.
In an attempt to minimize the signal integrity analysis that would otherwise be required, use these PCB design
guidelines as a reference of an interconnect system to satisfy both waveform quality and timing requirements
(accounting for both PCB routing mismatch and PCB SI degradation). Be sure to compare any variation from
these recommendations with PCB signal integrity analysis or lab measurements.
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8.4.8 Calibration and Debug Support
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DMD_HS Differential Signals
DMD_LS Signals
Figure 30. DMD Interface Board Stack-Up Details
ADVANCE INFORMATION
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8.4.10 Device Functional Modes
ADVANCE INFORMATION
DLPC3478 device has two functional modes (ON/OFF) controlled by a single pin PROJ_ON:
• When pin PROJ_ON is set high, the projector automatically powers up and an image is projected from the
DMD.
• When pin PROJ_ON is set low, the projector automatically powers down and only microwatts of power are
consumed.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DLPC3478 device controller is required to be coupled with DLP3010 DMD to provide a reliable display
solution for various data and video display applications. The DMDs are spatial light modulators which reflect
incoming light from an illumination source to one of two directions, with the primary direction being into a
projection or collection optic. Each application is derived primarily from the optical architecture of the system and
the format of the data coming into the device. Applications of interest include accessory projectors, projectors
embedded in display devices like notebooks, laptops, tablets, and hot spots. Other applications include wearable
(near-eye or head mounted) displays, interactive display, low latency gaming display, and digital signage.
9.1.1 DLPC3478 System Design Consideration
ADVANCE INFORMATION
System power regulation: It is acceptable for VDD_PLLD and VDD_PLLM to be derived from the same regulator
as the core VDD, but to minimize the AC noise component are typically filtered as recommended in the PCB
Layout Guidelines for Internal ASIC PLL Power.
9.2 Typical Application
9.2.1 3D Depth Capture with DLP Using External Pattern Streaming Mode
The DLPC3478 controller with DLP3010 DMD enables high accuracy and very small form factor 3D Depth
capture products. Figure 31 shows a typical 3D depth capture system block diagrams using external pattern
streaming mode.
HDMI
1.8V
2.3 V to 5.5 V
Keypad
1.8V
SYSPWR
PROJ_ON
1.1V
Reg
PROJ_ON
GPIO_8 (Normal Park)
SPI
Flash
VCC_FLSH
SPI_1
PARKZ
System Controller
SPI_0
Microcontroller
DLPC3478
eDRAM
Parallel I/F 28
I2C
1.1V
1.8V
DC Supplies
Video Front End
VSPI
SPI(4)
RESETZ
INTZ
LED_SEL(2)
L3
VLED
DLPA200x
Current
Sense
L1
Monochrome
(1)
Illumination
CMP_PWM
RC_CHARGE
L2
Spare R/W
GPIO
VCC_INTF
Focus
stepper
motor
Illuminator
3
BIAS, RST, OFS
CMP_OUT
1.8 V
VIO
1.1 V
VCORE
TSTPT_4
GPIO_7
Illumination
Optics
TRIG_OUT1
TRIG_OUT2
Thermistor
WVGA
DLP3010
DDR DMD
Sub-LVDS DATA (18)
CTRL
Focus motor position sensor
Included in DLP® Chip Set
Non-DLP components
Copyright © 2018, Texas Instruments Incorporated
(1)
Options to elect different LEDs, but only 1 channel used at a time
Figure 31. External Pattern Streaming Mode
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Typical Application (continued)
9.2.1.1 Design Requirements
A high-accuracy, 3D depth capture product is created by using a DLP chipset comprised of DLP3010 DMD,
DLPC3478 controller and DLPA2000 PMIC/LED drive. The DLPC3478 simplifies the pattern generation, the
DLPA2000 provides the needed analog functions and DMD displays the required patterns for accurate 3D depth
capture.
In addition to the three DLP devices in the chipset, other components may be required to complete the
application. Minimally, a flash component is required to store patterns, the software, and the firmware in order to
control the DLPC3478 controller.
For connecting the DLPC3478 controller to the host processing for receiving patterns or video data parallel
interface is used. Connect an I2C iinterface to the host processor to send commands to the DLPC3478 controller.
The only power supplies needed external to the projector are the battery (SYSPWR) and a regulated 1.8-V
supply. A single signal (PROJ_ON) controls the entire DLP system power. When PROJ_ON is high, the DLP
system turns on and when PROJ_ON is low, the DLPC3478 turns off and draws only a few microamperes of
current on SYSPWR. When PROJ_ON is low, the 1.8-V power supply can remain at 1.8 V for use by other sub
systems. When PROJ_ON is low, the DLPA2000 draws no current on the 1.8-V supply.
9.2.1.2 Detailed Design Procedure
For connecting the DLP3010 DMD, the DLPC3478 controller and the DLPA2000 PMIC/LED driver see the
reference design schematic. An example board layout is included in the reference design data base. Follow the
layout guidelines shown in to achieve reliable DLP system results.
9.2.1.3 Application Curve
9.2.2 3D Depth Sensor DLP Using Internal Pattern Streaming Mode
Figure 32 shows a typical 3D depth capture system block diagrams using internal pattern streaming mode.
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ADVANCE INFORMATION
DLPC3478 controller supports any illumination source including IR light source (LEDs or VCSE), UV light source
or visible light source (Red, Green or Blue LEDs or lasers).
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Typical Application (continued)
2.3 V to 5.5 V
DC Supplies
Microcontroller
Front End
MSP430
Tiva
VSPI
1.8 V
1.1 V
SYSPWR
PROJ_ON
SPI
Flash
1.8 V
1.8 V
1.1-V
Reg
PROJ_ON
GPIO_8 (Normal Park)
VCC_FLSH
PARKZ
SPI_0
HOST_IRQ
SPI_1
DLPC3478
eDRAM
I2C
SPI(4)
RESETZ
INTZ
LED_SEL(2)
L3
Focus
stepper
motor
VLED
DLPA200x
Current
Sense
L1
Monochrome
(1)
Illumination
CMP_PWM
RC_CHARGE
VCC_INTF
L2
Illuminator
Spare R/W
GPIO
3
BIAS, RST, OFS
CMP_OUT
ADVANCE INFORMATION
TRIG_IN
3DR
1.8 V
VIO
1.1 V
VCORE
TSTPT_4
TRIG_OUT1
GPIO_7
TRIG_OUT2
Illumination
Optics
Thermistor
WVGA
DLP3010
DDR DMD
Sub-LVDS DATA (18)
CTRL
Focus motor position sensor
Included in DLP® Chip Set
Non-DLP components
(1)
Options to elect different LEDs, but only 1 channel used at a time
Figure 32. Internal Pattern Streaming Mode
9.2.2.1 Design Requirements
The design requirements for the 3D Depth capture system using Internal Pattern Streaming Mode is identical to
the design procedure for the 3D Depth capture system External Pattern Streaming Mode. (See the Design
Requirements section.)
9.2.2.2 Detailed Design Procedure
The design procedure for the 3D Depth Sensor DLP Using Internal Pattern Streaming Mode is identical to the
design procedure for the 3D Depth Sensor DLP Using External Pattern Streaming Mode. (See the Detailed
Design Procedure section.)
9.2.2.3 Application Curve
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10 Power Supply Recommendations
10.1 System Power-Up and Power-Down Sequence
Although the DLPC3478 requires an array of power supply voltages, (for example, VDD, VDDLP12,
VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is assumed
to be the typical configuration), then there are no restrictions regarding the relative order of power supply
sequencing to avoid damaging the DLPC3478. (This is true for both power-up and power-down scenarios).
Similarly, there is no minimum time between powering-up or powering-down the different supplies if VDDLP12 is
tied to the 1.1-V VDD supply.
Although there is no risk of damaging the DLPC3478 if the above power sequencing rules are followed, the
following additional power sequencing recommendations must be considered to ensure proper system operation.
• To ensure that DLPC3478 output signal states behave as expected, ensure that all DLPC3478 I/O supplies
remain applied while VDD core power is applied. If VDD core power is removed while the I/O supply
(VCC_INTF) is applied, then the output signal state associated with the inactive I/O supply enters into a high
impedance state.
• Additional power sequencing rules may exist for devices that share the supplies with the DLPC3478, and thus
these devices may force additional system power sequencing requirements.
Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be
drawn. This added leakage does not affect normal DLPC3478 operation or reliability.
Figure 33 and Figure 34 show the DLPC3478 power-up and power-down sequence for both the normal PARK
and fast PARK operations of the DLPC3478 ASIC.
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If however VDDLP12 is not tied to the VDD supply, then VDDLP12 must be powered-on after the VDD supply is
powered-on, and powered-off before the VDD supply is powered-off. In addition, if VDDLP12 is not tied to VDD,
then VDDLP12 and VDD supplies are typically powered on or powered off within 100 ms of each other.
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System Power-Up and Power-Down Sequence (continued)
0 µs
Min
PROJ_ON input
(GPIO_8)
VCC_INTF (1.8 to 3.3 V)
VCC_FLSH (1.8 to 3.3 V)
VDD (1.1 V)
Point at which all supplies reach 95% of
their specified nominal values.
VDD_PLLM/D (1.1 V)
ADVANCE INFORMATION
VDDLP12 (if not
tied to VDD)
PARKZ must be set high a minimum
of 0 µs before RESETZ is released to
support auto-initialization.
VCC18 (1.8 V)
0 µs
Max
PARKZ
PLL_REFCLK
VCC18 must remain ON long
enough to satisfy DMD power
sequencing requirements
defined in the DLPA200x
specification.
PLL_REFCLK may be active
before power is applied.
0 µs Min
RESETZ
5 ms Min
500 µs
Min
500 ms Min
PLL_REFCLK and all ASIC
supplies (except VDDLP12)
must remain active for a
minimum of 500 µs after
PROJ_ON goes low.
I2C activity should cease
immediately upon deassertion on PROJ_ON.
I2C (activity)
0 µs Min
0 µs
Min
HOST_IRQ
HOST_IRQ is driven high when
power and RESETZ are applied to
indicate the controller is not ready for
operation, and then is driven low after
initialization is complete.
PLL_REFCLK must become stable within
5 ms of all power being applied (for
external oscillator application this is
oscillator dependent and for crystal
applications this is crystal and ASIC
oscillator cell dependent).
I2C access can start immediately
after HOST_IRQ goes low (this
should occur within 500 ms from the
release of RESETZ).
HOST_IRQ is pulled high
immediately after RESETZ is
asserted low.
Figure 33. DLPC3478 Power-Up / PROJ_ON = 0 Initiated Normal PARK and Power-Down
52
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System Power-Up and Power-Down Sequence (continued)
PROJ_ON input
(GPIO_8)
VCC_INTF (1.8 to 3.3 V)
VCC_FLSH (1.8 to 3.3 V)
VDD (1.1 V)
VDD_PLLM/D (1.1 V)
Point at which all supplies reach 95% of
their specified nominal values.
0 µs
Min
PARKZ must be set high a minimum
of 0 µs before RESETZ is released to
support auto-initialization.
VCC18 (1.8 V)
VCC18 must remain ON long
enough to satisfy DMD power
sequencing requirements defined
in the DLPA2000 specification.
0 µs
Max
PARKZ
32 µs Min
PLL_REFCLK
PLL_REFCLK may be active
before power is applied.
0 µs Min
RESETZ
5 ms Min
PARKZ must be set low a
minimum of 32 µs before any
power is removed (except
VDDLP12), before PLL_REFCLK
is stopped and before RESETZ is
asserted low to allow time for the
DMD mirrors to be parked.
500 ms Min
I2C activity should cease
immediately upon active low
assertion of PARKZ.
I2C (activity)
0 µs Min
0 µs
Min
HOST_IRQ
HOST_IRQ is driven high when
power and RESETZ are applied to
indicate the controller is not ready for
operation, and then is driven low after
initialization is complete.
PLL_REFCLK must become stable within
5 ms of all power being applied (for
external oscillator application this is
oscillator dependent and for crystal
applications this is crystal and ASIC
oscillator cell dependent).
I2C access can start immediately
after HOST_IRQ goes low (this
should occur within 500 ms from the
release of RESETZ)
HOST_IRQ is pulled high
immediately after RESETZ is
asserted low.
Figure 34. DLPC3478 Power-Up / PARKZ = 0 Initiated Fast PARK and Power-Down
10.2 DLPC3478 Power-Up Initialization Sequence
An external power monitor holds the DLPC3478 device in a system reset state during power-up by driving
RESETZ to a logic low state. It continues to assert system reset until all ASIC voltages have reached minimum
specified voltage levels, PARKZ is asserted high, and input clocks are stable. During this time, the device drives
most ASIC outputs to an inactive state and configures all bidirectional signals as inputs to avoid contention. ASIC
outputs that are not driven to an inactive state are tri-stated. These include LED_SEL_0, LED_SEL_1, SPICLK,
SPIDOUT, and SPICSZ0 (see RESETZ pin description for full signal descriptions in Pin Configuration and
Functions. After power is stable and the PLL_REFCLK_I clock input to the DLPC3478 is stable, then RESETZ is
typically deactivated (set to a logic high). The DLPC3478 then performs a power-up initialization routine that first
locks its PLL followed by loading self configuration data from the external flash. Upon release of RESETZ all
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VDDLP12 (if not tied to VDD)
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DLPC3478 Power-Up Initialization Sequence (continued)
DLPC3478 I/Os become active. Immediately following the release of RESETZ, the device drives the HOST_IRQ
signal high to indicate that the auto initialization routine is in progress. However, because a pullup resistor
connects the signal HOST_IRQ, this signal goes high before the DLPC3478 device actively drives it high. Upon
completion of the auto-initialization routine, the DLPC3478 drives HOST_IRQ low to indicate the initialization
done state of the DLPC3478 device has been reached.
NOTE
The host processor can start sending I2C commands after HOST_IRQ goes low.
10.3 DMD Fast PARK Control (PARKZ)
The PARKZ signal acts as an early warning signal that alerts the ASIC 40 µs before DC supply voltages have
dropped below specifications in fast PARK operation. This alert allows the ASIC time to park the DMD, ensuring
the integrity of future operation. Typically, the reference clock continues to run and RESETZ remains deactivated
for at least 40 µs after PARKZ has been deactivated (set to a logic low) to allow the park operation to complete.
10.4 Hot Plug Usage
ADVANCE INFORMATION
The DLPC3478 device provides fail-safe I/O on all host interface signals (signals powered by VCC_INTF). This
protection allows these inputs to be driven high even when no I/O power is applied. Under this condition, the
device does not load the input signal nor draw excessive current that could degrade ASIC reliability. For
example, the I2C bus from the host to other components is not affected by powering off VCC_INTF to the
DLPC3478 device. TI recommends the application include weak pullup or pulldown components on signals
feeding back to the host to avoid floating inputs.
If the I/O supply (VCC_INTF) is powered off, but the core supply (VDD) is powered on, then the corresponding
input buffer may experience added leakage current, but this does not damage the DLPC3478.
10.5 Maximum Signal Transition Time
Unless otherwise noted, 10 ns is the maximum recommended 20 to 80% rise or fall time to avoid input buffer
oscillation. This applies to all DLPC3478 input signals. However, the PARKZ input signal includes an additional
small digital filter that ignores any input buffer transitions caused by a slower rise or fall time for up to 150 ns.
54
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11 Layout
11.1 Layout Guidelines
11.1.1 PCB Layout Guidelines for Internal ASIC PLL Power
The following guidelines are recommended to achieve desired ASIC performance relative to the internal PLL.
The DLPC3478 contains 2 internal PLLs which have dedicated analog supplies (VDD_PLLM , VSS_PLLM,
VDD_PLLD, VSS_PLLD). As a minimum, isolate VDD_PLLx power and VSS_PLLx ground pins using a simple
passive filter consisting of two series Ferrites and two shunt capacitors (to widen the spectrum of noise
absorption). The recommended values are for one 0.1-µf capacitor and one 0.01-µf capacitor. Place all four
components as close to the ASIC as possible. It is critical to keep the leads of the high frequency capacitors as
short as possible. Connect both capacitors across VDD_PLLM and VSS_PLLM / VDD_PLLD and VSS_PLLD
respectfully on the ASIC side of the Ferrites.
The PCB layout is critical to PLL performance. It is vital to treat the quiet ground and power as analog signals.
Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC3478 to both capacitors and then
through the series ferrites to the power source. Make the power and ground traces as short as possible, parallel
to each other, and as close as possible to each other.
Signal VIA
PCB Pad
VIA to Common Analog
Digital Board Power Plane
ASIC Pad
1
VIA to Common Analog
Digital Board Ground Plane
2
3
4
5
A
Local
Decoupling
for the PLL
Digital Supply
F
Signal
Signal
Signal
VSS
G
Signal
Signal
VSS_
PLLM
VSS
GND
FB
VDD_
PLLM
J
PLL_
REF
CLK_O
VDD_
PLLD
VSS_
PLLD
VSS
0.01uF
PLL_
REF
CLK_I
0.1uF
H
1.1 V
PWR
FB
Crystal Circuit
VSS
VDD
VDD
Figure 35. PLL Filter Layout
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Ferrite bead specification recommendations:
• DC resistance less than 0.40 Ω
• Impedance at 10 MHz equal to or greater than 180 Ω
• Impedance at 100 MHz equal to or greater than 600 Ω
DLPC3478
DLPS111 – MARCH 2018
www.ti.com
Layout Guidelines (continued)
11.1.2 DLPC3478 Reference Clock
The DLPC3478 requires an external reference clock to feed its internal PLL. A crystal or oscillator can supply this
reference. For flexibility, the DLPC3478 accepts either of two reference clock frequencies (see Table 13), but
both must have a maximum frequency variation of ±200 ppm (including aging, temperature, and trim component
variation). When a crystal is used, several discrete components are also required as shown in Figure 36.
PLL_REFCLK_I
PLL_REFCLK_O
RFB
RS
Crystal
C
L1
C
L2
ADVANCE INFORMATION
A.
CL = Crystal load capacitance (farads)
B.
CL1 = 2 × (CL – Cstray_pll_refclk_i)
C.
CL2 = 2 × (CL – Cstray_pll_refclk_o)
D.
Where: Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the ASIC
pin pll_refclk_i. Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with
the ASIC pin pll_refclk_o.
Figure 36.
11.1.2.1 Recommended Crystal Oscillator Configuration
Table 12. Crystal Port Characteristics
PARAMETER
NOM
UNIT
PLL_REFCLK_I TO GND capacitance
1.5
pF
PLL_REFCLK_O TO GND capacitance
1.5
pF
Table 13. Recommended Crystal Configuration (1) (2)
PARAMETER
RECOMMENDED
Crystal circuit configuration
Parallel resonant
Crystal type
Fundamental (first harmonic)
Crystal nominal frequency
24 or 16
Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200
UNIT
MHz
PPM
Maximum startup time
1.0
ms
Crystal equivalent series resistance (ESR)
120 max
Ω
Crystal load
6
pF
RS drive resistor (nominal)
100
Ω
RFB feedback resistor (nominal)
1Meg
Ω
CL1 external crystal load capacitor
See equation in Figure 36 notes
pF
CL2 external crystal load capacitor
See equation in Figure 36 notes
pF
PCB layout
A ground isolation ring around the
crystal is recommended
(1)
(2)
56
Temperature range of –30°C to +85°C
The crystal bias is determined by the ASIC's VCC_INTF voltage rail, which is variable (not the VCC18 rail).
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If the application uses an external oscillator, the oscillator output must drive the PLL_REFCLK_I pin on the
DLPC3478 ASIC and the PLL_REFCLK_O pins must remain unconnected.
Table 14. DLPC3478 Recommended Crystal Parts (1) (2) (3)
PASSED
DVT
(1)
(2)
(3)
TEMPERATURE
AND AGING
ESR
LOAD
CAPACITANCE
24 MHz
±50 ppm
120-Ω max
8 pF
24 MHz
±100 ppm
120-Ω max
6 pF
24 MHz
±145 ppm
120-Ω max
6 pF
MANUFACTURER
PART NUMBER
SPEED
Yes
KDS
DSX211G-24.000M-8pF-50-50
Yes
Murata
XRCGB24M000F0L11R0
Yes
NDK
NX2016SA 24M
EXS00A-CS05733
These crystal devices appear compatible with the DLPC3478, but only those marked with yes in the DVT column have been validated.
Crystal package sizes: 2.0 × 1.6 mm for both crystals.
Operating temperature range: –30°C to +85°C for all crystals.
11.1.3 General PCB Recommendations
TI recommends 1-oz. copper planes in the PCB design to achieve needed thermal connectivity.
To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused
ASIC input pins be tied through a pullup resistor to its associated power supply or a pulldown to ground. For
ASIC inputs with an internal pullup or pulldown resistors, it is unnecessary to add an external pullup or pulldown
unless specifically recommended. Internal pullup and pulldown resistors are weak. Do not expect them to drive
the external line. The DLPC3478 device implements very few internal resistors and these are noted in the pin list.
When external pullup or pulldown resistors are needed for pins that have built-in weak pullups or pulldowns, use
the value 8 kΩ (max).
Never tie unused output-only pins directly to power or ground. Instead leave them open.
When possible, TI recommends that unused bidirectional I/O pins be configured to their output state such that
the pin can be left open. If this control is not available and the pins may become an input, then they are typically
pulled-up (or pulled-down) using an appropriate, dedicated resistor.
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11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
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11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
Table 15. Max Pin-to-Pin PCB Interconnect Recommendations
SIGNAL INTERCONNECT TOPOLOGY
DMD BUS SIGNAL
UNIT
SINGLE BOARD SIGNAL ROUTING
LENGTH
MULTI-BOARD SIGNAL ROUTING
LENGTH
6.0
152.4
See
inch
(mm)
6.0
152.4
See
inch
(mm)
DMD_LS_CLK
6.5
165.1
See
inch
(mm)
DMD_LS_WDATA
6.5
165.1
See
inch
(mm)
DMD_LS_RDATA
6.5
165.1
See
(1)
inch
(mm)
DMD_DEN_ARSTZ
7.0
177.8
See
(1)
inch
(mm)
DMD_HS_CLK_P
DMD_HS_CLK_N
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
ADVANCE INFORMATION
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
(1)
58
Due to board variations, these are impossible to define. Any board designs simulate using SPICE with the ASIC IBIS models to ensure
single routing lengths do not exceed requirements.
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Table 16. High Speed PCB Signal Routing Matching Requirements (1) (2) (3) (4)
SIGNAL GROUP LENGTH MATCHING
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH (5)
UNIT
DMD_HS_CLK_P
DMD_HS_CLK_N
±1.0
(±25.4)
inch
(mm)
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
(1)
(2)
(3)
(4)
(5)
DMD
DMD_LS_WDATA
DMD_LS_RDATA
DMD_LS_CLK
±0.2
(±5.08)
inch
(mm)
DMD
DMD_DEN_ARSTZ
N/A
N/A
inch
(mm)
These values apply to PCB routing only. They do not include any internal package routing mismatch associated with the DLPC3478, the
DMD.
DMD HS data lines are differential, thus these specifications are pair-to-pair.
Training is applied to DMD HS data lines, so defined matching requirements are slightly relaxed.
DMD LS signals are single ended.
Mismatch variance applies to high-speed data pairs. For all high-speed data pairs, the maximum mismatch between pairs are typically 1
mm or less.
11.1.6 Number of Layer Changes
• Single-ended signals: Minimize the number of layer changes.
• Differential signals: Individual differential pairs can be routed on different layers, but ensure that the signals of
a given pair do not change layers.
11.1.7 Stubs
• Avoid using stubs.
11.1.8 Terminations
• DMD_HS differential signals require no external termination resistors.
• The DMD_LS_CLK and DMD_LS_WDATA signal paths typically include a 43-Ω series termination resistor
located as close as possible to the corresponding ASIC pins.
• The DMD_LS_RDATA signal path typically include a 43-Ω series termination resistor located as close as
possible to the corresponding DMD pin.
• DMD_DEN_ARSTZ does not require a series resistor.
11.1.9 Routing Vias
• Be sure to minimize the number of vias on DMD_HS signals and do not exceed two.
• Any and all vias on DMD_HS signals are typically located as close to the ASIC as possible.
• The number of vias on the DMD_LS_CLK and DMD_LS_WDATA signals are typically minimized and do not
exceed two.
• Locate any and all vias on the DMD_LS_CLK and DMD_LS_WDATA signals as close to the ASIC as
possible.
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DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
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11.2 Layout Example
ADVANCE INFORMATION
Figure 37. Example Layout
11.3 Thermal Considerations
The underlying thermal limitation for the DLPC3478 is that the maximum operating junction temperature (TJ) not
be exceeded (this is defined in the ). This temperature is dependent on operating ambient temperature, airflow,
PCB design (including the component layout density and the amount of copper used), power dissipation of the
DLPC3478, and power dissipation of surrounding components. The DLPC3478’s package is designed primarily
to extract heat through the power and ground planes of the PCB. Thus, copper content and airflow over the PCB
are important factors.
The recommended maximum operating ambient temperature (TA) is provided primarily as a design target and is
based on maximum DLPC3478 power dissipation and RθJA at 0 m/s of forced airflow, where RθJA is the thermal
resistance of the package as measured using a JEDEC standard high-k 2s2p PCB with two, 1-oz. power planes.
This JEDEC test PCB is not necessarily representative of the DLPC3478 PCB; the reported thermal resistance
may not be accurate in the actual product application. Although the actual thermal resistance may be different, it
is the best information available during the design phase to estimate thermal performance. However, after the
PCB is designed and the product is built, TI highly recommended that thermal performance be measured and
validated.
To do this, measure the top center case temperature under the worse case product scenario (max power
dissipation, max voltage, max ambient temperature) and validated not to exceed the maximum recommended
case temperature (TC). This specification is based on the measured φJT for the DLPC3478 package and provides
a relatively accurate correlation to junction temperature. Take care when measuring this case temperature to
prevent accidental cooling of the package surface. TI recommends a small (approximately 40 gauge)
thermocouple. The bead and thermocouple wire typically contact the top of the package and are covered with a
minimal amount of thermally conductive epoxy. Route the wires closely along the package and the board surface
to avoid cooling the bead through the wires.
60
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Device Nomenclature
DLPC3478
DLPC347xRXXX
XXXXXXXXXX-TT
LLLLLL.ZZZ
PH YYWW
ADVANCE INFORMATION
12.1.2.1 Device Markings
1
2
SC
3
4
5
Terminal A1 corner identifier
Marking Definitions:
Line 1:
DLP® Device Name: DLPC3478 device name ID.
SC: Solder ball composition
e1: Indicates lead-free solder balls consisting of SnAgCu
G8: Indicates lead-free solder balls consisting of tin-silver-copper (SnAgCu) with silver content
less than or equal to 1.5% and that the mold compound meets TI's definition of green.
Line 2:
TI Part Number
DLP® Device Name: DLPC347x = x indicates 8 device name ID.
R corresponds to the TI device revision letter for example A, B or C
XXX corresponds to the device package designator.
Line 3:
XXXXXXXXXX-TT Manufacturer part number
Line 4:
LLLLLL.ZZZ Foundry lot code for semiconductor wafers and lead-free solder ball marking
LLLLLL: Fab lot number
ZZZ: Lot split number
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Device Support (continued)
Line 5:
PH YYWW: Package assembly information
PH: Manufacturing site
YYWW: Date code (YY = Year :: WW = Week)
NOTE
1. Engineering prototype samples are marked with an X suffix appended to the TI part
number. For example, 2512737-0001X.
2. See , for DLPC347x resolutions on the DMD supported per part number.
12.1.3 Video Timing Parameter Definitions
Active Lines Per Frame (ALPF) Defines the number of lines in a frame containing displayable data: ALPF is a
subset of the TLPF.
Active Pixels Per Line (APPL) Defines the number of pixel clocks in a line containing displayable data: APPL
is a subset of the TPPL.
ADVANCE INFORMATION
Horizontal Back Porch (HBP) Blanking Number of blank pixel clocks after horizontal sync but before the first
active pixel. Note: HBP times are reference to the leading (active) edge of the respective sync
signal.
Horizontal Front Porch (HFP) Blanking Number of blank pixel clocks after the last active pixel but before
Horizontal Sync.
Horizontal Sync (HS) Timing reference point that defines the start of each horizontal interval (line). The
absolute reference point is defined by the active edge of the HS signal. The active edge (either
rising or falling edge as defined by the source) is the reference from which all horizontal blanking
parameters are measured.
Total Lines Per Frame (TLPF) Defines the vertical period (or frame time) in lines: TLPF = Total number of lines
per frame (active and inactive).
Total Pixel Per Line (TPPL) Defines the horizontal line period in pixel clocks: TPPL = Total number of pixel
clocks per line (active and inactive).
Vertical Sync (VS) Timing reference point that defines the start of the vertical interval (frame). The absolute
reference point is defined by the active edge of the VS signal. The active edge (either rising or
falling edge as defined by the source) is the reference from which all vertical blanking parameters
are measured.
Vertical Back Porch (VBP) Blanking Number of blank lines after the leading edge of vertical sync but before
the first active line.
Vertical Front Porch (VFP) Blanking Number of blank lines after the leading edge of the last active line but
before vertical sync.
TPPL
Vertical Back Porch (VBP)
APPL
Horizontal
Back
Porch
(HBP)
ALPF
Horizontal
Front
Porch
(HFP)
TLPF
Vertical Front Porch (VFP)
62
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12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 17. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DLPA2000
Click here
Click here
Click here
Click here
Click here
DLPA2005
Click here
Click here
Click here
Click here
Click here
DLPA3000
Click here
Click here
Click her
Click here
Click here
12.3 Community Resources
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
IntelliBright, E2E are trademarks of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ADVANCE INFORMATION
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
DLPC3478
DLPS111 – MARCH 2018
www.ti.com
13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
DLPC3748ZEZ
(1)
ADVANCE INFORMATION
(2)
(3)
(4)
(5)
(6)
Status
(1)
ACTIVE
Package
Type
Package
Drawing
Pins
Package
Qty
NFBGA
ZEZ
201
1
Eco Plan
(2)
TBD
Lead/Ball
Finish (3)
Call TI
MSL Peak Temp
(4)
Op Temp (°C)
Level-3-260C-168 HR
Device Marking (5) (6)
–30 to 85
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
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Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
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MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
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continuation of the previous line and the two combined represent the entire Device Marking for that device.
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Product Folder Links: DLPC3478
PACKAGE OUTLINE
ZEZ0201A
NFBGA - 1 mm max height
SCALE 1.000
PLASTIC BALL GRID ARRAY
13.1
12.9
A
B
BALL A1 CORNER
13.1
12.9
1 MAX
C
SEATING PLANE
0.31
TYP
0.21
BALL TYP
0.1 C
11.2 TYP
SYMM
(0.9) TYP
R
11.2
TYP
P
N
M
L
K
J
H
G
F
E
D
C
(0.9) TYP
SYMM
201X
B
0.4
0.3
0.15
0.08
C A
C
B
A
0.8 TYP
BALL A1 CORNER
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15
0.8 TYP
4221521/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZEZ0201A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
201X ( 0.4)
1
2
3
4
5
6
7
8
10
9
12
11
13
14
15
A
(0.8) TYP
B
C
D
E
F
G
SYMM
H
J
K
L
M
N
P
R
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
( 0.4)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
( 0.4)
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NOT TO SCALE
4221521/A 03/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZEZ0201A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
( 0.4) TYP
(0.8) TYP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
(0.8) TYP
C
D
E
F
G
SYMM
H
J
K
L
M
N
P
R
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4221521/A 03/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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