AN2682 Application note Connecting I2S audio devices to the STR7/STR9 MCU Introduction This application note describes how to interface the STR7xx SPI peripheral with an audio device (Codec, ADC, DAC, filter...) using the I2S protocol via an external interface consisting of a low cost small CPLD. The design is referenced to the I2S protocol specification, so any I2S device is able to interface with the STR7xx and STR91x MCU through this bridge. To avoid using extra hardware, an I2S solution could be implemented entirely by firmware but this would put a huge load on the CPU. The SPI to I2S bridge solution proposed in this application note is made with a very low cost hardware (about 1$) using a CPLD with less than 32 macrocells and a minimum of firmware overhead. Only one Timer (one Output Compare), 6 GPIOs and the DMA peripheral are used. The DMA available on STR75x and STR91x allows the CPU to be totally free for other tasks, and on STR71x the CPU load is 3.9% at 32 MHz MCLK frequency. The footprint is less than 5 Kbytes in Thumb mode. The example CPLD described in this application note was built for the STR71x and STR750 microcontrollers but can be easily tailored to the STR91x or STM32. January 2008 Rev 1 1/15 www.st.com Contents AN2682 - Application note Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 I2S protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 CPLD design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 STR711 implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Hardware implemention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 STR711 firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.1 4 CPU usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STR750 implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 STR750 firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 AN2682 - Application note General description 1 General description 1.1 I2S protocol I2S (IC to IC Sound) is an audio data transfer standard using a three-line bus for serial and synchronous data transmission. Data are transmitted on the SD line (Serial Data) in Little Endian format (MSB first). Data length is not limited (usually 16/20/24/32/64 bits). Data are synchronized by the SCK (Serial Clock) rising or falling edge for the transmitter, and falling edge only for the receiver. Refer to Figure 1. Data represent stereo digital sound, so each sample contains two words, the right channel sample and the left channel sample. Instead of using two data channels, muxing is performed by transmitting each word in half a sampling period and that allows, by doubling the sampling rate, to transmit two words per period. A control signal WS (Word Select) is then used to determine if the word being sent is the right or the left one. This signal also determines the beginning and the end of the data: there is no need to fix the data length. Receiver and transmitter data lengths can therefore be different, as well as the right and left data lengths. WS is synchronized either on the rising or the falling edge of SCK and precedes the MSB by one SCK period in order to have enough time for storing and shifting operations. As in the SPI protocol, there must be a master and a slave. The master controls and provides the SCK clock and the WS signal, while the slave only sends or receives data. The master can be the receiver or the transmitter or a third element (Controller). Refer to Figure 2. Figure 1. I2S Philips protocol waveforms 16/32-bit CK WS Transmission Reception 16-bit or 32-bit SD MSB LSB MSB Left channel Right channel 3/15 General description Figure 2. AN2682 - Application note I2S protocol signal description and configuration SCK SCK WS Transmitter Receiver WS Transmitter SD Receiver SD Transmitter = Master Receiver = Master Controller SCK Transmitter WS Receiver SD Controller = Master 1.2 SPI protocol The SPI is chosen to implement this solution because its protocol is the most similar to the I2S protocol. It uses four pins: ● Two pins (MOSI and MISO) to transmit and receive serial data ● One pin (SCLK) for data clocking (either rising or falling edge modes are available) ● One pin (nSS) to choose between master and slave modes. When nSS is tied to Gnd, the SPI peripheral functions in Slave mode: it receives the data clock (SCLK) from the master which controls how and when data are transmitted or received. When nSS is tied to Vcc, the SPI peripheral functions in master mode and SCLK is then an output. MISO is the Master Input in master mode and the Slave Output in slave mode. MOSI is the Master Output in master mode and the Slave Input in slave mode. There are two main differences between the I2S and SPI protocols: ● The I2S clock is continuous while the SPI clock is generated only during word transmission and is stopped afterwards. ● The data format in SPI protocol is fixed to 16 or 8 bits only, while the data in I2S can have any length. Due to these two differences, the SPI peripheral cannot be configured in master mode in this case. This is due to the fact that in SPI master mode, data are transmitted with a delay between the words. Besides, many difficulties would arise when other tasks are performed by the microcontroller. So the solution uses the SPI in slave mode. 4/15 AN2682 - Application note 2 CPLD design CPLD design The CLPD design is based on the MAX3000A 32 macrocell device shown in Figure 3. Figure 3. MAX3000A CPLD pin description The CPLD bridge is intended to function as the master for both SPI and I2S devices. Since the SPI peripheral is bidirectional, two I2S devices can be connected at once, as long as they have the same SCK clock (some I2S devices are also bidirectional). When a single device is interfaced to the microcontroller, the unused direction logic can simply be ignored and has no effect on the interface. The CPLD bridge connections with the STR7/9 MCU and the I2S audio device(s) are illustrated in Figure 4. Figure 4. SPI to I2S CPLD bridge connections AF MOSI SDo GPIO/AF MISO SDi GPIO/AF SCLK Audio CPLD interface STR7/9 MCU PWM OCMPA GPIO GPIO CLK Start SCK I2S device(s) WSo WSi Conf The Conf pin is used only in configuration mode. In communication mode, it can be used for any other application purpose. 5/15 CPLD design AN2682 - Application note The I2S signal combination chosen for this solution is: ● Transmitter SD active on SCK falling edge ● Receiver SD active on SCK falling edge ● WS active on SCK falling edge The CPLD brige functions in two modes: 1. Configuration mode: When the Start signal is low, the interface waits for configuration parameters. These parameters are transmitted through a three-bit register named Conf_Reg: Figure 5. Conf_Reg content bit 2 Transmit bit 1 bit 0 Receive DW The Transmit and Receive bits activate or disactivate the corresponding directions in or out of the CPLD interface. DW (Double Word), when set, enables the support of any data format from 17 to 32 bits by setting a WS length of 32 bits instead of 16. The configuration register is set by the MISO line clocked by the falling edge of the Conf signal while Start is low. 2. Communication mode: This mode is active when the Start signal is high. The interface generates the SCLK and SCK signals with their associated delays. It also controls the WS signal as well as the data lengths. The CPLD implementation is illustrated in Figure 6. Figure 6. SPI to I2S CPLD bridge internal diagram CLK Start Conf_reg MISO CLK Start WSt Delay control DW Receive Transmit Mode select Conf CLK TR enable 1 TR enable 2 SCLK MOSI MISO Central DW CLK block 16 bits SDo WSo WSt CLK WS generator 32bits Start SCK SDi Start I2S clock control SCKi WSi The solution is synthesized on ALTERA QUARTUSII software using a MAX3000A 32 macrocell device. The implementation is done with 17 macrocells. The VHDL code implementation is provided with this AN for STR71x and STR750. The STR750 VHDL code can also be used for the STR91x and STM32 microcontroller. 6/15 AN2682 - Application note STR711 implementation example 3 STR711 implementation example 3.1 Hardware implemention The CPLD and STR711 SPI connections are illustrated in Figure 7 TCLK 32 44 7 1 TDO 38 43 TMS 13 2 VCCIO 15 TDI 3.3 V VCCIO 35 JTAG to USB Blaster connector VCCINT 3 1 TCLK 2 Gnd 3 TDO VCCINT 23 R Left in HiZ input state E Left in HiZ input state Start P0.12 3 CLK OCMPA 40 4 MISO MISO 52 5 MOSI MOSI 53 6 SCLK SCLK 54 8 Conf P0.13 5 9 WSo nSS 55 Gnd 10 17 11 SDo 4 Vcc Gnd 5 TMS Gnd 22 12 SCK 6 NC Gnd 7 NC 30 14 WSi 8 NC Gnd 36 16 SDi Gnd 42 9 TDI 10 Gnd STR711 MAX3000A and STR711 SPI connections EPM3064 ALC10-N Figure 7. I2S Audio device 7/15 STR711 implementation example 3.2 AN2682 - Application note STR711 firmware description This section describes how to use the SPI to I2S bridge in your application firmware, the description is based on the source code for STR71x provided with this application note. First, the STR71x peripherals are initialized: ● The TIM1 timer is configured in PWM mode with a period and duty cycle corresponding to the user defined CLK frequency. ● The BSPI0 is configured in slave mode, with falling edge clock (CPOL=0, CPHA=1), 16 bit format, 10-word Transmit and Receive FIFO depth, clock divider calculated to correspond to the user-defined BSPI clock frequency and Transmit FIFO empty interrupt enabled (or Receive FIFO full interrupt if receive-only mode is active). ● The EIC interrupt controller is configured to enable BSPI interrupt IRQ with the highest priority. The STR71x microcontroller performs two main functions: 8/15 1. Configuration function: the microcontroller gets the user-defined Conf_Reg register value from the DEFINE statements, then sets the Start pin low and transmits the three bits clocked by the Conf falling edge. 2. Communication function: After setting the Start signal high, the microcontroller waits for an internal interrupt indicating that the transmit FIFO is empty or that the receive FIFO is full. Then in the interrupt handler, the transmit FIFO is loaded from the audio file and the receive FIFO is read and loaded in the corresponding file. This whole operation is done while the last word is being transmitted and received (bidirectional BSPI shift register). This results in fluent data transfer with no delays or breaks. AN2682 - Application note 3.2.1 STR711 implementation example CPU usage In order to estimate the efficiency of this solution, for integration in different applications, we can calculate the CPU load relative to the I2S communication. This value determines the ratio of time dedicated to the I2S task. This value is calculated as follows: C = Tc ------T T is time between the transmission of two words, so: 1 T = ---------------- × 16 × DW × T F SCLK Where DW=1 or 2 depending on the word format (1 to 16 bits or 2 for 17 to 32 bits), and TF is the FIFO size. Tc is the CPU usage time, obtained (considering a mean instruction length of 3 CPU cycles), by adding: ● The time required to load the FIFOs (2 x TF x 3 CPU cycles). ● The time needed to save and reload the context (16 + 26 CPU cycles). ● The interrupt code execution time (47 x 3 CPU cycles). ● Other durations need to be added such as the latency between the APB and the AHB buses, the time related to the library operations, the optimization type used... Determining the exact duration of all these terms is outside the scope of this document and requires specific and detailed explanations for each case. The intention here is to give a simplified overview of the performance. For a 32 MHz MCLK frequency, 16-bit format and 10-word FIFO length, the CPU usage is therefore: C = 3.9% 9/15 STR711 implementation example Figure 8. AN2682 - Application note STR71x firmware flowchart Begin Initialize peripherals (BSPI, XTI, TIM, EIC, GPIO...) Generate CLK Configuration mode Set Conf_Reg Communication mode End of audio file? BSPI Interrupt NO YES TrFIFO empty? Configuration mode NO YES Load TrFIFO (10 words) END RcFIFO full? NO Increment File pointer File NO YES Tr & Rc mode? YES Read RcFIFO (10 words) File Increment File pointer End of File? YES Disable BSPI interrupts Clear Flags END 10/15 NO AN2682 - Application note STR750 implementation example 4 STR750 implementation example 4.1 Hardware implementation The CPLD and STR750 SSP connections are illustrated in Figure 9. TCLK 32 44 7 1 TDO 38 43 TMS 13 2 VCCIO 15 TDI 3.3 V VCCIO 35 JTAG to USB Blaster connector VCCINT 3 4.2 1 TCLK VCCINT 23 R Left in HiZ input state E Left in HiZ input state Start P2.18 32 CLK PWM1 81 4 MISO S0.MISO 77 5 MOSI S0.MOSI 76 6 SCLK S0.SCLK 78 8 Conf P2.19 9 WSo 2 Gnd Gnd 3 TDO Gnd 17 11 SDo 4 Vcc Gnd TMS 22 12 SCK 5 Gnd 6 NC 30 14 WSi 7 NC Gnd 36 16 SDi Gnd 42 8 NC 9 TDI 10 Gnd 10 31 STR750 MAX3000A and STR750 SSP connections EPM3064 ALC10-N Figure 9. I2S Audio device STR750 firmware description For the STR750, the DMA is used instead of the interrupt method. That makes the software more simple and, since the DMA automatically transfers the data from peripheral to memory and from memory to peripheral there is no CPU load. The STR750 SSP peripheral is configured in SPI Motorola mode. 11/15 STR750 implementation example AN2682 - Application note First, the STR750 peripherals are initialized: ● The TIM0/PWM timer is configured in PWM mode with a period and duty cycle corresponding to the user defined CLK frequency. ● The SSP0 is configured in slave mode, rising edge clock (CPOL=1, CPHA=1), 16 bit format, 8 words Transmit and Receive FIFO depth. ● The DMA is configured to enable SSP Transmit (from memory to peripheral) on channel 0 and SSP Receive (from peripheral to memory) on channel 1. The STR75x microcontroller performs two main functions: 1. Configuration function: the microcontroller gets the user-defined Conf_Reg register value from the DEFINE statements, then sets Start pin low and transmit the three bits clocked by Conf falling edge. 2. Communication function: After setting the Start signal high, only the DMA is active and it loads the Transmit FIFO from memory whenever it is half empty and loads the memory from the Receive FIFO whenever it is half full. The CPU is totally free for any other application tasks. Figure 10. STR75x firmware flowchart Begin Initialize peripherals (SSP, TIM0, DMA, GPIO...) End Of Count Stop PWM counter Generate CLK Clear Flags Configuration mode END Set Conf_Reg End Of Count Communication mode END In this flowchart, the DMA function is not shown because it works in the background and has no effect on the CPU. The same flowchart can be used for STR91x. The STR75x firmware can be easily tailored to any STR91x or STM32 microcontroller. 12/15 AN2682 - Application note 5 Conclusion Conclusion This application note gives a straightforward and low cost solution for using the STR7xx SPI peripheral with an audio device (Codec, ADC, DAC, filter...) using I2S protocol via an external interface consisting of a low cost small CPLD. This solution can be easily tailored to the STR91x and STM32 microcontrollers. 13/15 Revision history 6 AN2682 - Application note Revision history Table 1. 14/15 Document revision history Date Revision 08-Jan-2008 1 Changes Initial release. AN2682 - Application note Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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