Sample & Buy Product Folder Support & Community Tools & Software Technical Documents bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 bq51025 WPC v1.1 Compliant Single Chip Wireless Power Receiver With Proprietary 10-W Power Delivery 1 Features 3 Description • The bq51025 device is a fully-contained wireless power receiver capable of operating in the Wireless Power Consortium (WPC) Qi protocol, which allows a wireless power system to deliver 5 W to the system with Qi inductive transmitters and up to 10 W when operating with the bq500215 primary-side controller. The bq51025 device provides a single device power conversion (rectification and regulation) as well as the digital control and communication as per WPC v1.1 specification. With market-leading 84% system efficiency and adjustable output voltage, the bq51025 device allows for unparalleled system optimization. With a maximum output voltage of 10 V, the bq51025 offers a flexible solution that offers a wireless power solution for 2S battery application and allows optimal thermal performance of the system. The I2C interface allows system designers to implement new features such as aligning a receiver on the transmitter surface or detecting foreign objects on the receiver. The bq51025 device complies with the WPC v1.1 communication protocol making it compatible with all WPC transmitter solutions. The receiver allows for synchronous rectification, regulation and control, and communication to all exist in a market-leading form factor, efficiency, and solution size. 1 • • • • Robust 10-W Receiver Solution Using Proprietary Protocol With TI's 10-W bq500215 Transmitter – Post-Regulation LDO to Protect External Charger Input from Rectifier Output Transients; Inductorless Solution for Lowest Height – Adjustable Output Voltage (4.5 to 10 V) for Coil and Thermal Optimization – Supports 2S Battery Configuration (Non-WPC compliant) – Fully Synchronous Rectifier With 96% Efficiency – 97% Efficient Post Regulator – 84% System Efficiency at 10 W WPC v1.1 Compliant Communication and Control for Compatibility With Current TX Solutions Patented Transmitter Pad Detect Function Improves User Experience Power Signal Frequency Measurement Allows Host to Determine Optimal Placement on TX Surface I2C Communication With Host Device Information(1) 2 Applications • • • • • PART NUMBER Smart Phones, Tablets, and Headsets Point-of-Sale Devices 2S Battery Applications Power Banks Other Portable Devices PACKAGE bq51025 DSBGA (42) BODY SIZE (NOM) 3.60 mm × 2.89 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic bq51025 System Load AD-EN AD OUT CCOMM1 C4 COMM1 CBOOT1 BOOT1 C3 AC1 100% 90% 80% 70% HOST TS/CTRL COMM2 NTC TMEM CLAMP2 C5 CLAMP1 RMEM Efficiency VIREG BOOT2 CCOMM2 CCLAMP1 R8 R9 AC2 CCLAMP2 RECT R6 VO_REG C2 CBOOT2 R7 RECT C1 COIL bq51025 System Efficiency With bq500215 TX Controller 60% 50% 40% WPG PD_DET 30% PMODE SCL 20% CM_ILIM SDA ILIM FOD PGND VOUT = 10V VOUT = 7V VOUT = 5V 10% 0 R1 RFOD 0 1 2 3 4 5 6 Output Power (W) 7 8 9 10 D001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 5 8.1 8.2 8.3 8.4 8.5 8.6 5 5 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 9.1 Overview ................................................................... 9 9.2 9.3 9.4 9.5 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Register Maps ......................................................... 11 12 18 21 10 Application and Implementation........................ 27 10.1 Application Information.......................................... 27 10.2 Typical Applications .............................................. 27 11 Power Supply Recommendations ..................... 39 12 Layout................................................................... 40 12.1 Layout Guidelines ................................................. 40 12.2 Layout Example .................................................... 40 13 Device and Documentation Support ................. 41 13.1 Trademarks ........................................................... 41 13.2 Electrostatic Discharge Caution ............................ 41 13.3 Glossary ................................................................ 41 14 Mechanical, Packaging, and Orderable Information ........................................................... 41 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2014) to Revision B Page • Updated Features and Description to include 2S support ..................................................................................................... 1 • Added 2S Battery Application to Applications ....................................................................................................................... 1 • Corrected RILIM threshold for EPT 0x02 to match Electrical Characteristics ........................................................................ 15 • Corrected section numbering for TMEM ............................................................................................................................. 29 • Added design example section for Standalone 10-V Power Supply for 2S Charging System............................................. 35 Changes from Original (September 2014) to Revision A • 2 Page Updated device status from product preview to production .................................................................................................. 1 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 6 Device Comparison Table Device Mode bq51221 Dual (WPC v1.1, PMA) More bq51020 WPC v1.1 bq51025 WPC v1.1, Proprietary 10 W Autonomous mode detection, I2C control, adjustable output voltage Stand-alone solution, adjustable output voltage, highest system efficiency I2C control, adjustable output voltage, 10-W maximum output power 7 Pin Configuration and Functions YFP Package 42-Pin DSBGA (Top View) A1 PGND A2 PGND A3 PGND A4 PGND A5 PGND A6 PGND B1 AC1 B2 AC1 B3 AC1 B4 AC2 B5 AC2 B6 AC2 C1 BOOT1 C2 RECT C3 RECT C4 RECT C5 RECT C6 BOOT2 D1 OUT D2 OUT D3 OUT D4 OUT D5 OUT D6 OUT E1 CLMP1 E2 AD E3 AD_EN E4 SCL E5 VIREG E6 CLMP2 F1 COMM1 F2 FOD F3 PMODE F4 SDA F5 WPG F6 COMM2 G1 VO_REG G2 ILIM G3 CM_ILIM G4 TS/CTRL G5 TMEM G6 PD_DET Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 3 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com Pin Functions PIN NAME NO. TYPE DESCRIPTION B1 AC1 B2 I B3 AC input power from receiver resonant tank B4 AC2 B5 I B6 AD E2 I Adapter sense pin AD-EN E3 O Push-pull driver for dual PFET circuit that can pass AD input to the OUT pin; used for adapter MUX control BOOT1 C1 O BOOT2 C6 O CLAMP1 E1 O CLAMP2 E6 O COMM1 F1 O COMM2 F6 O CM_ILIM G3 I Enables communication current limit when pulled low or left floating. FOD F2 I Input that is used for scaling the received power message ILIM G2 I/O Output current or overcurrent level programming pin O Output pin, used to deliver power to the load O Open-drain output that allows user to sense when receiver is on transmitter — Power and logic ground O Filter capacitor for the internal synchronous rectifier Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier Open-drain FETs used to clamp the secondary voltage by providing low impedance across secondary Open-drain FETs used to communicate with primary by varying reflected impedance D1 D2 D3 OUT D4 D5 D6 PD_DET G6 A1 A2 A3 PGND A4 A5 A6 C2 C3 RECT C4 C5 SCL E4 I SDA F4 I/O PMODE F3 O Indicates receiver mode of operation: Low = Proprietary 10-W mode, High = Low-power mode. Gate drive output for external current limit switch. Connect 5-MΩ resistor to ground. Leave floating if unused. TMEM G5 O TMEM allows the capacitor to be connected to GND so energy from transmitter ping can be stored to retain memory of state. TS/CTRL G4 I Temperature sense. Can be pulled high to send end power transfer (EPT) – charge complete to TX. Can be pulled low to send EPT – over temperature VO_REG G1 I Sets the regulation voltage for output. Default value is 0.5 V. VIREG E5 I Rectifier voltage feedback WPG F5 O Open-drain output that allows user to sense when power is transferred to load 4 SCL and SDA are used for I2C communication. Connect to ground if not needed. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) Input voltage (2) MIN MAX AC1, AC2 –0.8 20 RECT, COMM1, COMM2, OUT, CLAMP1, CLAMP2, WPG, PD_DET –0.3 20 AD, AD-EN –0.3 30 BOOT1, BOOT2 –0.3 20 7 UNIT V SCL, SDA, PMODE, CM_ILIM, FOD, TS/CTRL, ILIM, TMEM, VIREG, VO_REG –0.3 Input current AC1, AC2 (RMS) 2.5 A Output current OUT 2.5 A Output sink current WPG, PD_DET 15 mA Output sink current COMM1, COMM2 1 TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) (2) A All voltages are with respect to the PGND pin, unless otherwise noted. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 8.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM) 100 pF, 1.5 kΩ (1) UNIT ±2000 Charged device model (CDM) (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VRECT RECT voltage range IOUT Output current IAD-EN Sink current ICOMM COMMx sink current TJ Junction temperature MIN MAX 4 11 2.0 0 UNIT V A 1 mA 500 mA 125 ºC 8.4 Thermal Information THERMAL METRIC (1) YFP (DSBGA) 42 Pins RθJA Junction-to-ambient thermal resistance 49.7 RθJC(top) Junction-to-case (top) thermal resistance 0.2 RθJB Junction-to-board thermal resistance 6.1 ψJT Junction-to-top characterization parameter 1.4 ψJB Junction-to-board characterization parameter 6.0 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 5 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 8.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) , ILOAD = IOUT PARAMETER TEST CONDITIONS MIN TYP MAX 2.9 VUVLO Undervoltage lockout VRECT: 0 to 3 V 2.8 VHYS-UVLO Hysteresis on UVLO VRECT: 3 to 2 V 393 VRECT-OVP Input overvoltage threshold VRECT: 5 to 16 V VHYS-OVP Hysteresis on OVP VRECT: 16 to 5 V VRECT(REG) Voltage at RECT pin set by communication with primary VRECT(TRACK) VRECT regulation above VOUT ILOAD-HYS ILOAD hysteresis for dynamic I falling VRECT thresholds as a % of IILIM LOAD VRECT-DPM Rectifier undervoltage protection, restricts IOUT at VRECT-DPM VRECT-REV Rectifier reverse voltage protection with a supply at the output 14.6 15.1 VILIM = 1.2 V V mV 15.6 1.5 V V Lower of VOUT + 0.2 or 11.0 VOUT + 0.120 UNIT 140 V mV 4% 3 3.1 3.2 V VRECT-REV = VOUT – VRECT, VOUT = 10 V 8.8 9.2 V VOUT ≤ 5 V, 0°C ≤ TJ ≤ 85°C 20 35 µA 215 230 Ω QUIESCENT CURRENT IOUT(standby) Quiescent current at the output when wireless power is disabled ILIM SHORT CIRCUIT RILIM-SHORT Highest value of RILIM resistor considered a fault (short). Monitored for IOUT > 100 mA tDGL-Short Deglitch time transition from ILIM short to IOUT disable ILIM_SC ILIM-SHORT,OK enables the ILIM short comparator when IOUT is greater than this value ILOAD: 0 to 200 mA ILIM-SHORT,OK Hysteresis for ILIM-SHORT,OK comparator ILOAD: 200 to 0 mA 20 mA HYSTERESIS IOUT-CL Maximum output current limit Maximum ILOAD that can be delivered for 1 ms when ILIM is shorted 3.7 A RILIM: 200 to 50 Ω. IOUT latches off, cycle power to reset 1 110 125 ms 140 mA OUTPUT VO_REG Feedback voltage set point KILIM Current programming factor for hardware short circuit protection IOUT_RANGE Current limit programming range ICOMM Output current limit during communication ILOAD = 2000 mA, VO_REG resistor divider ratio = 9:1 0.4968 0.5019 0.5077 ILOAD = 1 mA, VO_REG resistor divider ratio = 9:1 0.4971 0.5017 0.5079 ILOAD = 1000 mA, VO_REG resistor divider ratio = 19:1 0.4977 0.5027 0.5091 ILOAD = 1 mA, VO_REG resistor divider ratio = 19:1 0.4978 0.5029 0.5098 RILIM = KILIM / IILIM, where IILIM is the hardware current limit IOUT = 900 mA 6 842 AΩ 2300 IOUT ≥ 400 mA IOUT – 50 100 mA ≤ IOUT < 400 mA IOUT + 50 IOUT < 100 mA tHOLD-OFF V Hold off time for the communication current limit during startup mA 200 1 Submit Documentation Feedback mA s Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) , ILOAD = IOUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TS/CTRL VTS-Bias TS bias voltage (internal) ITS-Bias < 100 µA and communication is active (periodically driven, see tTS/CTRLMeas) VCTRL-HI CTRL pin threshold for a high VTS/CTRL: 50 to 150 mV TTS/CTRL-Meas Time period of TS/CTRL measurements, when TS is being driven TS bias voltage is only driven when power packets are sent VTS-HOT Voltage at TS pin when device shuts down 1.8 90 105 V 120 mV 1700 ms 0.38 V 155 °C 20 °C THERMAL PROTECTION TJ(OFF) Thermal shutdown temperature TJ(OFF-HYS) Thermal shutdown hysteresis OUTPUT LOGIC LEVELS ON WPG VOL Open-drain WPG pin ISINK = 5 mA 550 mV IOFF,STAT WPG leakage current when disabled VWPG = 20 V 1 µA COMM PIN RDS-ON(COMM) COMM1 and COMM2 ƒCOMM Signaling frequency on COMMx pin for WPC IOFF,COMM COMMx pin leakage current VRECT = 2.6 V Ω 1 2.00 VCOMM1 = 20 V, VCOMM2 = 20 V Kb/s 1 µA CLAMP PIN RDS- CLAMP1 and CLAMP2 Ω 0.5 ON(CLAMP) ADAPTER ENABLE VAD-EN VAD rising threshold voltage VAD 0 V to 5 V VAD-EN-HYS VAD-EN hysteresis VAD 5 V to 0 V IAD Input leakage current VRECT = 0 V, VAD = 5 V RAD_EN-OUT Pullup resistance from AD-EN to OUT when adapter mode is disabled and VOUT > VAD VAD = 0 V, VOUT = 5 V VAD_EN-ON Voltage difference between VAD VAD = 5 V, 0°C ≤ TJ ≤ 85°C and VAD-EN when adapter mode VAD = 9 V, 0°C ≤ TJ ≤ 85°C is enabled 3.5 3.6 3.8 450 V mV 50 μA 230 350 Ω 4 4.5 5 V 3 6 7 V SYNCHRONOUS RECTIFIER ISYNC-EN IOUT at which the synchronous rectifier enters half synchronous mode IOUT: 200 to 0 mA 100 mA ISYNC-EN-HYST Hysteresis for IOUT,RECT-EN (fullIOUT: 0 to 200 mA synchronous mode enabled) 40 mA VHS-DIODE High-side diode drop when the rectifier is in half synchronous mode IAC-VRECT = 250 mA, and TJ = 25°C 0.7 V VIL Input low threshold level SDA V(PULLUP) = 1.8 V, SDA VIH Input high threshold level SDA V(PULLUP) = 1.8 V, SDA VIL Input low threshold level SCL V(PULLUP) = 1.8 V, SCL VIH Input high threshold level SCL V(PULLUP) = 1.8 V, SCL I2C 2 I C speed Typical 0.4 1.4 V 0.4 1.4 Product Folder Links: bq51025 V V 100 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated V kHz 7 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 8.6 Typical Characteristics 0.506 855 0.505 852.5 850 0.504 0.503 KILIM (A:) VO_REG (V 847.5 0.502 0.501 845 842.5 840 837.5 0.5 835 0.499 832.5 830 0.498 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 IOUT (A) 0 2 200 400 600 D002 800 1000 1200 1400 1600 1800 2000 ILOAD (mA) D003 Temperature = 25°C Figure 2. KILIM as a Function of Load Current Figure 1. Output Regulation as a Function of Load 2.815 0.85 2.8125 0.8 2.81 2.8075 0.75 VO_REG (V) VUVLO (V) 2.805 2.8025 2.8 2.7975 0.7 0.65 0.6 2.795 2.7925 0.55 2.79 2.785 -40 IOUT = 1mA IOUT = 1A 0.5 2.7875 0.45 -20 0 20 40 60 Temperature (qC) 80 100 120 0 1 2 3 4 I2C Code D004 Figure 3. UVLO as a Function of Junction Temperature 5 6 7 D005 Figure 4. VO_REG by Different I2C Codes, Resistor Divider Ratio = 9:1 0.505 0.5 0.495 VO_REG (V) 0.49 0.485 0.48 0.475 0.47 0.465 0.46 IOUT = 1mA IOUT = 1A 0.455 0.45 0 I2C Code 1 D006 Figure 5. VO_REG by Different I2C Codes, Resistor Divider Ratio = 19:1 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9 Detailed Description 9.1 Overview WPC-based wireless power systems consist of a charging pad (primary, transmitter) and the secondary-side equipment (receiver). The coils in the charging pad and secondary equipment magnetically couple to each other when the receiver is placed on the transmitter. Power is transferred from the primary to the secondary by transformer action between the coils. The receiver can achieve control over the amount of power transferred by getting the transmitter to change the field strength by changing the frequency, duty cycle, or voltage rail energizing the primary coil. The receiver equipment communicates with the primary by modulating the load seen by the primary. This load modulation results in a change in the primary coil current or primary coil voltage, or both, which is measured and demodulated by the transmitter. In WPC, the system communication is digital (packets that are transferred from the secondary to the primary). Differential biphase encoding is used for the packets. The bit rate is 2 kb/s. Various types of communication packets are defined. These include identification and authentication packets, error packets, control packets, power usage packets, and end power transfer packets, among others. The bq51025 incorporates a two-way proprietary authentication with the bq500215 primary controller that allows optimal power transfer and system performance up to 10-W output power while still complying with WPC v1.1 specifications. Figure 6. Wireless Power System Indicating the Functional Integration of the bq51025 The bq51025 device integrates fully-compliant WPC v1.1 communication protocol to streamline the wireless power receiver designs (no extra software development required). Other unique algorithms such as Dynamic Rectifier Control are integrated to provide best-in-class system efficiency while keeping the smallest solution size of the industry. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 9 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com Overview (continued) As a WPC system, when the receiver (shown in Figure 6) is placed on the charging pad, the secondary coil couples to the magnetic flux generated by the coil in the transmitter, which consequently induces a voltage in the secondary coil. The internal synchronous rectifier feeds this voltage to the RECT pin, which in turn feeds the LDO which feeds the output. The bq51025 device identifies and authenticates itself to the primary using the COMMx pins, switching on and off the COMM FETs, and hence, switching in and out COMM capacitors. If the authentication is successful, the primary remains powered-up. Using a proprietary authentication protocol, the bq51025 determines if the 10-W bq500215 primary controller is powering the device, in which case the bq51025 device allows operation up to 10W. If the bq51025 determines that a standard WPC-compliant transmitter is powering it, it allows operation up to 5-W. The bq51025 device measures the voltage at the RECT pin, calculates the difference between the actual voltage and the desired voltage VRECT(REG) and sends back error packets to the transmitter. This process goes on until the input voltage settles at VRECT(REG) MAX. During a load change, the dynamic rectifier algorithm sets the target voltage between VRECT(REG) MAX and VRECT(REG) MIN, as shown in Table 1. This algorithm enhances the transient response of the power supply. After the voltage at the RECT pin is at the desired value, the pass FET is enabled. The voltage control loop ensures that the output voltage is maintained at VOUT(REG), powering the downstream charger. The bq51025 device meanwhile continues to monitor the input voltage, and keeps sending control error packets (CEP) to the primary, on average, every 250 ms. If a large transient occurs, the feedback to the primary speeds up to 32-ms communication periods to converge on an operating point in less time. 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9.2 Functional Block Diagram , OUT VREF,ILIM VILIM + _ VOUT,FB VOUT,REG + _ RECT VOREG VREF,IABS VIABS,FB + _ VIN,FB VIN,DPM + _ ILIM AD + _ VREFAD,OVP BOOT2 + _ BOOT1 VREFAD,UVLO /AD-EN AC1 AC2 Sync Rectifier Control VIREG TS COMM1 COMM2 DATA_ OUT ADC CLAMP1 VBG,REF VIN,FB VOUT,FB VILIM VIABS,FB TS/CTRL VIABS,REF VIC,TEMP VFOD CLAMP2 Digital Control OVP /WPG + _ VFOD VRECT VOVP,REF SCL FOD SCL /PD_DET SDA SDA 50uA CM_ILIM TMEM 5W_MODE PMODE PMODE PGND Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 11 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 9.3 Feature Description 9.3.1 Dynamic Rectifier Control The Dynamic Rectifier Control algorithm offers the end-system designer optimal transient response for a given maximum output current setting. This is achieved by providing enough voltage headroom across the internal regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target. Therefore, a transient response depends on the loosely-coupled transformer's output-impedance profile. The Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed at the output of the internal regulator (output of the bq51025 device). A 1-A application allows up to a 2-Ω output impedance. Figure 13 shows the Dynamic Rectifier Control behavior during active power transfer. 9.3.2 Dynamic Power Scaling The Dynamic Power Scaling feature allows for the loss characteristics of the bq51025 device to be scaled based on the maximum expected output power in the end application. This effectively optimizes the efficiency for each application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the maximum output current. Note that the maximum output current is set by the KILIM term and the RILIM resistance (where RILIM = KILIM / IILIM). The flow diagram in Figure 13 shows how the rectifier is dynamically controlled (Dynamic Rectifier Control) based on the voltage level at the ILIM pin (VILIM). This voltage represents a fixed percentage of the IILIM setting. Table 1 summarizes how the rectifier behavior is dynamically adjusted based on two different RILIM settings. Table 1 is shown for IMAX, which is the maximum operating output current and is typically lower than IILIM (about 20% lower). See RILIM Calculations for more details on how to set IILIM. Table 1. Dynamic Rectifier Regulation (1) Output Current Percentage (Low-Power Mode) (1) (2) Output Current Percentage (Proprietary Mode) Low Power (5-W) Mode RILIM = 700 Ω IILIM = 0.6 A (IMAX = 0.5 A) Low Power (5-W) Mode RILIM = 700 Ω IILIM = 1.2 A (IMAX = 1 A) Proprietary 10-W Mode RILIM = 495 Ω IILIM = 1.7 A (IMAX = 1.4 A) VRECT (2) 0 to 10% 0 to 5% 0 to 0.05 A 0 to 0.05 A 0 to 0.070 A VOUT + 2.0 10 to 20% 5 to 10% 0.05 to 0.1 A 0.05 to 0.1 A 0.070 to 0.14 A VOUT + 1.6 20 to 40% 10 to 20% 0.1 to 0.2 A 0.1 to 0.2 A 0.14 to 0.28 A VOUT + 0.6 >40% >20% >0.2 A >0.2 A >0.28 A VOUT + 0.12 ROS = Open. The relation between VILIM and ILIM has some dependency on the ROS value. VRECT is regulated to a maximum of 11 V. Table 1 shows the shift in the Dynamic Rectifier Control behavior based on the two different RILIM settings. With the rectifier voltage (VRECT) as the input to the internal LDO, this adjustment in the Dynamic Rectifier Control thresholds dynamically adjusts the power dissipation across the LDO where, PDIS VRECT VOUT IOUT (1) Figure 22 shows how the Dynamic Power Scaling feature reduces the VRECT with increased load, allowing the post-regulation LDO to have maximum headroom at low load conditions for better load transient performance and minimal power dissipation at high loads. Note that this feature balances efficiency with optimal system transient response. 9.3.3 VO_REG Calculations The bq51025 device allows the designer to set the output voltage by setting a feedback resistor divider network from the OUT pin to the VO_REG pin, as seen in Figure 7. Select the resistor divider network so that the voltage at the VO_REG pin is 0.5 V (default setting) at the desired output voltage. The target VO_REG voltage can be changed through I2C by changing Table 4 12 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 OUT R7 VO_REG R6 Figure 7. VO_REG Network Choose the desired output voltage VOUT and R6: 0.5 V K VO VOUT R6 (2) K VO u R7 1 K VO (3) 9.3.4 RILIM Calculations The bq51025 device includes a means of providing hardware overcurrent protection (IILIM) through an analog current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable output current (for example, current compliance). The RILIM resistor size also sets the thresholds for the dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The calculation for the total RILIM resistance is as follows: KILIM RILIM IILIM (4) 51 5ILIM ± 5FOD (5) The RILIM allows for the ILIM pin to reach 1.2 V when operating in proprietary mode (up to 10-W output power) when the output current is equal to IILIM. When the receiver operates in standard WPC low-power mode, the ILIM pin voltage threshold is changed from 1.2 to 0.6 V, setting the low-power mode current limit to half of that at the proprietary mode setting. In the case where having the current limit change by a factor of two between modes is not desired, the two current limit levels may be independently controlled in two ways: • By programming the IO_REG level through I2C • By changing the effective RILIM value for each mode by using an external switch controlled by the PMODE pin To adjust the current limit for each mode through I2C, RILIM is chosen using Equation 4 where IILIM is the current limit for proprietary mode (that is, higher current setting). The host should first set the desired current limit value for low-power mode as a percentage of IILIM through the IO_REG bits and then disable the 2X current scaling by setting the I2C_ILIM bit in Table 5 and Table 6 respectively to enable programmability. By default, IO_REG is set to the highest current setting allowed by RILIM (that is, 100% of IILIM). If I2C control is not available, the current limit for low power and proprietary modes can be set independently by shorting a portion of the R1 resistance using an external switch as shown in Figure 8. RILIM is calculated using Equation 4, where IILIM is the desired current limit for proprietary mode. The resistance to set the current limit in low-power mode, RILIM_LP is calculated by Equation 6. RILIM-LP KILIM 2 u IILIM-LP where IILIM_LP is the desired current limit value in low-power mode (6) Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 13 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com The value for R1_A is given by RILIM_LP – RFOD. The value of R1_B is then RILIM – R1_A – RFOD. Note that with this method IILIM must be less than 2 × IILIM_LP PMODE FOD ROS RECT ILIM R1_A R1_B RFOD Figure 8. Current Limit Setting for bq51025 Using External Switch When choosing IILIM, consider the following two possible operating conditions: • If the user's application requires an output current equal to or greater than the external IILIM that the circuit is designed for (input current limit on the charger where the receiver device is tied higher than the external IILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output does not drop to zero. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the charger pulls the output of the receiver device to ground when the receiver device enters current regulation. • If the user's applications are designed to extract less than the IILIM, typical designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10% more than maximum current is drawn from the output. Such a design would have input current limit on the charger lower than the external ILIM of the receiver device. However, in both cases, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC communication. The following calculations show how such a design is achieved: KILIM RILIM 1.1 u IILIM (7) 51 5ILIM ± 5FOD where ILIM is the hardware current limit (8) When referring to the application diagram shown in Typical Applications, RILIM is the sum of the R1 and RFOD resistance (that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the application. To obtain the tool for calculating RFOD, contact your TI representative. Use RFOD to allow the receiver implementation to comply with WPC v1.1 requirements related to received power accuracy. 9.3.5 Adapter Enable Functionality The bq51025 device can also help manage the multiplexing of adapter power to the output and can shut off the TX when the adapter is plugged in and is above the VAD-EN. After the adapter is plugged in and the output turns off, the RX device sends an EPT to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V below AD, which allows the device to turn on the back-to-back PMOS connected between AD and OUT (see Figure 32). Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. Note that it is required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions. Also, when AD mode is enabled, no load can be pulled from the RECT pin because this could cause an internal device overvoltage in the bq51025 device. 14 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9.3.6 Turning Off the Transmitter The WPC v1.1 specification allows the receiver to turn off the transmitter and put the system in a low-power standby mode. There are two different ways to accomplish this with the bq51025 device. The EPT charge complete (WPC) can be sent to the TX by pulling the TS pin high (above 1.4 V). The bq51025 device will then sense this and send the appropriate signal to the TX, thus putting the TX in a low-power standby mode. 9.3.6.1 WPC v1.1 EPT The WPC allows for a special command to terminate power transfer from the TX-termed EPT packet. The WPC v1.1 specifies the following reasons and their corresponding data field value in Table 2. Table 2. EPT Codes in WPC (1) (2) Reason Value Condition (1) Unknown 0x00 AD > 3.6 V Charge complete 0x01 TS/CTRL > 1.4 V Internal fault 0x02 TJ > 150°C or RILIM < 215 Ω Over temperature 0x03 TS < VHOT, or TS/CTRL < 100 mV (2) Over voltage 0x04 VRECT voltage does not converge and stays higher than target Battery failure 0x06 Not sent Reconfigure 0x07 Not sent No response 0x08 Not sent The Condition column corresponds to the case where the bq51025 device sends the WPC EPT command. The TS < VTS-HOT condition refers to using an external thermistor for temperature control. The TS/CTRL <100-mV condition refers to driving the TS/CTRL pin from external GPIO. 9.3.7 Communication Current Limit Communication current limit is a feature that allows for error-free communication to happen between the RX and TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current during communication with the TX. The communication current limit is set according to Table 3. The communication current limit can be enabled by pulling CM_ILIM pin low or disabled by pulling the CM_ILIM pin high (>1.4 V) . An internal pulldown enables communication current limit when the CM_ILIM pin is left floating. Table 3. Communication Current Limit IOUT Communication Current Limit 0 mA < IOUT < 100 mA None 100 mA < IOUT < 400 mA IOUT + 50 mA 400 mA < IOUT < Max current IOUT – 50 mA When the communication current limit is enabled, the amount of current that the load can draw is limited. If the charger in the system does not have a VIN-DPM feature, the output of the receiver collapses if communication current limit is enabled. Please note that power dissipation within the device will increase during current limiting, lowering overall system efficiency. To disable communication current limit, pull CM_ILIM pin high. 9.3.8 PD_DET and TMEM PD_DET is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM is higher than 1.6 V, PD_DET is low. The voltage on the TMEM pin depends on capturing the energy from the digital ping from the transmitter and storing it on the C5 capacitor in Figure 9. After the receiver sends an EPT (charge complete), the transmitter shuts down and goes into a low-power mode. However, it continues to check if the receiver would like to renegotiate a power transfer by periodically performing the digital ping. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes the capacitor. The designer can choose a bleedoff resistor, RMEM, in parallel with C5 that sets the time constant so that the TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is indeterminate and depends on each transmitter manufacturer. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 15 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com TMEM RMEM C5 Figure 9. TMEM Configuration Set capacitor on C5 = TMEM to 2.2 µF. Resistor RMEM across C5 can be set by understanding the duration between digital pings (tping). Set the resistor such that: t ping 4uC5 R MEM (9) PD_DET typically requires a pullup resistor to an external source. A higher current through the PD_DET pin may affect the output regulation of the device. To improve regulation, TI recommends pullup resistor values in the range of 15 to 100 kΩ. 9.3.9 TS/CTRL The bq51025 device includes a ratiometric external temperature sense function. The temperature sense function has a low ratiometric threshold which represents a hot condition. TI recommends an external temperature sensor to provide safe operating conditions for the receiver product. This pin is best used for monitoring the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC) resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to adjust the NTC to match the trip point of the device. The implementation in Figure 10 shows the series-parallel resistor implementation for setting the threshold at which VTS-HOT is reached. When the VTS-HOT threshold is reached, the device will send an EPT – overtemperature signal for a WPC transmitter. VTSB (1.8 V) R2 20 k TS/CTRL R1 NTC R3 Figure 10. NTC Resistor Setup Figure 10 shows a parallel resistor setup that can be used to adjust the trip point of VTS-HOT. After the NTC is chosen and RNTCHOT at VTS-HOT is determined from the data sheet of the NTC, use Equation 10 to calculate R1 and R3. In many cases, depending on the NTC resistor, R1 or R3 can be omitted. To omit R1, set R1 to 0, and to omit R3, set R3 to 10 MΩ in the calculation. RNTCHOT R1 u R3 VTSHOT 1.8 V u RNTCHOT R1 R3 RNTCHOT R1 u R3 RNTCHOT R1 R3 16 R2 Submit Documentation Feedback (10) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9.3.10 PMODE Pin Connect a 5-MΩ resistor to ground in order to use PMODE to indicate the receiver mode of operation. PMODE is high when in low-power mode and low in proprietary mode. This pin may be used to control the gate of an NMOS switch to change the RILIM, and hence, the current limit based on the maximum power allowed by the transmitter (10 W for bq500215, 5 W or less otherwise). This pin may be left floating if not used. and show the PMODE behavior during startup. 9.3.11 I2C Communication The bq51025 device allows for I2C communication with the internal CPU. The I2C address for the device is 0x6C. In case the I2C is not used, ground SCL and SDA. See Register Maps for more information. 9.3.12 Input Overvoltage If the input voltage suddenly increases in potential for some condition (for example, a change in position of the equipment on the charging pad), the voltage-control loop inside the bq51025 device becomes active, and prevents the output from going beyond VOUT(REG). The receiver then starts sending back error packets every 32 ms until the input voltage comes back to an acceptable level, and then maintains the error communication every 250 ms. If the input voltage increases in potential beyond VRECT_OVP, the device switches off the LDO and informs the primary to terminate power. In addition, a proprietary voltage protection circuit is activated by means of CCLAMP1 and CCLAMP2 that protects the device from voltages beyond the maximum rating of the device. 9.3.13 Alignment Aid Using Frequency Information The bq51025 device provides the host through I2C with power signal frequency information that would enable it to determine the optimal alignment position on the charging surface of a frequency-controlled transmitter. For these WPC transmitters, the power signal frequency increases as the coupling between the primary and secondary coils increases. By finding the position in the charging pad that has the highest frequency, the host can determine that the best possible alignment with the transmitter coil has been achieved. The bq51025 continuously stores a measurement of the power signal frequency in I2C register 0xFB to provide the host the information it needs to determine optimal placement. The power signal frequency is given by: u &RGH 0.982 T AC where ƒAC is the power signal frequency measured at the AC pins in kHz and code is the decimal value in the 0xFB register (11) Figure 11 shows the expected register values across the frequency range. 80 I2C Code (Decimal) 70 60 50 40 30 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 Frequency (kHz) 175 180 185 190 195 200 205 210 D014 2 Figure 11. I C Code vs Power Signal Frequency Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 17 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 9.4 Device Functional Modes At startup operation, the bq51025 device must comply with proper handshaking to be granted a power contract from the WPC transmitter. The transmitter initiates the handshake by providing an extended digital ping after analog ping detects an object on the transmitter surface. If a receiver is present on the transmitter surface, the receiver then provides the signal strength, configuration, and identification packets to the transmitter (see volume 1 of the WPC specification for details on each packet). These are the first three packets sent to the transmitter. The only exception is if there is a true shutdown condition on the AD or TS/CTRL pins where the receiver shuts down the transmitter immediately. See Table 2 for details. After the transmitter has successfully received the signal strength, configuration, and identification packets, the receiver is granted a power contract and is then allowed to control the operating point of the power transfer. With the use of the bq51025 device Dynamic Rectifier Control algorithm, the receiver informs the transmitter to adjust the rectifier voltage to approximately 8 V prior to enabling the output supply. For startup flow diagram details, see Figure 12. To operate in 10-W mode, the bq51025 device performs a proprietary handshaking procedure with the transmitter. If the transmitter (bq500215) responds to the bq51025 handshake, a 10-W power contract is granted and the bq51025 operates in 10-W mode, setting the proper output current limit and control. If there is no response from the transmitter, the bq51025 device defaults to 5-W mode operation. 18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 Device Functional Modes (continued) Tx Powered without Rx Active Tx Extended Digital Ping AD/TS-CTRL EPT Condition? Yes Send EPT packet with reason value No Signal Stength, Identification & Configuration Received by Tx? No Yes No Is Transmitter bq500215? Yes 10-W Power Contract Established. All proceeding control is dictated by the Rx. WPC Power Contract Established. All proceeding control is dictated by the Rx. Yes VRECT < 8 V? Send control error packet to increase VRECT No Startup operating point established. Enable the Rx output. Rx Active Power Transfer Stage Figure 12. Wireless Power Startup Flow Diagram on WPC TX Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 19 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com Device Functional Modes (continued) After the startup procedure is established, the receiver enters the active-power transfer stage (considered the main loop of operation). The Dynamic Rectifier Control algorithm determines the rectifier voltage target based on a percentage of the maximum output current level setting (set by KILIM and RILIM). The receiver sends control error packets to converge on these targets. As the output current changes, the rectifier voltage target dynamically changes. As a note, the feedback loop of the WPC system is relatively slow, it can take up to 150 ms to converge on a new rectifier voltage target. It should be understood that the instantaneous transient response of the system is open loop and dependent on the receiver coil output impedance at that operating point. The main loop also determines if any conditions in Table 2 are true in order to discontinue power transfer. Figure 13 shows the active-power transfer loop. Rx Active Power Transfer Stage Rx Shutdown conditions per the EPT Table? Yes Send EPT packet with reason value Tx Powered without Rx Active No Yes Is VILIM < 0.05 V? VRECT target = Minimum of (VOUT + 2 V) or 11V. Send control error packets to converge. No Yes VRECT target = VOUT + 1.6 V. Send control error packets to converge. Is VILIM < 0.1 V? No Yes VRECT target = VOUT + 0.6 V. Send control error packets to converge. Is VILIM < 0.2 V? No VRECT target = VOUT + 0.12 V. Send control error packets to converge. Measure Received Power and Send Value to Tx Figure 13. Active Power Transfer Flow Diagram on WPC TX 20 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9.5 Register Maps Locations 0x01 and 0x02 can be written at any time. Locations 0xE0 to 0xFF are only functional when VRECT > VUVLO. When VRECT goes below VUVLO, locations 0xE0 to 0xFF are reset. 9.5.1 Wireless Power Supply Current Register 1 Table 4. Wireless Power Supply Current Register 1 (READ / WRITE) Memory Location: 0x01, Default State: 00000001 BIT (1) NAME READ / WRITE FUNCTION B7 (MSB) Read / Write Not used B6 Read / Write Not used B5 Read / Write Not used B4 Read / Write Not used B3 Read / Write Not used 450, 500, 550, 600, 650, 700, 750, or 800 mV (1) Changes VO_REG target Default value 001 B2 VOREG2 Read / Write B1 VOREG1 Read / Write B0 VOREG0 Read / Write Maximum output voltage is limited to 10 V. Maximum VO_REG setting is 0.5 V when default output voltage is set to 10 V with external resistor divider (19:1 ratio) 9.5.2 Wireless Power Supply Current Register 2 Table 5. Wireless Power Supply Current Register 2 (READ / WRITE) Memory Location: 0x02, Default State: 00000111 BIT NAME READ / WRITE B7 (MSB) JEITA Read / Write Not used Read / Write Not used B6 B5 ITERM2 Read / Write B4 ITERM1 Read / Write B3 ITERM0 Read / Write B2 IOREG2 Read / Write B1 IOREG1 Read / Write B0 IOREG0 Read / Write FUNCTION Not used. 10%, 20%, 30%, 40%, 50%, 60%, 80%, and 100% of IILIM current based on configuration 000, 001, ….111 9.5.3 Wireless Power Supply Current Register 3 Table 6. Wireless Power Supply Current Register 3 (READ / WRITE) Memory Location: 0xF0, Reset State: 00000000 BIT NAME READ / WRITE B7 Reserved Read/Write B6 Reserved Read / Write B5 Reserved Read / Write B4 Reserved Read / Write B3 Reserved Read / Write B2 Reserved Read / Write B1 I2C_ILIM Read / Write B0 Reserved Read / Write FUNCTION Set bit to 1 to disable 2× current limit scaling between low-power and proprietary modes. Must be set to 1 to correctly adjust the current limit for each mode through I2C Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 21 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 9.5.4 I2C Mailbox Register Table 7. I2C Mailbox Register (READ / WRITE) Memory Location: 0xE0, Reset State: 10000000 BIT NAME READ / WRITE B7 USER_PKT_DONE Read/Write USER_PKT_ERR Read B4 FOD Mailer Read / Write Not used B3 ALIGN Mailer Read / Write Setting this bit to 1 enables alignment aid mode where the CEP = 0 is sent until this bit is set to 0 (or CPU reset occurs) B2 FOD Scaler Read / Write Not used, write to 0 if register is written B1 Reserved Read / Write B0 Reserved Read / Write B6 B5 FUNCTION Set bit to 0 to send proprietary packet with header in 0xE2. CPU checks header to pick relevant payload from 0xF1 to 0xF4 This bit will be set to 1 after the user packet with the header in register 0xE2 is sent. 00 01 10 11 = No error in sending packet = Error: No transmitter present = Illegal header found: packet will not be sent = Error: Not defined yet 9.5.5 I2C Mailbox Register 2 Table 8. I2C Mailbox Register 2 (READ / WRITE) Memory Location: 0xEF, Reset State: 00000000 BIT NAME READ / WRITE B7 PMODE Read B6 Reserved Read / Write B5 Reserved Read / Write B4 Reserved Read / Write B3 Reserved Read / Write B2 Reserved Read / Write B1 Reserved Read / Write B0 Reserved Read / Write FUNCTION Power mode 0 = Low-power mode 5 W 1 = Proprietary 10 W 9.5.6 I2C Mailbox Register 3 Table 9. I2C Mailbox Register 3 (READ) Memory Location: 0xFB, Reset State: 00000000 22 BIT NAME READ / WRITE B7 FREQ7 Read B6 FREQ6 Read B5 FREQ5 Read B4 FREQ4 Read B3 FREQ3 Read B2 FREQ2 Read B1 FREQ1 Read B0 FREQ0 Read FUNCTION Power signal frequency. See Equation 11 for calculation. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9.5.7 Wireless Power Supply FOD RAM Table 10. Wireless Power Supply FOD RAM (READ / WRITE) Memory Location: 0xE1, Reset State: 00000000 (1) (1) BIT NAME READ / WRITE B7 (MSB) ESR_ENABLE Read / Write FUNCTION Enables I2C based ESR in received power, Enable = 1, Disable = 0 B6 OFF_ENABLE Read / Write Enables I2C based offset power, Enable = 1, Disable = 0 B5 RoFOD5 Read / Write B4 RoFOD4 Read / Write B3 RoFOD3 Read / Write 000 = 0 mW 001 = 78 mW 010 = 156 mW 011 = 234 mW 100 = 312 mW 101 = 390 mW 110 = 468 mW 111 = 546 mW The value is added to received power message B2 RsFOD2 Read / Write B1 RsFOD1 Read / Write 101 = ESR 110 = ESR 111 = ESR x 0.5 B0 RsFOD0 Read / Write 000 = ESR 001 = ESR 010 = ESR × 2 011 = ESR × 3 100 = ESR × 4 A non-zero value changes the I2R calculation resistor and offset in the received power calculation by a factor shown in the table. 9.5.8 Wireless Power User Header RAM Table 11. Wireless Power User Header RAM (WRITE) Memory Location: 0xE2, Reset State: 00000000 (1) (1) BIT READ / WRITE B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write Must write a valid WPC v1.1 Proprietary Packet Header to enable proprietary package. Reserved headers (Control Error Packet, Received Power Packet, and so forth) may not be used. As soon as mailer (0xE0) is written, payload bytes are sent on the next available communication slot as determined by CPU. When payload is sent, the mailer (USER_PKT_DONE) is set to 1. 9.5.9 Wireless Power USER VRECT Status RAM Table 12. Wireless Power USER VRECT Status RAM (READ) Memory Location: 0xE3, Reset State: 00000000 Range – 0 to 12 V This register reads back the VRECT voltage with LSB = 46 mV BIT NAME READ / WRITE B7 (MSB) VRECT7 Read B6 VRECT6 Read B5 VRECT5 Read B4 VRECT4 Read B3 VRECT3 Read B2 VRECT2 Read B1 VRECT1 Read B0 VRECT0 Read FUNCTION LSB = 46 mV Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 23 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 9.5.10 Wireless Power VOUT Status RAM Table 13. Wireless Power VOUT Status RAM (READ) Memory Location: 0xE4, Reset State: 00000000 This register reads back the VOUT voltage with LSB = 46 mV BIT NAME Read / Write B7 (MSB) VOUT7 Read / Write B6 VOUT6 Read / Write B5 VOUT5 Read / Write B4 VOUT4 Read / Write B3 VOUT3 Read / Write B2 VOUT2 Read / Write B1 VOUT1 Read / Write B0 VOUT0 Read / Write FUNCTION LSB = 46 mV 9.5.11 Wireless Power Proprietary Mode REC PWR MSByte Status RAM Table 14. Wireless Power Proprietary Mode REC PWR MSByte Status RAM (READ) (1) Memory Location: 0xE7, Reset State: 00000000 This register reads back the MSByte for received power in Proprietary 10-W Mode only (1) BIT Read / Write B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write For proprietary mode, Received power (mW) = (10000/128) × REC PWR MSByte + (10000 / (256 × 128)) × REC PWR LSByte 9.5.12 Wireless Power REC PWR LSByte Status RAM Table 15. Wireless Power REC PWR LSByte Status RAM (READ) (1) Memory Location: 0xE8, Reset State: 00000000 (1) 24 BIT Read / Write B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write This register reads back the received power in low-power mode with LSB = 39 mW. In proprietary mode, this register reads back the LSByte for received power. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 9.5.13 Wireless Power Prop Packet Payload RAM Byte 0 Table 16. Wireless Power Prop Packet Payload RAM Byte 0 (WRITE) Memory Location: 0xF1, Reset State: 00000000 BIT Read / Write B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write 9.5.14 Wireless Power Prop Packet Payload RAM Byte 1 Table 17. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE) Memory Location: 0xF2, Reset State: 00000000 BIT Read / Write B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write 9.5.15 Wireless Power Prop Packet Payload RAM Byte 2 Table 18. Wireless Power Prop Packet Payload RAM Byte 2 (WRITE) Memory Location: 0xF3, Reset State: 00000000 BIT Read / Write B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 25 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 9.5.16 Wireless Power Prop Packet Payload RAM Byte 3 Table 19. Wireless Power Prop Packet Payload RAM Byte 3 (WRITE) Memory Location: 0xF4, Reset State: 00000000 26 BIT Read / Write B7 (MSB) Read / Write B6 Read / Write B5 Read / Write B4 Read / Write B3 Read / Write B2 Read / Write B1 Read / Write B0 Read / Write Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The bq51025 device complies with WPC v1.1 standard. There are several tools available for the design of the system. Obtain these tools by checking the product page at www.ti.com. The following sections detail how to design a WPC v1.1 mode RX system. 10.2 Typical Applications 10.2.1 WPC v1.1 Power Supply 7-V Output With 1.4-A Maximum Current With I2C System Load Q1 bq51025 AD-EN AD OUT CCOMM1 C4 COMM1 CBOOT1 BOOT1 C1 C3 AC1 COIL R8 VIREG BOOT2 HOST TS/CTRL COMM2 CCOMM2 CCLAMP1 R6 R9 AC2 CCLAMP2 RECT VO_REG C2 CBOOT2 R7 RECT NTC TMEM CLAMP2 C5 CLAMP1 RMEM WPG PD_DET PMODE SCL CM_ILIM SDA ILIM R1 FOD RFOD PGND ROS RECT Figure 14. Schematic Using bq51025 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 27 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com Typical Applications (continued) 10.2.1.1 Design Requirements Table 20. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VOUT 7V IOUT MAXIMUM 1.4 A 10.2.1.2 Detailed Design Procedure To start the design procedure, determine the following: • Output voltage • Maximum output current 10.2.1.3 Output Voltage Set Point The output voltage of the bq51025 device can be set by adjusting a feedback resistor divider network. The resistor divider network is used to set the voltage gain at the VO_REG pin. The device is intended to operate where the voltage at the VO_REG pin is set to 0.5 V. This value is the default setting and can be changed through I2C. In Figure 15, R6 and R7 are the feedback network for the output voltage sense. OUT C4 R7 R6 VO_REG Figure 15. Voltage Gain for Feedback K VO R6 0.5 V VOUT (12) K VO u R7 1 K VO (13) Choose R7 to be a standard value. In this case, take care to choose R6 and R7 to be fairly large values so as to not dissipate an excessive amount of power in the resistors and thereby lower efficiency. KVO is set to be 0.5 / 7 = 1/14, choose R7 to be 130 kΩ, and thus R6 to be 10 kΩ. After R6 and R7 are chosen, the same values should be used on the VI_REG resistor divider (R9 and R8). This allows the device to regulate the rectifier voltage properly and accurately track the output voltage. 10.2.1.4 Output and Rectifier Capacitors Set C4 between 1 and 4.7 µF. This example uses 3.3 µF. Set C3 between 22 and 44 µF. This example uses 44 µF to minimize output ripple. 28 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 10.2.1.5 TMEM Set C5 to 2.2 µF. To determine the bleedoff resistor, the WPC transmitters (for which the PD_DET is being set for) needs to be determined. After the ping timing (time between two consecutive digital pings after EPT charge complete is sent) is determined, the bleedoff resistor RMEM can be determined. This example uses TI transmitter EVMs as the use case. In this case, the time between pings is 5 s. To set the time constant using Equation 9, RMEM is set to 560 kΩ. 10.2.1.6 Maximum Output Current Set Point ILIM FOD1 R1 ROS RECT RFOD Figure 16. Current Limit Setting for bq51025 The bq51025 device includes a means of providing hardware overcurrent protection by means of an analog current regulation loop. The hardware current limit provides a level of safety by clamping the maximum allowable output current (for example, a current compliance). The RILIM resistor size also sets the thresholds for the dynamic rectifier levels, and thus providing efficiency tuning per each application’s maximum system current. The calculation for the total RILIM resistance is as follows: KILIM RILIM IILIM (14) 51 5ILIM ± 5FOD (15) The RILIM allows for the ILIM pin to reach 1.2 V at an output current equal to IILIM in 10-W mode and reach 0.6 V in 5-W mode. When choosing IILIM, consider two possible operating conditions: • If the application requires an output current equal to or greater than external ILIM that the circuit is designed for (input current limit on the charger where the RX is delivering power to is higher than the external ILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the RX device output is tied to by lowering the amount of current being drawn. This ensures that the RX output does not collapse. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the charger pulls the output of the RX device to ground when the RX device enters current regulation. • If the applications are designed to extract less than the IMAX, typical designs should leave a design margin of at least 20% so that the voltage at ILIM pin reaches 1.2 V when 20% more than maximum current of the system (IMAX) is drawn from the output of the RX. Such a design would have input current limit on the charger lower than the external current limit of the RX device. In both cases, however, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC v1.1 Communication. See Communication Current Limit for more details. The following calculations show how such a design is achieved: KILIM RILIM 1.2 u I ILIM (16) 51 5ILIM ± 5FOD (17) Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 29 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com When referring to the application diagram shown in Figure 16, RILIM is the sum of the R1 and RFOD resistance (that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the FOD application note that can be obtained by contacting your TI representative. This is used to allow the RX implementation to comply with WPC v1.1 requirements related to received power accuracy. Also note that in many applications, the resistor ROS is necessary to comply with WPC V1.1 requirements. In such a case, the offset on the FOD pin from the voltage on RFOD can cause a shift in the calculation that can reduce the expected current limit. Therefore, it is always a good idea to check the output current limit after FOD calibration is performed according to the FOD section. Unfortunately, because the RECT voltage is not deterministic, and depends on transmitter operation to a certain degree, it is not possible to determine R1 with ROS present in a deterministic manner. In this example, set maximum current for the example to be 1.4 A at 10 W and 700 mA at 5-W mode. Set IILIM = 1.7 A to allow for the 20% margin. RILIM 842 1.7A 495Ö (18) 10.2.1.7 I2C The I2C lines are used to communicate with the device. To enable the I2C, they can be pulled up to an internal host bus. The device address is 0x6C. 10.2.1.8 Communication Current Limit Communication current limit allows the device to communicate with the transmitter in an error-free manner by decoupling the coil from load transients on the OUT pin during WPC communication. In some cases, this communication current limit feature is not desirable. In this design, the user enables the communication current limit by tying the CM_ILIM pin to GND. If this is not needed, the CM_ILIM pin can be tied to the OUT pin to disable the communication current limit. In this case, take care that the voltage on the CM_ILIM pin does not exceed the maximum rating of the pin. 10.2.1.9 Receiver Coil The receiver coil design is the most open part of the system design. The choice of the receiver inductance, shape, and materials all intimately influence the parameters themselves in an intertwined manner. This design can be complicated and involves optimizing many different aspects; refer to the EVM user's guide (SLUUBSS). The typical choice of the inductance of the receiver coil for a 10-W, 7-V solution is between 15 and 16 µH. 10.2.1.10 Series and Parallel Resonant Capacitors Resonant capacitors, C1 and C2, are set according to WPC specification. The equations for calculating the values of the resonant capacitors are shown: -1 2 é ù C1 = ê fS ´ 2p ´ L'S ú ë û -1 é 2 1ù C2 = ê fD ´ 2p ´ LS ú C1 ûú ëê ( ) ( ) (19) Because the bq51025 can provide up to 10 W of output power, TI highly recommends that the resonant capacitors have very-low ESR and dissipate as little power as possible for better thermal performance. TI highly recommends NP0/C0G ceramic material capacitors. 10.2.1.11 Communication, Boot, and Clamp Capacitors Set CCOMMx to a value ranging from C1 / 8 to C1 / 3. The higher the value of the communication capacitors, the easier it is to comply with the WPC specification. However, higher capacitors do lower the overall efficiency of the system. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. Set CBOOTx as 15 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. Set CCLAMPx as 470 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. 30 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 10.2.1.12 Application Curves CM_ILIM = High CH1 = VRECT CH3 = PMODE CH2 = VOUT CH4 = ILOAD CM_ILIM = High Figure 17. 7-V RX Start-Up With 9-Ω Load on a 5-W WPC TX CM_ILIM = High CH1 = VRECT CH2 = VOUT CH4 = ILOAD CM_ILIM = High RILIM = 495: RILIM = 700: VRECT (V) VILIM (V) 0.8 0.4 0.2 VOUT = 7V ROS = Open 0 0 0.2 0.4 0.6 0.8 1 IOUT (A) 1.2 1.4 1.6 1.8 CH2 = VOUT CH4 = ILOAD 9.5 9.25 9 8.75 8.5 8.25 8 7.75 7.5 7.25 7 6.75 6.5 6.25 6 RILIM = 495: RILIM = 700: 0 D007 Figure 21. ILIM Voltage as a Function of Load Current CH1 = VRECT Figure 20. 1450- to 0-mA Load Dump with 7-V RX on bq500215 TX 1.2 0.6 CH2 = VOUT CH4 = ILOAD Figure 18. 7-V RX Start-Up With 5-Ω Load on a bq500215 TX Figure 19. 0- to 1450-mA Step with 7-V RX on bq500215 TX 1 CH1 = VRECT CH3 = PMODE 0.2 0.4 0.6 0.8 IOUT (A) 1 1.2 1.4 D008 Figure 22. Rectifier Regulation as a Function of RILIM on bq500215 TX, 7-V RX Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 31 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 90% 90% 80% 80% 70% 70% 60% 60% Efficiency 100% Efficiency 100% 50% 40% 50% 40% 30% 30% bq500210 bq500211 bq500412 20% 10% VOUT = 5V VOUT = 7V VOUT= 10V 20% 10% 0 0 0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 IOUT (A) 0 0.8 1 2 3 4 D011 CM_ILIM = High 5 6 POUT (W) 7 8 9 10 D0012 CM_ILIM = High Figure 23. Efficiency on Various 5-W WPC TX, 7-V RX Figure 24. Efficiency on 10-W bq500215 TX 200 7.1 bq500412 (A6) bq500212A (A11) 190 7.08 7.06 180 7.04 170 VOUT (V) Frequency (kHz) Wurth 760 308 201 coil Vishay IWAS4832FEEB150J50 Vishay IWAS4832FEEB150J50 160 150 140 7.02 7 6.98 6.96 130 6.94 120 6.92 110 6.9 0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 IOUT (A) 0.8 0 0.2 D010 Figure 25. Frequency Range of 7-V, 5-W Mode on a WPC TX 0.4 0.6 0.8 IOUT (A) 1 1.2 1.4 1.6 D009 Figure 26. Output Regulation on bq500215 TX 10 9 8 VRECT (V) 7 6 5 4 3 2 1 0 1 2 3 4 5 6 VOUT (V) 7 8 9 10 Figure 27. VRECT Foldback in Current Limit on a WPC TX 32 CH1 = VRECT CH3 = AD_EN D013 CH2 = VOUT CH4 = AD Figure 28. AD_EN Functionality upon 5-V USB Connection, 10-V RX, No Load Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 12000 0 10000 -6 8000 -12 6000 -18 4000 -24 Min Max Difference 2000 0 0 CH1 = VRECT CH3 = AD_EN 0.2 0.4 CH2 = VOUT CH4 = AD Figure 29. AD_EN Functionality upon 5-V USB Removal, 10-V RX, 1-A Load 0.6 0.8 ILOAD(A) 1 1.2 -30 -36 1.4 Difference between Max and Min Value (mW) SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 Reported Received Power (mW) www.ti.com D015 Figure 30. Received Power Variation (mW) vs IOUT (mA) on a WPC TX CH2 = VTS Figure 31. TS Voltage Bias Without TS Resistor Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 33 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 10.2.2 Standalone 10-V WPC v1.1 Power Supply With 1-A Maximum Output Current in System Board When the bq5102x device is implemented as an embedded device on the system board, the same design procedure as for an I2C system should be used, but the I2C pins are to be connected to ground.The VO_REG and VIREG resistor dividers are chosen to achieve 10-V output and RILIM is chosen to allow a maximum current of 1 A (IILIM = 1.2 A for 20% margin). Refer to WPC v1.1 Power Supply 7-V Output With 1.4-A Maximum Current With I2C for details on how these resistor values are calculated. A typical coil inductance for 10-V is between 15 and 17 µH. It is important to note that even if the same receiver coil and tuning as for a 7-V RX solution are used (see Receiver Coil and Series and Parallel Resonant Capacitors), the RFOD and ROS values need to be updated to accurately determine the received power. System Load Q1 bq51025 AD-EN AD OUT CCOMM1 C4 COMM1 CBOOT1 BOOT1 C1 C3 AC1 COIL R8 VIREG BOOT2 HOST TS/CTRL COMM2 CCOMM2 CCLAMP1 R6 R9 AC2 CCLAMP2 RECT VO_REG C2 CBOOT2 R7 RECT NTC TMEM CLAMP2 C5 CLAMP1 PD_DET PMODE WPG SCL CM_ILIM ILIM R1 RMEM FOD RFOD R10 SDA PGND ROS RECT Figure 32. bq51025 Embedded in a System Board 34 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 10.2.3 Standalone 10-V Power Supply With 1-A Maximum Output Current for 2S Charging System For the bq51025 to work properly as a supply to a 2S charger, the bq51025 output voltage must not drop below the minimum input charging voltage of the charger, which may be around 9 V depending on the charger IC. In a WPC tuned Rx/TX system, the power delivered to the load may change during Rx/Tx communication due to the capacitive modulation when CCOMM1 and CCOMM2 are connected form AC1 and AC2 pins to ground. If the power delivered to the load decreases, the VRECT voltage will drop and so may VOUT. if the charger IC does not have input DPM. If the power delivered to the load does not change or increases for a given current, the VRECT voltage will increase and the bq51025 will regulate the voltage. NOTE The following design example is for a 2S charging system where the charger IC does not have input DPM feature. bq51025 AD-EN System Load AD OUT CCOMM1 C4 COMM1 R7 CBOOT1 BOOT1 C1 RECT DCLAMP RECT C3 AC1 R6 R8 VO_REG COIL R9 VIREG AC2 CBOOT2 BOOT2 HOST TS/CTRL COMM2 CCOMM2 OUT NTC TMEM CLAMP2 C5 CLAMP1 RMEM PD_DET PMODE WPG SCL CM_ILIM D1 ILIM R1 FOD RFOD SDA PGND ROS RECT Figure 33. bq51025 Embedded in a 2S Battery System Board Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 35 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 10.2.3.1 Design Requirements Table 21. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VOUT 10 V IOUT MAXIMUM 1A 10.2.3.2 Detailed Design Procedure To start the design procedure, determine the following: • Output voltage • Maximum output current 10.2.3.3 Output Voltage Set Point The output voltage of the bq51025 device can be set by adjusting a feedback resistor divider network as described in Output Voltage Set Point. The ratio of VO_REG and VIREG resistor dividers are chosen to achieve 10-V based on the 0.5-V feedback voltage. Following Equation 12 and Equation 13, R6 and R7 are selected to be 11.3KΩ- and 215-kΩ, respectively. The same values are used on R9 and R8 in the VIREG divider. 10.2.3.4 Output and Rectifier Capacitors Set C4 to at least 3.3 µF. Set C3 to at least 44 µF to minimize output ripple. Use capacitors rated for 25 V or higher. 10.2.3.5 TMEM Follow procedure described in TMEM. 10.2.3.6 Maximum Output Current Set Point Follow the procedure described in Maximum Output Current Set Point. 10.2.3.7 I2C Connect I2C lines to ground. 10.2.3.8 Communication Current Limit Communication current limit must be disabled. Connect CM_ILIM pin to voltage supply making sure it does not exceed maximum absolute rating for the pin. If only the battery voltage is available, use a 5-V Zener diode (D1) to clamp the voltage. 10.2.3.9 Receiver Coil The receiver coil design is the most open part of the system design. The choice of the receiver inductance, shape, and materials all intimately influence the parameters themselves in an intertwined manner. This design can be complicated and involves optimizing many different aspects. The typical choice of the inductance of the receiver coil for a 10-W, 10-V solution is between 15 and 16 µH. 10.2.3.10 Series Resonant Capacitors In order for the bq51025 to work properly as a supply to a 2S charger, the bq51025 output voltage must not drop below the minimum input charging voltage of the charger, which may be around 9 V depending on the charger IC. In a WPC tuned Rx/Tx system, the power delivered to the load may change during Rx/Tx communication due to the capacitive modulation when CCOMM1 and CCOMM2 are connected from AC1 and AC2 pins to ground. If the power delivered to the load decreases, the VRECT voltage will drop and so may VOUT if the charger IC does not have VIN-DPM function. If the power delivered to the load does not change or increases for a given current, the VRECT voltage will increase and the bq51025 will regulate the voltage to a fixed value. The following section discusses the tuning procedure to ensure that the output voltage level is maintained during communication when operating with a bq51025 based transmitter. 36 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 10.2.3.10.1 Tuning Procedure NOTE The following tuning procedure results in a system that is not compliant with WPC specification and is only designed to operate with a given bq500215 based transmitter. 1. Measure the effective self-inductance of the bq500215 based transmitter (primary) coil, LP' , and receiver (secondary) coil, LS'. The measurements must be done on the final charging system setup (that is, battery and any other friendly metal of the device is included as well as any cover material that determines the distance between the coil and charging surface). Make the measurement at the optimal alignment position. 2. Measure the mutual inductance, LM and calculate the coupling factor given by: k LM LS ' LP ' (20) 3. A first-order approximation of the series capacitance is given by: 1 C1 ( 2S f ) 2 LS ' (1 k 2 ) k 2 LS ' 4S f C P LP ' (21) Where f is the operating frequency of the transmitter, which is 130 kHz and CP is the transmitter resonant capacitance which is 247 nF. 4. Make sure C1 as well as CCOMM1 and CCOMM2 are populated and place the receiver with best possible alignment on the transmitter and start power transfer. Using an oscilloscope, monitor the VRECT voltage during communication at maximum load. If VRECT decreases during communication, increase C1 until the voltage remains flat. Note that the larger the VRECT voltage increase is during communication at maximum load, the larger the losses on the device. The voltage increase in VRECT is larger with lower load and lower coupling, so it is important to keep the VRECT voltage as low as possible during communication at maximum load and coupling to maximize efficiency across charging area and load range. Figure 35 and Figure 36 show how the VRECT voltage behavior after tuning 10.2.3.11 Communication, Boot, and Clamp Capacitors Set CCOMMx to a value ranging from C1 / 8 to C1 / 3. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. For this example 56-nF capacitors are chosen. Set CBOOTx as 15 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. CCLAMPx is not populated since a external clamping diode is used. 10.2.3.12 VRECT Clamp Connect a 12-V Zener diode (DCLAMP) from VRECT to ground. This diode prevents the rectifier voltage from overshoot above VRECT-OVP level, preventing unwanted resets during large load transients during communication. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 37 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 10.2.3.13 Application Curves CH1 = VRECT CH1 = VRECT CH2 = VOUT CH4 = ILOAD Figure 35. 10-V Tuned RX VOUT at Center Position With 1-A Load Figure 34. 10-V Tuned RX Start-Up With 1-A Load CH1 = VRECT CH2 = VOUT CH4 = ILOAD CH2 = VOUT CH4 = ILOAD CH1 = VRECT Figure 36. 10-V Tuned RX VOUT at Center Position With No load CH2 = VOUT CH4 = ILOAD Figure 37. 1-A to 0-mA Load Dump With 10-V Tuned RX 100% 90% 80% Efficiency 70% 60% 50% 40% 30% 20% 10% CH1 = VRECT CH2 = VOUT CH4 = ILOAD 0 0 Figure 38. 100-mA to 1-A Load Transient With 10-V Tuned RX 38 Submit Documentation Feedback 0.1 0.2 0.3 0.4 0.5 0.6 IOUT (A) 0.7 0.8 0.9 1 D016 Figure 39. Efficiency With 10-V Tuned RX Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 11 Power Supply Recommendations These devices are intended to be operated within the ranges shown in the Recommended Operating Conditions. Because the system involves a loosely coupled inductor setup, the voltages produced on the receiver are a function of the inductances and the available magnetic field. Ensure that the design in the worst case keeps the voltages within the Absolute Maximum Ratings. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 39 bq51025 SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 www.ti.com 12 Layout 12.1 Layout Guidelines • • • • • • Keep the trace resistance as low as possible on AC1, AC2, and OUT. Detection and resonant capacitors need to be as close to the device as possible. COMM, CLAMP, and BOOT capacitors need to be placed as close to the device as possible. Via interconnect on GND net is critical for appropriate signal integrity and proper thermal performance. High-frequency bypass capacitors need to be placed close to RECT and OUT pins. ILIM and FOD resistors are important signal paths and the loops in those paths to GND must be minimized. Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main source of noise in the board. These traces should be shielded from other components in the board. It is usually preferred to have a ground copper area placed underneath these traces to provide additional shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components. For a 1.4-A fast-charge current application, the current rating for each net is as follows: • AC1 = AC2 = 2.2 A • OUT = 2.5 A • RECT = 200 mA (RMS) • COMMx = 600 mA • CLAMPx = 1000 mA • All others can be rated for 10 mA or less. 12.2 Layout Example AD is also a power trace. Keep the trace resistance as low as possible on AC1, AC2, and OUT. Isolate noisy traces using GND trace. Place signal and sensing components as close as possible to the IC. Place detection and resonant capacitors Cd and Cs here. It is always a good practice to place high frequency bypass capacitors next to RECT and OUT. The via interconnect is important and must be optimized near the power pad of the IC and the GND for good thermal dissipation. Place COMM, CLAMP, and BOOT capacitors as close as possible to the IC terminals. Figure 40. Layout Recommendation 40 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 bq51025 www.ti.com SLUSBX7B – SEPTEMBER 2014 – REVISED MARCH 2015 13 Device and Documentation Support 13.1 Trademarks All trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: bq51025 41 PACKAGE OPTION ADDENDUM www.ti.com 13-Nov-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) BQ51025YFPR ACTIVE DSBGA YFP 42 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BQ51025 BQ51025YFPT ACTIVE DSBGA YFP 42 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BQ51025 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 13-Nov-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Nov-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) BQ51025YFPR DSBGA YFP 42 3000 330.0 12.4 BQ51025YFPT DSBGA YFP 42 250 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.99 3.71 0.81 8.0 12.0 Q1 2.99 3.71 0.81 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Nov-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ51025YFPR DSBGA YFP 42 3000 367.0 367.0 35.0 BQ51025YFPT DSBGA YFP 42 250 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE YFP0042 DSBGA - 0.5 mm max height SCALE 4.700 DIE SIZE BALL GRID ARRAY B E A BUMP A1 CORNER D C 0.5 MAX SEATING PLANE BALL TYP 0.19 0.13 0.05 C 2 TYP SYMM G F D: Max = 3.586 mm, Min =3.526 mm E SYMM 2.4 TYP E: Max = 2.874 mm, Min =2.814 mm D C 0.3 0.2 0.015 42X B C A B A 0.4 TYP 1 2 3 4 5 6 0.4 TYP 4221555/B 04/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YFP0042 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 42X ( 0.23) 1 2 3 4 6 5 A (0.4) TYP B C SYMM D E F G SYMM LAND PATTERN EXAMPLE SCALE:25X ( 0.23) METAL 0.05 MAX METAL UNDER SOLDER MASK 0.05 MIN ( 0.23) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221555/B 04/2015 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com EXAMPLE STENCIL DESIGN YFP0042 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 42X ( 0.25) 1 2 4 3 5 6 A (0.4) TYP METAL TYP B C SYMM D E F G SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X 4221555/B 04/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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