16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs AD4000/AD4004/AD4008 Data Sheet FEATURES and AD4008 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs, respectively. They incorporate ease of use features that reduce signal chain power consumption, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive these ADCs directly while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off of common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes Low power 9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS (VDD only) 70 µW at 10 kSPS, 14 mW at 2 MSPS (total) SNR: 93 dB typical at 1 kHz, VREF = 5 V; 90 dB typical at 100 kHz THD: −115 dB typical at 1 kHz, VREF = 5 V; −95 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Pseudo differential (single-ended) analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay, valid first conversion First conversion accurate Guaranteed operation: −40°C to +125°C SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface Ability to daisy-chain multiple ADCs and busy indicator 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Operating from a 1.8 V supply, the AD4000/AD4004/AD4008 sample an analog input (IN+) from 0 V to VREF with respect to a ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V. The AD4000 consumes only 14 mW at 2 MSPS with a minimum SCK rate of 70 MHz in turbo mode, the AD4004 consumes only 7 mW at 1 MSPS, and the AD4008 consumes only 3.5 mW at 500 kSPS. The AD4000/AD4004/AD4008 all achieve ±1.0 LSB integral nonlinearity error (INL) maximum, guaranteed no missing codes at 16 bits, and 93 dB signal-to-noise ratio (SNR) for 1 kHz inputs. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus, and provides an optional busy indicator. The AD4000/AD4004/AD4008 are compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. APPLICATIONS Automatic test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems The AD4000/AD4004 are available in a 10-lead MSOP and a 10-lead LFCSP, and the AD4008 is available in a 10-lead LFCSP, with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). GENERAL DESCRIPTION The AD4000/AD4004/AD4008 are low noise, low power, high speed, 16-bit, precision successive approximation register (SAR) analog-to-digital converters (ADCs). The AD4000, AD4004, FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V VREF VREF /2 0 IN+ HIGH-Z MODE REF AD4000/ AD4004/ AD4008 16-BIT SAR ADC IN– VDD VIO TURBO MODE SERIAL INTERFACE STATUS BITS SPAN CLAMP COMPRESSION GND 1.8V TO 5V SDI SCK SDO 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) CNV 14956-001 10µF 1.8V Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4000/AD4004/AD4008 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 20 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 21 General Description ......................................................................... 1 Ease of Drive Features ............................................................... 22 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 23 Revision History ............................................................................... 3 Power Supply............................................................................... 24 Specifications..................................................................................... 4 Digital Interface .......................................................................... 24 Timing Specifications .................................................................. 7 Register Read/Write Functionality........................................... 25 Absolute Maximum Ratings............................................................ 9 Status Word ................................................................................. 27 Thermal Resistance ...................................................................... 9 CS Mode, 3-Wire Turbo Mode ................................................. 28 ESD Caution .................................................................................. 9 CS Mode, 3-Wire Without Busy Indicator ............................. 29 Pin Configurations and Function Descriptions ......................... 10 CS Mode, 3-Wire with Busy Indicator .................................... 30 Typical Performance Characteristics ........................................... 11 CS Mode, 4-Wire Turbo Mode ................................................. 31 Terminology .................................................................................... 16 CS Mode, 4-Wire Without Busy Indicator ............................. 32 Theory of Operation ...................................................................... 17 Circuit Information .................................................................... 17 Converter Operation .................................................................. 18 Transfer Functions...................................................................... 18 Applications Information .............................................................. 19 Typical Application Diagrams .................................................. 19 CS Mode, 4-Wire with Busy Indicator .................................... 33 Daisy-Chain Mode ..................................................................... 34 Layout Guidelines....................................................................... 35 Evaluating the AD4000/AD4004/AD4008 Performance .......... 35 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 36 Rev. C | Page 2 of 36 Data Sheet AD4000/AD4004/AD4008 REVISION HISTORY 10/2017—Rev. B to Rev. C Changes to Features Section ............................................................ 1 Added Multiplexed Applications Section ....................................21 Changes to Ordering Guide ...........................................................36 9/2017—Rev. A to Rev. B Added AD4008 ................................................................... Universal Changes to Title, Features Section, General Description Section, and Figure 1........................................................................................ 1 Changes to Table 1 ............................................................................ 4 Changes to Timing Specifications Section and Table 2................ 7 Changes to Table 4 ............................................................................ 8 Changes to Table 5 ............................................................................ 9 Changes to Typical Performance Characteristics Section Layout .. 11 Changes to Figure 19 ............................................................................... 13 Added Figure 25; Renumbered Sequentially ...............................14 Changes to Figure 28 ......................................................................14 Change to Zero Error Definition, Terminology Section............16 Changes to Circuit Information Section and Table 8 .................17 Changes to Converter Operation Section and Note 1 and Note 2, Table 9 .................................................................................18 Changes to High Frequency Input Signals Section, Figure 36 Caption, and Figure 37 Caption ....................................................21 Added Figure 38 ..............................................................................21 Changes to Input Span Compression Section, High-Z Mode Section, Figure 40, and Figure 41 Caption ...................................22 Changes to Figure 42 Caption, Figure 43 Caption, Power Supply Section, and Figure 44 Caption .....................................................23 Changes to Figure 45, Digital Interface Section, and Table 11 ........ 24 Changes to Register Read/Write Functionality Section and Figure 46 Caption ............................................................................25 Changes to CS Mode, 3-Wire Turbo Mode Section ...................28 Changes to CS Mode, 3-Wire with Busy Indicator Section .......30 Changes to CS Mode, 4-Wire Turbo Mode Section ...................31 Changes to CS Mode, 4-Wire with Busy Indicator Section .......33 Changes to Daisy-Chain Mode Section .......................................34 Changed Evaluating the AD4000/AD4004 Performance Section to Evaluating the AD4000/AD4004/AD4008 Performance Section ..............................................................................................35 Changes to Evaluating the AD4000/AD4004/AD4008 Performance Section .......................................................................35 Changes to Ordering Guide ...........................................................36 4/2017—Rev. 0 to Rev. A Added AD4004 ................................................................... Universal Changes to Title, Features Section, General Description Section, and Figure 1 ....................................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Table 7 ............................................................................ 9 Changes to Figure 19 and Figure 21 ............................................. 12 Changes to Figure 24 ...................................................................... 13 Added Figure 25; Renumbered Sequentially ............................... 13 Moved Terminology Section ......................................................... 15 Changes to Circuit Information Section and Table 8 ................. 16 Changes to Figure 33 ...................................................................... 18 Changes to RC Filters Section ....................................................... 19 Changes to High Frequency Input Signals Section .................... 20 Changes to High-Z Mode Section, Figure 38, and Figure 39 .... 21 Changes to Long Acquisition Phase Section and Figure 43 ...... 22 Changes to Digital Interface Section and Register Read/Write Functionality Section ...................................................................... 23 Changes to Figure 45 ...................................................................... 24 Changes to CS Mode, 3-Wire Turbo Mode Section ................... 26 Added Figure 48 .............................................................................. 26 Changes to CS Mode, 4-Wire Turbo Mode ................................. 29 Added Figure 54 .............................................................................. 29 Changes to Figure 56 and Figure 57 ............................................. 30 Changes to Layout Guidelines Section and Evaluating the AD4000/AD4004 Performance Section ....................................... 33 Updated Outline Dimensions........................................................ 34 Changes to Ordering Guide Section............................................. 34 10/2016—Revision 0: Initial Version Rev. C | Page 3 of 36 AD4000/AD4004/AD4008 Data Sheet SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input Current Test Conditions/Comments Min 16 IN+ voltage (VIN+) − IN− voltage (VIN−) VIN+ to GND VIN− to GND Span compression enabled Acquisition phase, T = 25°C High-Z mode enabled, converting dc input at 2 MSPS 0 −0.1 −0.1 0.1 × VREF THROUGHPUT Complete Cycle AD4000 AD4004 AD4008 Conversion Time Acquisition Phase 1 AD4000 AD4004 AD4008 Throughput Rate 2 AD4000 AD4004 AD4008 Transient Response 3 DC ACCURACY No Missing Codes Integral Nonlinearity Error (INL) 500 1000 2000 270 Max Unit Bits VREF VREF + 0.1 +0.1 0.9 × VREF 0.3 1 V V V V nA µA 290 ns ns ns ns 320 290 790 1790 ns ns ns 0 0 0 2 1 500 150 16 −1.0 −0.8 −0.5 T = 0°C to 85°C Differential Nonlinearity Error (DNL) Transition Noise Zero Error Zero Error Drift 4 Gain Error Gain Error Drift4 Power Supply Sensitivity 1/f Noise 5 AC ACCURACY Dynamic Range Total RMS Noise fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) Oversampled Dynamic Range Typ −4.5 −0.55 −20 −0.92 VDD = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz 91 91 Oversampling ratio (OSR) = 256, VREF = 5 V Rev. C | Page 4 of 36 MSPS MSPS kSPS ns 0.5 6 Bits LSB LSB LSB LSB LSB ppm/°C LSB ppm/°C LSB µV p-p 93.5 37 dB µV rms 93 112 −115 92.5 dB dB dB dB 117 dB ±0.2 ±0.2 ±0.15 0.5 ±3 +1.0 +0.8 +0.5 +4.5 +0.55 +20 +0.92 Data Sheet Parameter fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR SFDR THD SINAD fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter REFERENCE Voltage Range, VREF Current AD4000 AD4004 AD4008 INPUT OVERVOLTAGE CLAMP IN+/IN− Current, IIN+/IIN− VIN+/VIN− at Maximum IIN+/IIN− VIN+/VIN− Clamp On/Off Threshold Deactivation Time REF Current at Maximum IIN+ DIGITAL INPUTS Logic Levels Input Low Voltage, VIL Input High Voltage, VIH AD4000/AD4004/AD4008 Test Conditions/Comments Typ 85.5 87.5 115 −113 87 dB dB dB dB 90 −95 89 dB dB dB 85 −91 84 10 1 1 dB dB dB MHz ns ps rms 85.5 2.4 VREF = 5 V 2 MSPS 1 MSPS 500 kSPS Max 5.1 0.75 0.325 0.185 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V 5.25 2.68 VIN+ > VREF VIO > 2.7 V VIO ≤ 2.7 V VIO > 2.7 V VIO ≤ 2.7 V mA mA V V V V ns µA +0.3 × VIO +0.2 × VIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V µA µA pF Serial 16 bits, straight binary Conversion results available immediately after completed conversion 0.4 VIO − 0.3 1.71 1.71 VDD and VIO = 1.8 V, T = 25°C Rev. C | Page 5 of 36 1.8 1.6 V 50 50 6 ISINK = 500 µA ISOURCE = −500 µA Unit mA mA mA 5.4 3.1 5.4 2.8 360 100 −0.3 −0.3 0.7 × VIO 0.8 × VIO −1 −1 Input Low Current, IIL Input High Current, IIH Input Pin Capacitance DIGITAL OUTPUTS Data Format Pipeline Delay Output Low Voltage, VOL Output High Voltage, VOH POWER SUPPLIES VDD VIO Standby Current Min 1.89 5.5 V V V V µA AD4000/AD4004/AD4008 Parameter Power Dissipation VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance Data Sheet Test Conditions/Comments VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 500 kSPS, high-Z mode enabled 1 MSPS, high-Z mode enabled 2 MSPS, high-Z mode enabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 500 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled Min TMIN to TMAX −40 Typ 70 3.5 7 14 4 8 16 2.5 4.9 9.75 0.9 1.9 3.75 0.1 0.2 0.5 7 Max 4.2 8.2 16 5 9.9 19 +125 Unit µW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW nJ/sample °C The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 23. 1 Rev. C | Page 6 of 36 Data Sheet AD4000/AD4004/AD4008 TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. See Figure 2 for the timing voltage levels. Table 2. Digital Interface Timing Parameter CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE ACQUISITION PHASE 1 AD4000 AD4004 AD4008 TIME BETWEEN CONVERSIONS AD4000 AD4004 AD4008 CNV PULSE WIDTH (CS MODE) 2 Symbol tCONV tACQ Min 270 Typ 290 Max 320 Unit ns SCK PERIOD (CS MODE) 3 VIO > 2.7 V VIO > 1.7 V SCK PERIOD (DAISY-CHAIN MODE) 4 VIO > 2.7 V VIO > 1.7 V SCK LOW TIME SCK HIGH TIME SCK FALLING EDGE TO DATA REMAINS VALID DELAY SCK FALLING EDGE TO DATA VALID DELAY VIO > 2.7 V VIO > 1.7 V CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) VIO > 2.7 V VIO > 1.7 V CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY 5 CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tSCK tQUIET1 tQUIET2 tDIS 190 60 SDI VALID SETUP TIME FROM CNV RISING EDGE SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tSSDICNV tHSDICNV 2 2 ns ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV tSSDISCK tHSDISCK 12 2 2 ns ns ns 290 790 1790 ns ns ns 500 1000 2000 10 ns ns ns ns 9.8 12.3 ns ns 20 25 3 3 1.5 ns ns ns ns ns tCYC tCNVH tSCK tSCKL tSCKH tHSDO tDSDO 7.5 10.5 ns ns 10 13 ns ns ns ns ns tEN 20 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2. 1 Y% VIO1 X% VIO1 tDELAY VIH2 VIL2 VIH2 VIL2 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30. VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1. 2MINIMUM Figure 2. Voltage Levels for Timing Rev. C | Page 7 of 36 14956-002 tDELAY AD4000/AD4004/AD4008 Data Sheet Table 3. Register Read/Write Timing Parameter READ/WRITE OPERATION CNV Pulse Width 1 SCK Period VIO > 2.7 V VIO > 1.7 V SCK Low Time SCK High Time READ OPERATION CNV Low to SDO D15 MSB Valid Delay VIO > 2.7 V VIO > 1.7 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 2.7 V VIO > 1.7 V CNV Rising Edge to SDO High Impedance WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CNV Rising Edge to SCK Edge Hold Time CNV Falling Edge to SCK Active Edge Setup Time 1 Symbol Min tCNVH tSCK 10 ns 9.8 12.3 3 3 ns ns ns ns tSCKL tSCKH Typ Max Unit tEN tHSDO tDSDO ns ns ns 7.5 10.5 20 ns ns ns 1.5 tDIS tSSDISCK tHSDISCK tHCNVSCK tSCNVSCK 10 13 2 2 0 6 ns ns ns ns For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode 3-Wire and 4-Wire Turbo Mode and Six Status Bits 3-Wire and 4-Wire Mode 3-Wire and 4-Wire Mode and Six Status Bits Test Conditions/Comments fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V Rev. C | Page 8 of 36 Min Typ Max Unit 2 2 2 1.86 1.82 1.69 1.64 1.5 MSPS MSPS MSPS MSPS MSPS MSPS MSPS MSPS Data Sheet AD4000/AD4004/AD4008 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 5. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering ESD Ratings Human Body Model Machine Model Field Induced Charged Device Model 1 2 Rating Table 6. Thermal Resistance −0.3 V to VREF + 0.4 V or ±130 mA2 −0.3 V to +6.0 V −0.3 V to +2.1 V −6 V to +2.4 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 260°C reflow as per JEDEC J-STD-020 Package Type1 RM-10 CP-10-9 θJA2 147 114 θJC3 38 33 Unit °C/W °C/W Test Condition 1: thermal impedance simulated values are based upon use of 2S2P JEDEC PCB. See the Ordering Guide. 2 θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. 3 θJC is the junction-to-case thermal resistance. 1 ESD CAUTION 4 kV 200 V 1.25 kV See the Analog Inputs section for an explanation of IN+ and IN−. Current condition tested over a 10 ms time interval. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 9 of 36 AD4000/AD4004/AD4008 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN+ 3 10 VIO AD4000/ AD4004 IN+ 3 TOP VIEW (Not to Scale) GND 5 9 SDI 8 SCK 7 SDO 6 CNV GND 5 TOP VIEW (Not to Scale) 10 VIO 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. 14956-003 REF 1 VDD 2 IN– 4 IN– 4 AD4000/ AD4004/ AD4008 14956-004 REF 1 VDD 2 Figure 4. 10-Lead LFCSP Pin Configuration Figure 3. 10-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 VDD IN+ P AI 4 5 6 IN− GND CNV AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P N/A 2 EPAD P 1 2 Description Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 µF, X7R ceramic capacitor. 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. Analog Input. This input is referred to analog ground sense pin (IN−). The device samples the voltage differential between IN+ and IN− on the leading edge on CNV. The operating input range of IN+ − IN− is 0 V to VREF. Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet the specified performance. AI is analog input, P is power, DI is digital input, and DO is digital output. N/A means not applicable. Rev. C | Page 10 of 36 Data Sheet AD4000/AD4004/AD4008 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted. 0.5 0.20 +125°C +25°C –40°C 0.4 0.15 0.3 0.10 0.1 DNL (LSB) INL (LSB) 0.2 0 –0.1 0.05 0 –0.05 –0.2 –0.10 –0.3 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE –0.20 14956-200 –0.5 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V 14956-203 +125°C +25°C –40°C –0.15 –0.4 Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V 0.3 0.20 +125°C +25°C –40°C 0.2 0.15 0.10 DNL (LSB) INL (LSB) 0.1 0 0.05 0 –0.05 –0.1 –0.10 –0.2 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE –0.20 14956-201 –0.3 0 16384 24576 32768 40960 49152 57344 65536 CODE Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V 0.4 0.20 0.3 0.15 0.2 0.10 0.1 0.05 DNL (LSB) 0 –0.1 0 –0.05 –0.2 –0.10 –0.3 –0.15 SPAN COMPRESSION ENABLED HIGH-Z ENABLED 0 8192 16384 24576 32768 CODE 40960 49152 57344 65536 –0.20 14956-202 –0.4 Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V SPAN COMPRESSION ENABLED HIGH-Z ENABLED 0 8192 16384 24576 32768 CODE 40960 49152 57344 65536 14956-205 INL (LSB) 8192 14956-204 +125°C +25°C –40°C –0.15 Figure 10. DNL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V Rev. C | Page 11 of 36 AD4000/AD4004/AD4008 Data Sheet 50000 90000 VREF = 2.5V VREF = 5V 45000 40000 70000 60000 CODE COUNT 30000 25000 20000 0 0 14956-206 ADC CODE 32760 32761 32762 32763 32764 32765 32766 32767 32768 32769 32770 32771 32772 32773 32774 32775 32776 32777 32778 32779 32780 10000 32760 32761 32762 32763 32764 32765 32766 32767 32768 32769 32770 32771 32772 32773 32774 32775 32776 32777 32778 32779 32780 5000 Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V ADC CODE Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and VREF = 5 V 0 0 VREF = 5V SNR = 92.47dB THD = –115.10dB SINAD = 92.41dB –40 –60 –80 –100 –120 –140 –160 –40 –60 –80 –100 –120 –140 10k 100k 1M –180 100 14956-207 1k 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), Wide View, VREF = 5 V 14956-210 –160 FREQUENCY (Hz) Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 2.5 V 0 0 VREF = 5V SNR = 90.16 dB THD = –94.52dB SINAD = 88.33dB –20 FUNDAMENTAL AMPLITUDE (dB) –40 VREF = 2.5V SNR = 87.54dB THD = –112.33dB SINAD = 87.49dB –20 FUNDAMENTAL AMPLITUDE (dB) –20 –180 100 14956-209 20000 10000 FUNDAMENTAL AMPLITUDE (dB) 40000 30000 15000 –60 –80 –100 –120 –140 –160 –40 VREF = 5V SNR = 84.65 dB THD = –90.80dB SINAD = 83.89dB –60 –80 –100 –120 –140 –160 –180 1k 10k 100k FREQUENCY (Hz) 1M 14956-211 FUNDAMENTAL AMPLITUDE (dB) 50000 Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View –180 1k 10k 100k FREQUENCY (Hz) Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View Rev. C | Page 12 of 36 1M 14956-208 CODE COUNT 35000 –20 VREF = 2.5V VREF = 5V 80000 Data Sheet AD4000/AD4004/AD4008 –110 15.3 ENOB SINAD SNR 93 15.2 113 THD SFDR –111 112 15.1 111 –112 15.0 14.8 90 14.7 110 –113 THD (dB) 14.9 91 ENOB (Bits) 109 –114 108 –115 107 –116 108 14.5 88 –117 107 14.4 3.3 3.6 3.9 4.2 4.5 14.3 5.1 4.8 –118 2.4 REFERENCE VOLTAGE (V) 4.5 106 5.1 4.8 111 THD SFDR –102 15.10 110 –104 109 –106 108 –108 107 –110 106 –112 105 –114 104 91.6 –116 103 91.4 –40 –118 –40 92.8 92.4 92.2 15.00 THD (dB) 15.05 ENOB (Bits) 92.6 92.0 91.8 14.95 14.90 –20 0 20 40 60 80 100 14956-220 120 TEMPERATURE (°C) 40 60 80 100 120 93.4 DYNAMIC RANGE fIN = 1kHz fIN = 10kHz 15.25 93.2 115 15.20 SNR, SINAD (dB) 93.0 110 105 15.15 92.8 15.10 92.6 15.05 100 92.4 95 92.2 15.00 ENOB SINAD SNR 92.0 1 2 4 8 16 32 64 128 DECIMATION RATE 256 512 1024 2048 14956-214 SNR (dB) 20 Figure 21. THD and SFDR vs. Temperature, fIN = 1 kHz 125 90 0 TEMPERATURE (°C) Figure 18. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz 120 102 –20 ENOB (Bits) SNR, SINAD (dB) 3.3 3.6 3.9 4.2 REFERENCE VOLTAGE (V) –100 15.15 SNR SINAD ENOB 93.0 3.0 Figure 20. THD and SFDR vs. Reference Voltage, fIN = 1 kHz Figure 17. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference Voltage, fIN = 1 kHz 93.2 2.7 SFDR (dB) 3.0 14956-222 2.7 14956-213 87 2.4 14956-216 14.6 89 Figure 19. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS Rev. C | Page 13 of 36 14.95 0 10 20 30 40 50 60 tQUIET2 (ns) Figure 22. SNR, SINAD, and ENOB vs. tQUIET2 70 14956-217 SNR, SINAD (dB) 92 SFDR (dB) 94 AD4000/AD4004/AD4008 Data Sheet ZERO ERROR AND GAIN ERROR (LSB) 1.0 953 952 951 950 0 2 4 6 8 10 TIME (Seconds) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 7 3.0 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 3.5 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 4 3 2 0 20 40 60 80 100 120 60 80 100 120 2.5 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 2.0 1.5 1.0 0 –40 14956-226 –20 TEMPERATURE (°C) –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 24. Operating Current vs. Temperature, AD4000, 2 MSPS Figure 27. Operating Current vs. Temperature, AD4004, 1 MSPS 2.0 0.8 1.8 1.6 1.4 1.2 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 1.0 0.8 0.6 0.4 0.6 0.5 0.4 0.3 0.2 0.1 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 14956-325 0.2 0 –40 2MSPS 1MSPS 500kSPS 0.7 REFERENCE CURRENT (mA) OPERATING CURRENT (mA) 40 0.5 1 0 –40 20 Figure 26. Zero Error and Gain Error vs. Temperature 8 5 0 TEMPERATURE (°C) Figure 23. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples Averaged per Reading 6 –20 14956-232 948 14956-218 949 ZERO ERROR GAIN ERROR 0.8 Figure 25. Operating Current vs. Temperature, AD4008, 500 kSPS 0 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 REFERENCE VOLTAGE (V) Figure 28. Reference Current vs. Reference Voltage Rev. C | Page 14 of 36 5.1 14956-219 ADC OUTPUT READING (µV) 954 14956-223 955 Data Sheet AD4000/AD4004/AD4008 23 12 11 VIO = 5.0V VIO = 3.3V VIO = 1.8V 21 19 9 17 tDSDO (ns) 8 7 6 5 15 13 11 4 3 9 2 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 Figure 29. Standby Current vs. Temperature 5 0 20 40 60 80 100 120 140 160 180 LOAD CAPACITANCE (pF) Figure 30. tDSDO vs. Load Capacitance Rev. C | Page 15 of 36 200 220 14956-228 7 1 14956-224 STANDBY CURRENT (µA) 10 AD4000/AD4004/AD4008 Data Sheet TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 32). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal voltage that results in the first code transition (½ LSB above analog ground) and the actual voltage producing that code. Gain Error The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±0.5 LSB accuracy. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. ENOB = (SINADdB − 1.76)/6.02 ENOB is expressed in bits. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. C | Page 16 of 36 Data Sheet AD4000/AD4004/AD4008 THEORY OF OPERATION IN+ SWITCHES CONTROL LSB MSB REF 32,768C 16,384C 4C 2C C SW+ C BUSY COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 14956-006 CNV IN– Figure 31. ADC Simplified Schematic CIRCUIT INFORMATION The AD4000/AD4004/AD4008 are high speed, low power, singlesupply, precise, 16-bit pseudo differential ADCs based on a SAR architecture. The AD4000 is capable of converting 2,000,000 samples per second (2 MSPS), the AD4004 is capable of converting 1,000,000 samples per second (1 MSPS), and the AD4008 is capable of converting 500,000 samples per second (500 kSPS). The power consumption of the AD4000/AD4004/AD4008 scales with throughput because they power down in between conversions. When operating at 10 kSPS, for example, they typically consume 70 µW, making them ideal for batterypowered applications. The AD4000/AD4004/AD4008 also have a valid first conversion after being powered down for long periods, which can further reduce power consumed in applications in which the ADC does not need to be constantly converting. The AD4000/AD4004/AD4008 provide the user with an on-chip track-and-hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. The AD4000/AD4004/AD4008 incorporate a multitude of unique ease of use features that result in a lower system power and smaller footprint. The AD4000/AD4004/AD4008 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. This combination allows the use of lower bandwidth and lower power amplifiers as drivers. It has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 14). When high-Z mode is enabled, the ADC input has a low input charging current at low input signal frequencies as well as improved distortion over a wide frequency range up to 100 kHz. For frequencies greater than 100 kHz and multiplexing, disable high-Z mode. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4000/AD4004/AD4008, along with turbo mode, allows low clock rates to read back conversions, even when running at their respective maximum throughput rates. Note that, for the AD4000, the full throughput rate of 2 MSPS can be achieved only with turbo mode enabled. The AD4000/AD4004/AD4008 can interface with any 1.8 V to 5 V digital logic family. These devices are available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. The AD4000/AD4004/AD4008 are pin for pin compatible with some of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs 400 kSPS to 500 kSPS Bits 201 181 100 kSPS 250 kSPS AD7989-12 AD76912 AD40112, AD76902, AD7989-52 161 AD7684 AD76872 163 AD7680, AD7683, AD7988-12 AD76852, AD7694 AD76882, AD76932, AD79162 AD76862, AD7988-52, AD40082 143 AD7940 AD79422 1 2 3 True differential. Pin for pin compatible. Pseudo differential. Rev. C | Page 17 of 36 AD79462 ≥1000 kSPS AD40202 AD40032, AD40072, AD79822, AD79842 AD40012, AD40052, AD79152 AD40002, AD40042, AD79802, AD79832 Not applicable AD4000/AD4004/AD4008 Data Sheet During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via the SW+ and SW− switches. All independent switches connect the other terminal of each capacitor to the analog inputs. The capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. The differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and VREF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …, VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and a busy signal indicator. TRANSFER FUNCTIONS The ideal transfer characteristics for the AD4000/AD4004/AD4008 are shown in Figure 32 and Table 9. 111...111 111...110 111...101 000...010 000...001 000...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 14956-007 The AD4000/AD4004/AD4008 are SAR-based ADCs using a charge redistribution sampling digital-to-analog converter (DAC). Figure 31 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the comparator inputs. Because the AD4000, the AD4004, and the AD4008 have onboard conversion clocks, the serial clock, SCK, is not required for the conversion process. ADC CODE (STRAIGHT BINARY) CONVERTER OPERATION Figure 32. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Table 9. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 2 Analog Input, VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 µV 0V VREF = 5 V with Span Compression Enabled (V) 4.499939 2.500061 2.5 2.499939 0.50006103 0.5 Digital Output Code 0xFFFF1 0x8001 0x8000 0x7FFF 0x0001 0x00002 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.9 × VREF with span compression enabled). This output code is also the code for an underranged analog input (VIN+ − VIN− below 0 V with span compression disabled and below 0.1 × VREF with span compression enabled). Rev. C | Page 18 of 36 Data Sheet AD4000/AD4004/AD4008 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS Figure 34 shows a recommended connection diagram when using a single-supply system. This setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. Figure 33 shows an example of the recommended connection diagram for the AD4000/AD4004/AD4008 when multiple supplies are available. This configuration is used for best performance because the amplifier supplies can be selected to allow the maximum signal range. V+ ≥ +6.5V REF1 LDO 1.8V AMP VCM = VREF /2 5V 10kΩ 100nF 10kΩ 1.8V TO 5V HOST SUPPLY R VREF VCM = VREF /2 100nF 10µF V+ AMP REF C 0V VDD VIO SDI IN+ V– AD4000/ AD4004/ AD4008 SCK DIGITAL HOST (MICROPROCESSOR/ FPGA) SDO IN– CNV GND 14956-008 3-WIRE/4-WIRE INTERFACE V– ≤ –0.5V Figure 33. Typical Application Diagram with Multiple Supplies V+ = 5V REF1 LDO AMP VCM = VREF /2 4.096V 10kΩ 10kΩ 1.8V 100nF 100nF 1.8V TO 5V HOST SUPPLY 10µF1 R 0.9 × VREF VCM = VREF /2 0.1 × VREF AMP REF C VDD VIO SDI IN+ AD4000/ AD4004/ AD40082 3 IN– SCK SDO DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV GND 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE 2SPAN COMPRESSION MODE ENABLED. 3SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION. SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R). Figure 34. Typical Application Diagram with a Single Supply Rev. C | Page 19 of 36 14956-009 3-WIRE/4-WIRE INTERFACE AD4000/AD4004/AD4008 Data Sheet ANALOG INPUTS Figure 35 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the AD4000/AD4004/AD4008. REF D1 VIN REXT RIN CIN IN+ CEXT CPIN D2 CLAMP 14956-010 0V TO 15V GND Figure 35. Equivalent Analog Input Circuit Input Overvoltage Clamp Circuit Most ADC analog inputs, IN+ and IN−, have no overvoltage protection circuitry apart from ESD protection diodes. During an overvoltage event, an ESD protection diode from an analog input pin (IN+ or IN−) to REF forward biases and shorts the input pin to REF, potentially overloading the reference or causing damage to the device. The AD4000/AD4004/AD4008 internal overvoltage clamp circuit with a larger external resistor (REXT = 200 Ω) eliminates the need for external protection diodes and protects the ADC inputs against dc overvoltages. In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range of the device. In this case, the AD4000/AD4004/AD4008 internal voltage clamp circuit ensures that the voltage on the input pin does not exceed VREF + 0.4 V and prevents damage to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference, which is particularly important for systems that share the reference among multiple ADCs. If the analog input exceeds the reference voltage by 0.4 V, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. The clamp turns on before D1 (see Figure 35) and can sink up to 50 mA of current. When the clamp is active, it sets the overvoltage (OV) clamp flag bit in the register that can be read back (see Table 14), which is a sticky bit that must be read to be cleared. The status of the clamp can also be checked in the status bits using an OV clamp flag (see Table 15). The clamp circuit does not dissipate static power in the off state. Note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. The external RC filter is usually present at the ADC input to band limit the input signal. During an overvoltage event, excessive voltage is dropped across REXT, and REXT becomes part of a protection circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF for correct operation of the clamp. See Table 1 for input overvoltage clamp specifications. The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. By using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. Switched Capacitor Input During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 40 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are open, the input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and limits noise. RC Filter Values The RC filter value (represented by R and C in Figure 33 and Figure 34) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. Lower input signal bandwidth means that the RC cutoff can be lower, thereby reducing noise into the converter. For optimum performance at various throughputs, use the recommended RC values (200 Ω, 180 pF) and the ADA4805-1. The RC values shown in Table 10 are chosen for ease of drive considerations and greater ADC input protection. The combination of a large R value (200 Ω) and small C value results in a reduced dynamic load for the amplifier to drive. The smaller value of C means fewer stability and phase margin concerns with the amplifier. The large value of R limits the current into the ADC input when the amplifier output exceeds the ADC input range. Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths Input Signal Bandwidth (kHz) <10 <200 >200 Multiplexed R (Ω) See the High-Z Mode section 200 200 200 C (pF) See the High-Z Mode section 180 120 120 Rev. C | Page 20 of 36 Recommended Amplifier See the High-Z Mode section ADA4805-1 ADA4897-1 ADA4897-1 Data Sheet AD4000/AD4004/AD4008 DRIVER AMPLIFIER CHOICE Although the AD4000/AD4004/AD4008 are easy to drive, the driver amplifier must meet the following requirements: 14.0 ENOB (Bits) 14.2 86 13.8 13.6 82 13.4 10k 100k 14956-212 37 μV π 2 2 (37 μV ) + 2 f −3 dB (NeN ) 13.2 1M INPUT FREQUENCY (Hz) Figure 36. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C –80 High Frequency Input Signals The AD4000/AD4004/AD4008 ac performance over a wide input frequency range using a 5 V reference voltage is shown in Figure 36 and Figure 37. Unlike other traditional SAR ADCs, the AD4000/AD4004/AD4008 maintain exceptional ac performance for input frequencies up to the Nyquist frequency with minimal performance degradation. Note that the input frequency is limited to the Nyquist frequency of the sample rate in use. 115 –90 110 –95 105 –100 100 –105 95 –110 90 –115 85 –120 1k 10k SFDR (dB) –85 80 1M 100k 14956-215 For ac applications, the driver must have a THD performance commensurate with the AD4000/ AD4004/AD4008. For multichannel multiplexed applications, the driver amplifier and the analog input circuit of the AD4000/ AD4004/AD4008 must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0001525%, 15.25 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This settling may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. 120 THD SFDR INPUT FREQUENCY (Hz) Figure 37. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C Multiplexed Applications The AD4000/AD4004/AD4008 significantly reduce system complexity and cost for multiplexed applications that require superior performance in terms of noise, power, and throughput. Figure 38 shows a simplified block diagram of a multiplexed data acquisition system including a multiplexer, an ADC driver, and the precision SAR ADC. MULTIPLEXER R ADC DRIVER C SAR ADC R C R C C Figure 38. Multiplexed Data Acquisition Signal Chain Using the AD4000/AD4004/AD4008 Rev. C | Page 21 of 36 14956-040 • 14.4 88 80 1k where: f−3 dB is the input bandwidth, in megahertz, of the AD4000/ AD4004/AD4008 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. • 14.6 84 THD (dB) SNRLOSS = 20 log 15.0 14.8 90 SNR, SINAD (dB) The noise generated by the driver amplifier must be kept low enough to preserve the SNR and transition noise performance of the AD4000/AD4004/AD4008. The noise from the driver is filtered by the single-pole, low-pass filter of the analog input circuit made by RIN and CIN, or by the external filter, if one is used. Because the typical noise of the AD4000/AD4004/AD4008 is 37 µV rms, the SNR degradation due to the amplifier is ENOB SINAD SNR 92 SENSORS • 15.2 94 AD4000/AD4004/AD4008 Data Sheet 25 15 5 0 –5 –10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 14956-221 –25 INPUT DIFFERENTIAL VOLTAGE (V) Figure 40. Input Current vs. Input Differential Voltage, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C 90% OF VREF = 3.69V DIGITAL OUTPUT +FSR ALL 2N CODES ANALOG INPUT –FSR Figure 39. Span Compression The AD4000/AD4004/AD4008 incorporate high-Z mode, which reduces the nonlinear charge kickback when the capacitor DAC switches back to the input at the start of acquisition. Figure 40 shows the input current of the AD4000/AD4004/AD4008 with high-Z mode enabled and disabled. The low input current makes the ADC easier to drive than the traditional SAR ADCs available in the market, even with high-Z mode disabled. The input current reduces further to submicroampere range when high-Z mode is enabled. The high-Z mode is disabled by default but can be enabled by writing to the register (see Table 14). Disable high-Z mode for input frequencies above 100 kHz or when multiplexing. Additionally, the AD4000/AD4004/AD4008 can be driven with a much higher source impedance than traditional SARs, which means the resistor in the RC filter can have a value 10 times larger than previous SAR designs and with high-Z mode enabled can tolerate even larger impedance. Figure 41 shows the THD performance for various source impedances with high-Z mode disabled and enabled. –75 –80 –85 –90 500Ω HIGH-Z OFF 500Ω HIGH-Z ON 1000Ω HIGH-Z OFF 1000Ω HIGH-Z ON –95 –100 200Ω HIGH-Z OFF 200Ω HIGH-Z ON –105 –110 –115 1 2 5 10 INPUT FREQUENCY (kHz) 20 50 14956-225 ADC IN+ 14956-300 VREF = 4.096V To achieve the optimum data sheet performance from high resolution precision SAR ADCs, system designers are often forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor SAR ADC inputs for their precision applications, which is commonly encountered in designing a precision data acquisition signal chain. The benefits of high-Z mode are low input current for slow (<10 kHz) or dc type signals and improved distortion (THD) performance over a frequency range of up to 100 kHz. High-Z mode allows a choice of lower power and lower bandwidth precision amplifiers with a lower RC filter cutoff to drive the ADC, removing the need for dedicated high speed ADC drivers, which saves system power, size, and cost in precision, low bandwidth applications. High-Z mode allows the amplifier and RC filter in front of the ADC to be chosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor SAR ADC inputs. THD (dB) In single-supply applications, it is desirable to use the full range of the ADC; however, the amplifier can have some headroom and footroom requirements, which can be a problem, even if it is a rail-to-rail input and output amplifier. The AD4000/AD4004/ AD4008 include a span compression feature, which increases the headroom and footroom available to the amplifier by reducing the input range by 10% from the top and bottom of the range while still accessing all available ADC codes (see Figure 39). The SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the reduced input range when span compression is enabled. Span compression is disabled by default but can be enabled by writing to the relevant register bit (see the Digital Interface section). High-Z Mode 10 –20 Input Span Compression 10% OF VREF = 0.41V DISABLED, 2MSPS DISABLED, 1MSPS DISABLED, 500kSPS ENABLED, 2MSPS ENABLED, 1MSPS ENABLED, 500kSPS –15 EASE OF DRIVE FEATURES 5V HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z 20 INPUT CURRENT (μA) Switching multiplexer channels typically results in large voltage steps at the ADC inputs. To ensure an accurate conversion result, the step must be given adequate time to settle before the ADC samples its inputs (on the rising edge of CNV). The settling time error is dependent on the drive circuitry (multiplexer and ADC driver), RC filter values, and the time when the multiplexer channels are switched. Switch the multiplexer channels immediately after tQUIET1 has elapsed from the start of the conversion to maximize settling time and to prevent corruption of the conversion result. To avoid conversion corruption, do not switch the channels during the tQUIET1 time. If the analog inputs are multiplexed during the quiet conversion time (tQUIET1), the current conversion may be corrupted. Figure 41. THD vs. Input Frequency for Various Source Impedances, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C Rev. C | Page 22 of 36 Data Sheet AD4000/AD4004/AD4008 95 85 80 75 70 ADA4077-1 HIGH-Z ADA4077-1 HIGH-Z ADA4610-1 HIGH-Z ADA4610-1 HIGH-Z 260.482kHz 497.981kHz 1.3MHz 2.27MHz 1.3kΩ 680Ω 680Ω 390Ω 470pF 470pF 180pF 180pF RC FILTER BANDWIDTHS (Hz), RESISTOR (Ω), CAPACITOR (pF) ENABLED DISABLED ENABLED DISABLED 4.42MHz 200Ω 180pF 14956-229 SNR (dB) 90 Figure 42. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers, fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C –75 –80 –85 –90 –95 –100 –105 –110 –115 ADA4077-1 HIGH-Z ADA4077-1 HIGH-Z ADA4610-1 HIGH-Z ADA4610-1 HIGH-Z ENABLED DISABLED ENABLED DISABLED 260.482kHz 497.981kHz 1.3MHz 2.27MHz 1.3kΩ 680Ω 680Ω 390Ω 470pF 470pF 180pF 180pF RC FILTER BANDWIDTHS (Hz), RESISTOR (Ω), CAPACITOR (pF) 4.42MHz 200Ω 180pF 14956-231 When high-Z mode is enabled, the ADC consumes approximately 1 mW per MSPS of extra power; however, this is still significantly lower than using dedicated ADC drivers like the ADA4807-1. For any system, the front end usually limits the overall ac/dc performance of the signal chain. The data sheets of the selected precision amplifiers, shown in Figure 42 and Figure 43, show that their own noise and distortion performance dominates the SNR and THD specification at a certain input frequency. –70 THD (dB) Figure 42 and Figure 43 show the AD4000/AD4004/AD4008 SNR and THD performance using the ADA4077-1 (supply current per amplifier (ISY) = 400 µA) and ADA4610-1 (ISY = 1.50 mA) precision amplifiers when driving the AD4000/AD4004/ AD4008 at full throughput for high-Z mode both enabled and disabled with various RC filter values. These amplifiers achieve 91 dB to 92 dB typical SNR and close to −100 dB typical THD with high-Z enabled for a 2.27 MHz RC bandwidth. THD is approximately 5 dB better with high-Z mode enabled, even for large R values greater than 200 Ω. SNR maintains close to 85 dB even with a very low RC filter cutoff. Figure 43. THD vs. RC Filter Bandwidths for Various Precision ADC Drivers, fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C Long Acquisition Phase The AD4000/AD4004/AD4008 also feature a fast conversion time of 290 ns, which results in a long acquisition phase. The acquisition is further extended by a key feature of the AD4000/ AD4004/AD4008: the ADC returns to the acquisition phase typically 100 ns before the end of the conversion. This feature provides an even longer time for the ADC to acquire the new input voltage. A longer acquisition phase reduces the settling requirement on the driving amplifier, and a lower power/ bandwidth amplifier can be chosen. The longer acquisition phase means that a lower RC filter (represented by R and C in Figure 33 and Figure 34) cutoff can be used, which means a noisier amplifier can also be tolerated. A larger value of R can be used in the RC filter with a corresponding smaller value of C, reducing amplifier stability concerns without affecting distortion performance significantly. A larger value of R also results in reduced dynamic power dissipation in the amplifier. See Table 10 for details on setting the RC filter bandwidth and choosing a suitable amplifier. VOLTAGE REFERENCE INPUT A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input. For higher performance and lower drift, use a reference such as the ADR4550. Use a low power reference such as the ADR3450 at the expense of a slight decrease in the noise performance. It is recommended to use a reference buffer such as the ADA4807-1 between the reference and the ADC reference input. It is important to consider the optimum capacitance necessary to keep the reference buffer stable as well as to meet the minimum ADC requirement stated previously in this section (that is, a 10 µF ceramic chip capacitor, CREF). Rev. C | Page 23 of 36 AD4000/AD4004/AD4008 Data Sheet POWER SUPPLY DIGITAL INTERFACE The AD4000/AD4004/AD4008 use two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, VIO and VDD can be tied together for 1.8 V operation. The ADP7118 low noise, CMOS, low dropout (LDO) linear regulator is recommended to power the VDD and VIO pins. The AD4000/AD4004/AD4008 are independent of power supply sequencing between VIO and VDD. Additionally, the AD4000/AD4004/AD4008 are insensitive to power supply variations over a wide frequency range, as shown in Figure 44. Although the AD4000/AD4004/AD4008 have a reduced number of pins, they offer flexibility in their serial interface modes. The AD4000/AD4004/AD4008 can also be programmed via 16-bit SPI writes to the configuration registers. 80 PSRR (dB) 75 The AD4000/AD4004/AD4008 provide a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line, similar to a shift register. 70 The mode in which the device operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI is high, and daisy-chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, daisy-chain mode is always selected. 65 55 100 1k 10k 100k 1M FREQUENCY (Hz) 14956-230 60 Figure 44. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C The AD4000/AD4004/AD4008 power down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. This feature makes the device ideal for low sampling rates (even a few samples per second) and battery-powered applications. Figure 45 shows the AD4000/AD4004/AD4008 total power dissipation and individual power dissipation for each rail. 100k 10k VDD VIO REF TOTAL POWER 100 10 1 0.01 10 POWER DISSIPATION MEASUREMENTS APPLY TO EACH PRODUCT OVER ITS SPECIFIED THROUGHPUT RANGE. 100 1k The busy indicator feature is enabled in CS mode if CNV or SDI is low when the ADC conversion ends. The state of SDO on power-up is either low or high-Z, depending on the states of CNV and SDI, as shown in Table 11. CNV 0 0 1 1 1k 0.1 In either 3-wire or 4-wire mode, the AD4000/AD4004/AD4008 offer the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. Table 11. State of SDO on Power-Up 10k THROUGHPUT (SPS) 100k 1M 2M 14956-227 POWER DISSIPATION (µW) When in CS mode, the AD4000/AD4004/AD4008 are compatible with SPI, QSPI™, MICROWIRE®, digital hosts, and DSPs. In this mode, the AD4000/AD4004/AD4008 can use either a 3-wire or 4wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This interface is useful in low jitter sampling or simultaneous sampling applications. Figure 45. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V, 25°C SDI 0 1 0 1 SDO Low Low Low High-Z The AD4000/AD4004/AD4008 have turbo mode capability in both 3-wire and 4-wire mode. Turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. Turbo mode allows a slower SPI clock rate, making interfacing simpler. The maximum throughput of 2 MSPS for the AD4000 can be achieved only with turbo mode enabled and a minimum SCK rate of 70 MHz. Rev. C | Page 24 of 36 Data Sheet AD4000/AD4004/AD4008 The SCK rate must be sufficiently fast to ensure that the conversion result is clocked out before another conversion is initiated. The minimum required SCK rate for an application can be derived based on the sample period (tCYC), the number of bits that must be read (including data and optional status bits), and which digital interface mode is used. Timing diagrams and explanations for each digital interface mode are given in the digital modes of operation sections (see the CS Mode, 3-Wire Turbo Mode section through the Daisy-Chain Mode section). Status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. There are six status bits in total as described in Table 15. All access to the register map must start with a write to the 8-bit command register in the SPI interface block. The AD4000/ AD4004/AD4008 ignore all 1s until the first 0 is clocked in (represented by WEN in Figure 46, Figure 47, and Table 12); the value loaded into the command register is always a 0 followed by seven command bits. This command determines whether that operation is a write or a read. The AD4000/AD4004/ AD4008 command register is shown in Table 13. Table 13. Command Register Bit 7 WEN Bit 6 R/W Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 1 Bit 1 0 Bit 0 0 The AD4000/AD4004/AD4008 are configured by 16-bit SPI writes to the desired configuration register. The 16-bit word can be written via the SDI line while CNV is held low. The 16-bit word consists of an 8-bit header and 8-bit register data. For isolated systems, the ADuM141D is recommended, which can support the 70 MHz SCK rate required to run the AD4000 at its full throughput of 2 MSPS. All register read/writes must occur while CNV is low. Data on SDI is clocked in on the rising edge of SCK. Data on SDO is clocked out on the falling edge of SCK. At the end of the data transfer, SDO is put in a high impedance state on the rising edge of CNV if daisy-chain mode is not enabled. If daisy-chain mode is enabled, SDO goes low on the rising edge of CNV. Register reads are not allowed in daisy-chain mode. REGISTER READ/WRITE FUNCTIONALITY A register write requires three signal lines: SCK, CNV, and SDI. During a register write, to read the current conversion results on SDO, the CNV pin must be brought low after the conversion is completed; otherwise, the conversion results may be incorrect on SDO. However, the register write occurs regardless. The AD4000/AD4004/AD4008 register bits are programmable and their default statuses are shown in Table 12. The register map is shown in Table 14. The OV clamp flag is a read only sticky bit, and it is cleared only if the register is read and the overvoltage condition is no longer present. The OV clamp flag gives an indication of overvoltage condition when it is set to 0. Table 12. Register Bits Register Bits OV Clamp Flag Span Compression High-Z Mode Turbo Mode Enable Six Status Bits Default Status 1 bit, 1 = inactive (default) 1 bit, 0 = disabled (default) 1 bit, 0 = disabled (default) 1 bit, 0 = disabled (default) 1 bit, 0 = disabled (default) The LSB of each configuration register is reserved because a user reading 16-bit conversion data may be limited to a 16-bit SPI frame. The state of SDI on the last bit in the SDI frame may be the state that then persists when CNV rises. Because interface mode is partly set based on the SDI state when CNV rises, in this scenario, the user may need to set the final SDI state. The timing diagrams in Figure 46 through Figure 48 show how data is read and written when the AD4000/AD4004/AD4008 are configured in register read, write, and daisy-chain mode. Table 14. Register Map ADDR[1:0] 0x0 Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Enable six status bits Bit 3 Span compression Rev. C | Page 25 of 36 Bit 2 High-Z mode Bit 1 Turbo mode Bit 0 OV clamp flag (read only sticky bit) Reset 0xE1 AD4000/AD4004/AD4008 Data Sheet tCYC tCNVH tSCK CNV tSCNVSCK 1 2 3 4 5 6 7 8 9 10 11 tHSDISCK 1 WEN R/W 0 1 0 1 ADDR[1:0] 1 0 1 0 1 0 0 0 D15 D14 14 15 16 tHSDO tDSDO tEN SDO 13 tSCKH tSSDISCK SDI 12 D13 D12 D11 D10 D9 D8 B7 tDIS B6 B5 B4 B3 B2 B1 14956-018 SCK tSCKL X B0 Figure 46. Register Read Timing Diagram (X Means Don’t Care) tCYC tSCK tCNVH 1 tHCNVSCK CNV tSCNVSCK SCK 1 tSCKL 2 3 4 5 9 10 tHSDISCK 11 12 13 14 15 16 tSCKH tSSDISCK SDI 1 WEN R/W 0 1 0 1 0 0 1 0 1 0 B7 ADDR[1:0] 0 B6 0 D15 D14 D13 D12 D11 D10 B4 B3 B2 B1 1 B0 tHSDO tDSDO EN SDO B5 D8 D9 D7 D6 D5 D4 D3 D2 D1 D0 14956-019 CONVERSION RESULT ON BITS[D15:D0] 1THE USER MUST WAIT tCONV WHEN READING BACK THE CONVERSION RESULT AND PERFORMING A REGISTER WRITE AT THE SAME TIME. Figure 47. Register Write Timing Diagram tCYC tCNVH tSCK CNV tSCNVSCK SCK tSCKL 1 24 tSCKH SDIA SDOA/SDIB 0 COMMAND (0x14) 0 DATA (0xAB) COMMAND (0x14) 0 DATA (0xAB) 0 0 COMMAND (0x14) Figure 48. Register Write Timing Diagram, Daisy-Chain Mode Rev. C | Page 26 of 36 0 14956-020 tDIS SDOB Data Sheet AD4000/AD4004/AD4008 STATUS WORD The SDO line returns to high impedance after the sixth status bit is clocked out (except in daisy-chain mode). The user is not required to clock out all status bits to start the next conversion. The serial interface timing for CS mode, 3-wire without busy indicator, including status bits, is shown in Figure 49. The 6-bit status word can be appended to the end of a conversion result, and the default conditions of these bits are shown in Table 15. The status bits must be enabled in the register setting. When the OV clamp flag is a 0, it indicates an overvoltage condition. The OV clamp flag status bit updates on a per conversion basis. SDI = 1 tCYC tCNVH CN V ACQ ACQUISITION CONVERSION ACQUISITION tSCK tCONV tQUIET2 tSCKL 1 2 3 14 21 22 tSCKH tHSDO tEN SDO 20 16 15 tDSDO D15 D14 D13 tDIS D1 D0 B1 B0 14956-021 SCK STATUS BITS[5:0] Figure 49. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High) Table 15. Status Bits (Default Conditions) Bit 5 OV clamp flag Bit 4 Span compression Bit 3 High-Z mode Rev. C | Page 27 of 36 Bit 2 Turbo mode Bit 1 Reserved Bit 0 Reserved AD4000/AD4004/AD4008 Data Sheet When SDI is forced high, a rising edge on CNV initiates a conversion. The previous conversion data is available to read after the CNV rising edge. The user must wait tQUIET1 time after CNV is brought high before bringing CNV low to clock out the previous conversion result. The user must also wait tQUIET2 time after the last falling edge of SCK to when CNV is brought high. CS MODE, 3-WIRE TURBO MODE This mode is typically used when a single AD4000/AD4004/ AD4008 device is connected to an SPI-compatible digital host. It provides additional time during the end of the ADC conversion process to clock out the previous conversion result, providing a lower SCK rate. The AD4000 can achieve a throughput rate of 2 MSPS only when turbo mode is enabled and using a minimum SCK rate of 70 MHz. With turbo mode enabled, the AD4004 can also achieve its maximum throughput rate of 1 MSPS with a minimum SCK rate of 22 MHz, and the AD4008 can achieve its maximum throughput rate of 500 kSPS with a minimum SCK rate of 10 MHz. The connection diagram is shown in Figure 50, and the corresponding timing diagram is shown in Figure 51. When the conversion is complete, the AD4000/AD4004/AD4008 enter the acquisition phase and power down. When CNV goes low, the MSB is output to SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. This mode replaces the 3-wire with busy indicator mode by programming the turbo mode bit, Bit 1 (see Table 14). CONVERT DIGITAL HOST CNV VIO AD4000/ AD4004/ AD4008 SDI DATA IN SDO 14956-147 SCK CLK Figure 50. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High) SDI = 1 tCYC CNV tACQ ACQUISITION ACQUISITION CONVERSION tSCK CONV tSCKL QUIET2 tQUIET1 1 2 3 14 15 tSCKH tHSDO tEN SDO 16 tDSDO D15 D14 D13 tDIS D1 D0 Figure 51. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High) Rev. C | Page 28 of 36 14956-026 SCK Data Sheet AD4000/AD4004/AD4008 then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is typically used when a single AD4000/AD4004/ AD4008 device is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 52, and the corresponding timing diagram is shown in Figure 53. When the conversion is complete, the AD4000/AD4004/AD4008 enter the acquisition phase and power down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. After a conversion is initiated, it continues until completion irrespective of the state of CNV. This feature can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and There must not be any digital activity on SCK during the conversion. CONVERT DIGITAL HOST CNV VIO AD4000/ AD4004/ AD4008 SDI DATA IN SDO 14956-022 SCK CLK Figure 52. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV tACQ ACQUISITION CONVERSION tSCK tCONV tSCKL SCK 1 2 3 14 tHSDO 15 16 tSCKH tEN SDO tQUIET2 tDSDO D15 D14 D13 tDIS D1 Figure 53. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High) Rev. C | Page 29 of 36 D0 14956-023 ACQUISITION AD4000/AD4004/AD4008 Data Sheet the data reading controlled by the digital host. The AD4000/ AD4004/AD4008 then enter the acquisition phase and power down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is typically used when a single AD4000/AD4004/ AD4008 device is connected to an SPI-compatible digital host with an interrupt input (IRQ). The connection diagram is shown in Figure 54, and the corresponding timing diagram is shown in Figure 55. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion, irrespective of the state of CNV. Prior to the minimum conversion time, CNV can select other SPI devices, such as analog multiplexers; however, CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple AD4000/AD4004/AD4008 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. It is recommended to keep this contention as short as possible to limit extra power dissipation. There must not be any digital activity on the SCK during the conversion. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate CONVERT VIO DIGITAL HOST CNV 1kΩ VIO AD4000/ AD4004/ AD4008 SDO DATA IN IRQ SCK 14956-024 SDI CLK Figure 54. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV tACQ ACQUISITION CONVERSION tSCK tCONV tQUIET2 tSCKL SCK 1 2 3 15 tHSDO 16 17 tSCKH tDSDO SDO D15 D14 tDIS D1 Figure 55. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High) Rev. C | Page 30 of 36 D0 14956-025 ACQUISITION Data Sheet AD4000/AD4004/AD4008 With SDI high, a rising edge on CNV initiates a conversion. The previous conversion data is available to read after the CNV rising edge. The user must wait tQUIET1 time after CNV is brought high before bringing SDI low to clock out the previous conversion result. The user must also wait tQUIET2 time after the last falling edge of SCK to when CNV is brought high. CS MODE, 4-WIRE TURBO MODE This mode is typically used when a single AD4000/AD4004/ AD4008 device is connected to an SPI-compatible digital host. It provides additional time during the end of the ADC conversion process to clock out the previous conversion result, providing a lower SCK rate. The AD4000 can achieve a throughput rate of 2 MSPS only when turbo mode is enabled and using a minimum SCK rate of 70 MHz. With turbo mode enabled, the AD4004 can also achieve its maximum throughput rate of 1 MSPS with a minimum SCK rate of 22 MHz, and the AD4008 can achieve its maximum throughput rate of 500 kSPS with a minimum SCK rate of 10 MHz. The connection diagram is shown in Figure 56, and the corresponding timing diagram is shown in Figure 57. When the conversion is complete, the AD4000/AD4004/ AD4008 enter the acquisition phase and power down. The ADC result can be read by bringing the SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance. This mode replaces the 4-wire with busy indicator mode by programming the turbo mode bit, Bit 1 (see Table 14). CS1 CONVERT VIO DIGITAL HOST CNV AD4000/ AD4004/ AD4008 SDO DATA IN IRQ SCK 14956-153 SDI 1kΩ CLK Figure 56. CS Mode, 4-Wire Turbo Mode Connection Diagram CNV tCYC tSSDICNV SDI tHSDICNV ACQUISITION tACQ ACQUISITION CONVERSION tSCK tCONV tSCKL tQUIET2 tQUIET1 1 2 3 14 tHSDO 16 tSCKH tEN SDO 15 tDIS tDSDO D15 D14 D13 Figure 57. CS Mode, 4-Wire Turbo Mode Timing Diagram Rev. C | Page 31 of 36 D1 D0 14956-031 SCK AD4000/AD4004/AD4008 Data Sheet time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. CS MODE, 4-WIRE WITHOUT BUSY INDICATOR This mode is typically used when multiple AD4000/AD4004/ AD4008 devices are connected to an SPI-compatible digital host. When the conversion is complete, the AD4000/AD4004/ AD4008 enter the acquisition phase and power down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another AD4000/ AD4004/AD4008 can be read. A connection diagram example using two AD4000/AD4004/ AD4008 devices is shown in Figure 58, and the corresponding timing diagram is shown in Figure 59. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers; however, SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV AD4000/ AD4004/ AD4008 SDO SDI DEVICE A DEVICE B SCK SCK DIGITAL HOST SDO 14956-027 SDI CNV AD4000/ AD4004/ AD4008 DATA IN CLK Figure 58. CS Mode, 4-Wire Without Busy Indicator Connection Diagram tCYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV tQUIET2 tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 2 14 3 tHSDO 16 17 18 30 31 32 tDIS tDSDO tEN SDO 15 tSCKH D15 D14 D13 D1 D0 D15 D14 Figure 59. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram Rev. C | Page 32 of 36 D1 D0 14956-028 SCK Data Sheet AD4000/AD4004/AD4008 CS MODE, 4-WIRE WITH BUSY INDICATOR select other SPI devices, such as analog multiplexers; however, SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. This mode is typically used when a single AD4000/AD4004/ AD4008 device is connected to an SPI-compatible digital host with an interrupt input (IRQ), and when it is desired to keep CNV, which samples the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD4000/ AD4004/AD4008 then enter the acquisition phase and power down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance. The connection diagram is shown in Figure 60, and the corresponding timing diagram is shown in Figure 61. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can CS1 CONVERT VIO DIGITAL HOST CNV AD4000/ AD4004/ AD4008 SDO DATA IN IRQ SCK 14956-029 SDI 1kΩ CLK Figure 60. CS Mode, 4-Wire with Busy Indicator Connection Diagram tCYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV tQUIET2 tSSDICNV SDI tSCK tHSDICNV tSCKL SCK 1 2 3 15 16 17 tSCKH tHSDO tDSDO tDIS SDO D15 D14 D1 Figure 61. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram Rev. C | Page 33 of 36 D0 14956-030 tEN AD4000/AD4004/AD4008 Data Sheet the daisy-chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. The maximum conversion rate is reduced because of the total readback time. DAISY-CHAIN MODE Use this mode to daisy-chain multiple AD4000/AD4004/AD4008 devices on a 3-wire or 4-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. It is possible to write to each ADC register in daisy-chain mode. The timing diagram is shown in Figure 48. This mode requires 4-wire operation because data is clocked in on the SDI line with CNV held low. The same command byte and register data can be shifted through the entire chain to program all ADCs in the chain with the same register contents, which requires 8 × (N + 1) clocks for N ADCs. It is possible to write different register contents to each ADC in the chain by writing to the furthest ADC in the chain first, using 8 × (N + 1) clocks, and then the second furthest ADC with 8 × N clocks, and so forth until reaching the nearest ADC in the chain, which requires 16 clocks for the command and register data. It is not possible to read register contents in daisy-chain mode; however, the six status bits can be enabled if the user wants to determine the ADC configuration. Note that enabling the status bits requires six extra clocks to clock out the ADC result and the status bits per ADC in the chain. Turbo mode cannot be used in daisy-chain mode. A connection diagram example using two AD4000/AD4004/ AD4008 devices is shown in Figure 62, and the corresponding timing diagram is shown in Figure 63. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects daisy-chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO, and the AD4000/AD4004/AD4008 enter the acquisition phase and power down. The remaining data bits stored in the internal shift register are clocked out of SDO by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK rising edges. Each ADC in CONVERT CNV AD4000/ AD4004/ AD4008 SDI SDO DEVICE A DEVICE B SCK SCK DIGITAL HOST SDO DATA IN 14956-032 SDI CNV AD4000/ AD4004/ AD4008 CLK Figure 62. Daisy-Chain Mode, Connection Diagram SDIA = 0 tCYC CNV tACQ CONVERSION ACQUISITION tCONV tSCK tQUIET2 tSCKL tQUIET2 SCK 1 2 3 14 15 tSSDISCK tHSCKCNV 16 17 18 30 31 32 tSCKH tHSDISCK tEN DA15 SDOA = SDIB DA14 DA13 DA1 DA0 tHSDO tDIS tDSDO SDOB DB15 DB14 DB13 DB1 DB0 DA15 Figure 63. Daisy-Chain Mode, Serial Interface Timing Diagram Rev. C | Page 34 of 36 DA14 DA1 DA0 14956-033 ACQUISITION Data Sheet AD4000/AD4004/AD4008 LAYOUT GUIDELINES The PCB that houses the AD4000/AD4004/AD4008 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD4000/AD4004/AD4008, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD4000/AD4004/AD4008 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Avoid crossover of digital and analog signals. EVALUATING THE AD4000/AD4004/AD4008 PERFORMANCE Other recommended layouts for the AD4000/AD4004/AD4008 are outlined in the user guide of the evaluation board for the AD4000 (EVAL-AD4000FMCZ). The evaluation board package includes a fully assembled and tested evaluation board with the AD4000, documentation, and software for controlling the board from a PC via the EVAL-SDP-CH1Z. The EVAL-AD4000FMCZ can also be used to evaluate the AD4004/AD4008 by limiting the throughput to 1 MSPS/500 kSPS, respectively, in its software (see the UG-1042). At least one ground plane must be used. It can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD4000/AD4004/AD4008 devices. Finally, decouple the VDD and VIO power supplies of the AD4000/AD4004/AD4008 with ceramic capacitors, typically 0.1 µF, placed close to the AD4000/AD4004/AD4008 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. 14956-034 The AD4000/AD4004/AD4008 voltage reference input (REF) has a dynamic input impedance. Decouple the REF pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against) the REF and GND pins and connect them with wide, low impedance traces. Figure 64. Example Layout of the AD4000 (Top Layer) 14956-035 An example of the AD4000 layout following these rules is shown in Figure 64 and Figure 65. Note that the AD4004/ AD4008 layout is equivalent to the AD4000 layout. Figure 65. Example Layout of the AD4000 (Bottom Layer) Rev. C | Page 35 of 36 AD4000/AD4004/AD4008 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 66. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIE W TOP VIEW PKG-004362 0.80 0.75 0.70 SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 SIDE VIEW 0.30 0.25 0.20 0.20 MIN PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 02-07-2017-C PIN 1 INDEX AREA Figure 67. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD4000BRMZ AD4000BRMZ-RL7 AD4000BCPZ-RL7 AD4004BRMZ AD4004BRMZ-RL7 AD4004BCPZ-RL7 AD4008BCPZ-RL7 EVAL-AD4000FMCZ 1 2 Integral Nonlinearity (INL) ±1.0 LSB ±1.0 LSB ±1.0 LSB ±1.0 LSB ±1.0 LSB ±1.0 LSB ±1.0 LSB Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 10-Lead MSOP, Tube 10-Lead MSOP, Reel 10-Lead LFCSP, Reel 10-Lead MSOP, Tube 10-Lead MSOP, Reel 10-Lead LFCSP, Reel 10-Lead LFCSP, Reel AD4000 Evaluation Board Compatible with EVAL-SDP-CH1Z Ordering Quantity 50 1000 1500 50 1000 1500 1500 Package Option RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9 CP-10-9 Branding Y61 Y61 Y61 C8F C8F C8F C8S Z = RoHS Compliant Part. The EVAL-AD4000FMCZ can also be used to evaluate the AD4004 and AD4008 by setting the throughput to 1 MSPS and 500 kSPS in its software, respectively (see UG-1042). ©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14956-0-10/17(C) Rev. C | Page 36 of 36