STMicroelectronics E-L6202 Dmos full bridge driver Datasheet

L6201
L6202 - L6203
®
DMOS FULL BRIDGE DRIVER
SUPPLY VOLTAGE UP TO 48V
5A MAX PEAK CURRENT (2A max. for L6201)
TOTAL RMS CURRENT UP TO
L6201: 1A; L6202: 1.5A; L6203/L6201PS: 4A
RDS (ON) 0.3 Ω (typical value at 25 °C)
CROSS CONDUCTION PROTECTION
TTL COMPATIBLE DRIVE
OPERATING FREQUENCY UP TO 100 KHz
THERMAL SHUTDOWN
INTERNAL LOGIC SUPPLY
HIGH EFFICIENCY
DESCRIPTION
The I.C. is a full bridge driver for motor control applications realized in Multipower-BCD technology
which combines isolated DMOS power transistors
with CMOS and Bipolar circuits on the same chip.
By using mixed technology it has been possible to
optimize the logic circuitry and the power stage to
achieve the best possible performance. The
DMOS output transistors can operate at supply
voltages up to 42V and efficiently at high switch-
MULTIPOWER BCD TECHNOLOGY
Powerdip 12+3+3
SO20 (12+4+4)
Multiwatt11
PowerSO20
ORDERING NUMBERS:
L6201 (SO20)
L6201PS (PowerSO20)
L6202 (Powerdip18)
L6203 (Multiwatt)
ing speeds. All the logic inputs are TTL, CMOS
and µC compatible. Each channel (half-bridge) of
the device is controlled by a separate logic input,
while a common enable controls both channels.
The I.C. is mounted in three different packages.
BLOCK DIAGRAM
July 2003
1/20
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6201 - L6202 - L6203
PIN CONNECTIONS (Top view)
SO20
POWERDIP
GND
1
20
GND
N.C.
2
19
N.C.
N.C.
N.C.
3
18
OUT2
4
17
ENABLE
VS
5
16
SENSE
OUT1
6
15
Vref
BOOT1
7
14
BOOT2
IN1
8
13
IN2
N.C.
9
12
N.C.
GND
10
11
GND
D95IN216
PowerSO20
MULTIWATT11
2/20
L6201 - L6202 - L6203
PINS FUNCTIONS
Device
Name
Function
10
SENSE
A resistor Rsense connected to this pin provides feedback for
motor current control.
11
ENAB
LE
When a logic high is present on this pin the DMOS POWER
transistors are enabled to be selectively driven by IN1 and IN2.
3
N.C.
Not Connected
4
GND
Common Ground Terminal
L6201
L6201PS
L6202
L6203
1
16
1
2
17
2
3
2,3,9,12,
18,19
4,5
–
–
1, 10
5
GND
Common Ground Terminal
6,7
–
6
GND
Common Ground Terminal
8
–
7
N.C.
Not Connected
9
4
8
OUT2
Ouput of 2nd Half Bridge
6
1
10
5
9
2
Vs
Supply Voltage
11
6
10
3
OUT1
Output of first Half Bridge
12
7
11
4
BOOT1
A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
13
8
12
5
IN1
Digital Input from the Motor Controller
6
14,15
–
13
GND
Common Ground Terminal
–
11, 20
14
GND
Common Ground Terminal
16,17
–
15
GND
Common Ground Terminal
18
13
16
7
IN2
Digital Input from the Motor Controller
19
14
17
8
BOOT2
A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
20
15
18
9
Vref
Internal voltage reference. A capacitor from this pin to GND is
recommended. The internal Ref. Voltage can source out a
current of 2mA max.
ABSOLUTE MAXIMUM RATINGS
Symbol
Vs
VOD
VIN, VEN
Io
Vsense
Value
Unit
Power Supply
Parameter
52
V
Differential Output Voltage (between Out1 and Out2)
60
V
– 0.3 to + 7
V
5
5
10
1
A
A
A
A
– 1 to + 4
V
Input or Enable Voltage
Pulsed Output Current
for L6201PS/L6202/L6203 (Note 1)
– Non Repetitive (< 1 ms) for L6201
for L6201PS/L6202/L6203
DC Output Current
for L6201 (Note 1)
Sensing Voltage
Vb
Boostrap Peak Voltage
60
V
Ptot
Total Power Dissipation:
Tpins = 90°C for L6201
for L6202
Tcase = 90°C for L6201PS/L6203
Tamb = 70°C for L6201 (Note 2)
for L6202 (Note 2)
for L6201PS/L6203 (Note 2)
4
5
20
0.9
1.3
2.3
W
W
W
W
W
W
– 40 to + 150
°C
Tstg, Tj
Storage and Junction Temperature
Note 1: Pulse width limited only by junction temperature and transient thermal impedance (see thermal characteristics)
Note 2: Mounted on board with minimized dissipating copper area.
3/20
L6201 - L6202 - L6203
THERMAL DATA
Symbol
Rth j-pins
Rth j-case
Rth j-amb
Value
Parameter
Thermal Resistance Junction-pins
Thermal Resistance Junction Case
Thermal Resistance Junction-ambient
L6201
L6201PS
L6202
L6203
15
–
85
–
–
13 (*)
12
–
60
–
3
35
max
max.
max.
Unit
°C/W
(*) Mounted on aluminium substrate.
ELECTRICAL CHARACTERISTICS (Refer to the Test Circuits; Tj = 25°C, VS = 42V, Vsens = 0, unless
otherwise specified).
Symbol
Parameter
Vs
Supply Voltage
Vref
Reference Voltage
IREF
Output Current
Is
Quiescent Supply Current
Test Conditions
Min.
Typ.
Max.
Unit
12
36
48
V
IREF = 2mA
EN = H VIN = L
EN = H VIN = H
EN = L ( Fig. 1,2,3)
13.5
IL = 0
V
2
mA
10
10
8
15
15
15
mA
mA
mA
30
100
KHz
fc
Commutation Frequency (*)
Tj
Thermal Shutdown
150
°C
Td
Dead Time Protection
100
ns
TRANSISTORS
OFF
IDSS
Leakage Current
Fig. 11 Vs = 52 V
RDS
On Resistance
Fig. 4,5
Drain Source Voltage
Fig. 9
IDS = 1A
IDS = 1.2A
IDS = 3A
1
mA
0.55
Ω
ON
VDS(ON)
Vsens
0.3
L6201
L6202
L6201PS/0
3
Sensing Voltage
0.3
0.36
0.9
–1
V
V
V
4
V
SOURCE DRAIN DIODE
Vsd
trr
tfr
Forward ON Voltage
Reverse Recovery Time
Fig. 6a and b
EN = L
ISD = 1A L6201
EN = L
ISD = 1.2A L6202
ISD = 3A L6201PS/03 EN =
L
dif
= 25 A/µs
dt
IF = 1A
IF = 1.2A
IF = 3A
0.9 (**)
0.9 (**)
1.35(**)
V
V
V
300
ns
200
ns
L6201
L6202
L6203
Forward Recovery Time
LOGIC LEVELS
VIN L, VEN L
Input Low Voltage
– 0.3
0.8
V
VIN H, VEN H
Input High Voltage
2
7
V
IIN L, IEN L
Input Low Current
VIN, VEN = L
–10
µA
IIN H, IEN H
Input High Current
VIN, VEN = H
4/20
30
µA
L6201 - L6202 - L6203
ELECTRICAL CHARACTERISTICS (Continued)
LOGIC CONTROL TO POWER DRIVE TIMING
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t1 (Vi)
Source Current Turn-off Delay
Fig. 12
300
ns
t2 (Vi)
Source Current Fall Time
Fig. 12
200
ns
t3 (Vi)
Source Current Turn-on Delay
Fig. 12
400
ns
t4 (Vi)
Source Current Rise Time
Fig. 12
200
ns
t5 (Vi)
Sink Current Turn-off Delay
Fig. 13
300
ns
t6 (Vi)
Sink Current Fall Time
Fig. 13
200
ns
t7 (Vi)
Sink Current Turn-on Delay
Fig. 13
400
ns
t8 (Vi)
Sink Current Rise Time
Fig. 13
200
ns
(*) Limited by power dissipation
(**) In synchronous rectification the drain-source voltage drop VDS is shown in fig. 4 (L6202/03); typical value for the L6201 is of 0.3V.
Figure 1: Typical Normalized IS vs. Tj
Figure 2: Typical Normalized Quiescent Current
vs. Frequency
Figure 3: Typical Normalized IS vs. VS
Figure 4: Typical RDS (ON) vs. VS ~ Vref
5/20
L6201 - L6202 - L6203
Figure 5: Normalized RDS (ON)at 25°C vs. Temperature Typical Values
Figure 6a: Typical Diode Behaviour in Synchronous Rectification (L6201)
Figure 6b: Typical Diode Behaviour in Synchronous Rectification (L6201PS/02/03)
Figure 7a: Typical Power Dissipation vs IL
(L6201)
Figure 7b: Typical Power Dissipation vs IL
(L6201PS, L6202, L6203))
6/20
L6201 - L6202 - L6203
Figure 8a: Two Phase Chopping
Figure 8b: One Phase Chopping
IN1 = H
IN 2 = H
EN = H
Figure 8c: Enable Chopping
7/20
L6201 - L6202 - L6203
TEST CIRCUITS
Figure 9: Saturation Voltage
Figure 10: Quiescent Current
Figure 11: Leakage Current
8/20
L6201 - L6202 - L6203
Figure 12: Source Current Delay Times vs. Input Chopper
42V
for
L6201PS/02/03
Figure 13: Sink Current Delay Times vs. Input Chopper
42V
for
L6201PS/02/03
9/20
L6201 - L6202 - L6203
CIRCUIT DESCRIPTION
The L6201/1PS/2/3 is a monolithic full bridge
switching motor driver realized in the new Multipower-BCD technology which allows the integration of multiple, isolated DMOS power transistors
plus mixed CMOS/bipolar control circuits. In this
way it has been possible to make all the control
inputs TTL, CMOS and µC compatible and eliminate the necessity of external MOS drive components. The Logic Drive is shown in table 1.
Figure 15: Current Typical Spikes on the Sensing Pin
Table 1
Inputs
IN1
IN2
VEN = H
L
L
H
H
L
H
L
H
VEN = L
X
X
Output Mosfets (*)
Sink 1, Sink 2
Sink 1, Source 2
Source 1, Sink 2
Source 1, Source 2
All transistors turned oFF
L = Low
H = High
X = DON’t care
(*) Numbers referred to INPUT1 or INPUT2 controlled output stages
Although the device guarantees the absence of
cross-conduction, the presence of the intrinsic diodes in the POWER DMOS structure causes the
generation of current spikes on the sensing terminals. This is due to charge-discharge phenomena
in the capacitors C1 & C2 associated with the
drain source junctions (fig. 14). When the output
switches from high to low, a current spike is generated associated with the capacitor C1. On the
low-to-high transition a spike of the same polarity
is generated by C2, preceded by a spike of the
opposite polarity due to the charging of the input
capacity of the lower POWER DMOS transistor
(fig. 15).
Figure 14: Intrinsic Structures in the POWER
DMOS Transistors
TRANSISTOR OPERATION
ON State
When one of the POWER DMOS transistor is ON
it can be considered as a resistor RDS (ON)
throughout the recommended operating range. In
this condition the dissipated power is given by :
PON = RDS (ON) ⋅ IDS2 (RMS)
The low RDS (ON) of the Multipower-BCD process
can provide high currents with low power dissipation.
OFF State
When one of the POWER DMOS transistor is
OFF the VDS voltage is equal to the supply voltage and only the leakage current IDSS flows. The
power dissipation during this period is given by :
POFF = VS ⋅ IDSS
The power dissipation is very low and is negligible
in comparison to that dissipated in the ON
STATE.
Transitions
As already seen above the transistors have an intrinsic diode between their source and drain that
can operate as a fast freewheeling diode in
switched mode applications. During recirculation
with the ENABLE input high, the voltage drop
across the transistor is RDS (ON) ⋅ ID and when it
reaches the diode forward voltage it is clamped.
When the ENABLE input is low, the POWER
MOS is OFF and the diode carries all of the recirculation current. The power dissipated in the transitional times in the cycle depends upon the voltage-current waveforms and in the driving mode.
(see Fig. 7ab and Fig. 8abc).
Ptrans. = IDS (t) ⋅ VDS (t)
10/20
L6201 - L6202 - L6203
Boostrap Capacitors
To ensure that the POWER DMOS transistors are
driven correctly gate to source voltage of typ. 10
V must be guaranteed for all of the N-channel
DMOS transistors. This is easy to be provided for
the lower POWER DMOS transistors as their
sources are refered to ground but a gate voltage
greater than the supply voltage is necessary to
drive the upper transistors. This is achieved by an
internal charge pump circuit that guarantees correct DC drive in combination with the boostrap circuit. For efficient charging the value of the boostrap capacitor should be greater than the input
capacitance of the power transistor which is
around 1 nF. It is recommended that a capacitance of at least 10 nF is used for the bootstrap. If
a smaller capacitor is used there is a risk that the
POWER transistors will not be fully turned on and
they will show a higher RDS (ON). On the other
hand if a elevated value is used it is possible that
a current spike may be produced in the sense resistor.
Reference Voltage
To by-pass the internal Ref. Volt. circuit it is recommended that a capacitor be placed between its
pin and ground. A value of 0.22 µF should be sufficient for most applications. This pin is also protected against a short circuit to ground: a max.
current of 2mA max. can be sinked out.
Dead Time
To protect the device against simultaneous conduction in both arms of the bridge resulting in a
rail to rail short circuit, the integrated logic control
provides a dead time greater than 40 ns.
Thermal Protection
A thermal protection circuit has been included
that will disable the device if the junction temperature reaches 150 °C. When the temperature has
fallen to a safe level the device restarts the input
and enable signals under control.
APPLICATION INFORMATION
Recirculation
During recirculation with the ENABLE input high,
the voltage drop across the transistor is RDS
(ON)⋅ IL, clamped at a voltage depending on the
characteristics of the source-drain diode. Although the device is protected against cross conduction, current spikes can appear on the current
sense pin due to charge/discharge phenomena in
the intrinsic source drain capacitances. In the application this does not cause any problem because the voltage spike generated on the sense
resistor is masked by the current controller circuit.
Rise Time Tr (See Fig. 16)
When a diagonal of the bridge is turned on current begins to flow in the inductive load until the
maximum current IL is reached after a time Tr.
The dissipated energy EOFF/ON is in this case :
EOFF/ON = [RDS (ON) ⋅ IL2 ⋅ Tr] ⋅ 2/3
Load Time TLD (See Fig.16)
During this time the energy dissipated is due to
the ON resistance of the transistors (ELD) and due
to commutation (ECOM). As two of the POWER
DMOS transistors are ON, EON is given by :
ELD = IL2 ⋅ RDS (ON) ⋅ 2 ⋅ TLD
In the commutation the energy dissipated is :
ECOM = VS ⋅ IL ⋅ TCOM ⋅ fSWITCH ⋅ TLD
Where :
TCOM = TTURN-ON = TTURN-OFF
fSWITCH = Chopping frequency.
Fall Time Tf (See Fig. 16)
It is assumed that the energy dissipated in this
part of the cycle takes the same form as that
shown for the rise time :
EON/OFF = [RDS (ON) ⋅ IL2 ⋅ Tf] ⋅ 2/3
Figure 16.
11/20
L6201 - L6202 - L6203
Quiescent Energy
The last contribution to the energy dissipation is
due to the quiescent supply current and is given by:
EQUIESCENT = IQUIESCENT ⋅ Vs ⋅ T
Total Energy Per Cycle
ETOT = EOFF/ON + ELD + ECOM +
+ EON/OFF + EQUIESCENT
The Total Power Dissipation PDIS is simply :
PDIS = ETOT/T
Tr = Rise time
TLD = Load drive time
Tf = Fall time
Td = Dead time
T = Period
T = Tr + TLD + Tf + Td
DC Motor Speed Control
Since the I.C. integrates a full H-Bridge in a single
package it is idealy suited for controlling DC motors. When used for DC motor control it performs
the power stage required for both speed and direction control. The device can be combined with
a current regulator like the L6506 to implement a
transconductance amplifier for speed control, as
shown in figure 17. In this particular configuration
only half of the L6506 is used and the other half
of the device may be used to control a second
Figure 17: Bidirectional DC Motor Control
12/20
motor.
The L6506 senses the voltage across the sense
resistor RS to monitor the motor current: it compares the sensed voltage both to control the
speed and during the brake of the motor.
Between the sense resistor and each sense input
of the L6506 a resistor is recommended; if the
connections between the outputs of the L6506
and the inputs of the L6203 need a long path, a
resistor must be added between each input of the
L6203 and ground.
A snubber network made by the series of R and C
must be foreseen very near to the output pins of
the I.C.; one diode (BYW98) is connected between each power output pin and ground as well.
The following formulas can be used to calculate
the snubber values:
R ≅ VS/lp
C = lp/(dV/dt) where:
VS is the maximum Supply Voltage foreseen on
the application;
Ip is the peak of the load current;
dv/dt is the limited rise time of the output voltage
(200V/µs is generally used).
If the Power Supply Cannot Sink Current, a suitable large capacitor must be used and connected
near the supply pin of the L6203. Sometimes a
capacitor at pin 17 of the L6506 let the application
better work. For motor current up to 2A max., the
L6202 can be used in a similar circuit configuration for which a typical Supply Voltage of 24V is
recommended.
L6201 - L6202 - L6203
BIPOLAR STEPPER MOTORS APPLICATIONS
Bipolar stepper motors can be driven with one
L6506 or L297, two full bridge BCD drivers and
very few external components. Together these
three chips form a complete microprocessor-tostepper motor interface is realized.
As shown in Fig. 18 and Fig. 19, the controller
connect directly to the two bridge BCD drivers.
External component are minimalized: an R.C. network to set the chopper frequency, a resistive divider (R1; R2) to establish the comparator reference voltage and a snubber network made by R
and C in series (See DC Motor Speed Control).
Figure 18: Two Phase Bipolar Stepper Motor Control Circuit with Chopper Current Control
L6201
L6201PS
L6202
L6203
L6201
L6201PS
L6202
L6203
Figure 19: Two Phase Bipolar Stepper Motor Control Circuit with Chopper Current Control and Translator
L6201
L6201PS
L6202
L6203
L6201
L6201PS
L6202
L6203
13/20
L6201 - L6202 - L6203
It could be requested to drive a motor at VS lower
than the minimum recommended one of 12V
(See Electrical Characteristics); in this case, by
accepting a possible small increas in the RDS (ON)
resistance of the power output transistors at the
lowest Supply Voltage value, may be a good solution the one shown in Fig. 20.
Figure 21: Typical RTh J-amb vs. "On Board"
Heatsink Area (L6201)
Figure 20: L6201/1P/2/3 Used at a Supply Voltage Range Between 9 and 18V
L6201
L6201PS
L6202
L6203
THERMAL CHARACTERISTICS
Thanks to the high efficiency of this device, often
a true heatsink is not needed or it is simply obtained by means of a copper side on the P.C.B.
(L6201/2).
Under heavy conditions, the L6203 needs a suitable cooling.
By using two square copper sides in a similar way
as it shown in Fig. 23, Fig. 21 indicates how to
choose the on board heatsink area when the
L6201 total power dissipation is known since:
RTh j-amb = (Tj max. – Tamb max) / Ptot
Figure 22 shows the Transient Thermal Resistance vs. a single pulse time width.
Figure 23 and 24 refer to the L6202.
For the Multiwatt L6203 addition information is
given by Figure 25 (Thermal Resistance JunctionAmbient vs. Total Power Dissipation) and Figure
26 (Peak Transient Thermal Resistance vs. Repetitive Pulse Width) while Figure 27 refers to the
single pulse Transient Thermal Resistance.
14/20
Figure 22: Typical Transient RTH in Single Pulse
Condition (L6201)
Figurre 23: Typical RTh J-amb vs. Two "On Board"
Square Heatsink (L6202)
L6201 - L6202 - L6203
Figure 24: Typical Transient Thermal Resistance
for Single Pulses (L6202)
Figure 25: Typical RTh J-amb of Multiwatt
Package vs. Total Power Dissipation
Figure 26: Typical Transient Thermal Resistance
for Single Pulses with and without
Heatsink (L6203)
Figure 27: Typical Transient Thermal Resistance
versus Pulse Width and Duty Cycle
(L6203)
15/20
L6201 - L6202 - L6203
mm
DIM.
MIN.
a1
0.51
B
0.85
b
b1
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.40
0.033
0.50
0.38
0.055
0.020
0.50
D
0.015
0.020
24.80
0.976
E
8.80
0.346
e
2.54
0.100
e3
20.32
0.800
F
7.10
0.280
I
5.10
0.201
L
OUTLINE AND
MECHANICAL DATA
3.30
0.130
Powerdip 18
Z
16/20
2.54
0.100
L6201 - L6202 - L6203
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
SO20
K
0˚ (min.)8˚ (max.)
L
h x 45˚
A
B
e
A1
K
C
H
D
20
11
E
1
0
1
SO20MEC
17/20
L6201 - L6202 - L6203
DIM.
mm
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
3.6
0.1
0.142
0.3
a2
0.004
0.012
3.3
0.130
a3
0
0.1
0.000
0.004
b
0.4
0.53
0.016
0.021
c
0.23
0.32
0.009
0.013
D (1)
15.8
16
0.622
0.630
0.386
D1
9.4
9.8
0.370
E
13.9
14.5
0.547
e
1.27
e3
E1 (1)
0.570
0.450
11.1
E2
0.429
0.437
2.9
0.114
E3
5.8
6.2
0.228
0.244
G
0
0.1
0.000
0.004
H
15.5
15.9
0.610
h
L
0.626
1.1
0.8
JEDEC MO-166
0.043
1.1
N
Weight: 1.9gr
0.050
11.43
10.9
OUTLINE AND
MECHANICAL DATA
MAX.
0.031
0.043
8˚ (typ.)
S
8˚ (max.)
T
10
0.394
PowerSO20
(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.
N
R
N
a2
b
A
e
DETAIL A
c
a1
DETAIL B
E
e3
H
DETAIL A
lead
D
slug
a3
DETAIL B
20
11
0.35
Gage Plane
-C-
S
SEATING PLANE
L
G
E2
E1
BOTTOM VIEW
C
(COPLANARITY)
T
E3
1
h x 45
10
PSO20MEC
D1
0056635
18/20
L6201 - L6202 - L6203
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
5
0.197
B
2.65
0.104
C
1.6
D
OUTLINE AND
MECHANICAL DATA
0.063
1
0.039
E
0.49
0.55
0.019
0.022
F
0.88
0.95
0.035
0.037
G
1.45
1.7
1.95
0.057
0.067
0.077
G1
16.75
17
17.25
0.659
0.669
0.679
H1
19.6
0.772
H2
20.2
0.795
L
21.9
22.2
22.5
0.862
0.874
0.886
L1
21.7
22.1
22.5
0.854
0.87
0.886
L2
17.4
18.1
0.685
L3
17.25
17.5
17.75
0.679
0.689
0.713
0.699
L4
10.3
10.7
10.9
0.406
0.421
0.429
L7
2.65
2.9
0.104
M
4.25
4.55
4.85
0.167
0.179
0.191
0.114
M1
4.73
5.08
5.43
0.186
0.200
0.214
S
1.9
2.6
0.075
0.102
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
Multiwatt11 V
19/20
L6201 - L6202 - L6203
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics – Printed in Italy – All Rights Reserved
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