TI BQ2203APNN Nv controller with battery monitor Datasheet

bq2203A
NV Controller With Battery Monitor
Features
General Description
ä Power monitoring and switching
for nonvolatile control of SRAMs
ä Write-protect control
ä Battery-low and battery-fail indicators
ä Reset output for system power-on
reset
ä Input decoder for control of up to
2 banks of SRAM
ä 3-volt primary cell input
ä 3-volt rechargeable battery input/output
The CMOS bq2203A SRAM Nonvolatile
Controller With Battery Monitor provides all the necessary functions for converting one or two banks of standard
CMOS SRAM into nonvolatile
read/write memory. The bq2203A is
compatible with the Personal Computer
Memory Card International Association
(PCMCIA) recommendations for
battery-backed static RAM memory
cards.
A precision comparator monitors the 5V
VCC input for an out-of-tolerance condition. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect
banks of SRAM.
Pin Connections
Power for the external SRAMs is
switched from the VCC supply to the
battery-backup supply as VCC decays. On a subsequent power-up, the
V OUT supply is automatically
switched from the backup supply to
the VCC supply. The external SRAMs
are write-protected until a powervalid condition exists. The reset output provides power-fail and power-on
resets for the system. The battery
monitor indicates battery-low and
battery-fail conditions.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
Pin Names
VOUT
1
16
VCC
BCP
2
15
BCS
NC
3
14
CE
A
4
13
CECON1
BCF
5
12
CECON2
NC
6
11
BCL
THS
7
10
RST
VSS
8
9
NC
VOUT
RST
THS
CE
CECON1,
CECON2
A
BCF
BCL
BCP
BCS
NC
VCC
VSS
16-Pin Narrow DIP or SOIC
Supply output
Reset output
Threshold select input
chip-enable active low input
Conditioned chip-enable outputs
Bank select input
Battery fail push-pull output
Battery low push-pull output
3V backup supply input
3V rechargeable backup supply input/output
No connect
5-volt supply input
Ground
PN220301.eps
Functional Description
If THS is tied to VCC, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to VSS or VCC for proper operation.
Two banks of CMOS static RAM can be battery-backed using the VOUT and the conditioned chip-enable output pins
from the bq2203A. As the voltage input VCC slews down
during a power failure, the two conditioned chip-enable
outputs, CE CON1 and CE CON2 , are forced inactive
independent of the chip-enable input CE.
If a memory access is in process to any of the two external banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time tWPT (150µs maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.
This activity unconditionally write-protects external SRAM
as VCC falls to an out-of-tolerance threshold VPFD. VPFD is
selected by the threshold select input pin, THS. If THS is
tied to VSS, the power-fail detection occurs at 4.62V typical
for 5% supply operation.
Nov. 1994 B
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bq2203A
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to the external backup energy source. CECON1 and CECON2 are held high by the
VOUT energy source.
The reset output (RST) goes active within tPFD (150µs
maximum) after VPFD, and remains active for a minimum of 40ms (120ms maximum) after power returns
valid. The RST output can be used as the power-on reset for a microprocessor. Access to the external RAM
may begin when RST returns inactive.
During power-up, VOUT is switched back to the 5V supply as VCC rises above the backup cell input voltage
sourcing VOUT. Outputs CECON1 and CECON2 are held
inactive for time t CER (120ms maximum) after the
power supply has reached VPFD, independent of the CE
input, to allow for processor stabilization.
Energy Cell Inputs—BCP, BCS
During power-valid operation, the CE input is passed
through to one of the two CECON outputs with a propagation delay of less than 10ns. The CE input is output on
one of the two CECON output pins depending on the level
of bank select input A, as shown in the Truth Table.
Two backup energy source inputs are provided on the
bq2203A—a primary cell BCP and a secondary cell BCS.
The primary cell input is designed to accept any 3V primary battery (non-rechargeable), typically some type of
lithium chemistry. If a primary cell is not to be used, the
BCP pin should be tied to VSS. The secondary cell input
BCS is designed to accept constant-voltage currentlimited rechargeable cells.
Bank select input A is usually tied to a high-order address pin so that a large nonvolatile memory can be designed using lower-density memory devices. Nonvolatility and decoding are achieved by hardware hookup as
shown in Figure 1.
During normal 5V power valid operation, 3.3V typical is output on the BCS pin and is current-limited internally. Although this charging method can be used with various 3V
secondary cells, it is specifically designed for a Panasonic VL
(vanadium-lithium) series of rechargeable cells.
5V
bq2203A
VCC
VOUT
BCF
BCL
From Address
Decoder
A
CECON1
CE
CECON2
BCP
RST
VCC
VCC
CMOS
SRAM
CMOS
SRAM
CE
CE
To Microprocessor
THS
3V Primary
Cell
VSS
BCS
3V Secondary
Cell
FG220301.eps
Figure 1. Hardware Hookup (5% Supply Operation)
Nov. 1994 B
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bq2203A
If a secondary cell is not to be used, the BCS pin must be
tied directly to VSS.
VCC falling below VPFD starts the comparison of BCS
and BCP. The BC input comparison continues until VCC
rises above VSO. Power to VOUT begins with BCS and
switches to BCP only when BCS is less than BCP minus
VBSO. The controller alternates to the higher BC voltage
when the difference between the BC input voltages is
greater than VBSO. Alternating the backup batteries allows one-at-a-time battery replacement and efficient use
of both backup batteries.
VPFD
VCC
VSO
To prevent battery drain when there is no valid data to
retain, VOUT, CECON1, and CECON2 are internally isolated from BCP and BCS by either of two methods:
■
Initial connection of a battery to BCP or BCS (VCC
grounded) or
■
Presentation of an isolation signal on CE.
0.5 VCC
CE
700ns
TD220101.eps
A valid isolation signal requires CE low as VCC crosses
both VPFD and VSO during a power-down. See Figure
2. Between these two points in time, CE must be
brought to VCC*(0.48 to 0.52) and held for at least 700ns.
The isolation signal is invalid if CE exceeds VCC*0.54 at
any point between VCC crossing VPFD and VSO.
Figure 2. Battery Isolation Signal
The isolation function is terminated and the appropriate
battery is connected to VOUT, CECON1, and CECON2 by
powering VCC up through VPFD.
Battery Monitor—BCL, BCF
As VCC rises past VPFD, the battery voltage on BCP is
compared with a dual-voltage reference. The result of
this comparison is latched internally, and output after
tBC when VCC rises past VPFD. If the battery voltage on
BCP is below VBL, then BCL is asserted low. If the battery is below VBF, then BCL and BCF are asserted low.
The results of this comparison remain latched until VCC
falls below VPFD.
Truth Table
Input
Output
CE
A
CECON1
CECON2
H
X
H
H
L
L
L
H
L
H
H
L
Nov. 1994 B
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bq2203A
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to +7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to +7.0
V
VT ≤ VCC + 0.3
0 to 70
°C
Commercial
TOPR
Operating temperature
-40 to +85
°C
“N” Industrial
TSTG
Storage temperature
-55 to +125
°C
TBIAS
Temperature under bias
-40 to +85
°C
TSOLDER
Soldering temperature
260
°C
IOUT
VOUT current
200
mA
Note:
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (TA = TOPR)
Symbol
VCC
Parameter
Supply voltage
VBCP
VBCS
Backup cell input voltage
Minimum
Typical
Maximum
Unit
4.75
5.0
5.5
V
THS = VSS
4.50
5.0
5.5
V
THS = VCC
2.0
-
4.0
V
VCC < VBC
2.0
-
4.0
V
VCC < VBC
0
0
0
V
VSS
Supply voltage
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
THS
Threshold select
-0.3
-
VCC + 0.3
V
Note:
Notes
Typical values indicate operation at TA = 25°C, VCC = 5V.
Nov. 1994 B
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bq2203A
bq2203A
DC Electrical Characteristics (TA = TOPR, VCC = 5V ± 10%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
-
-
±1
µA
Conditions/Notes
ILI
Input leakage current
VIN = VSS to VCC
VOH
Output high voltage
2.4
-
-
V
IOH = -2.0mA
VOHB
VOH, backup supply
VBC - 0.3
-
-
V
VBC > VCC, IOH = -10µA
VOL
Output low voltage
-
-
0.4
V
IOL = 4.0mA
ICC
Operating supply current
-
3
6
mA
VPFD
Power-fail detect voltage
4.55
4.62
4.75
V
THS = VSS
4.30
4.37
4.50
V
THS = VCC
No load on outputs
VSO
Supply switch-over voltage
-
VBC
-
V
ICCDR
Data-retention mode
current
-
-
100
nA
VBC
Active backup cell voltage
-
VBCS
-
V
VBCS > VBCP + VBSO
-
VBCP
-
V
VBCP > VBCS + VBSO
No load on outputs
VBSO
Battery switch-over voltage
0.25
0.4
0.6
V
RBCS
BCS charge output internal
resistance
500
1000
1750
Ω
VBCSO ≥ 3.0V
VBCSO
BCS charge output voltage
3.15
3.3
3.5
V
VCC > VPFD, RST inactive,
full charge or no load
IOUT1
VOUT current
-
-
160
mA
VOUT ≥ VCC - 0.3V
IOUT2
VOUT current
-
100
-
µA
VOUT ≥ VBC - 0.2V
VBL
Voltage battery low
2.3
-
2.5
V
BCP input only
VBF
Voltage battery fail
2.0
-
2.2
V
BCP input only
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC.
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
CIN
Input capacitance
-
-
8
pF
Input voltage = 0V
COUT
Output capacitance
-
-
10
pF
Output voltage = 0V
Note:
This parameter is sampled and not 100% tested.
Nov. 1994 B
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bq2203A
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5ns
Input and output timing reference levels
1.5V (unless otherwise specified)
Output load (including scope and jig)
See Figure 3
5V
960
CECON
510
100pF
FG220102.eps
Figure 3. Output Load
Power-Fail Control (TA = TOPR)
Symbol
Parameter
Min.
Typ.
Max.
Unit
tPF
VCC slew 4.75 to 4.25 V
300
-
-
µs
tFS
VCC slew 4.25 V to VSO
10
-
-
µs
tPU
VCC slew 4.25 to 4.75 V
0
tCED
Chip-enable propagation delay
tCER
Chip-enable recovery time
tRR
Conditions
-
-
µs
7
10
ns
40
80
120
ms
Time during which SRAM is writeprotected after VCC passes VPFD on
power-up
VPFD to RST inactive
tCER
-
tCER
ms
Time, after VCC becomes valid, before
RST is cleared
tAS
Input A set up to CE
0
-
-
ns
tWPT
Write-protect time
40
100
150
µs
Delay after VCC slews down past
VPFD before SRAM is write-protected
tR
VPFD to RST active
tWPT
-
tWPT
µs
Delay after VCC slews down past
VPFD before RST is active
tBC
VPFD to BCL/BCF active
tCER
-
tCER
ms
Delay after VCC slews up past VPFD
before BCL or BCF is active
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Nov. 1994 B
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bq2203A
Power-Down Timing
tPF
4.75
VPFD
tFS
4.25
VCC
VSO
CE
tWPT
VOHB
CECON
tR
RST
TD220202.eps
Power-Up Timing
tPU
VCC
4.25
VSO
4.75
VPFD
tCER
CE
CECON
tCED
VOHB
tCED
tRR
RST
tBC
BCL
BCF
TD220302.eps
Address-Decode Timing
A
tAS
CE
tCED
CECON1
tCED
CECON2
TD220204.eps
Nov. 1994 B
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bq2203A
16-Pin SOIC Narrow
16-Pin SN (SOIC Narrow)
D
e
Dimension
Minimum
A
0.060
A1
0.004
B
0.013
C
0.007
D
0.385
E
0.150
e
0.045
H
0.225
L
0.015
All dimensions are in inches.
B
E
H
Maximum
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
A
C
A1
.004
L
Nov. 1994 B
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bq2203A
16-Pin DIPNarrow
16-Pin PN (DIP Narrow)
Dimension
Minimum
A
0.160
A1
0.015
B
0.015
B1
0.055
C
0.008
D
0.740
E
0.300
E1
0.230
e
0.300
G
0.090
L
0.115
S
0.020
All dimensions are in inches.
Nov. 1994 B
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Maximum
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
bq2203A
Data Sheet Revision History
Change No.
Page No.
1
-
Changed data sheet from “Preliminary” to “Final”
1
5
Changed maximum charge output internal resistance (RBCS)
Note:
Description
Nature of Change
Was: 1500Ω
Is: 1750Ω
Change 1 = Nov. 1994 B changes from Dec. 1992 A.
Nov. 1994 B
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bq2203A
Ordering Information
bq2203A
Temperature Range:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*
Package Option:
PN = 16-pin plastic DIP Narrow
SN = 16-pin SOIC Narrow
Device:
bq2203A SRAM Nonvolatile Controller
With Battery Monitor and Reset
*Contact factory for availability.
Nov. 1994 B
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