AD EVAL-AD7768-4FMCZ 8-/4-channel, 24-bit, simultaneous sampling adcs with power scaling, 110.8 khz bw Datasheet

8-/4-Channel, 24-Bit, Simultaneous Sampling
ADCs with Power Scaling, 110.8 kHz BW
AD7768/AD7768-4
Data Sheet
FEATURES
Low latency sinc5 filter
Wideband brick wall filter: ±0.005 dB pass-band ripple
from dc to 102.4 kHz
Analog input precharge buffers
Power supply
AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
64-lead LQFP package, no exposed pad
Temperature range: −40°C to +105°C
Precision ac and dc performance
8-/4-channel simultaneous sampling
256 kSPS maximum ADC output data rate per channel
108 dB dynamic range
110.8 kHz maximum input bandwidth (−3 dB bandwidth)
−120 dB total harmonic distortion (THD) typical
±2 ppm of full-scale range (FSR) integral nonlinearity
(INL), ±50 µV offset error, ±30 ppm gain error
Optimized power dissipation vs. noise vs. input bandwidth
Selectable power, speed, and input bandwidth (BW) modes
Fast: highest speed; 110.8 kHz BW, 51.5 mW per channel
Median: half speed, 55.4 kHz BW, 27.5 mW per channel
Eco: lowest power, 13.8 kHz BW, 9.375 mW per channel
Input BW range: dc to 110.8 kHz
Programmable input bandwidth/sampling rates
Cyclic redundancy check (CRC) error checking on data interface
Daisy-chaining
Linear phase digital filter
APPLICATIONS
Data acquisition systems: USB/PXI/Ethernet
Instrumentation and industrial control loops
Audio test and measurement
Vibration and asset condition monitoring
3-phase power quality analysis
Sonar
High precision medical electroencephalogram (EEG)/
electromyography (EMG)/electrocardiogram (ECG)
FUNCTIONAL BLOCK DIAGRAM
AVDD1A,
AVDD1B
AVDD2A, REGCAPA,
AVDD2B REGCAPB
REFx+ REFx–
DGND
IOVDD
DREGCAP
BUFFERED
VCM
AIN0+
CH 0
AIN0–
P
AIN1+
CH 1
AIN1–
P
P
P
AIN2+
CH 2
AIN2–
P
AIN3+
CH 3
AIN3–
P
AIN4+
CH 4*
AIN4–
P
AIN5+
CH 5*
AIN5–
P
AIN6+
CH 6*
AIN6–
P
AIN7+
CH 7*
AIN7–
P
P
P
P
P
P
P
×8
Σ-Δ
ADC
1.8V
LDO
1.8V
LDO
PRECHARGE
REFERENCE
BUFFERS
SYNC_IN
SYNC_OUT
START
OFFSET,
GAIN PHASE
CORRECTION
DIGITAL
FILTER
ENGINE
RESET
FORMAT1*
FORMAT0
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
SINC5
LOW LATENCY
FILTER
Σ-Δ
ADC
ADC
OUTPUT
DATA
SERIAL
INTERFACE
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
WIDEBAND
LOW RIPPLE
FILTER
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
OFFSET,
GAIN PHASE
CORRECTION
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
AVSS
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4*
DOUT5*
DOUT6*, DIN
DOUT7*
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
DRDY
SPI
CONTROL
INTERFACE
ST0/CS
ST1*/SCLK
DEC0/SDO
DEC1/SDI
PIN/SPI
AD7768/AD7768-4
XTAL2/MCLK
*THESE CHANNELS/PINS EXIST ONLY ON THE AD7768.
XTAL1
MODE3/GPIO3
TO
MODE0/GPIO0
FILTER/GPIO4
14001-001
VCM
VCM
Figure 1.
Rev. A
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AD7768/AD7768-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
AD7768 Register Map Details (SPI Control).............................. 72
Applications ....................................................................................... 1
AD7768 Register Map................................................................ 72
Functional Block Diagram .............................................................. 1
Channel Standby Register ......................................................... 74
Revision History ............................................................................... 3
Channel Mode A Register ......................................................... 74
General Description ......................................................................... 5
Channel Mode B Register ......................................................... 75
Specifications..................................................................................... 6
Channel Mode Select Register .................................................. 75
1.8 V IOVDD Specifications ..................................................... 12
Power Mode Select Register ...................................................... 76
Timing Specifications ................................................................ 16
General Device Configuration Register .................................. 76
1.8 V IOVDD Timing Specifications ....................................... 17
Absolute Maximum Ratings.......................................................... 21
Data Control: Soft Reset, Sync, and Single-Shot Control
Register ........................................................................................ 77
Thermal Resistance .................................................................... 21
Interface Configuration Register.............................................. 78
ESD Caution ................................................................................ 21
Digital Filter RAM Built In Self Test (BIST) Register............ 78
Pin Configurations and Function Descriptions ......................... 22
Status Register ............................................................................. 79
Typical Performance Characteristics ........................................... 30
Revision Identification Register ............................................... 79
Terminology .................................................................................... 40
GPIO Control Register .............................................................. 79
Theory of Operation ...................................................................... 41
GPIO Write Data Register ......................................................... 80
Clocking, Sampling Tree, and Power Scaling ............................. 41
GPIO Read Data Register .......................................................... 80
Noise Performance and Resolution.......................................... 42
Analog Input Precharge Buffer Enable Register Channel 0 to
Channel 3 .................................................................................... 80
Applications Information .............................................................. 44
Power Supplies ............................................................................ 45
Device Configuration ................................................................ 46
Pin Control .................................................................................. 46
SPI Control .................................................................................. 49
SPI Control Functionality ......................................................... 50
SPI Control Mode Extra Diagnostic Features ........................ 53
Circuit Information ........................................................................ 54
Core Signal Chain....................................................................... 54
Analog Inputs .............................................................................. 55
VCM ............................................................................................. 56
Reference Input ........................................................................... 56
Clock Selection ........................................................................... 56
Digital Filtering ........................................................................... 56
Decimation Rate Control .......................................................... 58
Antialiasing ................................................................................. 58
Calibration ................................................................................... 59
Data Interface .................................................................................. 61
Setting the Format of Data Output .......................................... 61
ADC Conversion Output: Header and Data .......................... 62
Analog Input Precharge Buffer Enable Register Channel 4 to
Channel 7 .................................................................................... 81
Positive Reference Precharge Buffer Enable Register ............ 81
Negative Reference Precharge Buffer Enable Register .......... 82
Offset Registers ........................................................................... 82
Gain Registers ............................................................................. 83
Sync Phase Offset Registers ...................................................... 83
ADC Diagnostic Receive Select Register ................................ 83
ADC Diagnostic Control Register ........................................... 84
Modulator Delay Control Register........................................... 85
Chopping Control Register ....................................................... 85
AD7768-4 Register Map Details (SPI Control) .......................... 86
AD7768-4 Register Map ............................................................ 86
Channel Standby Register ......................................................... 88
Channel Mode A Register ......................................................... 88
Channel Mode B Register ......................................................... 89
Channel Mode Select Register .................................................. 89
Power Mode Select Register ...................................................... 89
General Device Configuration Register .................................. 90
Functionality ................................................................................... 71
Data Control: Soft Reset, Sync, and Single-Shot Control
Register ........................................................................................ 91
GPIO Functionality .................................................................... 71
Interface Configuration Register.............................................. 91
Rev. A | Page 2 of 99
Data Sheet
AD7768/AD7768-4
Digital Filter RAM Built In Self Test (BIST) Register ............92
Negative Reference Precharge Buffer Enable Register ........... 95
Status Register..............................................................................92
Offset Registers............................................................................ 96
Revision Identification Register ................................................93
Gain Registers .............................................................................. 96
GPIO Control Register ...............................................................93
Sync Phase Offset Registers ....................................................... 96
GPIO Write Data Register .........................................................94
ADC Diagnostic Receive Select Register ................................. 96
GPIO Read Data Register ..........................................................94
ADC Diagnostic Control Register ............................................ 97
Analog Input Precharge Buffer Enable Register Channel 0
And Channel 1.............................................................................94
Modulator Delay Control Register ........................................... 97
Analog Input Precharge Buffer Enable Register Channel 2
And Channel 3.............................................................................95
Outline Dimensions ........................................................................ 99
Positive Reference Precharge Buffer Enable Register .............95
Chopping Control Register........................................................ 98
Ordering Guide ........................................................................... 99
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Added AD7768-4 ............................................................... Universal
Changed Precharge Analog Input Reference to Analog Input
Precharge ........................................................................ Throughout
Changes to General Description Section ....................................... 5
Changes to Table 1 ............................................................................ 6
Changes to Table 2 ..........................................................................12
Changes to Table 3 and t30 Parameter, Table 4 .............................16
Changes to Table 5 ..........................................................................17
Changes to t30 Parameter, Table 6 and Figure 2 ...........................18
Changes to Figure 4 and Figure 7..................................................19
Changes to Figure 8 and Figure 9..................................................20
Changes to Figure 10 and Table 9 .................................................22
Added Figure 11 and Table 10; Renumbered Sequentially ........26
Changes to Typical Performance Characteristics Section .........30
Changes to Theory of Operation Section and Clocking,
Sampling Tree, and Power Scaling Section ..................................41
Changes to Table 11 ........................................................................42
Added Example of Power vs. Noise Performance Optimization
Section and Clocking Out the ADC Conversion Results
(DCLK) Section ...............................................................................42
Changes to Applications Information Section and Figure 73 ...44
Changes to Table 14 and Power Supplies Section .......................45
Moved 1.8 V IOVDD Operation Section.....................................46
Changes to Figure 75, Analog Supply Internal Connectivity
Section, and Pin Control Section ..................................................46
Added Figure 76 ..............................................................................47
Changes to Channel Standby Section and Accessing the ADC
Register Map Section ......................................................................49
Added Table 22 ................................................................................49
Changes to Channel Configuration Section ................................50
Changes to Channel Modes Section, Reset over SPI Control
Interface Section, Sleep Mode Section, and Channel Standby
Section ..............................................................................................51
Changes to MCLK Source Selection Section, Interface
Configuration Section, and ADC Synchronization over SPI
Section ..............................................................................................52
Added Figure 81 ..............................................................................52
Changes to RAM Built In Self Test Section ................................. 53
Changes to Analog Inputs Section and Figure 85....................... 55
Added Figure 86 .............................................................................. 55
Added Table 27 ................................................................................ 56
Changes to VCM Section, Reference Input Section, and Digital
Filtering Section .............................................................................. 56
Changes to Figure 87, Figure 88, and Figure 89 .......................... 57
Changes to Antialiasing Section and Modulator Sampling
Frequency Section ........................................................................... 58
Changes to Modulator Chopping Frequency Section and
Table 29, and Modulator Saturation Point Section, .................... 59
Changes to Sync Phase Offset Adjustment Section .................... 60
Changes to Setting the Format of Data Output Section ............ 61
Added Table 32 and Figure 93 ....................................................... 61
Changes to Figure 94 Caption and ADC Conversion Output:
Header and Data Section ............................................................... 62
Changes to Data Interface: Standard Conversion Operation
Section .............................................................................................. 63
Changes to Figure 99 ...................................................................... 64
Added Figure 100 ............................................................................ 64
Added Figure 101 ............................................................................ 65
Changes to Daisy-Chaining Section and Figure 104.................. 66
Added Figure 105 ............................................................................ 67
Changes to CRC Check on Data Interface Section .................... 68
Changes to Table 35 ........................................................................ 69
Changes to Table 36 ........................................................................ 70
Changes to GPIO Functionality Section and Figure 108........... 71
Added Figure 109 ............................................................................ 71
Changes to AD7768 Register Map Details (SPI Control) Section
and Table 37 ..................................................................................... 72
Changes to Channel Standby Register Section ........................... 74
Changes to Table 42 and Table 43 ................................................. 76
Changes to Table 44 ........................................................................ 77
Changes to Table 45 and Table 46 ................................................. 78
Changes to Table 49 ........................................................................ 79
Changes to Table 61 ........................................................................ 85
Added AD7768-4 Register Map Details (SPI Control) Section and
Table 63 ...................................................................................................... 86
Rev. A | Page 3 of 99
AD7768/AD7768-4
Data Sheet
Added Table 64 and Table 65 ................................................................. 88
Added Table 66, Table 67, and Table 68 ............................................... 89
Added Table 69 ......................................................................................... 90
Added Table 70 and Table 71 ................................................................. 91
Added Table 72 and Table 73 ................................................................. 92
Added Table 74 and Table 75 ................................................................. 93
Added Table 76, Table 77, and Table 78 ............................................... 94
Added Table 79, Table 80, and Table 81 ...............................................95
Added Table 82, Table 83, Table 84, and Table 85 ..............................96
Added Table 86 and Table 87 .................................................................97
Added Table 88 .........................................................................................98
Changes to Ordering Guide ...................................................................99
1/16—Revision 0: Initial Version
Rev. A | Page 4 of 99
Data Sheet
AD7768/AD7768-4
GENERAL DESCRIPTION
The AD7768/AD7768-4 are 8-channel and 4-channel,
simultaneous sampling sigma-delta (Σ-Δ) analog-to-digital
converters (ADCs), respectively, with a Σ-Δ modulator and digital
filter per channel, enabling synchronized sampling of ac and dc
signals.
Within these filter options, the user can improve the dynamic
range by selecting from decimation rates of ×32, ×64, ×128,
×256, ×512, and ×1024. The ability to vary the decimation
filtering optimizes noise performance to the required input
bandwidth.
The AD7768/AD7768-4 achieve 108 dB dynamic range at a
maximum input bandwidth of 110.8 kHz, combined with typical
performance of ±2 ppm INL, ±50 µV offset error, and ±30 ppm
gain error.
Embedded analog functionality on each ADC channel makes
design easier, such as a precharge buffer on each analog input
that reduces analog input current and a reference precharge
buffer per channel reduces input current and glitches on the
reference input terminals.
The AD7768/AD7768-4 user can trade off input bandwidth,
output data rate, and power dissipation, and select one of three
power modes to optimize for noise targets and power
consumption. The flexibility of the AD7768/AD7768-4 allows
them to become reusable platforms for low power dc and high
performance ac measurement modules.
The AD7768/AD7768-4 have three modes: fast mode (256 kSPS
maximum, 110.8 kHz input bandwidth, 51.5 mW per channel),
median mode (128 kSPS maximum, 55.4 kHz input bandwidth,
27.5 mW per channel) and eco mode (32 kSPS maximum,
13.8 kHz input bandwidth, 9.375 mW per channel).
The AD7768/AD7768-4 offer extensive digital filtering
capabilities, such as a wideband, low ±0.005 dB pass-band
ripple, antialiasing low-pass filter with sharp roll-off, and
105 dB stop band attenuation at the Nyquist frequency.
The device operates with a 5 V AVDD1A and AVDD1B supply,
a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to
3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation
section for specific requirements for operating at 1.8 V IOVDD).
The device requires an external reference; the absolute input
reference voltage range is 1 V to AVDD1 − AVSS.
For the purposes of clarity within this document, the AVDD1A
and AVDD1B supplies are referred to as AVDD1 and the AVDD2A
and AVDD2B supplies are referred to as AVDD2. For the negative
supplies, AVSS refers to the AVSS1A, AVSS1B, AVSS2A,
AVSS2B, and AVSS pins.
The specified operating temperature range is −40°C to +105°C.
The device is housed in a 10 mm × 10 mm 64-lead LQFP package
with a 12 mm × 12 mm printed circuit board (PCB) footprint.
Frequency domain measurements can use the wideband linear
phase filter. This filter has a flat pass band (±0.005 dB ripple)
from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at
128 kSPS, or from dc to 12.8 kHz at 32 kSPS.
Throughout this data sheet, multifunction pins, such as
XTAL2/MCLK, are referred to either by the entire pin name or
by a single function of the pin, for example MCLK, when only
that function is relevant.
The AD7768/AD7768-4 also offer sinc response via a sinc5
filter, a low latency path for low bandwidth, and low noise
measurements. The wideband and sinc5 filters can be selected
and run on a per channel basis.
Rev. A | Page 5 of 99
AD7768/AD7768-4
Data Sheet
SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 2.25 V to 3.6 V, AVSS = DGND = 0 V, REFx+ =
4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, wideband filter, fCHOP =
fMOD/32, TA = −40°C to +105°C, unless otherwise noted. See Table 2 for specifications at 1.8 V IOVDD.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR), per
Channel1
−3 dB Bandwidth
Data Output Coding
No Missing Codes2
DYNAMIC PERFORMANCE
Fast
Dynamic Range
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-andDistortion Ratio (SINAD)
Total Harmonic Distortion
(THD)
Spurious-Free Dynamic
Range (SFDR)
Median
Dynamic Range
SNR
SINAD
THD
SFDR
Eco
Dynamic Range
SNR
SINAD
THD
SFDR
INTERMODULATON DISTORTION
(IMD)3
Test Conditions/Comments
Min
Fast
8
Median
Eco
Fast, wideband filter
Median, wideband filter
Eco, wideband filter
4
1
Typ
Max
Unit
256
kSPS
128
32
110.8
55.4
13.8
Twos complement, MSB first
24
For 1.8 V operation, see Table 2; for
dynamic range and SNR across all decimation rates, see Table 12 and Table 13
Decimation by 32, 256 kSPS ODR
Shorted input, wideband filter
1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter
Wideband filter
1 kHz, −0.5 dBFS, sine wave input
Decimation by 32, 32 kHz ODR
Shorted input, wideband filter
Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave
input
Wideband filter, 1 kHz, −0.5 dBFS, sine
wave input
1 kHz, −0.5 dBFS, sine wave input
1 kHz, −0.5 dBFS, sine wave input
Bits
106.2
108
dB
109
106
104.7
111
107.8
107.5
dB
dB
dB
1 kHz, −0.5 dBFS, sine wave input
Decimation by 32, 128 kHz ODR
Shorted input, wideband filter
Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave
input
Wideband filter, 1 kHz, −0.5 dBFS, sine
wave input
1 kHz, −0.5 dBFS, sine wave input
1 kHz, −0.5 dBFS, sine wave input
kSPS
kSPS
kHz
kHz
kHz
−120
−107
dB
128
dBc
106.2
109
108
111
dB
dB
106
107.8
dB
105.8
107.5
−120
128
dB
dB
dBc
−113
106.2
109
108
111
dB
dB
106
107.8
dB
105.8
107.5
−120
128
−113
dB
dB
dBc
fa = 9.7 kHz, fb = 10.3 kHz
Second order
Third order
−125
−125
Rev. A | Page 6 of 99
dB
dB
Data Sheet
Parameter
ACCURACY
INL
Offset Error4
Offset Error Drift
Gain Error4
Gain Drift vs. Temperature2
VCM PIN
Output
Load Regulation (∆VOUT/∆IL)
Voltage Regulation
Short-Circuit Current
ANALOG INPUTS
Differential Input Voltage Range
Input Common-Mode Range2
Absolute Analog Input
Voltage Limits2
Analog Input Current
Unbuffered
Precharge Buffer On5
Input Current Drift
Unbuffered
Precharge Buffer On
EXTERNAL REFERENCE
Reference Voltage
Absolute Reference Voltage
Limits2
Average Reference Current
Average Reference Current Drift
Common-Mode Rejection
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter
Decimation Rate
Group Delay
Settling Time
Pass-Band Ripple2
Pass Band
Stop Band Frequency
Stop Band Attenuation
AD7768/AD7768-4
Test Conditions/Comments
See Table 2 for 1.8 V operation
Endpoint method
DCLK frequency ≤ 24 MHz
24 MHz to 32.768 MHz DCLK frequency2
DCLK frequency ≤ 24 MHz
24 MHz to 32.768 MHz DCLK frequency
TA = 25°C
Min
With respect to AVSS
Applies to the following VCM output
options only: VCM = ∆VOUT/∆(AVDD1 −
AVSS)/2; VCM = 1.65 V; and VCM = 2.5 V
See the Analog Inputs section
VREF = (REFx+) − (REFx−)
Typ
Max
Unit
±2
±50
±75
±250
±750
±30
±0.5
±7
±115
±150
ppm of FSR
µV
µV
nV/°C
nV/°C
ppm of FSR
ppm/°C
(AVDD1 −
AVSS)/2
400
5
V
30
mA
−VREF
AVSS
AVSS
Fast mode
Differential component
Common-mode component
±70
±1
µV/mA
µV/V
+VREF
AVDD1
AVDD1
V
V
V
±48
±17
−20
µA/V
µA/V
µA
±5
±31
nA/V/°C
nA/°C
Fast mode; see Figure 62
VREF = (REFx+) − (REFx−)
Reference precharge buffers off
1
AVSS − 0.05
AVDD1 − AVSS
AVDD1 + 0.05
V
V
Reference precharge buffer on
Fast mode; see Figure 63
Reference precharge buffers off
Reference precharge buffers on
Fast mode; see Figure 63
Reference precharge buffers off
Reference precharge buffers on
AVSS
AVDD1
V
FILTER = 0
Up to six selectable decimation rates; see
the Decimation Rate Control section
Latency
Complete settling, see Table 35
From dc to 102.4 kHz at 256 kSPS
±0.005 dB bandwidth
−0.1 dB bandwidth
−3 dB bandwidth
Attenuation > 105 dB
See the Wideband Low Ripple Filter section
Rev. A | Page 7 of 99
±72
±16
µA/V/channel
µA/V/channel
±1.7
±49
95
nA/V/°C
nA/V/°C
dB
32
1024
34/ODR
68/ODR
±0.005
0.4 × ODR
0.409 × ODR
0.433 × ODR
0.499 × ODR
105
sec
sec
dB
Hz
Hz
Hz
Hz
dB
AD7768/AD7768-4
Parameter
Sinc5 Filter
Decimation Rate
Group Delay
Settling Time
Pass Band
REJECTION
AC Power Supply Rejection
Ratio (PSRR)
AVDD1
AVDD2
IOVDD
DC PSRR
AVDD1
AVDD2
IOVDD
Analog Input Common-Mode
Rejection Ratio (CMRR)
DC
AC
Crosstalk
CLOCK
Crystal Frequency
External Clock (MCLK)
Duty Cycle
MCLK Pulse Width2
Logic Low
Logic High
CMOS Clock Input Voltage
High, VINH
Low, VINL
LVDS Clock2
Differential Input Voltage
Common-Mode Input
Voltage
Absolute Input Voltage
ADC RESET2
ADC Start-Up Time After Reset6
Minimum RESET Low Pulse
Width
LOGIC INPUTS
Input Voltage2
High, VINH
Data Sheet
Test Conditions/Comments
FILTER = 1
Up to six selectable decimation rates; see
the Decimation Rate Control section
Latency
Complete settling, see Table 36
−3 dB bandwidth
Typ
32
Max
Unit
1024
3/ODR
7/ODR
0.204 × ODR
sec
sec
Hz
90
100
75
dB
dB
dB
100
118
90
dB
dB
dB
95
−120
dB
dB
dB
VIN = 0.1 V, AVDD1 = 5 V, AVDD2 = 5 V,
IOVDD = 2.5 V
VIN = 1 V
VIN = 0.1 V
Up to 10 kHz
−0.5 dBFS input on adjacent channels
95
8
See the Timing Specifications section
For data sheet performance
Functionality
32.768
32.768
50:50
34
12.2
12.2
MHz
MHz
%
ns
ns
See the logic inputs parameter
RL = 100 Ω
100
800
Time to first DRDY, fast mode, decimation
by 32
tMCLK = 1/MCLK
1.58
650
1575
mV
mV
1.88
V
1.66
ms
2 × tMCLK
See Table 2 for 1.8 V operation
V
0.65 ×
IOVDD
Low, VINL
Hysteresis2
Leakage Current
0.04
−10
−10
RESET pin7
LOGIC OUTPUTS
Output Voltage2
High, VOH
Low, VOL
Min
+0.03
0.7
0.09
+10
+10
V
V
µA
µA
0.4
V
V
See Table 2 for 1.8 V operation
ISOURCE = 200 μA
ISINK = 400 µA
0.8 × IOVDD
Rev. A | Page 8 of 99
Data Sheet
Parameter
Leakage Current
Output Capacitance
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS
AVDD2 − AVSS
AVSS − DGND
IOVDD − DGND
POWER SUPPLY CURRENTS
AD7768
Fast Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Median Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Eco Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
AD7768-4
Fast Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Median Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Eco Mode
AVDD1 Current
AVDD2 Current
AD7768/AD7768-4
Test Conditions/Comments
Floating state
Floating state
Min
−10
Typ
Max
+10
Unit
µA
pF
1.05 × VREF
2.1 × VREF
V
V
V
2.5 to 3.3
5.5
5.5
0
3.6
V
V
V
V
36/57.5
37.5
63
27
40/64
40
67
29
mA
mA
mA
mA
18.5/29
21.3
34
16
20.5/32.5
23
37
18
mA
mA
mA
mA
5.1/8
9.3
12.5
8
5.8/9
10.1
13.7
9
mA
mA
mA
mA
18.2/28.8
18.8
43.5
37
20.3/32.5
20.3
46.8
40
mA
mA
mA
mA
17
18.6
mA
9.3/14.7
10.7
24.4
21
10.5/16.6
11.7
26.4
23
mA
mA
mA
mA
11
12.3
mA
2.7/4.1
4.7
3.1/4.7
5.3
mA
mA
10
−1.05 × VREF
0.4 × VREF
See Table 2 for 1.8 V operation
Maximum output data rate, CMOS MCLK,
eight DOUTx signals, all supplies at
maximum voltages, all channels in
Channel Mode A except where
otherwise specified
Eight channels active
Reference precharge buffers off/on
Wideband filter
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Sinc5 filter
Four Channels Active
Reference precharge buffers off/on
Wideband filter2
Wideband filter, SPI mode only;
Channel Mode A set to sinc5 filter8
Sinc5 filter2
Reference precharge buffers off/on
Wideband filter2
Wideband filter, SPI mode only;
Channel Mode A set to sinc5 filter8
Sinc5 filter2
Reference precharge buffers off/on
Rev. A | Page 9 of 99
4.5
2.0
−2.75
2.25
5.0
2.25 to 5.0
AD7768/AD7768-4
Parameter
IOVDD Current
AD7768 and AD7768-4—Two
Channels Active2
Fast Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Median Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Eco Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Standby Mode
Sleep Mode2
Crystal Excitation Current
POWER DISSIPATION
Full Operating Mode
AD7768
Wideband Filter
Fast
Median
Data Sheet
Test Conditions/Comments
Wideband filter2
Wideband filter, SPI mode only;
Channel Mode A set to sinc5 filter8
Sinc5 filter2
Serial peripheral interface (SPI) control
mode only; see the Channel Standby
section for details on disabling channels
Min
Reference precharge buffers off/on
Wideband filter
Wideband filter; disabled channels in
Channel Mode A, and set to sinc5 filter
mode8
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Wideband filter; disabled channels in
Channel Mode A, and set to sinc5 filter
mode8
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Wideband filter; disabled channels in
Channel Mode A, and set to sinc5 filter
mode8
Sinc5 filter
All channels disabled (sinc5 filter enabled)
Full power-down (SPI control mode only)
Extra current in IOVDD when using an
external crystal compared to using the
CMOS MCLK
External CMOS MCLK, all channels
active, MCLK = 32.768 MHz, all channels
in Channel Mode A except where
otherwise specified
Analog precharge buffers on
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
Rev. A | Page 10 of 99
Typ
10
9
Max
11.1
10
Unit
mA
mA
6.5
7.6
mA
9.3/14.7
9.5
33.7
23.4
10.5/16.6
10.5
36.3
25.5
mA
mA
mA
mA
11.9
13.3
mA
4.8/7.5
5.5
19.4
14.1
5.5/8.6
6.2
21.1
15.5
mA
mA
mA
mA
8.5
9.6
mA
1.52/2.2
2.4
8.6
7.2
1.77/2.6
3
9.7
8
mA
mA
mA
mA
5.8
6.5
0.73
540
6.7
8
1.2
mA
mA
mA
µA
412
446
mW
600
645
mW
631
681
mW
220
240
mW
320
345
mW
341
372
mW
Data Sheet
Parameter
Eco
Sinc5 Filter
Fast
Median
Eco
AD7768-4
Wideband Filter
Fast
Median
Eco
AD7768/AD7768-4
Test Conditions/Comments
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
Min
Typ
75
Max
85
Unit
mW
107
118
mW
124
137
mW
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
325
355
mW
475
525
mW
501
545
mW
175
195
mW
260
285
mW
277
304
mW
65
72
mW
95
105
mW
108
120
mW
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off2
SPI mode only; AVDD1 = 5.5 V, AVDD2 =
5.5 V, IOVDD = 3.6 V, reference precharge
buffers off, Channel Mode A set to sinc5
filter8
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off2
SPI mode only; AVDD1 = 5.5 V, AVDD2 =
5.5 V, IOVDD = 3.6 V, reference precharge
buffers off, Channel Mode A set to sinc5
filter8
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off2
SPI mode only; AVDD1 = 5.5 V, AVDD2 =
5.5 V, IOVDD = 3.6 V, reference precharge
buffers off, Channel Mode A set to sinc5
filter8
235
mW
336
mW
Rev. A | Page 11 of 99
360
392
mW
337
368
mW
127
mW
181
mW
198
218
mW
186
205
mW
49
mW
66
mW
77
87
mW
73
83
mW
AD7768/AD7768-4
Parameter
Sinc5 Filter
Fast
Median
Eco
Standby Mode
Sleep Mode2
Data Sheet
Test Conditions/Comments
Min
Typ
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
reference precharge buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
reference precharge buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD =
3.6 V, reference precharge buffers off
All channels disabled (sinc5 filter enabled),
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V2
AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V
Full power-down (SPI control mode),
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V
AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V
Max
Unit
168
mW
248
mW
265
291
mW
94
mW
137
mW
150
167
mW
40
mW
55
mW
64
1.8
2.5
2.7
74
mW
18
26
29
mW
mW
mW
4
5
6.5
mW
mW
mW
The output data rate ranges refer to the programmable decimation rates available on the AD7768/AD7668-4 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates
allow users a wider variation of ODR.
2
These specifications are not production tested but are supported by characterization data at initial product release.
3
See the Terminology section for more information about the fa and fb input frequencies.
4
Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration
reduces the gain error to the order of the noise for the programmed output data rate.
5
−25 µA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 −
AVSS)/2. The analog input current scales with the MCLK frequency and device power mode. See Figure 85 and Figure 86 for more details on how the analog input
current scales with input voltage.
6
For lower MCLK rates or higher decimation rates, use Table 35 and Table 36 to calculate any additional delay before the first DRDY pulse.
7
The RESET pin has an internal pull-up device to IOVDD.
8
Configuring Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be achieved. To do this,
the user must be operating in SPI control mode because it requires assigning channels to different channel modes (only possible in SPI control mode). If using pin
control mode, all channels, whether active or in standby, are assigned to the same channel group and use the same filter type. This means that, in pin control mode, a
higher current consumption is seen from disabled channels than can be achieved in SPI mode. See the Channel Modes section for more details.
1
E
E
1.8 V IOVDD SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V, AVSS = DGND = 0 V, REFx+ =
4.096 V and REFx− = 0 V, MCLK = 32.76 8 MHz, analog precharge buffers on, reference precharge buffers off, wideband filter, fCHOP =
fMOD/32, TA = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Fast
Dynamic Range
SNR
Test Conditions/Comments
For dynamic range and SNR across all decimation
rates, see Table 12 and Table 13
Decimation by 32, 256 kSPS ODR
Shorted input, wideband filter
Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input
Rev. A | Page 12 of 99
Min
Typ
106.2
109
106
108
111
107.8
Max
Unit
dB
dB
dB
Data Sheet
Parameter
SINAD1
THD
SFDR
Median
Dynamic Range
SNR
SINAD
THD
SFDR
Eco
Dynamic Range
SNR
SINAD
THD
SFDR
ACCURACY1
INL
Offset Error2
Offset Error Drift
Gain Error2
Gain Drift vs. Temperature
LOGIC INPUTS
Input Voltage1
High, VINH
Low, VINL
Hysteresis1
Leakage Current
AD7768/AD7768-4
Test Conditions/Comments
1 kHz, −0.5 dBFS, sine wave input
1 kHz, −0.5 dBFS, sine wave input
Decimation by 32, 128 kHz ODR
Shorted input, wideband filter
1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter
Wideband filter
1 kHz, −0.5 dBFS, sine wave input
1 kHz, −0.5 dBFS, sine wave input
Decimation by 32, 32 kHz ODR
Shorted input, wideband filter
Sinc5 filter, 1 kHz, −0.5 dBFS, sine wave input
Wideband filter, 1 kHz, −0.5 dBFS, sine wave input
1 kHz, −0.5 dBFS, sine wave input
1 kHz, −0.5 dBFS, sine wave input
AD7768
Fast Mode
AVDD1 Current
AVDD2 Current
Typ
107.5
−120
128
Max
−107
108
dB
109
106
105.8
111
107.8
107.5
−120
128
dB
dB
dB
dB
dBc
106.2
109
106
105.8
108
111
107.8
107.5
−120
128
−113
−113
±2
±7
DCLK frequency ≤ 24 MHz
24 MHz to 32.768 MHz DCLK frequency
DCLK frequency ≤ 24 MHz
24 MHz to 32.768 MHz DCLK frequency
TA = 25°C
±50
±75
±250
±750
±60
±0.5
±115
±170
0.04
−10
−10
+0.03
±120
±2
0.4
0.2
+10
+10
V
V
V
µA
µA
0.8 × IOVDD
0.4
+10
V
V
µA
pF
1.8
5.5
5.5
0
1.88
V
V
V
V
36/57.5
37.5
40/64
40
mA
mA
−10
10
DREGCAP shorted to IOVDD
Maximum output data rate, CMOS MCLK, eight DOUTx
signals, all supplies at maximum voltages, all channels in
Channel Mode A except where otherwise specified
Eight channels active
Reference precharge buffers off/on
Rev. A | Page 13 of 99
4.5
2.0
−2.75
1.72
dB
dB
dB
dB
dB
dBc
ppm of
FSR
µV
µV
nV/°C
nV/°C
ppm/FSR
ppm/°C
0.65 × IOVDD
ISOURCE = 200 µA
ISINK = 400 µA
Floating state
Floating state
Unit
dB
dB
dBc
106.2
Endpoint method
RESET pin
LOGIC OUTPUTS
Output Voltage1
High, VOH
Low, VOL
Leakage Current
Output Capacitance
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS
AVDD2 − AVSS
AVSS − DGND
IOVDD − DGND
POWER SUPPLY CURRENTS1
Min
103.8
5.0
2.25 to 5.0
AD7768/AD7768-4
Parameter
IOVDD Current
Median Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Eco Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
AD7768-4
Fast Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Median Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Eco Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
AD7768 and AD7768-4—
Two Channels Active
Fast Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Median Mode
AVDD1 Current
AVDD2 Current
IOVDD Current
Eco Mode
AVDD1 Current
AVDD2 Current
Data Sheet
Test Conditions/Comments
Wideband filter
Sinc5 filter
Min
Reference precharge buffers off/on
Wideband filter
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Sinc5 filter
Four channels active
Reference precharge buffers off/on
Wideband filter
Wideband filter, SPI mode only; Channel Mode A set
to sinc5 filter3
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Wideband filter, SPI mode only; Channel Mode A set
to sinc5 filter3
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Wideband filter, SPI mode only; Channel Mode A set
to sinc5 filter3
Sinc5 filter
SPI control mode only; see the Channel Standby section
for details on disabling channels
Reference precharge buffers off/on
Wideband filter
Wideband filter, SPI mode only; disabled channels in
Channel Mode A, and set to sinc5 filter3
Sinc5 filter
Reference precharge buffers off/on
Wideband filter
Wideband filter, SPI mode only; disabled channels in
Channel Mode A, and set to sinc5 filter3
Sinc5 filter
Reference precharge buffers off/on
Rev. A | Page 14 of 99
Typ
63
26
Max
69
28.4
Unit
mA
mA
18.5/29
21.3
34
15
20.5/32.5
23
36.8
16.8
mA
mA
mA
mA
5.1/8
9.3
11.6
7
5.8/9
10.1
12.9
8.1
mA
mA
mA
mA
18.2/28.8
18.8
43.9
36.8
20.3/32.5
20.3
47.7
41
mA
mA
mA
mA
16
17.7
mA
9.3/14.7
10.7
24
20.4
10.5/16.6
11.7
26.1
22.7
mA
mA
mA
mA
10
11.3
mA
2.7/4.1
4.7
9
8.1
3.1/4.7
5.3
10.2
9.2
mA
mA
mA
mA
5.5
6.5
mA
9.3/14.7
9.5
33.8
23.1
10.5/16.6
10.5
36.7
25.6
mA
mA
mA
mA
11
12.3
mA
4.8/7.5
5.5
18.9
13.4
5.5/8.6
6.2
20.6
15.1
mA
mA
mA
mA
7.4
8.6
mA
1.52/2.2
2.4
1.77/2.6
3
mA
mA
Data Sheet
Parameter
IOVDD Current
Standby Mode
Sleep Mode
Crystal Excitation Current
POWER DISSIPATION1
Full Operating Mode
AD7768
Wideband Filter
Fast
Median
Eco
Sinc5 Filter
Fast
Median
Eco
AD7768-4
Wideband Filter
Fast
Median
Eco
Sinc5 Filter
Fast
Median
Eco
Standby Mode
Sleep Mode
AD7768/AD7768-4
Test Conditions/Comments
Wideband filter
Wideband filter, SPI mode only; disabled channels in
Channel Mode A, and set to sinc5 filter3
Sinc5 filter
All channels disabled (sinc5 filter enabled)
Full power-down (SPI control mode)
Extra current in IOVDD when using an external crystal
compared to using the CMOS MCLK
External CMOS MCLK, all channels active, AVDD1 =
AVDD2 = 5.5 V, IOVDD = 1.88 V, MCLK = 32.768 MHz, all
channels in Channel Mode A except where otherwise
noted
Analog precharge buffers on
Eight channels active
Min
Typ
7.6
6.3
Max
8.8
7.2
Unit
mA
mA
4.8
6.5
0.73
540
5.8
8
1.2
mA
mA
mA
µA
Reference precharge buffers off
Reference precharge buffers on
Reference precharge buffers off
Reference precharge buffers on
Reference precharge buffers off
Reference precharge buffers on
524
638
284
342
98.5
118
571
704
309
375
109
130
mW
mW
mW
mW
mW
mW
Reference precharge buffers off
Reference precharge buffers off
Reference precharge buffers off
Four channels active
455
248
94
495
271
105
mW
mW
mW
Reference precharge buffers off
Reference precharge buffers on
Reference precharge buffers off
Reference precharge buffers on
Reference precharge buffers off
Reference precharge buffers on
287
345
156
185
58
66
314
381
172
206
66
75
mW
mW
mW
mW
mW
mW
Reference precharge buffers off
Reference precharge buffers off
Reference precharge buffers off
All channels disabled (sinc5 filter enabled)
Full power-down (SPI control mode)
234
129
51
257
144
59
17
4.5
mW
mW
mW
mW
mW
1.5
These specifications are not production tested but are supported by characterization data at initial product release.
Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration
reduces the gain error to the order of the noise for the programmed output data rate.
3
This configuration of setting Channel Mode A to the sinc5 filter and/or assigning disabled channels to Channel Mode A allows a lower power consumption to be
achieved due to the disabling of internal clocks on the disabled only and sinc5 only channel modes. This configuration requires assigning sinc5 and wideband filters to
different channels, or channel modes, and is only available in SPI control mode. In pin control mode, all channels, whether active or in standby, effectively use the
same channel mode. See the Channel Modes section for more details.
1
2
Rev. A | Page 15 of 99
AD7768/AD7768-4
Data Sheet
TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD;
CLOAD = 10 pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs; REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 5 and
Table 6 for timing specifications at 1.8 V IOVDD.
Table 3. Data Interface Timing1
Parameter
MCLK
fMOD
Description
Master clock
Modulator frequency
t1
t2
t3
t4
t5
t6
t7
t8
t10
t11
DRDY high time
DCLK rising edge to DRDY rising edge
DCLK rising to DRDY falling
DCLK rise to DOUTx valid
DCLK rise to DOUTx invalid
DOUTx valid to DCLK falling
DCLK falling edge to DOUTx invalid
DCLK high time, DCLK = MCLK/1
t8a = DCLK = MCLK/2
t8b = DCLK = MCLK/4
t8c = DCLK = MCLK/8
DCLK low time DCLK = MCLK/1
t9a = DCLK = MCLK/2
t9b = DCLK = MCLK/4
t9c = DCLK = MCLK/8
MCLK rising to DCLK rising
Setup time (daisy-chain inputs)
t12
Hold time (daisy-chain inputs)
t13
t14
START low time
MCLK to SYNC_OUT valid
t9
t15
t16
1
SYNC_IN setup time
SYNC_IN hold time
Test Conditions/Comments
Fast mode
Median mode
Eco mode
tDCLK = t8 + t9
Min
1.15
Typ
14
Unit
MHz
Hz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
1 × tMCLK
ns
tDCLK − 10%
Max
34
MCLK/4
MCLK/8
MCLK/32
28
2
0
1.5
−3.5
50:50 CMOS clock
tMCLK = 1/MCLK
50:50 CMOS clock
CMOS clock
DOUT6 and DOUT7 on the AD7768,
DIN on the AD7768-4
DOUT6 and DOUT7 on the AD7768,
DIN on the AD7768-4
CMOS clock
SYNC_OUT RETIME_EN bit disabled;
measured from falling edge of MCLK
SYNC_OUT RETIME_EN bit enabled;
measured from rising edge of MCLK
CMOS clock
CMOS clock
−3
9.5
9.5
tDCLK/2
(tDCLK/2) − 5
tDCLK/2
tDCLK/2
tDCLK/2
tMCLK
2 × tMCLK
4 × tMCLK
tMCLK/2
tMCLK
2 × tMCLK
4 × tMCLK
(tDCLK/2) + 5
tDCLK/2
30
4.5
22
ns
9.5
27.5
ns
0
10
ns
ns
These specifications are not production tested but are supported by characterization data at initial product release.
Table 4. SPI Control Interface Timing1
Parameter
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
Description
SCLK period
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
CS falling edge to data output enable
SCLK high time
SCLK low time
SCLK falling edge to SDO valid
SDO hold time after SCLK falling
SDI setup time
SDI hold time
SCLK enable time
Test Conditions/Comments
Min
100
26.5
27
22.5
20
20
Typ
Max
40.5
50
50
15
7
0
6
0
Rev. A | Page 16 of 99
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
Parameter
t28
t29
t30
1
Description
SCLK disable time
CS high time
CS low time
AD7768/AD7768-4
Test Conditions/Comments
Min
0
10
1.1 × tMCLK
2.2 × tMCLK
8.8 × tMCLK
fMOD = MCLK/4
fMOD = MCLK/8
fMOD = MCLK/32
Typ
Max
Unit
ns
ns
ns
ns
ns
These specifications are not production tested but are supported by characterization data at initial product release.
1.8 V IOVDD TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 =
DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C. tODR is
1/ODR.
Table 5. Data Interface Timing1
Parameter
MCLK
fMOD
Description
Master clock
Modulator frequency
t1
t2
t3
t4
t5
t6
t7
t8
t10
t11
DRDY high time
DCLK rising edge to DRDY rising edge
DCLK rising to DRDY falling
DCLK rise to DOUTx valid
DCLK rise to DOUTx invalid
DOUTx valid to DCLK falling
DCLK falling edge to DOUTx invalid
DCLK high time, DCLK = MCLK/1
t8a = DCLK = MCLK/2
t8b = DCLK = MCLK/4
t8c = DCLK = MCLK/8
DCLK low time DCLK=MCLK/1
t9a = DCLK = MCLK/2
t9b = DCLK = MCLK/4
t9c = DCLK = MCLK/8
MCLK rising to DCLK rising
Setup time (daisy-chain inputs)
t12
Hold time (daisy-chain inputs)
t13
t14
START low time
MCLK to SYNC_OUT valid
t9
t15
t16
1
SYNC_IN setup time
SYNC_IN hold time
Test Conditions/Comments
Min
1.15
14
Unit
MHz
Hz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
1 × tMCLK
ns
Fast mode
Median mode
Eco mode
tDCLK − 10%
Typ
MCLK/4
MCLK/8
MCLK/32
28
2
0
2.0
−4.5
50:50 CMOS clock
−4
8.5
8.5
tDCLK/2
50:50 CMOS clock
(tDCLK/2) − 5
CMOS clock
DOUT6 and DOUT7 on the
AD7768, DIN on the AD7768-4
DOUT6 and DOUT7 on the
AD7768, DIN on the AD7768-4
CMOS clock
SYNC_OUT RETIME_EN bit
disabled; measured from falling
edge of MCLK
SYNC_OUT RETIME_EN bit
enabled; measured from rising
edge of MCLK
CMOS clock
CMOS clock
tDCLK/2
tDCLK/2
tDCLK/2
tMCLK
2 × tMCLK
4 × tMCLK
tMCLK/2
tMCLK
2 × tMCLK
4 × tMCLK
(tDCLK/2) + 5
(tDCLK/2
37
10
31
ns
15
37
ns
0
11
These specifications are not production tested but are supported by characterization data at initial product release.
Rev. A | Page 17 of 99
Max
34
ns
ns
AD7768/AD7768-4
Data Sheet
Table 6. SPI Control Interface Timing1
Parameter
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
1
Description
SCLK period
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
CS falling edge to data output enable
SCLK high time
SCLK low time
SCLK falling edge to SDO valid
SDO hold time after SCLK falling
SDI setup time
SDI hold time
SCLK enable time
SCLK disable time
CS high time
CS low time
Test Conditions/Comments
Min
100
31.5
30
29
20
20
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
54
50
50
16
7
0
10
0
0
10
1.1 × tMCLK
2.2 × tMCLK
8.8 × tMCLK
fMOD = MCLK/4
fMOD = MCLK/8
fMOD = MCLK/32
These specifications are not production tested but are supported by characterization data at initial product release.
Timing Diagrams
t1
tODR
DRDY
t2
t8
DCLK
t3
MSB
LSB
14001-002
LSB
t9
t6
t7
Figure 2. Data Interface Timing Diagram
MCLK
t10
t8a
DCLK = MCLK/2
t9a
t8b
DCLK = MCLK/4
t9b
t8c
DCLK = MCLK/8
t9c
Figure 3. MCLK to DCLK Divider Timing Diagram
Rev. A | Page 18 of 99
14001-003
DOUTx
t5
t4
Data Sheet
AD7768/AD7768-4
tODR
DRDY
DCLK
t11
DOUT6
AND
DOUT7
14001-004
t12
Figure 4. Daisy-Chain Setup and Hold Timing Diagram
MCLK
START
t14
14001-005
t13
SYNC_OUT
Figure 5. Asynchronous START and SYNC_OUT Timing Diagram
MCLK
t15
t16
14001-006
SYNC_IN
t15
Figure 6. Synchronous SYNC_IN Pulse Timing Diagram
E
t30
CS
t18
t17
t19
t21
SCLK
SDO
MSB
t20
t24
Figure 7. SPI Serial Read Timing Diagram
Rev. A | Page 19 of 99
t23
14001-007
t22
AD7768/AD7768-4
Data Sheet
t30
CS
t18
SCLK
t25
MSB
14001-008
SDI
t26
LSB
Figure 8. SPI Serial Write Timing Diagram
t29
CS
t28
t27
Figure 9. SCLK Enable and Disable Timing Diagram
Rev. A | Page 20 of 99
14001-009
SCLK
Data Sheet
AD7768/AD7768-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
AVDD1, AVDD2 to AVSS1
AVDD1 to DGND
IOVDD to DGND
IOVDD, DREGCAP to DGND (IOVDD Tied
to DREGCAP for 1.8 V Operation)
IOVDD to AVSS
AVSS to DGND
Analog Input Voltage to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Storage Temperature Range
Pb-Free Temperature, Soldering
Reflow (10 sec to 30 sec)
Maximum Junction Temperature
Maximum Package Classification
Temperature
1
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +2.25 V
Table 8. Thermal Resistance
Package Type
64-Lead LQFP
−0.3 V to +7.5 V
−3.25 V to +0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
260°C
1
θJA
38
θJC
9.2
Unit
°C/W
JEDEC Board Layers
2P2S1
2P2S is a JEDEC standard PCB configuration per JEDEC Standard JESD51-7.
ESD CAUTION
150°C
260°C
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 21 of 99
AD7768/AD7768-4
Data Sheet
AIN4+
AIN4–
AVSS2B
REGCAPB
AVDD2B
AVSS
FORMAT1
FORMAT0
PIN/SPI
CLK_SEL
VCM
AVDD2A
REGCAPA
AVSS2A
AIN0–
AIN0+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AIN1–
1
48 AIN5–
AIN1+
2
47 AIN5+
46 AVSS1B
AVSS1A
3
AVDD1A
4
45 AVDD1B
REF1–
5
44 REF2–
REF1+
6
43 REF2+
AIN2–
7
42 AIN6–
AIN2+
8
AIN3–
9
AD7768
41 AIN6+
TOP VIEW
(Not to Scale)
40 AIN7–
AIN3+ 10
39 AIN7+
FILTER/GPIO4 11
38 SYNC_OUT
MODE0/GPIO0 12
37 START
MODE1/GPIO1 13
36 SYNC_IN
MODE2/GPIO2 14
35 IOVDD
MODE3/GPIO3 15
34 DREGCAP
ST0/CS 16
33 DGND
XTAL2/MCLK
XTAL1
RESET
DRDY
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
SUPPLY AND GROUND PINS
DIGITAL PINS
14001-010
ANALOG INPUTS AND OUTPUTS
DECOUPLING CAPACITOR PINS
DOUT4
DOUT5
DOUT6
DOUT7
DEC0/SDO
DEC1/SDI
ST1/SCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 10. AD7768 Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
AIN1−
AIN1+
AVSS1A
AVDD1A
REF1−
Type1
AI
AI
P
P
AI
6
REF1+
AI
7
8
9
10
11
AIN2−
AIN2+
AIN3−
AIN3+
FILTER/GPIO4
AI
AI
AI
AI
DI/O
Description
Negative Analog Input to ADC Channel 1.
Positive Analog Input to ADC Channel 1.
Negative Analog Supply. This pin is nominally 0 V.
Analog Supply Voltage, 5 V ± 10% with Respect to AVSS.
Reference Input, Negative. REF1− is the negative reference terminal for Channel 0 to Channel 3. The
REF1− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality
capacitor, and maintain a low impedance between this capacitor and Pin 3.
Reference Input, Positive. REF1+ is the positive reference terminal for Channel 0 to Channel 3.
The REF1+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external differential reference
voltage between REF1+ and REF1− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin
to AVSS with a high quality capacitor, and maintain a low impedance between this capacitor and
Pin 3.
Negative Analog Input to ADC Channel 2.
Positive Analog Input to ADC Channel 2.
Negative Analog Input to ADC Channel 3.
Positive Analog Input to ADC Channel 3.
Filter Select/General-Purpose Input/Output 4. In pin control mode, this pin selects the filter type.
Set this pin to Logic 1 for the sinc5 filter. This sinc5 filter is a low latency filter, and is best for dc
applications or where a user has specialized postfiltering implemented off chip.
Set this pin to Logic 0 for the wideband low ripple filter response. This filter has a steep
transition band and 105 dB stop band attenuation. Full attenuation at Nyquist (ODR/2) means
that no aliasing occurs at ODR/2 out to the first chopping zone.
When in SPI control mode, this pin can be used as a general-purpose input/output (GPIO4). See
Table 49 for more details.
Rev. A | Page 22 of 99
Data Sheet
AD7768/AD7768-4
Pin No.
12, 13,
14, 15
Mnemonic
MODE0/GPIO0,
MODE1/GPIO1,
MODE2/GPIO2,
MODE3/GPIO3
Type1
DI/DI/O
16
ST0/CS
DI
17
ST1/SCLK
DI
18
DEC1/SDI
DI
19
DEC0/SDO
DI/O
20
DOUT7
DI/O
21
DOUT6
DI/O
22
23
24
25
26
27
28
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DCLK
DO
DO
DO
DO
DO
DO
DO
29
DRDY
DO
30
RESET
DI
Description
Mode Selection/General-Purpose Input/Output Pin 0 to Pin 3.
In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling
power consumption, DCLK frequency, and the ADC conversion type, allowing one-shot
conversion operation.
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five generalpurpose input/output pins (GPIO4 to GPIO0). See Table 49 for more details.
Standby 0/Chip Select Input.
In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface. The
VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby
mode, the VCM voltage output is also disabled for maximum power savings. Channel 0 must be
enabled while VCM is being used externally to the AD7768.
Standby 1/Serial Clock Input.
In pin control mode, a Logic 1 on this pin places Channel 4 to Channel 7 into standby mode.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface. The crystal
excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby
mode, the crystal circuitry is also disabled for maximum power savings. Channel 4 must be
enabled while the external crystal is used on the AD7768.
Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC
channels. See Table 17 in the Setting the Decimation Rate section for more information.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7768 register
bank.
Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC
channels. See Table 17 in the Setting the Decimation Rate section for more information.
In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7768
registers.
Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDY. This pin acts
as a digital input from a separate AD7768 device if configured in a synchronized multidevice
daisy chain when the FORMATx pins are configured as 01. To use the AD7768 in a daisy chain,
hardwire the FORMATx pins as 01, 10, or 11, depending on the best interfacing format for the
application. When FORMATx is set to 01, 10, or 11, and daisy-chaining is not used, connect this
pin to ground through a pull-down resistor.
Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDY. This pin acts
as a digital input from a separate AD7768 device if configured in a synchronized multidevice
daisy chain. To use this pin in a daisy chain, hardwire the FORMATx pins as 01, 10, or 11,
depending on the best interfacing format for the application. When FORMATx is set to 01, 10, or
11, and daisy chaining is not used, connect this pin to ground through a pull-down resistor.
Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY
ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (digital signal
processor (DSP)/field-programmable gate array (FPGA)). This pin is synchronous with DRDY and
any conversion data output on DOUT0 to DOUT7 and is derived from the MCLK signal. This pin
is unrelated to the control SPI interface.
Data Ready. DRDY is a periodic signal output framing the conversion results from the eight
ADCs. This pin is synchronous to DCLK and DOUT0 to DOUT7.
Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to
perform a hard reset using this pin or, alternatively, to perform a soft reset by issuing a reset
over the SPI control interface
Rev. A | Page 23 of 99
AD7768/AD7768-4
Data Sheet
Pin No.
31
Mnemonic
XTAL1
Type1
DI
32
XTAL2/MCLK
DI
33
34
DGND
DREGCAP
P
AO
35
IOVDD
P
36
SYNC_IN
DI
37
START
DI
38
SYNC_OUT
DO
39
40
41
42
43
AIN7+
AIN7−
AIN6+
AIN6−
REF2+
AI
AI
AI
AI
AI
Description
Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into
standby mode, the crystal circuitry is also disabled for maximum power savings. Channel 4 must
be enabled while the external crystal is used on the AD7768. When used with an LVDS clock,
connect this pin to one trace of the LVDS signal pair. When used as an LVDS input, a rising edge
on this pin is detected as a rising MCLK edge by the AD7768.
Input 2 for CMOS or Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this
configuration.
External crystal: XTAL2 is connected to the external crystal.
LVDS clock: when used with an LVDS clock, connect this pin to the second trace of the LVDS
signal pair.
CMOS clock: this pin operates as an MCLK input. This pin is a CMOS input with a logic level of
IOVDD/DGND. When used as a CMOS clock input, a rising edge on this pin is detected as a rising
MCLK edge by the AD7768.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into
standby mode, the crystal circuitry is also disabled for maximum power savings. Channel 4 must
be enabled while the external crystal is used on the AD7768.
Digital Ground. This pin is nominally 0 V.
Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a high quality,
low ESR, 10 µF capacitor. For optimum performance, use a decoupling capacitor with an ESR
specification of less than 400 mΩ. This pin is not for use in circuits external to the AD7768. For
1.8 V IOVDD operation, connect this pin to IOVDD via an external trace to provide power to the
digital processing core.
Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the digital
processing core via the digital LDO when IOVDD is at least 2.25 V. For 1.8 V IOVDD operation,
connect this pin to DREGCAP via an external trace to provide power to the digital processing core.
Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. It is used in
the synchronization of any AD7768 that requires simultaneous sampling or is in a daisy chain.
Ignore the START and SYNC_OUT functions if the SYNC_IN pin is connected to the system
synchronization pulse. This signal pulse must be synchronous to the MCLK clock domain. In a
daisy-chained system of AD7768 devices, two successive synchronization pulses must be
applied to guarantee that all ADCs are synchronized. Two synchronization pulses are also
required in a system of more than one AD7768 device sharing a single MCLK signal, where the
DRDY pin of only one device is used to detect new data.
Start Signal. The START pulse synchronizes the AD7768 to other devices. The signal can be
asynchronous. The AD7768 samples the input and then outputs a SYNC_OUT pulse. This
SYNC_OUT pulse must be routed to the SYNC_IN pin of this device, and any other AD7768
devices that must be synchronized together. This means that the user does not need to run the
ADCs and their digital host from the same clock domain, which is useful when there are long
traces or back planes between the ADC and the controller. If this pin is not used, it must be tied
to a Logic 1 through a pull-up resistor. In a daisy-chained system of AD7768 devices, two
successive synchronization pulses must be applied to guarantee that all ADCs are synchronized.
Two synchronization pulses are also required in a system of more than one AD7768 device
sharing a single MCLK signal, where the DRDY pin of only one device is used to detect new data.
Synchronization Output. This pin operates only when the START input is used. When using the
START input feature, the SYNC_OUT pin must be connected to SYNC_IN via an external trace.
SYNC_OUT is a digital output that is synchronous to the MCLK signal; the synchronization signal
driven in on START is internally synchronized to the MCLK signal and is driven out on SYNC_OUT.
SYNC_OUT can also be routed to other AD7768 devices requiring simultaneous sampling and/or
daisy-chaining, ensuring synchronization of devices related to the MCLK clock domain. It must
then be wired to drive the SYNC_IN pin on the same AD7768 and on the other AD7768 devices.
Positive Analog Input to ADC Channel 7.
Negative Analog Input to ADC Channel 7.
Positive Analog Input to ADC Channel 6.
Negative Analog Input to ADC Channel 6.
Reference Input, Positive. REF2+ is the positive reference terminal for Channel 4 to Channel 7.
The REF2+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external differential reference
voltage between REF2+ and REF2− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to
AVSS with a high quality capacitor, and maintain a low impedance between this capacitor and Pin 46.
Rev. A | Page 24 of 99
Data Sheet
AD7768/AD7768-4
Pin No.
44
Mnemonic
REF2−
Type1
AI
45
46
47
48
49
50
51
52
53
54
55, 56
AVDD1B
AVSS1B
AIN5+
AIN5−
AIN4+
AIN4−
AVSS2B
REGCAPB
AVDD2B
AVSS
FORMAT1,
FORMAT0
P
P
AI
AI
AI
AI
P
AO
P
P
DI
57
PIN/SPI
DI
58
CLK_SEL
DI
59
VCM
AO
60
61
62
63
64
AVDD2A
REGCAPA
AVSS2A
AIN0−
AIN0+
P
AO
P
AI
AI
1
Description
Reference Input, Negative. REF2− is the negative reference terminal for Channel 4 to Channel 7.
The REF2− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high
quality capacitor, and maintain a low impedance between this capacitor and Pin 46.
Analog Supply Voltage. This pin is 5 V ± 10% with respect to AVSS.
Negative Analog Supply. This pin is nominally 0 V.
Positive Analog Input to ADC Channel 5.
Negative Analog Input to ADC Channel 5.
Positive Analog Input to ADC Channel 4.
Negative Analog Input to ADC Channel 4.
Negative Analog Supply. This pin is nominally 0 V.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
Negative Analog Supply. This pin is nominally 0 V.
Format Selection Pins. Hardwire the FORMATx pins to the required values in pin control and SPI
control mode. These pins set the number of DOUTx pins used to output ADC conversion data. The
FORMATx pins are checked by the AD7768 on power-up; the AD7768 then remains in this data
output configuration (see Table 31).
Pin Control/SPI Control. This pin sets the control method.
Logic 0 = pin control mode for the AD7768. Pin control mode allows a pin strapped
configuration of the AD7768 by tying logic input pins to required logic levels. Tie the logic pins
(MODE0 to MODE4, DEC0 and DEC1, and FILTER) as required for the configuration. See the Pin
Control section for more details.
Logic 1 = SPI control mode for the AD7768. Use the SPI control interface signals (CS, SCLK, SDI,
and SDO) for reading and writing to the AD7768 memory map.
Clock Select.
Logic 0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32 (Connect
Pin 31 to DGND).
Logic 1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is
applied to Pin 31 and Pin 32. The LVDS option is available only in SPI control mode. A write is
required to enable the LVDS clock option.
Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2 V, which is 2.5 V by default
in pin control mode. Configure this pin to (AVDD1 − AVSS)/2 V, 2.5 V, 2.14 V, or 1.65 V in SPI
control mode. When driving capacitive loads larger than 0.1 µF, it is recommended to place a
50 Ω series resistor between the pin and the capacitive load for stability. The VCM voltage
output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM
voltage output is also disabled for maximum power savings. Channel 0 must be enabled while
VCM is being used externally to the AD7768.
Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
Negative Analog Supply. This pin is nominally 0 V.
Negative Analog Input to ADC Channel 0.
Positive Analog Input to ADC Channel 0.
AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.
Rev. A | Page 25 of 99
AIN2+
AIN2–
AVSS2B
REGCAPB
AVDD2B
AVSS
DGND
FORMAT0
PIN/SPI
CLK_SEL
VCM
AVDD2A
REGCAPA
AVSS2A
AIN0–
Data Sheet
AIN0+
AD7768/AD7768-4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AIN1–
1
48 AIN3–
AIN1+
2
47 AIN3+
46 AVSS1B
AVSS1A
3
AVDD1A
4
45 AVDD1B
REF1–
5
44 REF2–
REF1+
6
43 REF2+
AVSS
7
AVSS
8
AD7768-4
42 AVSS
AVSS
9
TOP VIEW
(Not to Scale)
AVSS
10
FILTER/GPIO4
11
41 AVSS
40 AVSS
39 AVSS
38 SYNC_OUT
MODE0/GPIO0 12
37 START
MODE1/GPIO1 13
36 SYNC_IN
MODE2/GPIO2 14
35 IOVDD
MODE3/GPIO3 15
34 DREGCAP
ST0/CS
33 DGND
16
XTAL2/MCLK
XTAL1
RESET
DRDY
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
SUPPLY AND GROUND PINS
DIGITAL PINS
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
14001-011
ANALOG INPUTS AND OUTPUTS
DECOUPLING CAPACITOR PINS
DNC
DNC
DIN
DNC/DGND
DEC0/SDO
SCLK
DEC1/SDI
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 11. AD7768-4 Pin Configuration
Table 10. AD7768-4 Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
AIN1−
AIN1+
AVSS1A
AVDD1A
REF1−
Type1
AI
AI
P
P
AI
6
REF1+
AI
7 to 10,
39 to 42,
54
11
AVSS
AI
FILTER/GPIO4
DI/O
Description
Negative Analog Input to ADC Channel 1.
Positive Analog Input to ADC Channel 1.
Negative Analog Supply. This pin is nominally 0 V.
Analog Supply Voltage, 5 V ± 10% with respect to AVSS.
Reference Input Negative. REF1− is the negative reference terminal for Channel 0 and
Channel 1. The REF1− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to
AVSS with a high quality capacitor, and maintain a low impedance between this capacitor
and Pin 3.
Reference Input Positive. REF1+ is the positive reference terminal for Channel 0 and
Channel 1. The REF1+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external
differential reference voltage between REF1+ and REF1− in the range from 1 V to |AVDD1
− AVSS|. Decouple this pin to AVSS with a high quality capacitor, and maintain a low
impedance between this capacitor and Pin 3.
Negative Analog Supply. This pin is nominally 0 V.
Filter Select/General-Purpose Input-Output. In pin control mode, this pin selects the filter type.
Set this pin to Logic 1 for the sinc5 filter. This sinc5 filter is a low latency filter, and is best
for dc applications or where a user has specialized postfiltering implemented off chip.
Set this pin to Logic 0 for the wideband low ripple filter response. This filter has a steep
transition band and 105 dB stop band attenuation. Full attenuation at Nyquist (ODR/2)
means that no aliasing occurs at ODR/2 out to the first chopping zone.
When in SPI control mode, this pin can be used as a general-purpose input/output
(GPIO4). See Table 75 for more details.
Rev. A | Page 26 of 99
Data Sheet
AD7768/AD7768-4
Pin No.
12, 13,
14, 15
Mnemonic
MODE0/GPIO0,
MODE1/GPIO1,
MODE2/GPIO2,
MODE3/GPIO3
Type1
DI/DI/O
16
ST0/CS
DI
17
SCLK
DI
18
DEC1/SDI
DI
19
DEC0/SDO
DI/O
20
DNC/DGND
DO/DI
21
DIN
DI
22, 23
24
25
26
27
28
DNC
DOUT3
DOUT2
DOUT1
DOUT0
DCLK
DO
DO
DO
DO
DO
DO
29
DRDY
DO
30
RESET
DI
31
XTAL1
DI
Description
Mode Selection/General-Purpose Input/Output Pin 0 to Pin 3.
In pin control mode, the MODEx pins set the mode of operation for all ADC channels,
controlling power consumption, DCLK frequency, and the ADC conversion type, allowing
one-shot conversion operation.
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five generalpurpose input/output pins (GPIO4 to GPIO0). See Table 75 for more details.
Standby 0/Chip Select Input.
In pin control mode, a Logic 1 on this pin places Channel 0 to Channel 3 into standby
mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into
standby mode, the VCM voltage output is also disabled for maximum power savings.
Channel0 must be enabled while VCM is being used externally to the AD7768-4. The
crystal excitation circuitry is associated with the Channel 2 circuitry. If Channel 2 is put into
standby mode, the crystal circuitry is also disabled for maximum power savings. Channel 2
must be enabled while the external crystal is used on the AD7768-4.
Serial Clock Input.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface.
In pin control mode, tie this pin to a Logic 0 or DGND.
Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC
channels. See Table 17 in the Setting the Decimation Rate section.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7768-4
register bank.
Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC
channels. See Table 17 in the Setting the Decimation Rate section.
In SPI control mode, this pin is the serial data output pin, allowing readback from the
AD7768-4 registers.
Do Not Connect/Digital Ground. This is an unused pin. Leave this pin floating if FORMAT0 is
tied to logic low. If FORMAT0 is tied to logic high, connect this pin to DGND through a pulldown resistor.
Data Input Daisy Chain. This pin acts as a digital input from a separate AD7768-4 device if
configured in a synchronized multidevice daisy-chain. To use this pin in a daisy-chain,
hardwire the FORMAT0 pin to logic high. If FORMAT0 is tied to logic low, or the daisy
chaining input pin is not used, then tie this pin to DGND through a pull-down resistor.
Do Not Connect. Do not connect to this pin.
Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY
ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (DSP/FPGA).
This pin is synchronous with DRDY and any conversion data output on DOUT0 to DOUT3
and is derived from the MCLK signal. This pin is unrelated to the control SPI interface.
Data Ready. DRDY is a periodic signal output framing the conversion results from the four
ADCs. This pin is synchronous to DCLK and DOUT0 to DOUT3.
Hardware Asynchronous Reset Input. After the device is fully powered up, it is
recommended to perform a hard reset using this pin or, alternatively, to perform a soft
reset by issuing a reset over the SPI control interface
Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to
DGND. When used with an LVDS clock, it is recommended that this pin be connected to
one trace of the LVDS signal pair. When used as an LVDS input, a rising edge on this pin is
detected as a rising MCLK edge by the AD7768-4.
Rev. A | Page 27 of 99
AD7768/AD7768-4
Data Sheet
Pin No.
32
Mnemonic
XTAL2/MCLK
Type1
DI
33
34
DGND
DREGCAP
P
AO
35
IOVDD
P
36
SYNC_IN
DI
37
START
DI
38
SYNC_OUT
DO
43
REF2+
AI
44
REF2−
AI
45
46
47
48
49
50
51
52
AVDD1B
AVSS1B
AIN3+
AIN3−
AIN2+
AIN2−
AVSS2B
REGCAPB
P
P
AI
AI
AI
AI
P
AO
Description
Input 2 for CMOS/Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this
configuration.
External crystal: XTAL2 is connected to the external crystal.
LVDS: when used with an LVDS clock, connect this pin to the second trace of the LVDS
signal pair.
CMOS clock: this pin operates as an MCLK input. This pin is a CMOS input with logic level
of IOVDD/DGND. When used as a CMOS clock input, a rising edge on this pin is detected
as a rising MCLK edge by the AD7768-4.
Digital Ground. Nominally GND (0 V).
Digital LDO Regulator Output. Decouple this pin to DGND with a high quality, low ESR,
10 µF capacitor. For optimum performance, use a decoupling capacitor with an ESR
specification of less than 400 mΩ. This pin is not for use in circuits external to the AD7768-4.
For 1.8 V IOVDD operation, connect this pin to IOVDD via an external trace to provide
power to the digital processing core.
Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the
digital processing core, via the digital LDO, when IOVDD is at least 2.25 V. For 1.8 V IOVDD
operation, connect this pin to DREGCAP via an external trace to provide power to the
digital processing core.
Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. It is
used in the synchronization of any AD7768-4 that requires simultaneous sampling or is in
a daisy chain. The user can ignore the START and SYNC_OUT function if the AD7768-4
SYNC_IN pin is connected to the system synchronization pulse. This signal pulse must be
synchronous to the MCLK clock domain.
Start Signal. The START pulse acts to synchronize the AD7768-4 to other devices. The
signal can be asynchronous. The AD7768-4 samples the input and then outputs a
SYNC_OUT pulse. This SYNC_OUT pulse must be routed to the SYNC_IN pin of this device,
and any other AD7768-4 devices that must be synchronized together. This means that the
user does not need to run the ADCs and their digital host from the same clock domain,
which is useful when there are long traces or back planes between the ADC and the
controller. If this pin is not used, it must be tied to a Logic 1 through a pull-up resistor. In a
daisy-chained system of AD7768-4 devices, two successive synchronization pulses must
be applied to guarantee that all ADCs are synchronized. Two synchronization pulses are
also required in a system of more than one AD7768-4 device sharing a single MCLK signal,
where the DRDY pin of only one device is used to detect new data.
Synchronization Output. This pin operates only when the START input is used. When using
the START input feature, the SYNC_OUT must be connected to SYNC_IN via an external
trace. SYNC_OUT is a digital output that is synchronous to the MCLK signal; the synchronization signal driven in on START is internally synchronized to the MCLK signal and is driven
out on SYNC_OUT. SYNC_OUT can also be routed to other AD7768-4 devices requiring
simultaneous sampling and/or daisy-chaining, ensuring synchronization of devices
related to the MCLK clock domain. It must then be wired to drive the SYNC_IN pin on the
same AD7768-4 and on the other AD7768-4 devices.
Reference Input Positive. REF2+ is the positive reference terminal for Channel 2 and
Channel 3. The REF2+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external
differential reference voltage between REF2+ and REF2− in the range from 1 V to |AVDD1
− AVSS|. Decouple this pin to AVSS with a high quality capacitor, and maintain a low
impedance between this capacitor and Pin 3.
Reference Input Negative. REF2− is the negative reference terminal for Channel 2 and
Channel 3. The REF2− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to
AVSS with a high quality capacitor, and maintain a low impedance between this capacitor
and Pin 3.
Analog Supply Voltage. This pin is 5 V ± 10% with respect to AVSS.
Negative Analog Supply. This pin is nominally 0 V.
Positive Analog Input to ADC Channel 3.
Negative Analog Input to ADC Channel 3.
Positive Analog Input to ADC Channel 2.
Negative Analog Input to ADC Channel 2.
Negative Analog Supply. This pin is nominally 0 V.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
Rev. A | Page 28 of 99
Data Sheet
AD7768/AD7768-4
Pin No.
53
55
56
Mnemonic
AVDD2B
DGND
FORMAT0
Type1
P
P
DI
57
PIN/SPI
DI
58
CLK_SEL
DI
59
VCM
AO
60
61
62
63
64
AVDD2A
REGCAPA
AVSS2A
AIN0−
AIN0+
P
AO
P
AI
AI
1
Description
Analog Supply Voltage. 2 V to 5.5 V with respect to AVSS.
Digital Ground. This pin is nominally 0 V.
Format Selection. Hardwire the FORMAT0 pin to the required value in pin and SPI control
mode. This pin sets the number of DOUTx pins used to output ADC conversion data. The
FORMAT0 pin is checked by the AD7768-4 on power-up, the AD7768-4 then remains in this
data output configuration. See Table 32.
Pin Control/SPI Control. This pin sets the AD7768-4 control method.
Logic 0 = pin control mode for the AD7768-4. Pin control mode allows pin strapped
configuration of the AD7768-4 by tying logic input pins to required logic levels. Tie logic
pins MODE0 to MODE4, DEC0 and DEC1, and FILTER as required for the configuration. See the
Pin Control section for more details.
Logic 1 = SPI control mode for the AD7768-4. Use the SPI control interface signals (CS, SCLK,
SDI, and SDO) for reading and writing to the AD7768-4 memory map.
Clock Select.
Logic 0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32
(Connect Pin 31 to DGND).
Logic 1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is
applied to Pin 31 and Pin 32. The LVDS option is available only in SPI control mode. A write
is required to enable the LVDS clock option.
Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2 V, which is 2.5 V by
default in pin control mode. Configure this pin to (AVDD1 − AVSS)/2 V, 2.5 V, 2.14 V, or
1.65 V in SP control mode. When driving capacitive loads larger than 0.1 µF, it is
recommended to place a 50 Ω series resistor between the pin and the capacitive load for
stability. The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is
put into standby mode, the VCM voltage output is also disabled for maximum power
savings. Channel 0 must be enabled while VCM is being used externally to the AD7768-4.
Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
Negative Analog Supply. This pin is nominally 0 V.
Negative Analog Input to ADC Channel 0.
Positive Analog Input to ADC Channel 0.
AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.
Rev. A | Page 29 of 99
AD7768/AD7768-4
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 5 V, AVDD2 = 2.5 V, AVSS = 0 V, IOVDD = 2.5 V, VREF = 4.096 V, TA = 25°C, fast power mode, wideband filter, decimation =
×32, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, unless otherwise noted.
–40
–60
–60
–80
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
1k
FREQUENCY (Hz)
100
10k
100k
–200
14001-012
10
10
Figure 12. FFT, Fast Mode, Wideband Filter, −0.5 dBFS
0
–60
AMPLITUDE (dB)
–40
–60
–80
–100
–120
–140
–180
–180
–200
–200
10k
100k
10
Figure 13. FFT, Median Mode, Wideband Filter, −0.5 dBFS
0
–60
AMPLITUDE (dB)
–60
–80
–100
–120
–160
–180
–180
10k
SNR = 108.1dB
THD = –129.7dB
–120
–140
1k
FREQUENCY (Hz)
100k
–100
–160
100
10k
–80
–140
14001-016
AMPLITUDE (dB)
0
–40
10
1k
FREQUENCY (Hz)
–20
–40
–200
100
Figure 16. FFT, Median Mode, Wideband Filter, −6 dBFS
SNR = 108.0dB
THD = –129.7dB
–20
SNR = 108.1dB
THD = –128.8dB
–100
–160
1k
FREQUENCY (Hz)
100k
–120
–160
100
10k
–80
–140
14001-014
AMPLITUDE (dB)
0
–20
–40
10
1k
FREQUENCY (Hz)
Figure 15. FFT, Fast Mode, Wideband Filter, −6 dBFS
SNR = 107.9dB
THD = –129.3dB
–20
100
14001-018
AMPLITUDE (dB)
–40
–200
SNR = 107.9dB
THD = –129.8dB
–20
14001-020
–20
AMPLITUDE (dB)
0
SNR = 107.8dB
THD = –126.4dB
Figure 14. FFT, Eco Mode, Wideband Filter, −0.5 dBFS
–200
10
100
1k
FREQUENCY (Hz)
10k
Figure 17. FFT, Eco Mode, Wideband Filter, −6 dBFS
Rev. A | Page 30 of 99
14001-022
0
Data Sheet
AD7768/AD7768-4
–40
–60
–60
–80
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
–180
100
1k
FREQUENCY (Hz)
10k
100k
–200
14001-013
10
10
Figure 18. FFT, Fast Mode, Sinc5 Filter, −0.5 dBFS
0
–60
AMPLITUDE (dB)
–40
–60
–80
–100
–120
–80
–120
–140
–160
–160
–180
–180
–200
1k
FREQUENCY (Hz)
10k
100k
–200
10
Figure 19. FFT, Median Mode, Sinc5 Filter, −0.5 dBFS
0
–60
AMPLITUDE (dB)
–40
–80
–100
–120
–160
–180
–180
10k
SNR = 111.5dB
THD = –131.7dB
–100
–140
1k
FREQUENCY (Hz)
100k
–120
–160
100
10k
–80
–140
14001-017
AMPLITUDE (dB)
0
–60
10
1k
FREQUENCY (Hz)
–20
–40
–200
100
Figure 22. FFT, Median Mode, Sinc5 Filter, −6 dBFS
SNR = 111.1dB
THD = –130.1dB
–20
100k
–100
–140
100
10k
SNR = 111.1dB
THD = –130.2dB
–20
14001-015
AMPLITUDE (dB)
0
–40
10
1k
FREQUENCY (Hz)
Figure 21. FFT, Fast Mode, Sinc5 Filter, −6 dBFS
SNR = 111.1dB
THD = –128.8dB
–20
100
14001-019
AMPLITUDE (dB)
–40
–200
SNR = 111.1dB
THD = –129.3dB
–20
14001-021
–20
AMPLITUDE (dB)
0
SNR = 111.1dB
THD = –126.5dB
Figure 20. FFT, Eco Mode, Sinc5 Filter, −0.5 dBFS
–200
10
100
1k
FREQUENCY (Hz)
Figure 23. FFT, Eco Mode, Sinc5 Filter, −6 dBFS
Rev. A | Page 31 of 99
10k
14001-023
0
AD7768/AD7768-4
0
Data Sheet
SNR = 113.3dB
THD = –130.8dB
fS = 8.192kHz
fIN = 1kHz
–40
–60
AMPLITUDE (dB)
FAST
MEDIAN
ECO
250
NUMBER OF OCCURRENCES
–20
–80
–100
–120
–140
–160
200
150
100
50
500
FREQUENCY (Hz)
5000
0
–45
–41
–38
–34
–31
–27
–23
–20
–16
–13
–9
–5
–2
2
5
9
13
16
20
23
27
31
34
38
41
45
50
5
14001-026
–200
SHORTED NOISE (µV)
Figure 27. Shorted Noise, Sinc5 Filter
Figure 24. FFT One-Shot-Mode, Sinc5 Filter, Median Mode,
Decimation = ×64, −0.5 dBFS, SYNC_IN Frequency = MCLK/4000
0
SECOND-ORDER IMD = –135.2dB
THIRD-ORDER IMD = –129.3dB
200
NUMBER OF OCCURRENCES
–20
–40
–60
AMPLITUDE (dB)
14001-029
–180
–80
–100
–120
–140
–40°C
+25°C
+105°C
150
100
50
–160
10k
FREQUENCY (Hz)
100k
0
–50
–46
–42
–38
–34
–30
–26
–22
–18
–14
–10
–6
–2
2
6
10
14
18
22
26
30
34
38
42
46
50
1k
14001-276
–200
100
SHORTED NOISE (µV)
14001-057
–180
Figure 28. Shorted Noise vs. Temperature, Wideband Filter
Figure 25. IMD with Input Signals at 9.7 kHz and 10.3 kHz
15
14
FAST
MEDIAN
ECO
13
12
RMS NOISE (µV)
150
100
WIDEBAND
11
10
9
8
SINC5
50
7
6
TEMPERATURE (°C)
Figure 29. RMS Noise vs. Temperature, Fast Mode
Figure 26. Shorted Noise, Wideband Filter
Rev. A | Page 32 of 99
14001-058
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
35
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
42
39
5
14001-028
SHORTED NOISE (µV)
35
31
27
23
20
16
8
12
1
4
–3
–7
–11
–15
–18
–26
–22
–30
–37
–34
–41
0
–45
NUMBER OF OCCURRENCES
200
Data Sheet
AD7768/AD7768-4
15
0
14
–20
13
INTERFERER (1kHz) ON ALL OTHER CHANNELS
–40
AMPLITUDE (dB)
12
WIDEBAND
11
10
9
8
–60
–80
–100
–120
SINC5
–160
5
–180
TEMPERATURE (°C)
0
14001-059
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
35
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
6
2
1
3
5
4
6
7
CHANNEL
SNR AND DYNAMIC RANGE (dB)
14
13
RMS NOISE (µV)
12
WIDEBAND
11
10
9
SINC5
7
100
SNR, FAST
THD, FAST
90
6
fIN = 1kHz
80
TEMPERATURE (°C)
14001-060
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
35
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
5
0
5
10
15
20
25
30
35
40
MCLK FREQUENCY (MHz)
Figure 34. SNR, Dynamic Range, THD, and THD +N vs. MCLK Frequency
Figure 31. RMS Noise vs. Temperature, Eco Mode
0
12.0
11.8
–20
11.6
–40
11.4
–60
THD (dB)
11.2
VREF = 5.00V
VREF = 4.096V
VREF = 2.500V
11.0
10.8
–80
FAST
MEDIAN
ECO
–100
–120
10.6
–140
10.4
–160
10.2
10.0
0
1
2
3
4
5
6
CHANNEL
Figure 32. RMS Noise per Channel for Various VREF Values
7
–180
14001-061
RMS NOISE (µV)
DYNAMIC RANGE, FAST
THD + N, FAST
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
14001-062
110
15
THD AND THD + N (dB)
Figure 33. Crosstalk
Figure 30. RMS Noise vs. Temperature, Median Mode
8
14001-175
–140
7
10
100
10k
1k
INPUT FREQUENCY (Hz)
100k
14001-034
RMS NOISE (µV)
fIN = 3.15kHz
Figure 35. THD vs. Input Frequency, Three Power Modes, Wideband Filter
Rev. A | Page 33 of 99
AD7768/AD7768-4
Data Sheet
0
120
–20
118
116
–40
114
FAST
MEDIAN
ECO
–80
SNR (dB)
–100
–120
112
110
108
106
–140
104
–160
100
10
1k
10k
INPUT FREQUENCY (Hz)
100
–140
14001-035
–180
100k
–60
VREF = 2.500V
VREF = 4.096V
VREF = 5.000V
2
1
0
–1
–2
–140
–3
–160
–100
–80
–60
–40
–20
0
–4
–VREF
14001-307
–120
INPUT AMPLITUDE (dBFS)
0V
INPUT VOLTAGE (V)
+VREF
Figure 40. INL Error vs. Input Voltage for Various Voltage Reference (VREF)
Levels, Fast Mode
Figure 37. THD and THD + N vs. Input Amplitude, Wideband Filter
4
0
FAST THD
FAST THD + N
MEDIAN THD
MEDIAN THD + N
ECO THD
ECO THD + N
fIN = 1kHz
3
INL ERROR (ppm)
2
–60
–80
–100
–120
VREF = 2.500V
VREF = 4.096V
VREF = 5.000V
1
0
–1
–2
–140
–3
–160
–120
–100
–80
–60
–40
–20
0
INPUT AMPLITUDE (dBFS)
Figure 38. THD and THD + N vs. Input Amplitude, Sinc5 Filter
–4
–VREF
14001-308
–180
–140
0
3
–120
–40
–20
fIN = 1kHz
–100
–20
–40
4
FAST THD
FAST THD + N
MEDIAN THD
MEDIAN THD + N
ECO THD
ECO THD + N
–80
–180
–140
–60
14001-052
THD AND THD + N (dB)
–40
–80
Figure 39. SNR vs. Input Amplitude
INL ERROR (ppm)
–20
–100
INPUT AMPLITUDE (dBFS)
Figure 36. THD vs. Input Frequency, Three Power Modes, Sinc5 Filter
0
–120
14001-309
102
0V
INPUT VOLTAGE (V)
+VREF
14001-053
THD (dB)
–60
THD AND THD + N (dB)
FAST MODE, SINC5 FILTER
FAST MODE, WIDEBAND FILTER
MEDIAN MODE, SINC5 FILTER
MEDIAN MODE, WIDEBAND FILTER
ECO MODE, SINC5 FILTER
ECO MODE, WIDEBAND FILTER
Figure 41. INL Error vs. Input Voltage for Various Voltage Reference (VREF)
Levels, Median Mode
Rev. A | Page 34 of 99
Data Sheet
AD7768/AD7768-4
4
+105°C
+25°C
–40°C
50
3
INL ERROR (ppm)
NUMBER OF OCCURRENCES
VREF = 2.500V
VREF = 4.096V
VREF = 5.000V
2
1
0
–1
–2
40
30
20
10
–3
+VREF
0
–60
–50
–40
–30
–20
–10
0
10
20
OFFSET ERROR (µV)
Figure 42. INL Error vs. Input Voltage for Various Voltage Reference (VREF)
Levels, Eco Mode
Figure 45. Offset Error Distribution, DCLK = 24 MHz
1.5
+105°C
+25°C
–40°C
50
FULL SCALE (–4.015V TO +4.015V)
HALF SCALE (–2.008V TO +2.008V)
QUARTER SCALE (–1.004V TO +1.004V)
NUMBER OF OCCURRENCES
0.5
0
–0.5
30
20
+VREF
0
14001-055
0V
INPUT VOLTAGE (V)
–140 –120 –100
–20
0
20
40
120
–40°C
0°C
+25°C
+85°C
+105°C
NUMBER OF OCCURRENCES
100
0
–1
80
60
40
20
–3
0
INPUT VOLTAGE (V)
14001-056
–2
–4.0
–3.7
–3.4
–3.1
–2.7
–2.4
–2.1
–1.8
–1.4
–1.1
–0.8
–0.5
–0.2
0.2
0.5
0.8
1.1
1.4
1.8
2.1
2.4
2.7
3.1
3.4
3.7
4.0
INL ERROR (ppm)
–40
Figure 46. Offset Error Distribution, DCLK = 32 MHz
3
1
–60
OFFSET ERROR (µV)
Figure 43. INL Error vs. Input Voltage, Full-Scale, Half-Scale, and
Quarter-Scale Inputs
2
–80
14001-404
10
–1.0
–1.5
–VREF
40
Figure 44. INL Error vs. Input Voltage for Various Temperatures,
Fast Mode
–150 –100 –50
0
50
100
150
200
250
300
OFFSET ERROR DRIFT (nV/°C)
Figure 47. Offset Error Drift, DCLK = 24 MHz
Rev. A | Page 35 of 99
350
14001-401
INL ERROR (ppm)
1.0
14001-403
0V
INPUT VOLTAGE (V)
14001-054
–4
–VREF
AD7768/AD7768-4
Data Sheet
45
600
+105°C
+25°C
–40°C
40
NUMBER OF OCCURRENCES
NUMBER OF OCCURRENCES
500
35
30
25
20
15
10
400
300
200
100
5
0
50
100 150 200 250 300 350
OFFSET ERROR DRIFT (nV/°C)
0
–40 –35 –30 –25 –20 –15 –10 –5 0
Figure 51. Gain Error Distribution
600
60
500
50
NUMEBER OF OCCURRENCES
400
1.8V IOVDD
2.5V IOVDD
200
100
40
30
20
0
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34
DCLK FREQUENCY (MHz)
14001-040
10
0
2
Figure 49. Offset Drift vs. DCLK Frequency
4
3
5
7
6
8
9
10
GAIN ERROR (ppm)
11
14001-046
OFFSET DRIFT (nV/°C)
5 10 15 20 25 30 35
GAIN ERROR (ppm)
Figure 48. Offset Error Drift, DCLK = 32 MHz
300
14001-405
–350 –300 –250 –200 –150 –100 –50
14001-402
0
12
Figure 52. Channel to Channel Gain Error Matching
120
0
FAST MODE
60
MEDIAN MODE
AC CMRR (dB)
80
–40
ECO MODE
40
–60
–80
–100
–120
–140
20
25
TEMPERATURE (°C)
105
–180
10
100
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
Figure 53. AC CMRR vs. Input Frequency
Figure 50. Channel Offset Error Matching
Rev. A | Page 36 of 99
10M
14001-063
–160
0
–40
14001-047
OFFSET ERROR MATCHING (µV)
–20
100
Data Sheet
AD7768/AD7768-4
0
–20
–30
–40
AMPLITUDE (dB)
–20
–40
–50
CH0
CH4
–60
CH1
CH5
CH2
CH6
CH3
CH7
–80
–100
–70
–120
–80
–140
–90
–160
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–180
14001-310
–100
100
0.7
0.9
1.1
1.3
1.5
Figure 57. Wideband Filter Profile, Amplitude vs. fIN/fODR
–20
5
18000000
4
16000000
14000000
3
AIN
DOUT
–30
2
–40
1
10000000
0
8000000
–1
6000000
–2
4000000
–3
2000000
AIN (V)
AC PSRR (dB)
0.5
NORMALIZED INPUT FREQUENCY (fIN/fODR)
DCLK = 32.768MHz
AVDD2 = 5V + 100mV p-p
–10
0.3
0.1
Figure 54. AC PSRR vs. Frequency, AVDD1
0
ECO
MEDIAN
FAST
–60
–50
CH0
CH4
–60
CH1
CH5
CH2
CH6
14001-074
–10
AC PSRR (dB)
20
DCLK = 32.768MHz
AVDD1 = 5V + 100mV p-p
CH3
CH7
–70
12000000
DOUT (Code)
0
–80
–90
10k
100k
1M
10M
FREQUENCY (Hz)
10
30
40
50
60
70
0
80
SAMPLES
Figure 58. Step Response, Wideband Filter
Figure 55. AC PSRR vs. Frequency, AVDD2
0.005
0
ECO
MEDIAN
FAST
0.004
–10
0.003
–20
–40
DCLK = 32.768MHz, CH 7
DCLK = 32.768MHz, CH 7
DCLK = 8.192MHz, CH 7
DCLK = 8.192MHz, CH 7
0.002
AMPLITUDE (dB)
IOVDD = 1.8V,
IOVDD = 2.5V,
IOVDD = 1.8V,
IOVDD = 2.5V,
–30
–50
–60
–70
0.001
0
–0.001
–0.002
–80
–0.003
–90
–100
–110
100
–0.005
1k
10k
100k
1M
FREQUENCY (Hz)
10M
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
Figure 59. Wideband Filter Ripple
Figure 56. AC PSRR vs. Frequency, IOVDD
Rev. A | Page 37 of 99
0.40
NORMALIZED INPUT FREQUENCY (fIN/fODR)
0.45
0.50
14001-072
–0.004
14001-065
AC PSRR (dB)
20
14001-071
1k
0
14001-311
–4
–100
100
AD7768/AD7768-4
Data Sheet
–20
–40
–80
–100
–120
–140
MEASUREMENT LIMIT = 130dB
–200
0
1
2
3
4
5
6
NORMALIZED INPUT FREQUENCY (fIN/fODR)
14001-073
–180
18000000
4
16000000
0
8000000
–1
6000000
–2
4000000
–3
2000000
5
10
15
20
NUMBER OF OCCURRENCES
10000000
25
DOUT (Code)
1
0
–60
–70
–80
–40
60
40
0
2.42
2.43
2.44
2.45
2.46
2.47
VCM (V)
Figure 64. VCM Output Voltage Distribution
60
40
DIFFERENTIAL COMPONENT, NO PRECHARGE (µA/V)
35
FAST
40
SUPPLY CURRENT (mA)
ANALOG INPUT CURRENT (µA)
AVDD1 = 5V, AVSS = 0V
VCM_VSEL = 10
PART TO PART DISTRIBUTION
80
Figure 61. Step Response, Sinc5 Filter
30
20
105
20
0
30
SAMPLES
50
25
100
14001-070
AIN (V)
12000000
–4
FAST WITH PRECHARGE
FAST, NO PRECHARGE
MEDIAN WITH PRECHARGE
MEDIAN, NO PRECHARGE
ECO WITH PRECHARGE
ECO, NO PRECHARGE
–50
120
14000000
2
–40
Figure 63. Reference Input Current vs. Temperature, Reference Precharge
Buffers On/Off
5
AIN
DOUT
–30
TEMPERATURE (°C)
Figure 60. Sinc5 Filter Profile, Amplitude vs. fIN/fODR
3
–20
14001-312
–160
–10
COMMON-MODE COMPONENT, NO PRECHARGE (µA/V)
10
0
–10
TOTAL CURRENT, PRECHARGE ON (µA)
–20
25
20
MEDIAN
15
10
ECO
5
25
TEMPERATURE (°C)
105
14001-051
–30
–40
–40
30
Figure 62. Analog Input Current vs. Temperature, Analog Input Precharge
Buffers On/Off
Rev. A | Page 38 of 99
0
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
Figure 65. Supply Current vs. Temperature, AVDD1
110
14001-066
AMPLITUDE (dB)
–60
0
14001-050
REFERENCE INPUT CURRENT (µA/V/CHANNEL)
0
Data Sheet
AD7768/AD7768-4
500
40
450
FAST
35
FAST, WIDEBAND FILTER
30
TOTAL POWER (mW)
25
MEDIAN
20
15
10
–10
5
20
35
50
65
80
95
110
14001-067
–25
TEMPERATURE (°C)
Figure 66. Supply Current vs. Temperature, AVDD2
60
FAST, SINC5
FAST, WIDEBAND
MEDIAN, SINC5
MEDIAN, WIDEBAND
ECO, SINC5
ECO, WIDEBAND
50
40
30
20
10
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
110
14001-068
SUPPLY CURRENT (mA)
250
MEDIAN, WIDEBAND FILTER
200
150
MEDIAN, SINC5 FILTER
100
ECO, WIDEBAND FILTER
50
ECO, SINC5 FILTER
0
–40
25
TEMPERATURE (°C)
Figure 68. Total Power vs. Temperature
70
0
–40
300
ECO
5
0
–40
FAST, SINC5 FILTER
350
Figure 67. Supply Current vs. Temperature, IOVDD
Rev. A | Page 39 of 99
14001-069
SUPPLY CURRENT (mA)
400
105
AD7768/AD7768-4
Data Sheet
TERMINOLOGY
AC Common-Mode Rejection Ratio (AC CMRR)
AC CMRR is defined as the ratio of the power in the ADC output
at frequency, f, to the power of a sine wave applied to the commonmode voltage of AINx+ and AINx− at frequency, fS.
AC CMRR (dB) = 10log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Gain Error
The first transition (from 100 … 000 to 100 … 001) occurs at a
level ½ LSB above nominal negative full scale (−4.0959375 V for
the ±4.096 V range). The last transition (from 011 … 110 to
011 … 111) occurs for an analog voltage 1½ LSB below the
nominal full scale (+4.0959375 V for the ±4.096 V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Gain Error Drift
Gain error drift is the gain error change due to a temperature
change of 1°C. It is expressed in parts per million per degree
Celsius.
Integral Nonlinearity (INL) Error
INL error refers to the deviation of each individual code from a
line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs ½ LSB before the
first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is measured
from the middle of each code to the true straight line.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at the sum and difference frequencies of mfa and nfb,
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m or n are equal to 0. For
example, the second-order terms include (fa + fb) and (fa − fb),
and the third-order terms include (2fa + fb), (2fa − fb), (fa +
2fb), and (fa − 2fb).
The AD7768/AD7768-4 are tested using the CCIF standard,
where two input frequencies near to each other are used. In this
case, the second-order terms are usually distanced in frequency
from the original sine waves, and the third-order terms are
usually at a frequency close to the input frequencies. As a result,
the second-order and third-order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals, expressed in decibels.
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is as
follows:
LSB (V) = (2 × VREF)/2N
For the AD7768/AD7768-4, VREF is the difference voltage
between the REFx+ and REFx− pins, and N = 24.
Offset Error
Offset error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale
output code.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the full-scale transition point due to a change in the power
supply voltage from the nominal value.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal (excluding the
first five harmonics).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Rev. A | Page 40 of 99
Data Sheet
AD7768/AD7768-4
THEORY OF OPERATION
The AD7768 and AD7768-4 are 8-channel and 4-channel,
simultaneously sampled, low noise, 24-bit ∑-Δ ADCs,
respectively.
CLOCKING, SAMPLING TREE, AND POWER SCALING
Each ADC within the AD7768/AD7768-4 employs a Σ-Δ modulator whose clock runs at a frequency of fMOD. The modulator
samples the inputs at a rate of 2 × fMOD to convert the analog
input into an equivalent digital representation. These samples
therefore represent a quantized version of the analog input signal.
The Σ-Δ conversion technique is an oversampled architecture.
This oversampled approach spreads the quantization noise over
a wide frequency band (see Figure 69). To reduce the quantization
noise in the signal band, the high order modulator shapes the noise
spectrum so that most of the noise energy is shifted out of the
band of interest (see Figure 70). The digital filter that follows the
modulator removes the large out of band quantization noise
(see Figure 71).
For further information on the basics as well as more advanced
concepts of Σ-Δ ADCs, see the MT-022 Tutorial and the
MT-023 Tutorial.
Digital filtering has certain advantages over analog filtering.
First, it is insensitive to component tolerances and the variation
of component parameters over time and temperature. Because
digital filtering on the AD7768/AD7768-4 occurs after the analog
to digital conversion, it can remove some of the noise injected
during the conversion process; analog filtering cannot remove
noise injected during conversion. Second, the digital filter combines low pass-band ripple with a steep roll-off, and high stop
band attenuation, while also maintaining a linear phase response,
which is difficult to achieve in an analog filter implementation.
The AD7768/AD7768-4 include multiple ADC cores. Each of
these ADCs receives the same master clock signal, MCLK. The
MCLK signal can be sourced from one of three options: a CMOS
clock, a crystal connected between the XTAL1 and XTAL2 pins,
or in the form of an LVDS signal. The MCLK signal received by
the AD7768/AD7768-4 defines the modulator clock rate, fMOD,
and, in turn, the sampling frequency of the modulator of 2 ×
fMOD. The same MCLK signal is also used to define the digital
output clock, DCLK. The fMOD and DCLK internal signals are
synchronous with MCLK.
Figure 72 illustrates the clock tree from the MCLK input to the
modulator, the digital filter, and the DCLK output. There are
divider settings for MCLK and DCLK. These dividers in
conjunction with the power mode and digital filter decimation
settings are key to AD7768/AD7768-4 operation.
The AD7768/AD7768-4 have the ability to scale power consumption vs. the input bandwidth or noise desired. The user controls
two parameters to achieve this: MCLK division and power mode.
Combined, these two settings determine the clock frequency of
the modulator (fMOD) and the bias current supplied to each
modulator. The power mode (fast, median, or eco) sets the noise,
speed capability, and current consumption of the modulator. It
is the dominant control for scaling the power consumption of
the ADC. All settings of MCLK division and power mode apply
to all ADC channels.
DCLK_DIV
00: DCLK = MCLK/8
01: DCLK = MCLK/4
10: DCLK = MCLK/2
11: DCLK = MCLK/1
MCLK_DIV
MCLK/4
MCLK/8
MCLK/32
QUANTIZATION NOISE
ADC
MODULATOR
Figure 69. Σ-Δ ADC Quantization Noise (Linear Scale X-Axis)
POWER MODES:
FAST
MEDIAN
ECO
NOISE SHAPING
fMOD/2
14001-177
DIGITAL FILTER CUTOFF FREQUENCY
fMOD/2
DRDY
DOUTx
DECIMATION RATES = x32, x64,
x128, x256, x512, x1024
The modulator clock frequency (fMOD) is determined by selecting
one of three clock divider settings: MCLK/4, MCLK/8, or
MCLK/32.
Figure 70. Σ-Δ ADC Noise Shaping (Linear Scale X-Axis)
BAND OF INTEREST
DATA
INTERFACE
CONTROL
Figure 72. Sampling Structure, Defined by MCLK, DCLK_DIV, and MCLK_DIV
Settings
14001-176
BAND OF INTEREST
DIGITAL
FILTER
14001-076
BAND OF INTEREST
DCLK
14001-075
fMOD/2
Figure 71. Σ-Δ ADC Digital Filter Cutoff Frequency (Linear Scale X-Axis)
Although the MCLK division and power modes are independent
settings, there are restrictions that must be adhered to. A valid
range of modulator frequencies exists for each power mode.
Table 11 describes this recommended range, which allows the
device to achieve the best performance while minimizing power
consumption. The AD7768/AD7768-4 specifications do not cover
the performance and function beyond the maximum fMOD for a
given power mode.
Rev. A | Page 41 of 99
AD7768/AD7768-4
Data Sheet
For example, in fast mode, to maximize the speed of conversion
or input bandwidth, an MCLK of 32.768 MHz is required and
MCLK_DIV = 4 must be selected for a modulator frequency of
8.192 MHz.
Table 11. Recommended fMOD Range for Each Power Mode
Power Mode
Eco
Median
Fast
Recommended fMOD (MHz) Range,
MCLK = 32.768 MHz
0.036 to 1.024
1.024 to 4.096
4.096 to 8.192
This configuration maximizes the available decimation rate (or
oversampling ratio) for the bandwidth required and MCLK rate
available. The decimation averages the noise from the modulator,
maximizing the dynamic range.
To minimize power, use the following settings:
In SPI control mode, the user can program the power mode,
MCLK divider (MCLK_DIV), and DCLK frequency using
Register 0x04 and Register 0x07 (see Table 42 and Table 45 for
register information for the AD7768 or Table 68 and Table 71 for
the AD7768-4). Independent selection of the power mode and
MCLK_DIV allows full freedom in the MCLK speed selection to
achieve a target modulator frequency.
In pin control mode, the MODEx pins determine the power
mode, modulator frequency, and DCLK frequency. The modulator
frequency tracks the power mode. This means that fMOD is fixed
at MCLK/32 for eco mode, MCLK/8 for median mode, and
MCLK/4 for fast mode (see Table 20).
Example of Power vs. Noise Performance Optimization
Depending on the bandwidth of interest for the measurement,
the user can choose a strategy of either lowest current consumption or highest resolution. This choice is due to an overlap in
the coverage of each power mode. The devices offer the ability
to balance the MCLK division ratio with the rate of decimation
(averaging) set in the digital filter. Lower power can be achieved
by using lower modulator clock frequencies. Conversely, the
highest resolution can be achieved by using higher modulator
clock frequencies and maximizing the amount of oversampling.
As an example, consider a system constraint with a maximum
available MCLK of 16 MHz. The system is targeting a measurement bandwidth of approximately 25 kHz with the wideband
filter, setting the output data rate of the AD7768/AD7768-4 to
62.5 kHz. Because of the low MCLK frequency available and
system power budget, median power mode is used.
In median power mode, this 25 kHz input bandwidth can be
achieved by setting the MCLK division and decimation ratio to
balance, using two configurations. This flexibility is possible in
SPI control mode only.
•
•
•
•
•
MCLK = 16 MHz
Median power
fMOD = MCLK/4
MCLK = 16 MHz
Median power
fMOD = MCLK/8
Decimation = ×32 (digital filter setting)
ODR = 62.5 kHz
This configuration reduces the clocking speed of the modulator
and the digital filter.
Compared to Configuration A, Configuration B saves 48 mW
of power. The trade-off in the case of Configuration B is that the
digital filter must run at a 2× lower decimation rate. This 2×
reduction in decimation rate (or oversampling ratio) results in a
3 dB reduction in the dynamic range vs. Configuration A.
Clocking Out the ADC Conversion Results (DCLK)
The AD7768/AD7768-4 DCLK is a divided version of the
master clock input. As shown in Figure 72, the DCLK_DIV
setting determines the speed of the DCLK. DCLK is a
continuous clock.
The user can set the DCLK frequency rate to one of four
divisions of MCLK: MCLK/1, MCLK/2, MCLK/4, and
MCLK/8. Because there are eight channels and 32 bits of data
per conversion, the conversion time and the setting of DCLK
directly determine the number of data output lines that are
required via the FORMAT0 and FORMAT1 pin settings on the
AD7768, or the FORMAT0 pin on the AD7768-4. Thus, the
intended minimum decimation and desired DCLK_DIV setting
must be understood prior to choosing the setting of the
FORMATx pins.
NOISE PERFORMANCE AND RESOLUTION
Table 12 and Table 13 show the noise performance for the
wideband and sinc5 digital filters of the AD7768/AD7768-4 for
various output data rates and power modes. The noise values
and dynamic range specified are typical for the bipolar input
range with an external 4.096 V reference (VREF). The rms noise is
measured with shorted analog inputs, which are driven to
(AVDD1 − AVSS)/2 using the on-board VCM buffer output.
The dynamic range is calculated as the ratio of the rms shorted
input noise to the rms full-scale input signal range.
Dynamic Range (dB) = 20log10((2 × VREF/2√2)/(RMS Noise)
To maximize the dynamic range, use the following settings:
•
•
•
Decimation = ×64 (digital filter setting)
ODR = 62.5 kHz
Configuration B
Control of the settings for power mode, the modulator frequency
and the data clock frequency differs in pin control mode vs. SPI
control mode.
Configuration A
•
•
The LSB size with 4.096 V reference is 488 nV, and is calculated
as follows:
LSB (V) = (2 × VREF)/224
Rev. A | Page 42 of 99
AD7768/AD7768-4
Data Sheet
Table 12. Wideband Filter Noise: Performance vs. Output Data Rate (VREF = 4.096 V)
Output Data Rate (kSPS)
Fast Mode
256
128
64
32
16
8
Median Mode
128
64
32
16
8
4
Eco Mode
32
16
8
4
2
1
−3 dB Bandwidth (kHz)
Shorted Input Dynamic Range (dB)
RMS Noise (µV)
110.8
55.4
27.7
13.9
6.9
3.5
107.96
111.43
114.55
117.58
120.56
123.5
11.58
7.77
5.42
3.82
2.72
1.94
55.4
27.7
13.9
6.9
3.5
1.7
108.13
111.62
114.75
117.79
120.8
123.81
11.36
7.6
5.3
3.74
2.64
1.87
13.9
6.9
3.5
1.7
0.87
0.43
108.19
111.69
114.83
117.26
120.88
123.88
11.28
7.54
5.25
3.71
2.62
1.85
Table 13. Sinc5 Filter Noise: Performance vs. Output Data Rate (VREF = 4.096 V)
Output Data Rate (kSPS)
Fast Mode
256
128
64
32
16
8
Median Mode
128
64
32
16
8
4
Eco Mode
32
16
8
4
2
1
−3 dB Bandwidth (kHz)
Shorted Input Dynamic Range (dB)
RMS Noise (µV)
52.224
26.112
13.056
6.528
3.264
1.632
111.36
114.55
117.61
120.61
123.52
126.39
7.83
5.43
3.82
2.71
1.93
1.39
26.112
13.056
6.528
3.264
1.632
0.816
111.53
114.75
117.81
120.82
123.82
126.79
7.68
5.3
3.72
2.64
1.87
1.33
6.528
3.264
1.632
0.816
0.408
0.204
111.57
114.82
117.88
120.9
123.91
126.89
7.65
5.26
3.7
2.61
1.85
1.31
Rev. A | Page 43 of 99
AD7768/AD7768-4
Data Sheet
APPLICATIONS INFORMATION
•
•
•
The AD7768/AD7768-4 offer users a multichannel platform
measurement solution for ac and dc signal processing.
Flexible filtering allows the AD7768/AD7768-4 to be configured to simultaneously sample ac and dc signals on a per channel
basis. Power scaling allows users to trade off the input bandwidth
of the measurement vs. the current consumption. This ability,
coupled with the flexibility of the digital filtering, allows the
user to optimize the energy efficiency of the measurement,
while still meeting power, bandwidth, and performance targets.
•
•
•
Key capabilities that allow users to choose the AD7768/AD7768-4
as their platform high resolution ADC are highlighted as follows:
•
•
•
•
•
Eight fully differential or pseudo differential analog inputs
on the AD7768 (four channels on the AD7768-4).
Fast throughput simultaneous sampling ADCs catering for
input signals up to 110.8 kHz.
Three selectable power modes (fast, median, and eco) for
scaling the current consumption and input bandwidth of
the ADC for optimal measurement efficiency.
Analog input precharge and reference precharge buffers
reduce the drive requirements of external amplifiers.
Control of reference and analog input precharge buffers on a
per channel basis.
AVDD1A,
AVDD1B
Refer to Figure 73 and Table 14 for the typical connections
and minimum requirements to get started using the
AD7768/AD7768-4.
Table 15 shows the typical power and performance of the
AD7768/AD7768-4 for the available power modes, for each
filter type.
AVDD2A,
AVDD2B
IOVDD
SUGGESTED OP AMPS:
FAST MODE: ADA4896-2 OR ADA4807-2
MEDIAN MODE: ADA4940-2 OR ADA4807-2
ECO MODE: ADA4805-2
VCM
REGCAPA,
REGCAPB
AD7768/AD7768-4
DREGCAP
5V
AIN0+
ADA4940-1/
ADA4940-2
AIN0–
SINC5
LOW LATENCY FILTER
AIN7+*
24-BIT
Σ-Δ
ADC
AIN7–*
ADC
DATA
SERIAL
INTERFACE
SPI
CONTROL
INTERFACE
WIDEBAND
LOW RIPPLE FILTER
PRECHARGE
BUFFERS
ST0/CS
ST1*/SCLK
DEC0/SDO
DEC1/SDI
FILTER/GPIO4
AVSS
VIN
REFx– REFx+
XTAL2/MCLK
–
VIN
VOUT
ADR4540
SYNC_IN
SYNC_OUT
START
RESET
FORMATx
DRDY
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4*
DOUT5*
DOUT6*, DIN
DOUT7*
XTAL1
PIN/SPI
MODE3/GPIO3
TO
MODE0/GPIO0
+
ADA4841-1
14001-077
•
Wideband, low ripple, digital filter for ac measurement.
Fast sinc5 filter for precision low frequency measurement.
Two channel modes, defined by the user selected filter choice,
and decimation ratios, can be defined for use on different
ADC channels. This enables optimization of the input
bandwidth versus the signal of interest.
Option of SPI or pin strapped control and configuration.
Offset, gain, and phase calibration registers per channel.
Common-mode voltage output buffer for use by driver
amplifier.
On-board AVDD2 and IOVDD LDOs for the low power,
1.8 V, internal circuitry.
*THESE PINS EXIST ONLY ON THE AD7768.
Figure 73. Typical Connection Diagram
Rev. A | Page 44 of 99
Data Sheet
AD7768/AD7768-4
Table 14. Requirements to Operate the AD7768/AD7768-4
Requirement
Power Supplies
External Reference
External Driver Amplifiers
External Clock
FPGA or DSP
Description
5 V AVDD1 supply, 2.25 V to 5 V AVDD2 supply, 1.8 V or 2.5 V to 3.3 V IOVDD supply (ADP7104/ADP7118)
2.5 V, 4.096 V, or 5 V (ADR4525, ADR4540, or ADR4550)
The ADA4896-2, the ADA4940-1/ADA4940-2, the ADA4805-2, and the ADA4807-2
Crystal or a CMOS/LVDS clock for the ADC modulator sampling
Input/output voltage of 2.5 V to 3.6 V, or 1.8 V (see the 1.8 V IOVDD Operation section)
Table 15. Speed, Dynamic Range, THD, and Power Overview; Eight Channels Active, Decimate by 321
Power
Mode
Fast
Median
Eco
THD
(dB)
−115
−120
−120
Dynamic
Range (dB)
111
111
111
Sinc5 Filter
Bandwidth
Power Dissipation
(kHz)
(mW per channel)
52.224
41
26.112
22
6.528
8.5
Dynamic
Range (dB)
108
108
108
Wideband Filter
Bandwidth
Power Dissipation
(kHz)
(mW per channel)
110.8
52
55.4
28
13.9
9.5
Analog precharge buffers on, reference precharge buffers and VCM disabled, typical values, AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, VREF = 4.096 V, MCLK = 32.768 MHz,
DCLK = MCLK/4, TA = 25°C.
POWER SUPPLIES
The AD7768/AD7768-4 have three independent power
supplies: AVDD1 (AVDD1A and AVDD2A), AVDD2
(AVDD2A and AVDD2B), and IOVDD.
The reference potentials for these supplies are AVSS and DGND.
Tie all the AVSS supply pins (AVSS1A, AVSS1B, AVSS2A,
AVSS2B, and AVSS) to the same potential with respect to
DGND. AVDD1A, AVDD1B, AVDD2A, and AVDD2B are
referenced to this AVSS rail. IOVDD is referenced to DGND.
The supplies can be powered within the following ranges:
•
•
•
•
•
AVDD1 = 5 V ± 10%, relative to AVSS
AVDD2 = 2 V to 5.5 V, relative to AVSS
IOVDD (with internal regulator) = 2.25 V to 3.6 V, relative
to DGND
IOVDD (bypassing regulator) = 1.72 V to 1.88 V, relative to
DGND
AVSS = −2.75 V to 0 V, relative to DGND
The AVDD1A and AVDD1B (AVDD1) supplies power the analog
front end, reference input, and common-mode output circuitry.
AVDD1 is referenced to AVSS, and all AVDD1 supplies must be
tied to the same potential with respect to AVSS. If AVDD1 supplies
are used in a ±2.5 V split supply configuration, the ADC inputs are
truly bipolar. When using split supplies, reference the absolute
maximum ratings, which apply to the voltage allowed between
AVSS and IOVDD supplies.
The AVDD2A and AVDD2B (AVDD2) supplies connect to
internal 1.8 V analog LDO regulators. The regulators power the
ADC core. AVDD2 is referenced to AVSS, and all AVDD2 supplies
must be tied to the same potential with respect to AVSS. The
voltage on AVDD2 can range from 2 V (minimum) to 5.5 V
(maximum), with respect to AVSS.
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD also sets
the voltage levels for the SPI interface of the ADC. IOVDD is
referenced to DGND, and the voltage on IOVDD can vary from
2.25 V (minimum) to 3.6 V (maximum), with respect to DGND.
IOVDD can also be configured to run at 1.8 V. In this case, IOVDD
and DREGCAP must be tied together and must be within the
range of 1.72 V (minimum) to 1.88 V (maximum), with respect
to DGND. See the 1.8 V IOVDD Operation section for more
information on operating the AD7768/AD7768-4 at 1.8 V
IOVDD.
Recommended Power Supply Configuration
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a power solution that uses the ADP7118 is shown
in Figure 74. The ADP7118 provides positive supply rails for
optimal converter performance, creating either a single 5 V,
3.3 V, or dual AVDD1x and AVDD2x/IOVDD, depending on
the required supply configuration. The ADP7118 can operate
from input voltages of up to 20 V.
12V
INPUT
ADP7118
LDO
ADP7118
LDO
5V: AVDD1x
3.3V: AVDD2x/IOVDD
14001-078
1
Output
Data Rate
(kSPS)
256
128
32
Figure 74. Power Supply Configuration
Alternatively, the ADP7112 or ADP7104 can be selected for
powering the AD7768/AD7768-4. Refer to the AN-1120
Application Note for more information regarding low noise
LDO performance and power supply filtering.
Rev. A | Page 45 of 99
AD7768/AD7768-4
Data Sheet
1.8 V IOVDD Operation
DEVICE CONFIGURATION
The AD7768/AD7768-4 contain an internal 1.8 V LDO on the
IOVDD supply to regulate the IOVDD down to the operating
voltage of the digital core. This internal LDO allows the internal
logic to operate efficiently at 1.8 V and the input/output logic to
operate at the level set by IOVDD. The IOVDD supply is rated
from 2.25 V to 3.6 V for normal operation, and 1.8 V for LDO
bypass setup.
The AD7768/AD7768-4 have independent paths for reading
data from the ADC conversions and for controlling the device
functionality.
38
SYNC_OUT
37
START
36
SYNC_IN
IOVDD
35
DREGCAP
34
DGND
33
1.8V IOVDD
SUPPLY
Figure 75. DREGCAP and IOVDD Connection Diagram for 1.8 V IOVDD
Operation
Users can bypass the LDO by shorting the DREGCAP pin to
IOVDD (see Figure 75), which pulls the internal LDO out of
regulation and sets the internal core voltage and input/output
logic levels to the IOVDD level. When bypassing the internal
LDO, the maximum operating voltage of the IOVDD supply is
equal to the maximum operating voltage of the internal digital core,
which is 1.72 V to 1.88 V.
There are a number of performance differences to consider when
operating at 1.8 V IOVDD. See the 1.8 V IOVDD Specifications
section for detailed specifications while operating at 1.8 V IOVDD.
Analog Supply Internal Connectivity
The AD7768/AD7768-4 have two analog supply rails, AVDD1 and
AVDD2, which are both referred to AVSS. These supplies are
completely separate from the digital pins IOVDD, DREGCAP, and
DGND. To achieve optimal performance and isolation of the
ADCs, more than one device pin supplies these analog rails to the
internal ADCs.
•
•
•
•
•
Pin control mode: pin strapped digital logic inputs (which
allows a subset of the configurability options)
• SPI control mode: over a 3-wire or 4-wire SPI interface
(complete configurability)
On power-up, the state of the PIN/SPI pin determines the mode
used. Immediately after power-up, the user must apply a soft or
hard reset to the device when using either control mode.
Interface Data Format
14001-306
XTAL1
XTAL2/MCLK
RESET
DCLK
DRDY
28 29 30 31 32
For control, the device can be configured in either of two
modes. The two modes of configuration are
AVSS1A (Pin 3) and AVSS2A (Pin 62) are internally
connected.
AVSS (Pin 54) is connected to the substrate, and is connected
internally to AVSS1B (Pin 46) and AVSS2B (Pin 51).
The following supply and reference input pins are separate
on chip: AVDD1A, AVDD1B, AVDD2A, AVDD2B,
REF1+, REF1−, REF2+, and REF2−.
On the AD7768-4, the following AVSS pins are separate on
chip: Pin 7, Pin 8, Pin 9, Pin 10, Pin 39, Pin 40, Pin 41, and
Pin 42.
The details of which individual supplies are shorted internally are
given in this section for information purposes. In general,
connect the supplies as described in the Power Supplies section.
When operating the device, the data format of the serial interface is determined by the FORMAT0 and FORMAT1 pin settings
on the AD7768, or the FORMAT0 pin on the AD7768-4. Table 31
shows that each ADC can be assigned a DOUTx pin, or,
alternatively, the data can be arranged to share the DOUTx pins in
a time division multiplexed manner. For more details, see the
Data Interface section.
PIN CONTROL
Pin control mode eliminates the need for an SPI communication
interface. When a single known configuration is required by the
user, or when only limited reconfiguration is required, the number
of signals that require routing to the digital host can be reduced
using this mode. Pin control mode is useful in digitally isolated
applications where minimal adjustment of the configuration is
needed. Pin control offers a subset of the core functionality and
ensures a known state of operation after power-up, reset, or a
fault condition on the power supply. In pin control mode, the
analog input precharge buffers are enabled by default for best
performance. The reference input precharge buffers are disabled
in pin control mode.
After any change to the configuration in pin control mode, the
user must provide a sync signal to the AD7768/AD7768-4 by
applying the appropriate pulse to the START pin or SYNC_IN pin
to ensure that the configuration changes are applied correctly to
the ADC and digital filters.
Setting the Filter
The filter function chooses between the two filter settings. In
pin control mode, all ADC channels use the same filter type,
which is selected by the FILTER pin, as shown in Table 16.
Table 16. FILTER Control Pin
Logic Level
1
0
Rev. A | Page 46 of 99
Function
Sinc5 filter selected
Wideband filter selected
Data Sheet
AD7768/AD7768-4
Setting the Decimation Rate
The MODEx pins map to 16 distinct settings. The settings are
selected to optimize the use cases of the AD7768/AD7768-4,
allowing the user to reduce the DCLK frequency for lower, less
demanding power modes and selecting either the one-shot or
standard conversion modes.
Pin control mode allows selection from four possible decimation
rates. The decimation rate is selected via the DEC1 and DEC0 pins.
The chosen decimation rate is used on all ADC channels. Table 17
shows the truth table for the DECx pins.
See Table 20 for the complete selection of operating modes that
are available via the MODEx pins in pin control mode.
Table 17. Decimation Rate Control Pins Truth Table
DEC0
0
1
0
1
Decimation Rate
×32
×64
×128
×1024
The power mode setting automatically scales the bias currents
of the ADC and divides the applied MCLK signal to the correct
setting for that mode. Note that this is not the same as using SPI
control, where separate bit fields exist to control the bias currents
of the ADC and MCLK division.
Operating Mode
In pin control mode, the modulator rate is fixed for each power
mode to achieve the best performance. Table 19 shows the
modulator division for each power mode.
The MODE3 to MODE0 pins determine the configuration of all
channels when using pin control mode. The variables controlled by
the MODEx pins are shown in Table 18. The user selects how
much current the device consumes, the sampling speed of the
ADC (power mode), how fast the ADC result is received by the
digital host (DCLK_DIV), and how the ADC conversion is
initiated (conversion operation). Figure 76 illustrates the inputs
used to configure the AD7768 in pin control mode, and Figure 77
illustrates the inputs used to configure the AD7768-4 in pin
control mode.
Table 19. Modulator Rate, Pin Control Mode
Power Mode
Fast
Median
Eco
Diagnostics
Pin control mode offers a subset of diagnostics features. Internal
errors are reported in the status header output with the data
conversion results for each channel.
Table 18. MODEx Pins: Variables for Control
Control Variable
Sampling Speed/Power Consumption
Power Mode
Data Clock Output Frequency (DCLK_DIV)
Conversion Operation
Possible Settings
Fast
Median
Eco
DCLK = MCLK/1
DCLK = MCLK/2
DCLK = MCLK/4
DCLK = MCLK/8
Standard conversion
One-shot conversion
PIN CONTROL MODE
PIN/SPI = LOW
Internal CRC errors, memory map flipped bits, and external
clocks not detected are reported by Bit 7 of the status header
and indicate that a reset is required. The status header also
reports filter not settled, filter type, and filter saturated signals.
Users can determine when to ignore data by monitoring these
error flags. For more information on the status header, see the
ADC Conversion Output: Header and Data section.
CHANNEL STANDBY
CH 0 TO CH 3 STANDBY
CH 4 TO CH 7 STANDBY
PIN/SPI
ST0
ST1
OUTPUT DATA FORMAT
1 CHANNEL PER PIN
4 CHANNELS PER PIN
8 CHANNELS PER PIN
FORMAT0
FORMAT1
DOUT0
DOUT1
OPTION TO
SELECT
BETWEEN FILTERS
FILTER
DEC0/
DEC1
Modulator Rate, fMOD
MCLK/4
MCLK/8
MCLK/32
AD7768
TO DSP/
FPGA
DOUT7
MODE0
MODE1
MODE2
MODE3
DECIMATION RATES
/32
/64
/128
/1024
MODE CONFIGURATION
MODE 0x0 TO MODE 0xF
SET UP VIA 4 PINS
Figure 76. AD7768 Pin Configurable Functions
Rev. A | Page 47 of 99
14001-079
DEC1
0
0
1
1
AD7768/AD7768-4
Data Sheet
PIN CONTROL MODE
PIN/SPI = LOW
CHANNEL STANDBY
CH 0 TO CH 3 STANDBY
PIN/SPI
OUTPUT DATA FORMAT
1 CHANNEL PER PIN
4 CHANNELS PER PIN
FORMAT0
ST0
DOUT0
DOUT1
FILTER
AD7768-4
DOUT2
TO DSP/
FPGA
DOUT3
MODE0
MODE1
MODE2
MODE3
DEC0/
DEC1
DECIMATION RATES
/32
/64
/128
/1024
MODE CONFIGURATION
MODE 0x0 TO MODE 0xF
SET UP VIA 4 PINS
14001-300
OPTION TO
SELECT
BETWEEN FILTERS
Figure 77. AD7768-4 Pin Configurable Functions
Table 20. MODEx Selection Details: Pin Control Mode
Mode Hex.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
MODE3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MODE2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MODE1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MODE0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Configuration Example
where:
MCLK = 32.768 MHz.
fMOD is MCLK/32 for eco mode (see Table 19).
Decimation Ratio = 64.
DCLK Frequency
MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/1
MCLK/1
MCLK/2
MCLK/1
Data Conversion
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
One-shot
One-shot
One-shot
One-shot
Thus, for this example, where MCLK = 32.768 MHz,
In the example shown in Table 23, the lowest current consumption
is used, and the AD7768/AD7768-4 are connected to an FPGA.
The FORMATx pins are set such that all eight data outputs,
DOUT0 to DOUT7, connect to the FPGA. For the lowest
power, the lowest DCLK frequency is used. The input bandwidth
is set through the combination of selecting decimation by 64
and selecting the wideband filter.
ODR = fMOD ÷ Decimation Ratio
Power Mode
Eco
Eco
Eco
Eco
Median
Median
Median
Median
Fast
Fast
Fast
Fast
Eco
Median
Fast
Fast
ODR = (32.768 MHz/32) ÷ 64 = 16 kHz
Minimizing the DCLK frequency means selecting DCLK =
MCLK/8, which results in a 4 MHz DCLK signal. The period of
DCLK in this case is 1/4 MHz = 250 ns. The data conversion on
each DOUTx pin is 32 bits long. The conversion data takes 32 ×
250 ns = 8 μs to be output. All 32 bits must be output within the
ODR period of 1/16 kHz, which is approximately 64 μs. In this
case, the 8 μs required to read out the conversion data is well
within the 64 μs between conversion outputs. Therefore, this
combination, which is summarized in Table 23, is viable for use.
Rev. A | Page 48 of 99
Data Sheet
AD7768/AD7768-4
Channel Standby
SPI CONTROL
Table 21 and Table 23 show how the user can put channels into
standby mode. Set either ST0 or ST1 to Logic 1 to place banks of
four channels into standby mode. When in standby mode, the
channels are disabled but still hold their position in the output
data stream. The 8-bit header and 24-bit conversion result are
set to all zeros when the ADC channels are set to standby.
The AD7768/AD7768-4 have a 4-wire SPI interface that is
compatible with QSPI™, MICROWIRE®, and DSPs. The interface
operates in SPI Mode 0. In SPI Mode 0, SCLK idles low, the
falling edge of CS clocks out the MSB, the falling edge of SCLK
is the drive edge, and the rising edge of SCLK is the sample
edge. This means that data is clocked out on the falling/drive
edge and data is clocked in on the rising/sample edge.
The crystal excitation circuitry is associated with the Channel 4
(Channel 2 on the AD7768-4) circuitry. If Channel 4 (Channel 2
on the AD7768-4) is put into standby mode, the crystal circuitry is
also disabled for maximum power savings. Channel 4 must be
enabled while the external crystal is used on the AD7768.
Channel 2 must be enabled while the external crystal is used on
the AD7768-4.
Table 21. Truth Table for the AD7768 ST0 and ST1 Pins
ST1
0
0
ST0
0
1
1
0
1
1
Function
All channels operational.
Channel 0 to Channel 3 in
standby. Channel 4 to
Channel 7 operational.
Channel 4 to Channel 7 in
standby. Channel 0 to
Channel 3 operational.
All channels in standby.
Table 22. Truth Table for the AD7768-4 ST0 Pin
ST0
0
1
Function
All channels operational.
Channel 0 to Channel 3 in standby.
DRIVE EDGE
SAMPLE EDGE
14001-080
The VCM voltage output is associated with the Channel 0
circuitry. If Channel 0 is put into standby mode, the VCM
voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally
to the AD7768/AD7768-4.
Figure 78. SPI Mode 0 SCLK Edges
Accessing the ADC Register Map
To use SPI control mode, set the PIN/SPI pin to logic high. The
SPI control operates as a 16-bit, 4-wire interface, allowing read
and write access. Figure 80 shows the interface format between
the AD7768/AD7768-4 and the digital host.
The SPI serial control interface of the AD7768 is an independent
path for controlling and monitoring the AD7768. There is no
direct link to the data interface. The timing of MCLK and
DCLK is not directly related to the timing of the SPI control
interface. However, the user must ensure that the SPI reads and
writes satisfy the minimum t30 specification (see Table 4 and
Table 6) so that the AD7768/AD7768-4 can detect changes to
the register map.
SPI access is ignored during the period immediately after a
reset. Allow the full ADC start-up time after reset (see Table 1)
to elapse before accessing the AD7768/AD7768-4 over the SPI
interface.
Table 23. MODEx Example Selection
Mode Hex
0x3
MODE3
0
MODE2
0
MODE1
1
MODE0
1
Power Mode
Eco
Rev. A | Page 49 of 99
DCLK Frequency
MCLK/8
Data Conversion
Standard
AD7768/AD7768-4
Data Sheet


SPI Interface Details
Each SPI access frame is 16 bits long. The MSB (Bit 15) of the
SDI command is the R/W bit; 1 = read and 0 = write. Bits[14:8]
of the SDI command are the address bits.

The SPI control interface uses an off frame protocol. This means
that the master (FPGA/DSP) communicates with the AD7768/
AD7768-4 in two frames. The first frame sends a 16-bit instruction
(R/W, address, and data) and the second frame is the response
where the AD7768/AD7768-4 send 16 bits back to the master.



During the master write command, the SDO output contains
eight leading zeros, followed by eight bits of data, as shown in
Figure 80.

SPI CONTROL FUNCTIONALITY
Figure 79 illustrates the off frame protocol. Register access
responses are always offset by one CS frame. In Figure 79, the
response (read RESP 1) to the first command (CMD 1) is
output by the AD7768/AD7768-4 during the following CS
frame at the same time as the second command (CMD 2) is
being sent.
SPI control offers the superset of flexibility and diagnostics to
the user. The following sections highlight the functionality and
diagnostics offered when SPI control is used.
After any change to these configuration register settings, the
user must provide a sync signal to the AD7768/AD7768-4
through either the SPI_SYNC command, or by applying the
appropriate pulse to the START pin or SYNC_IN pin to ensure
that the configuration changes are applied correctly to the ADC
and digital filters.
SCLK
CS
CMD 1
CMD 2
14001-082
SDI
READ RESP 1
SDO
Eco power mode with fMOD = MCLK/32.
Interface configuration of DCLK = MCLK/8, header
output enabled, and CRC disabled.
Filter configuration of Channel Mode A and Channel Mode B
is set to sinc5 and decimation = ×1024.
Channel mode select is set to 0x00, and all channels are
assigned to Channel Mode A.
The analog input precharge buffers are enabled and the
reference precharge buffers are disabled on all channels.
The offset, gain, and phase calibration are set to the zero
position.
Continuous conversion mode is enabled.
Channel Configuration
The AD7768 has eight fully differential analog input channels.
The AD7768-4 has four fully differential analog input channels.
The channel configuration registers allow the channel to be
individually configured to adapt to the measurement required
on that channel. Channels can be enabled or disabled using the
channel standby register, Register 0x00. Analog input and
reference precharge buffers can be assigned per input terminal.
Gain, offset, and phase calibration can be controlled on a per
channel basis using the calibration registers. See the Per
Channel Calibration Gain, Offset, and Sync Phase section for
more information.
Figure 79. Off Frame Protocol
SPI Control Interface Error Handling
The AD7768/AD7768-4 SPI control interface detects whether it
has received an illegal command. An illegal command is a write
to a read only register, a write to a register address that does not
exist, or a read from a register address that does not exist. If any
of these illegal commands are received by the AD7768/AD7768-4,
the AD7768/AD7768-4 responds with an error output of 0x0E00.
SPI Reset Configuration
After a power-on or reset, the AD7768/AD7768-4 default
configuration is set to the following low current consumption
settings:
SCLK
SDI
R/W
SDO
0
A6 A5 A4 A3 A2 A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 80. Write/Read Command
Rev. A | Page 50 of 99
14001-081
CS
Data Sheet
AD7768/AD7768-4
Channel Modes
Table 25. Channel Mode Selection, Register 0x03
In SPI control mode, the user can set up two channel modes,
Channel Mode A (Register 0x01), and Channel Mode B
(Register 0x02). Each channel mode register can have a specific
filter type and decimation ratio. Using the channel mode select
register (Register 0x03), the user can assign each channel to
either Channel Mode A or Channel Mode B, which maps that
mode to the required ADC channels. These modes allow
different filter types and decimation rates to be selected and
mapped to any of the ADC channels.
Bits
[7:0]
When different decimation rates are selected on different
channels, the AD7768/AD7768-4 output a data ready signal at
the fastest selected decimation rate. Any channel that runs at a
lower output data rate is updated only at that slower rate. In
between valid result data, the data for that channel is set to zero
and the repeated data bit is set in the header status bits to
distinguish it from a real conversion result (see the ADC
Conversion Output: Header and Data section).
On the AD7768, consider Channel Mode A as the primary
group. In this respect, it is recommended that there always be at
least one channel assigned to Channel Mode A. If all eight
channels of the AD7768 are assigned to Channel Mode B,
conversion data is not output on the data interface for any of the
channels. This consideration does not affect the AD7768-4.
On the AD7768-4, it is recommended that Channel Mode A be
set to the sinc5 filter whenever possible. There is a small power
saving in IOVDD current when Channel Mode A is set to the
sinc5 filter compared to setting Channel Mode A to the wideband
filter.
For example, to assign two channels of the AD7768-4 to the
wideband filter, and the remaining two channels to the sinc5
filter, it is recommended to assign the two sinc5 filter channels
to Channel Mode A. Set Channel Mode A to the sinc5 filter, set
Channel Mode B to the wideband filter, and assign the two
wideband filter channels to Channel Mode B. Similarly, to
assign all four channels of the AD7768-4 to wideband filter,
assign all four channels to Channel Mode B. Set Channel Mode
B to the wideband filter, and keep Channel Mode A set to the
sinc5 filter. Assigning the channels in this way ensures that the
lowest IOVDD current is achieved.
Table 24. Channel Mode A/Channel Mode B, Register 0x01
and Register 0x02
Bits
3
Bit Name
FILTER_TYPE_x
Setting
0
1
[2:0]
DEC_RATE_x
000 to
101
Description
Filter output
Wideband filter
Sinc5 filter
Decimation rate
×32 to ×1024
Reset
0x1
Access
RW
0x5
RW
Bit Name
CH_x_MODE
Setting
0
1
Description
Channel x
Mode A
Mode B
Reset
0x0
Access
RW
Reset over SPI Control Interface
Two successive commands must be written to the AD7768/
AD7768-4 data control register to initiate a full reset of the
device over the SPI interface. This action fully resets all registers
to the default conditions. Details of the commands and their
sequence are shown in Table 44 for the AD7768 or Table 70 for
the AD7768-4.
After a reset over the SPI control interface, the AD7768/AD7768-4
respond to the first command sent to them with 0x0E00. This
response, in addition to the fact that all registers have assumed
their default values, indicates that the software reset succeeded.
Sleep Mode
Sleep mode puts the AD7768/AD7768-4 into their lowest power
mode. In sleep mode, all ADCs are disabled and a large portion
of the digital core is inactive.
The AD7768/AD7768-4 SPI remains active and is available to
the user when in sleep mode. Write to Register 0x04, Bit 7 to
exit sleep mode. For the lowest power consumption, select the
sinc5 filter before entering sleep mode.
Channel Standby
For efficient power usage, users can place the selected channels
into standby mode, effectively disabling them, when not in use.
Setting the bits in Register 0x00 disables the corresponding channel
(see Table 38 for the AD7768 or Table 64 for the AD7768-4). For
maximum power savings, switch disabled channels to the sinc5
filter using the channel mode configurations, which disables
some clocks associated with the wideband filters of those
channels.
For highest power savings when disabling channels on the
AD7768-4, set Channel Mode A to the sinc5 filter, and assign
the disabled channels to Channel Mode A, while keeping any
active channels in Channel Mode B.
The VCM voltage output is associated with the Channel 0
circuitry. If Channel 0 is put into standby mode, the VCM
voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally
to the AD7768/AD7768-4.
The crystal excitation circuitry is associated with the Channel 4
(Channel 2 on the AD7768-4) circuitry. If Channel 4 (Channel 2
on the AD7768-4) is put into standby mode, the crystal circuitry is
also disabled for maximum power savings. Channel 4 must be
enabled while the external crystal is used on the AD7768.
Channel 2 must be enabled while the external crystal is used on
the AD7768-4.
Rev. A | Page 51 of 99
AD7768/AD7768-4
Data Sheet
Clocking Selections
where MCLK ≥ DCLK.
The internal modulator frequency (fMOD) that is used by each of
the ADCs in the AD7768/AD7768-4 is derived from the
externally applied MCLK signal. The MCLK division bits allow
the user to control the ratio between the MCLK frequency and
the internal modulator clock frequency. This control allows the
user to select the division ratio that is best for their configuration.
With eight ADCs enabled, an MCLK rate of 32.768 MHz, an ODR
of 256 kSPS, and two DOUTx channels, DCLK (minimum) is
The appropriate clock configuration depends on the power
mode, the decimation rate, and the base MCLK frequency
available in the system. See the Clocking, Sampling Tree section
for further information on setting MCLK_DIV correctly.
MCLK Source Selection
The following clocking options are available as the MCLK input
source in SPI control mode:
where DCLK = MCLK/1.
For more information on the status header, CRC, and interface
configuration, see the Data Interface section.
CRC Protection
The AD7768/AD7768-4 can be configured to output a CRC
message per channel every 4 or 16 samples. This function is
available only with SPI control. CRC is enabled in the interface
control register, Register 0x07 (see the CRC Check on Data
Interface section).
ADC Synchronization over SPI
LVDS
External crystal
CMOS input MCLK
Setting CLK_SEL to logic low configures the AD7768/AD7768-4
for correct operation using a CMOS clock. Setting CLK_SEL to
logic high enables the use of an external crystal.
If CLK_SEL is set to logic high and Bit 3 of Register 0x04 is also
set, the application of an LVDS clock signal to the MCLK pin is
enabled. LVDS clocking is exclusive to SPI control mode and
requires the register selection for operation (see Table 42 for the
AD7768 or Table 68 for the AD7768-4).
The DCLK rate is derived from MCLK. DCLK division (the
ratio between MCLK and DCLK) is controlled in the interface
configuration selection register, Register 0x07 (see Table 45 for
the AD7768 or Table 71 for the AD7768-4).
The ADC synchronization over SPI allows the user to request a
synchronization pulse to the ADCs over the SPI interface. To
initiate the synchronization in this manner, write to Bit 7 in
Register 0x06 twice.
First, the user must write a 0, which sets SYNC_OUT low, and
then write a 1 to set the SYNC_OUT logic high again.
The SPI_SYNC command is recognized after the last rising edge of
SCLK in the SPI instruction, where the SPI_SYNC bit is changed
from low to high. The SPI_SYNC command is then output synchronously to the AD7768/AD7768-4 MCLK signal on the
SYNC_OUT pin. The user must connect the SYNC_OUT signal
to the SYNC_IN pin on the PCB.
IOVDD
AD7768/
AD7768-4
Interface Configuration
MASTER
CLOCK
The data interface is a master output interface, where ADC
conversion results are output by the AD7768/AD7768-4 at a
rate based on the mode selected. The interface consists of a data
clock (DCLK), the data ready (DRDY) framing output, and the
data output pins (DOUT0 to DOUT7 for the AD7768, DOUT0
to DOUT3 for the AD7768-4).
On the AD7768, the interface can be configured to output
conversion data on one, two, or eight of the DOUTx pins. The
DOUTx configuration for the AD7768 is selected using the
FORMATx pins (see Table 31).
START
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
SPI INTERFACE
SYNC_OUT
DRDY
DOUTx
SYNC_IN
DSP/
FPGA
Figure 81. Connection Diagram for Synchronization Using SPI_SYNC
The SYNC_OUT pin can also be routed to the SYNC_IN pins of
other AD7768/AD7768-4 devices, allowing simultaneous
sampling to occur across larger channel count systems. Any
daisy-chained system of AD7768/AD7768-4 devices requires that
all ADCs be synchronized.
On the AD7768-4, the interface can be configured to output
conversion data on one or four of the DOUTx pins. The
DOUTx configuration for the AD7768-4 is selected using
the FORMAT0 pin (see Table 32).
The DCLK rate is a direct division of the MCLK input and can
be controlled using Bits[1:0] of Register 0x07. The minimum
DCLK rate can be calculated as
DCLK (minimum) = Output Data Rate × Channels per
DOUTx × 32 bits
MCLK
14001-301
•
•
•
256 kSPS × 4 channels per DOUTx × 32 bits = 32.768 MHz
In a daisy-chained system of AD7768/AD7768-4 devices, two
successive synchronization pulses must be applied to guarantee
that all ADCs are synchronized. Two synchronization pulses are
also required in a system of more than one AD7768/AD7768-4
device sharing a single MCLK signal, where the DRDY pin of
only one device is used to detect new data.
Rev. A | Page 52 of 99
Data Sheet
AD7768/AD7768-4
As per any synchronization pulse present on the SYNC_IN pin,
the digital filters of the AD7768/AD7768-4 are reset by the
SPI_SYNC command. The full settling time of the filters must
then elapse before valid data is output on the data interface.
Analog Input Precharge Buffers
The AD7768/AD7768-4 contain precharge buffers on each
analog input to ease the drive requirements on the external
amplifier. Each analog input precharge buffer can be enabled or
disabled using the analog input precharge buffer registers (see
Table 52 and Table 53 for the AD7768 or Table 78 and Table 79
for the AD7768-4).
Reference Precharge Buffers
The AD7768/AD7768-4 contain reference precharge buffers on
each reference input to ease the drive requirements on the
external reference and help to settle any nonlinearity on the
reference inputs. Each reference precharge buffer can be
enabled or disabled using the reference precharge buffer
registers (see Table 54 and Table 55 for the AD7768 or Table 80
and Table 81 for the AD7768-4).
Per Channel Calibration Gain, Offset, and Sync Phase
The user can adjust the gain, offset, and sync phase of the
AD7768/AD7768-4. These options are available only in SPI
control mode. Further register information and calibration
instructions are available in the Offset Registers section, the Gain
Registers section, and the Sync Phase Offset Registers section.
See the Calibration section for information on calibration
equations.
GPIOs
The AD7768/AD7768-4 have five general-purpose input/output
(GPIO) pins available when operating in SPI control mode. For
further information on GPIO configuration, see the GPIO
Functionality section.
SPI CONTROL MODE EXTRA DIAGNOSTIC
FEATURES
RAM Built In Self Test
The RAM built in self test (BIST) is a coefficient check for the
digital filters. The AD7768/AD7768-4 DSP path uses some
internal memories for storing data associated with filtering and
calibration. A user may, if desired, initiate a built in self test (BIST)
of these memories. Normal conversions are not possible while
BIST is running. The test is started by writing to the BIST control
register, Register 0x08. The results and status of the test are
available in the status register, Register 0x09 (see Table 47 for the
AD7768 or Table 73 for the AD7768-4).
Normal ADC conversion is disrupted when this test is run. A
synchronization pulse is required after this test is complete to
resume normal ADC operation.
Revision Identification Number
The AD7768/AD7768-4 contain an identification register that
can be accessed in SPI control mode, the revision identification
register. This register is an excellent way to verify the correct
operation of the serial control interface. Register information is
available in the Revision Identification Register section.
Diagnostic Meter Mode
The diagnostic metering mode can be used to verify the
functionality of each ADC by internally passing a positive fullscale, midscale, or negative full-scale voltage to the ADC. The
user can then read the resulting ADC conversion result to
determine that the ADC is operating correctly. To configure
ADC conversion diagnostics, see the ADC Diagnostic Receive
Select Register section and the ADC Diagnostic Control Register
section.
Rev. A | Page 53 of 99
AD7768/AD7768-4
Data Sheet
CIRCUIT INFORMATION
CORE SIGNAL CHAIN
Table 11 shows the recommended fMOD frequencies for each
power mode, and Table 42 shows the register information for
the AD7768, and Table 68 shows the register information for
the AD7768-4.
The AD7768/AD7768-4 can use up to a 5 V reference and
converts the differential voltage between the analog inputs (AINx+
and AINx−) into a digital output. The analog inputs can be
configured as either differential or pseudo differential inputs. As a
pseudo differential input, either AINx+ or AINx− can be
connected to a constant input voltage (such as 0 V, GND, AVSS,
or some other reference voltage). The ADC converts the voltage
difference between the analog input pins into a digital code on
the output. Using a common-mode voltage of AVDD1/2 for the
analog inputs, AINx+ and AINx−, maximizes the ADC input
range. The 24-bit conversion result is in twos complement, MSB
first, format. Figure 82 shows the ideal transfer functions for the
AD7768/AD7768-4.
+FS – 1LSB
+FS – 1.5LSB
ANALOG INPUT
Figure 82. ADC Ideal Transfer Functions (FS is Full Scale)
Table 26. Output Codes and Ideal Input Voltages
Description
FS − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FS + 1 LSB
−FS
SYNC_OUT
SYNC_IN
Analog Input
(AINx+ − (AINx−))
VREF = 4.096 V
+4.095999512 V
+488 nV
0V
−488 nV
−4.095999512 V
−4.096 V
RESET
SIGNAL CHAIN
FOR SINGLE CHANNEL
PRECHARGE
BUFFER
Σ-Δ
MODULATOR
DATA
INTERFACE
CONTROL
DIGITAL
FILTER
AINx–
ESD
PROTECTION
DRDY
DOUTx
DCLK
CONTROL BLOCK
PIN/SPI
CONTROL
OPTION
PIN OR SPI
PIN CONTROL
FILTER/GPIO4
MODE3/GPIO3
TO
MODE0/GPIO0
SPI CONTROL
CS SCLK SDO SDI
Figure 83. Top Level Core Signal Chain and Control
Rev. A | Page 54 of 99
14001-182
AINx+
–FS + 1LSB
–FS + 0.5LSB
The AD7768/AD7768-4 have three selectable power modes. In
pin control mode, the modulator rate and power mode are tied
together for best performance. In SPI control mode, the user
can select the power mode and modulator MCLK divider settings.
The choice of power modes gives more flexibility to control the
bandwidth and power dissipation for the AD7768/AD7768-4.
START
100 ... 010
100 ... 001
100 ... 000
–FS
ADC Power Modes
MCLK
011 ... 111
011 ... 110
011 ... 101
14001-083
ADC CODE (TWOS COMPLEMENT)
Each ADC channel on the AD7768/AD7768-4 has an identical
signal path from the analog input pins to the data interface.
Figure 83 shows a top level implementation of the core signal
chain. Each ADC channel has its own Σ-Δ modulator that
oversamples the analog input and passes the digital representation
to the digital filter block. The modulator sampling frequency
(fMOD) ranges are explained in the Clocking, Sampling Tree, and
Power Scaling section. The data is filtered, scaled for gain and
offset (depending on user settings), and then output on the data
interface. Control of the flexible settings for the signal chain is
provided by either using the pin control or the SPI control set at
power-up by the state of the PIN/SPI input pin.
Digital Output Code,
Twos Complement (Hex.)
0x7FFFFF
0x000001
0x000000
0xFFFFFF
0x800001
0x800000
Data Sheet
AD7768/AD7768-4
ANALOG INPUTS
0
PRECHARGE BUFFERED AINx+
PRECHARGE BUFFERED AINx–
–5
–10
AIN (µA)
Figure 84 shows the AD7768/AD7768-4 analog front end. The
ESD protection diodes that are designed to protect the ADC
from some short duration overvoltage and ESD events are
shown on the signal path. The analog input is sampled at twice
the modulator sampling frequency, fMOD, which is derived from
MCLK. By default, the ADC internal sampling capacitors, CS1
and CS2, are driven by a per channel analog input precharge
buffer to ease the driving requirement of the external network.
–15
–20
BPS 0+
–25
AVDD1
AIN0+
–30
CS1
0
PHI 1
AVSS
BPS 0–
CS2
PHI 0
14001-084
AIN0–
AVSS
Figure 84. Analog Front End
The analog input precharge buffers provide the initial rough
charging of the switched capacitor network for 25% of the sampling
phase. During this first phase, the bypass switches, BPS 0+ and
BPS 0−, remain open. For the remaining 75% of the sampling
phase, the bypass switches are closed, and the fine accuracy
settling charge is provided by the external source. PHI 0 and PHI 1
represent the modulator clock sampling phases that switch the
input signals onto the sampling capacitors, CS1 and CS2.
The analog input precharge buffers reduce the switching kickback
from the sampling stage to the external circuitry. The precharge
buffer reduces the average input current by a factor of eight, and
makes the input current more signal independent, to reduce the
effects of sampling distortion. This reduction in drive requirements
allows pairing of the AD7768/AD7768-4 with lower power, lower
bandwidth front end driver amplifiers such as the ADA4940-1/
ADA4940-2.
4
The analog input precharge buffers can be turned on/off by means
of a register write to Register 0x11 and Register 0x12 (Precharge
Buffer Register 1 and Precharge Buffer Register 2). Each analog
input precharge buffer is selectable per channel. In pin control
mode, the analog input precharge buffers are always enabled for
optimum performance.
When the analog input precharge buffers are disabled, the
analog input current is sourced completely from the analog
input source. The unbuffered analog input current is calculated
from two components: the differential input voltage on the
analog input pair, and the analog input voltage with respect to
AVSS. With the precharge buffers disabled, for 32.768 MHz
MCLK in fast mode with fMOD = MCLK/4, the differential input
current is approximately 48 µA/V and the current with respect
to ground is approximately 17 µA/V.
For example, if the precharge buffers are off, with AIN1+= 5 V,
and AIN1− = 0 V, estimate the current in each input pin as
follows:
AIN1+ = 5 V × 48 µA/V + 5 V × 17 µA/V = 325 µA
AIN1− = −5 V × 48 µA/V + 0 V × 17 µA/V = −240 µA
400
When the precharge buffers are enabled, the absolute voltage with
respect to AVSS determines the majority of the current. The
maximum input current of approximately −25 µA is measured
when the analog input is close to either the AVDD1 or AVSS rails.
300
200
100
AIN (µA)
3
2
INPUT VOLTAGE (VDIFF)
Figure 86. Analog Input Current (AIN) vs. Input Voltage, Analog Input
Precharge Buffer On, VCM = 2.5 V, fMOD = 8.192 MHz
PHI 1
AVDD1
1
14001-192
PHI 0
With either precharge buffers enabled or disabled, the analog
input current scales linearly with the modulator clock rate. The
analog input current versus input voltage is shown in Figure 85.
0
–100
–200
–300
0
1
2
3
4
INPUT VOLTAGE (VDIFF)
5
6
14001-191
UNBUFFERED AINx+
UNBUFFERED AINx–
–400
Figure 85. Analog Input Current (AIN) vs. Input Voltage, Analog Input
Precharge Buffer Off, VCM = 2.5 V, fMOD = 8.192 MHz
Full settling of the analog inputs to the ADC requires the use
of an external amplifier. Pair amplifiers such as the ADA4805-2
for eco mode, the ADA4807-2 or ADA4940-1/ADA4940-2 for
median mode, and the ADA4807-2 or ADA4896-2 for fast mode
with the AD7768/AD7768-4 (see Table 27 for details). Running
the AD7768/AD7768-4 in median and eco modes or reducing
the MCLK rate reduces the load and speed requirements of the
amplifier; therefore, lower power amplifiers can be paired with
the analog inputs to achieve the optimum signal chain efficiency.
Rev. A | Page 55 of 99
AD7768/AD7768-4
Data Sheet
Table 27. Amplifier Pairing Options
Power Mode
Fast
Fast
Median
Eco
1
Amplifier
ADA4896-2
ADA4807-2
ADA4805-2
ADA4805-2
Amplifier Power
(mW/channel)1
40.6
13.6
7.5
7.525
Analog Input Precharge
Buffer
On
On
On
On
Total Power (Amplifier + AD7768)
(mW/channel)1
92.1
65.1
35.0
16.9
Typical power at 25°C.
With the precharge buffers on, REFx+ = 5 V, and REFx− = 0 V,
VCM
The AD7768/AD7768-4 provide a buffered common-mode
voltage output on Pin 59. This output can bias up analog input
signals. By incorporating the VCM buffer into the ADC, the
AD7768/AD7768-4 reduce component count and board space.
In pin control mode, the VCM potential is fixed to (AVDD1 −
AVSS)/2, and is enabled by default.
In SPI control mode, configure the VCM potential using the
general configuration register (Register 0x05). The output can
be enabled or disabled, and set to (AVDD1 − AVSS)/2, 1.65 V,
2.14 V, or 2.5 V, with respect to AVSS.
The VCM voltage output is associated with the Channel 0
circuitry. If Channel 0 is put into standby mode, the VCM
voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally
to the AD7768/AD7768-4.
REFERENCE INPUT
The AD7768/AD7768-4 have two differential reference input
pairs. On the AD7768 REF1+ and REF1− are the reference
inputs for Channel 0 to Channel 3, and REF2+ and REF2− are
for Channel 4 to Channel 7. On the AD7768-4 REF1+ and
REF1− are the reference inputs for Channel 0 and Channel 1,
and REF2+ and REF2− are for Channel 2 and Channel 3. The
absolute input reference voltage range is 1 V to AVDD1 − AVSS.
Like the analog inputs, the reference inputs have a precharge buffer
option. Each ADC has an individual buffer for each REFx+ and
REFx−. The precharge buffers help reduce the burden on the
external reference circuitry.
In pin control mode, the reference precharge buffers are off by
default. In SPI control mode, the user can enable or disable the
reference precharge buffers. In the case of unipolar analog
supplies, in SPI control mode, the user can achieve the best
performance and power efficiency by enabling only the REFx+
buffers. The reference input current scales linearly with the
modulator clock rate.
For 32 MHz MCLK and MCLK/4 fast mode, the differential
input current is ~72 µA/V per channel unbuffered, and
~16 µA/V per channel with the precharge buffers enabled.
For the best performance and headroom, it is recommended to
use a 4.096 V reference such as the ADR444 or the ADR4540.
For the best performance at high sampling rates, it is
recommended to use an external reference drive amplifier such
as the ADA4841-1 or the AD8031.
CLOCK SELECTION
The AD7768/AD7768-4 have an internal oscillator that is used
for initial power-up of the device. After the AD7768/AD7768-4
have completed their start-up routine, the devices normally
transfer control of the internal clocking to the externally applied
MCLK. The AD7768/AD7768-4 count the falling edges of the
external MCLK over a given number of internal clock cycles to
determine if the clock is valid and at least a frequency of 1.15 MHz.
If there is a fault with the external MCLK, the transfer of control
does not occur, the AD7768/AD7768-4 output an error in the
status header, and the clock error bit is set in the device status
register. No conversion data is output and a reset is required to
exit this error state.
Three clock source input options are available to the AD7768/
AD7768-4: external CMOS, crystal oscillator, or LVDS. The clock
is selected on power-up and is determined by the state of the
CLK_SEL pin.
If CLK_SEL = 0, the CMOS clock option is selected and the
clock is applied to Pin 32 (Pin 31 is tied to DGND).
If CLK_SEL = 1, the crystal or LVDS option is selected and the
crystal or LVDS is applied to Pin 31 and Pin 32. The LVDS
option is available only in SPI control mode. An SPI write to
Bit 3 of Register 0x04 enables the LVDS clock option.
DIGITAL FILTERING
The AD7768/AD7768-4 offer two types of digital filters. In SPI
control mode, these filters can be chosen on a per channel basis.
In pin control mode, only one filter can be selected for all channels.
The digital filters available on the AD7768/AD7768-4 are
•
•
With the precharge buffers off, REFx+ = 5 V, and REFx− = 0 V,
REFx± = 5 V × 72 µA/V = 360 µA
REFx± = 5 V × 16 µA/V = 80 µA
Sinc5 low latency filter, −3 dB at 0.204 × ODR
Wideband low ripple filter, −3 dB at 0.433 × ODR
Both filters can be operated in one of six different decimation rates,
allowing the user to choose the optimal input bandwidth and speed
of the conversion versus the desired power mode or resolution.
Rev. A | Page 56 of 99
Data Sheet
AD7768/AD7768-4
Sinc5 Filter
0
–20
–30
–40
AMPLITUDE (dB)
Most precision Σ-Δ ADCs use a sinc filter. The sinc5 filter offered
in the AD7768/AD7768-4 enables a low latency signal path
useful for dc inputs, for control loops, or where other specific
postprocessing is required. The sinc5 filter path offers the lowest
noise and power consumption. The sinc5 filter has a −3 dB BW
of 0.204 × ODR. Table 13 contains the noise performance for the
sinc5 filter across power modes and decimation ratios.
–10
–50
–60
–70
–80
–90
–100
0
–110
–20
–130
–60
–140
0
0.1
0.3
0.4
0.5
0.6
0.7
0.9
0.8
1.0
Figure 88. Wideband Filter Frequency Response
–100
0.010
–120
0.008
–160
0.006
–180
0.004
4
6
8
10
12
14
16
NORMALIZED INPUT FREQUENCY (fIN/fODR)
0
–0.002
The settling times for the AD7768/AD7768-4 when using the
sinc5 filter are shown in Table 36.
–0.004
Wideband Low Ripple Filter
–0.008
The wideband filter has a low ripple pass band, within ±0.005 dB
of ripple, of 0.4 × ODR. The wideband filter has full attenuation
at 0.499 × ODR (Nyquist), maximizing antialias protection. The
wideband filter has a pass-band ripple of ±0.005 dB and a stop
band attenuation of 105 dB from Nyquist out to fCHOP. For more
information on antialiasing and fCHOP aliasing, see the
Antialiasing section.
–0.010
The wideband filter is a very high order digital filter with a
group delay of approximately 34/ODR. After a synchronization
pulse, there is an additional delay from the SYNC_IN rising
edge to fully settled data. The settling times for the AD7768/
AD7768-4 when using the wideband filter are shown in Table 35.
See Table 12 for the noise performance of the wideband filter
across power modes and decimation rates.
AMPLITUDE (dB)
Figure 87. Sinc5 Filter Frequency Response (Decimation = ×32)
0.002
–0.006
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
14001-089
2
0.50
NORMALIZED INPUT FREQUENCY (fIN/fODR)
Figure 89. Wideband Filter Pass-Band Ripple
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0
10
20
30
40
50
60
OUTPUT DATA RATE SAMPLES
Figure 90. Wideband Filter Step Response
Rev. A | Page 57 of 99
70
80
14001-090
0
AMPLITUDE (dB)
–140
–200
0.2
NORMALIZED INPUT FREQUENCY (fIN/fODR)
–80
14001-088
–40
14001-086
AMPLITUDE (dB)
–120
AD7768/AD7768-4
Data Sheet
DECIMATION RATE CONTROL
Modulator Sampling Frequency
The AD7768/AD7768-4 have programmable decimation rates
for the digital filters. The decimation rates allow the user to reduce
the measurement bandwidth, reducing the speed but increasing the
resolution. When using the SPI control, control the decimation
rate on the AD7768/AD7768-4 through the channel mode registers. These registers set two separate channel modes with a given
decimation rate and filter type. Each ADC is mapped to one of
these modes via the channel mode select register. Table 28 details
both the decimation rates available, and the filter types for selection,
within Mode A and Mode B.
The AD7768/AD7768-4 modulator signal transfer function
includes a notch, at odd multiples of fMOD, to reject tones or
harmonics related to the modulator clock. The modulator itself
attenuate signals at frequencies of fMOD, 3 × fMOD., 5 × fMOD, and
so on. For an MCLK frequency of 32.768 MHz, the attenuation
is approximately 35 dB in fast mode, 41 dB in median mode,
and 53 dB in eco mode. Attenuation is increased by 6 dB across
each power mode, with every halving of the MCLK frequency,
for example, when reducing the clock from 32.768 MHz to
16.384 MHz.
In pin control mode, the decimation ratio is controlled by the
DEC0 and DEC1 pins; see Table 17 for decimation configuration in
pin control mode.
The modulator has no rejection to signals that are at frequencies in
zones around 2 × fMOD and all even multiples of fMOD.. Signals at
these frequencies are aliased by the AD7768/AD7768-4. For the
AD7768/AD7768-4, the first of these zones that requires protection is at 2 × fMOD. Because typical switch capacitor, discrete
time Σ-Δ modulators provide no protection to aliasing at the
frequency, fMOD, the AD7768/AD7768-4 provide a distinct
advantage in this regard.
Table 28. Channel x Mode Registers, Register 0x01 and
Register 0x02
Bits
3
Name
FILTER_TYPE_x
[2:0]
DEC_RATE_x
Logic Value
0
1
000
001
010
011
100
101
110
111
Decimation Rate
Wideband filter
Sinc5 filter
32
64
128
256
512
1024
1024
1024
ANTIALIASING
Because the AD7768/AD7768-4 are switched capacitor, discrete
time ADCs, the user may wish to employ external analog antialiasing filters to protect against fold back of out of band tones.
Within this section, an out of band tone refers to an input frequency greater than the pass band frequency specification of
the digital filter that is applied at the analog input.
When designing an antialiasing filter for the AD7768/AD7768-4,
three main aliasing regions must be taken into account. After
the alias requirements of each zone are understood, the user can
design an antialiasing filter to meet the needs of the specific
application. The three zones for consideration are related to the
modulator sampling frequency, the modulator chopping frequency, and the modulator saturation point.
Figure 91 shows the frequency response of the modulator and
wideband digital filter to out of band tones at the analog input.
Figure 91 shows the magnitude of an alias that is seen in band
vs. the frequency of the signal sampled at the analog input. The
relationship between the input signal and the modulator frequency
is expressed in a normalized manner as a ratio of the input signal
(fIN) to the modulator frequency (fMOD). This data demonstrates the
ADC frequency response relative to out of band tones when using
the wideband filter. The input frequency (fIN) is swept from dc to
20 MHz. In fast mode, using an 8.192MHz fMOD frequency, the
x-axis spans ratios of fIN/fMOD from 0 to 2.44 (equivalent to fIN of
0 Hz to 20 MHz). A similar characteristic occurs in median and
eco modes.
The notch appears in Figure 91 with the input frequency (fIN) at
fMOD (designated at fIN/fMOD = 1.00 on the x-axis). An input at this
frequency is attenuated by 35 dB, which adds to the attenuation of
any external antialiasing filter, thus reducing the frequency rolloff requirement of the external filter. If the plot is swept further
in frequency, the notch is seen to recur at fIN/fMOD = 3.00.
The point where fIN = 2 × fMOD (designated on the x-axis at 2.00)
offers 0 dB attenuation, indicating that all signals falling at this
frequency alias directly back into the ADC conversion results,
in accordance with sampling theory.
The AD7768/AD7768-4 wideband digital filter also offers an
added protection against aliasing. Because the wideband filter has
full attenuation at the Nyquist frequency (fODR/2, where fODR =
fMOD/Decimation Rate), input frequencies, and in particular
harmonics of input frequencies, that may fall close to fODR/2, do not
fold back into the pass-band of the AD7768/AD7768-4.
Rev. A | Page 58 of 99
Data Sheet
AD7768/AD7768-4
AD7768/AD7768-4 digital filter can pass when using a
decimate by 32 filter setting.
ALIAS MAGNITUDE (dB)
WITH RESPECT TO IN-BAND MAGNITUDE
0
–10
fCHOP = fMOD/32
fCHOP = fMOD/8
–20
–30
Table 29. External Antialiasing Filter Attenuation
–40
–50
RC Filter
First Order
Second Order
Third Order
–60
–70
–80
–90
–100
fMOD/32
(dB)
−6
−12
−18
fMOD/16
(dB)
−12
−24
−36
fMOD/8
(dB)
−18
−36
−54
2 × fMOD
(dB)
−42
−84
−126
–110
Modulator Saturation Point
–120
–130
2.500
fIN/fMOD
14001-197
2.375
2.250
2.125
2.000
1.875
1.750
1.625
1.500
1.375
1.250
1.125
1.000
0.875
0.750
0.625
0.500
0.375
0.250
0
–150
0.125
–140
Figure 91. AD7768/AD7768-4 Rejection of Out of Band Input Tones,
Wideband Filter, Decimation = ×32, fMOD = 8.192 MHz, Analog Input Sweep
from DC to 20 MHz
Modulator Chopping Frequency
Figure 91 plots two scenarios that relate to the chopping frequency
of the AD7768/AD7768-4 modulators.
The AD7768/AD7768-4 use a chopping technique in the modulator similar to that of a chopped amplifier to remove offset, offset
drift, and 1/f noise. The AD7768/AD7768-4 default chopping
rate is fMOD/32. In pin control mode, the chop frequency is
hardwired to fMOD/32. In SPI control mode, the user can select
the chop frequency to be either fMOD/32 or fMOD/8.
As shown in Figure 91, the stop band rejection of the digital filter is
reduced at frequencies that relate to even multiples of the
chopping frequency (fCHOP). All other out of band frequencies
(excluding those already discussed relating to the modulator clock
frequency fMOD) are rejected by the stop band attenuation of the
digital filter. An out of band tone with a frequency in the range of
(2 × fCHOP ) ± f3dB, where f3dB is the filter bandwidth employed, is
attenuated to the envelope determined by the chop frequency
setting (see Figure 91), and aliased into the pass band. Out of
band tones near additional even multiples of fCHOP (that is, N ×
fCHOP, where N is an even integer), are attenuated and aliased in
the same way.
Chopping at fMOD/32 offers the best performance for noise,
offset, and offset drift for the AD7768/AD7768-4.
For ac performance it may be useful to select chopping at fMOD/8
as this moves the first chopping tone to a higher frequency.
However, chopping at fMOD/8 may lead to slightly degraded
noise (approximately 1 dB loss in dynamic range) and offset
performance compared to the default chop rate of fMOD/32.
Table 29 shows the aliasing achieved by different order
antialiasing filter options at the critical frequencies of fMOD/32
and fMOD/8 for chop aliasing, fMOD/16 for modulator saturation,
and 2 × fMOD for the first zone with 0 dB attenuation. It assumes
the corner frequency of the antialiasing filter is at fMOD/64,
which is just above the maximum input bandwidth that the
A Σ-Δ modulator can be considered a standard control loop,
employing negative feedback. The control loop works to ensure
that the average processed error signal is very small over time. It
uses an integrator to remember preceding errors and force the
mean error to be zero. As the input signal rate of change increases
with respect to the modulator clock, fMOD, a larger voltage feedback
error is processed. Above a certain frequency, the error begins
to saturate the modulator.
For theAD7768/AD7768-4, the modulator may saturate for fullscale input frequencies greater than fMOD/16, depending on the
rate of change of input signal, input signal amplitude, and reference
input level. A half power input tone at fMOD/8 also causes the
modulator to saturate. In applications where there may be high
amplitude and frequency out of band tones, a first-order antialiasing filter is required with a −3 dB corner frequency set at fMOD/16 to
protect against modulator saturation. For example, if operating
the AD7768/AD7768-4 at full speed and using a decimation rate
of ×32 to achieve an output data rate of 256 kSPS, the modulator
rate is equal to 8.192 MHz. In this instance, to protect against
saturation, set the antialiasing filter −3 dB corner frequency to
512 kHz.
CALIBRATION
In SPI control mode, the AD7768/AD7768-4 offer users the ability
to adjust offset, gain, and phase delay on a per channel basis.
Offset Adjustment
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_
OFFSET_LSB registers are 24-bit, signed twos complement
registers for channel offset adjustment. If the channel gain setting is
at its ideal nominal value of 0x555555, an LSB of offset register
adjustment changes the digital output by −4/3 LSBs. For example,
changing the offset register from 0 to 100 changes the digital
output by −133 LSBs. Because offset calibration occurs before
gain calibration, the ratio of 4/3 changes linearly with gain
adjustment via the Channel x gain registers (see Table 56 and
Table 57 for the AD7768, or Table 82 and Table 83 for the
AD7768-4). After a reset or power cycle, the offset register values
revert to the default factory setting.
Rev. A | Page 59 of 99
AD7768/AD7768-4
Data Sheet
Gain Adjustment
Table 30. Phase Delay Resolution
Each ADC channel has an associated gain coefficient. The
coefficient is stored in three single-byte registers split up as
MSB, MID, and LSB. Each of the gain registers are factory
programmed. Nominally, this gain is around the value 0x555555
(for an ADC channel). The user may overwrite the gain register
setting. However, after a reset or power cycle, the gain register
values revert to the hard coded programmed factory setting.
Decimation
Ratio
×32
×64
×128
×256
×512
×1024
Calculate the approximate result that is output using the
following formula:
Resolution
1/fMOD
1/fMOD
1/fMOD
1/fMOD
2/fMOD
4/fMOD
Steps
32
64
128
256
256
256
Phase Register
Bits
[7:3]
[7:2]
[7:1]
[7:0]
[7:0]
[7:0]
Adjusting the sync phase of channels can affect the time to the
first DRDY pulse after the sync pulse, as well as the time to Bit 6
of the header status (filter not settled data bit) being cleared,
that is, the time to settled data.
 3 × VIN
 Gain 4,194,300
Data = 
× 2 21 − (Offset)  ×
×
V
4
2 42
 REF

where:
Offset is the offset register setting.
Gain is the gain register setting.
Sync Phase Offset Adjustment
The AD7768/AD7768-4 have one synchronization signal for all
channels. The sync phase offset register allows the user to vary
the phase delay on each of the channels relative to the synchronization edge received on the SYNC_IN pin.
By default, all ADC channels react simultaneously to the
SYNC_IN pulse. The sync phase registers can be programmed
to equalize known external phase differences on ADC input
channels, relative to one another. The range of phase compensation
is limited to a maximum of one conversion cycle, and the resolution
of the correction depends on the decimation rate in use.
Table 30 displays the resolution and register bits used for phase
offset for each decimation ratio.
If all channels are using the Sinc5 filter, the time to the first
DRDY pulse is not affected by the adjustment of the sync phase
offset, assuming that at least one channel has zero sync phase
offset adjustment. If all channels have a nonzero sync phase offset
setting, the time to the first DRDY pulse is delayed according to
the channel that has the least offset applied. Channels with a
sync offset adjustment setting that delays the internal sync signal,
relative to other channels, may not output settled data until
after the next DRDY pulse. In other words, there may be a delay
of one ODR period between the settled data being output by the
AD7768/AD7768-4 for the channels with added phase delay.
If all channels are using the wideband filter, the time to the first
DRDY pulse and the time to settled data is delayed according to
the channel with the maximum phase delay setting. In this case,
the interface waits for the latest channel and outputs data for all
channels when that channel is ready.
Rev. A | Page 60 of 99
Data Sheet
AD7768/AD7768-4
DATA INTERFACE
SETTING THE FORMAT OF DATA OUTPUT
with higher DCLK frequencies. For the best offset and offset
drift performance, use the lowest DCLK frequency possible.
The user can choose to reduce the DCLK frequency by an
appropriate selection of MCLK frequency, DCLK divider,
and/or the number of DOUTx lines used. Table 1 and Table 2
give the offset and offset drift specifications for ranges of DCLK
frequency, and Figure 49 shows the typical offset drift over a
range of DCLK frequencies.
The data interface format is determined by setting the FORMATx
pins. The logic state of the FORMATx pins are read on powerup and determine how many data lines (DOUTx) the ADC
conversions are output on.
Because the FORMATx pins are read on power-up of the
AD7768 and the device remains in this output configuration,
this function must always be hardwired and cannot be altered
dynamically. Table 31, Figure 92, Figure 93, and Figure 95 show
the formatting configuration for the digital output pins on the
AD7768.
FORMAT1
0
FORMAT0
0
Calculate the minimum required DCLK rate for a given data
interface configuration as follows:
0
1
1
X
Table 31. FORMATx Truth Table for the AD7768
DCLK (minimum) = Output Data Rate × Channels per
DOUTx × 32
where MCLK ≥ DCLK.
For example, if MCLK = 32.768 MHz, with two DOUTx lines,
DCLK (minimum) = 256 kSPS × 4 channels per DOUTx ×
32 = 32.768 Mbps
Therefore, DCLK = MCLK/1.
Description
Each ADC channel outputs on its own
dedicated pin. DOUT0 to DOUT7 are
in use.
The ADCs share the DOUT0 and
DOUT1 pins: Channel 0 to Channel 3
output on DOUT0. Channel 4 to
Channel 7 output on DOUT1. The ADC
channels share data pins in time
division multiplexed (TDM) output.
DOUT0 and DOUT1 are in use.
All channels output on the DOUT0 pin,
in TDM output. Only DOUT0 is in use.
Table 32. FORMAT0 Truth Table for the AD7768-4
Alternatively, if MCLK = 32.768 MHz, with eight DOUTx lines,
FORMAT0
0
DCLK (minimum) = 256 kSPS × 1 channel per DOUTx ×
32 = 8.192 Mbps
Description
Each ADC channel outputs on its own dedicated
pin. DOUT0 to DOUT3 are in use.
All channels output on the DOUT0 pin, in TDM
output. Only DOUT0 is in use.
1
Therefore, DCLK = MCLK/4.
Higher DCLK rates make it easier to receive the conversion data
from the AD7768/AD7768-4 with a lower number of DOUTx
lines; however, there is a trade-off against ADC offset performance
AD7768
DRDY
DCLK
EACH ADC HAS A
DEDICATED DOUTx PIN
FORMAT0
FORMAT1
0
0
DOUT0
CH 0
DOUT1
CH 1
CH 7
DAISY-CHAINING IS
NOT POSSIBLE IN THIS FORMAT
14001-092
DOUT7
DGND
Figure 92. AD7768 FORMATx = 00, Eight Data Output Pins
AD7768
DRDY
CHANNEL4 TO CHANNEL7
OUTPUT ON DOUT1
DCLK
1
0
DOUT0
FORMAT0
FORMAT1
DOUT1
DGND
DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT
Figure 93. AD7768 FORMATx = 01, Two Data Output Pins
Rev. A | Page 61 of 99
14001-193
CHANNEL0 TO CHANNEL3
OUTPUT ON DOUT0
IOVDD
AD7768/AD7768-4
Data Sheet
AD7768-4
DRDY
EACH ADC HAS A
DEDICATED DOUTx PIN
FORMAT0
0
DGND
CH 0
DOUT1
CH 1
DOUT2
CH 2
DOUT3
CH 3
DAISY-CHAINING IS
NOT POSSIBLE IN THIS FORMAT
14001-092
DCLK
DOUT0
Figure 94. AD7768-4 FORMAT0 = 0, Four Data Output Pins
AD7768
DRDY
IOVDD
1
1
FORMAT0
FORMAT1
DCLK
DOUT0
DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT
14001-194
CHANNEL0 TO CHANNEL7
OUTPUT ON DOUT0
Figure 95. AD7768 FORMATx = 10 or 11, or AD7768-4 FORMAT0 = 1, One Data Output Pin
ADC CONVERSION OUTPUT: HEADER AND DATA
Chip Error
The AD7768 data is output on the DOUT0 to DOUT7 pins,
depending on the FORMATx pins. The AD7768-4 data is
output on the DOUT0 to DOUT3 pins, depending on the
FORMAT0 pin. The actual structure of the data output for each
ADC result is shown in Figure 96. Each ADC result comprises
32 bits. The first eight bits are the header status bits, which
contain status information and the channel number. The names
of each of the header status bits are shown in Table 33, and their
functions are explained in the subsequent sections. This header
is followed by a 24-bit ADC output in twos complement coding,
MSB first.
The chip error bit indicates that a serious error has occurred. If
this bit is set, a reset is required to clear this bit. This bit indicates
that the external clock is not detected, a memory map bit has
unexpectedly changed state, or an internal CRC error has been
detected.
DRDY
N–1
HEADER N
8 BITS
ADC DATA N
24 BITS
Figure 96. ADC Output: 8-Bit Header, 24-Bit ADC Conversion Data
Table 33. Header Status Bits
Bit
7
6
5
4
3
[2:0]
Bit Name
CHIP_ERROR
Filter not settled
Repeated data
Filter type
Filter saturated
Channel ID[2:0]
14001-093
DOUTx
In the case where an external clock is not detected, the conversion
results are output as all zeros regardless of the analog input
voltages applied to the ADC channels.
Filter Not Settled
After power-up, reset, or synchronization, the AD7768/AD7768-4
clear the digital filters and begins conversion. Due to the weighting
of the digital filters, there is a delay from the first conversion to
fully settled data. The settling times for the AD7768/AD7768-4
when using the wideband and sinc5 filters are shown in Table 35
and Table 36, respectively. This bit is set if this settling delay has not
yet elapsed.
Repeated Data
If different channels use different decimation rates, data outputs
are repeated for the slower speed channels. In these cases, the
header is output as normal with the repeated data bit set to 1,
and the following repeated ADC result is output as all zeros.
This bit indicates that the conversion result of all zeros is not
real; it indicates that there is a repeated data condition because
two different decimation rates are selected. This condition can
only occur during SPI control of the AD7768/AD7768-4.
Rev. A | Page 62 of 99
Data Sheet
AD7768/AD7768-4
Filter Type
AD7768-4 supply the data, the data clock (DCLK), and a falling
edge framing signal (DRDY) to the slave device. All of these
signals are synchronous. The data interface connections to
DSP/FPGA are shown in Figure 102. The FORMATx pins
determine how the data is output from the AD7768/AD7768-4.
In pin control mode, all channels operate using one filter
selection. The filter selected in pin control mode is determined
by the logic level of the FILTER pin. In SPI control mode, the
digital filters can be selected on a per channel basis, using the
mode registers. This header bit is 0 for channels using the
wideband filter, and 1 for channels using the sinc5 filter.
Figure 97 through Figure 99 show the data interface operating
in standard mode at the maximum data rate. In all instances,
DRDY is asserted one clock cycle before the MSB of the data
conversion is made available on the data pin.
Filter Saturated
The filter saturated bit indicates that the filter output is clipping at
either positive or negative full scale. The digital filter clips if the
signal goes beyond the specification of the filter; it does not wrap.
The clipping may be caused by the analog input exceeding the
analog input range, or by a step change in the input, which may
cause overshoot in the digital filter. Clipping may also occur
when the combination of the analog input signal and the channel
gain register setting cause the signal seen by the filter to be
higher than the analog input range.
Each DRDY falling edge starts the output of the new ADC
conversion data. The first eight bits output after the DRDY falling
edge are the header bits; the last 24 bits are the ADC conversion
result.
Figure 97, Figure 98, and Figure 99 are distinct examples of the
impact of the FORMATx pins on the AD7768 output operating in
standard conversion operation. Figure 100 and Figure 101 show
two examples of the AD7768-4 interface configuration.
Channel ID
Figure 97 to Figure 99 represent running the AD7768 at
maximum data rate for the three FORMATx options.
The channel ID bits indicate the ADC channel from which the
succeeding conversion data originates (see Table 34).
Figure 97 shows FORMATx = 00 each ADC has its own data
out pin running at the MCLK/4 bit rate. In pin control mode, this is
achieved by selecting Mode 0xA (fast mode, DCLK = MCLK/4,
standard conversion, see Table 20) with the decimation rate set as
×32.
Table 34. Channel ID vs. Channel Number
Channel
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel ID 2
0
0
0
0
1
1
1
1
Channel ID 1
0
0
1
1
0
0
1
1
Channel ID 0
0
1
0
1
0
1
0
1
Figure 98 shows FORMATx = 01 share DOUT1 at the maximum
bit rate. In pin control mode, this is achieved by selecting Mode 0x8
(fast mode, DCLK = MCLK/1, standard conversion) with a
decimation rate of ×32.
If running in pin control mode, the example shown in Figure 99
represents Mode 0x4 (median mode, DCLK = MCLK/1,
standard conversion) with a decimation rate of ×32, giving the
maximum output data capacity possible on one DOUTx pin.
Data Interface: Standard Conversion Operation
In standard mode operation, the AD7768/AD7768-4 operate as
the master and stream data to the DSP or FPGA. The AD7768/
DCLK
SAMPLE N
SAMPLE N + 1
DOUT0
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
DOUT1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
DOUT7
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
Figure 97. AD7768 FORMATx = 00: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate
Rev. A | Page 63 of 99
14001-095
DRDY
AD7768/AD7768-4
Data Sheet
DCLK
SAMPLE N + 1
SAMPLE N
DRDY
DOUT0
CH0 (N)
CH1 (N)
CH2 (N)
CH3 (N)
CH0 (N+1)
CH1 (N+1)
CH2 (N+1)
CH3 (N+1)
DOUT1
CH4 (N)
CH5 (N)
CH6 (N)
CH7 (N)
CH4 (N+1)
CH5 (N+1)
CH6 (N+1)
CH7 (N+1)
14001-096
DOUT2
DOUT7
Figure 98. AD7768 FORMATx = 01: Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1, Maximum Data Rate
DCLK
SAMPLE N + 2
SAMPLE N + 1
SAMPLE N
DRDY
DOUT0
14001-097
DOUT1
DOUT7
Figure 99. AD7768 FORMATx = 11 or 10: Channel 0 to Channel 7 Output on DOUT0 Only, Maximum Data Rate
DCLK
SAMPLE N
SAMPLE N + 1
DOUT0
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
DOUT1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
DOUT2
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
DOUT3
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
D31 D30 D29 D28 D27 D...
D5
D4
D3
D2
D1
D0
Figure 100. AD7768-4 FORMAT0 = 0: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate
Rev. A | Page 64 of 99
14001-395
DRDY
Data Sheet
AD7768/AD7768-4
DCLK
SAMPLE N + 1
SAMPLE N
SAMPLE N + 2
DRDY
DOUT0
DOUT1
14001-302
DOUT2
DOUT3
Figure 101. AD7768-4 FORMAT0 = 1: Channel 0 to Channel 3 Output on DOUT0 Only, Maximum Data Rate
DSP/FPGA
AD7768
DCLK
DRDY
14001-094
DOUT0 TO
DOUT7
MCLK
Figure 102. Data Interface: Standard Conversion Operation, AD7768 = Master, DSP/FPGA = Slave
SYNC_IN
DOUT0
SETTLED
DATA
SETTLED
DATA
DOUT1
SETTLED
DATA
SETTLED
DATA
DOUT7
SETTLED
DATA
SETTLED
DATA
DRDY
32 DCLKs
32 DCLKs
Figure 103. AD7768 One-Shot Mode
Rev. A | Page 65 of 99
14001-098
tSETTLE
AD7768/AD7768-4
Data Sheet
One-shot mode is available in both SPI and pin control modes.
This conversion mode is available by selecting one of Mode 0xC to
Mode 0xF when in pin control mode. In SPI control mode, set
Bit 4 (one shot) of Register 0x06, the data control register.
Figure 103 shows the device operating in one-shot mode.
In one-shot mode, the AD7768/AD7768-4 are pseudo slaves.
Conversions occur on request by the master device, for example,
the DSP or FPGA. The SYNC_IN pin initiates the conversion
request. In one-shot mode, all ADCs run continuously; however,
the rising edge of the SYNC_IN pin controls the point in time
from which data is output.
To receive data, the master must pulse the SYNC_IN pin to
reset the filter and force DRDY low. DRDY subsequently goes
high to indicate to the master device that the device has valid
settled data available. Unlike standard mode, DRDY remains
high for the number of clock periods of valid data before it goes
low again; thus, in this conversion mode, it is an active high
frame of the data.
When the master pulses SYNC_IN and the AD7768/AD7768-4
receive the rising edge of this signal, the digital filter is reset and
the full settling time of the filter elapses before the data is available.
The duration of the settling time depends on the filter path and
decimation rate. Running one-shot mode with the sinc5 filter
allows the fastest throughput, because this filter has a lower
settling time than the wideband filter.
ADC device has its data interface in direct connection with the
digital host.
For the AD7768/AD7768-4, this connection can be implemented
by cascading DOUT0 and DOUT1 through a number of devices,
or just using DOUT0; whether two data output pins or only one
data output pin is enabled depends on the FORMATx pins. The
ability to daisy-chain devices and the limit on the number of
devices that can be handled by the chain is dependent on the
power mode, DCLK, and the decimation rate employed.
The maximum usable DCLK frequency allowed when daisychaining devices is limited by the combination of timing
specifications in Table 3 or Table 5, as well as by the propagation
delay of the data between devices and any skew between the MCLK
signals at each AD7768/AD7768-4 device. The propagation delay
and MCLK skew are dependent on the PCB layout and trace
lengths.
This feature is especially useful for reducing component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
When daisy-chaining, on the AD7768, DOUT6 and DOUT7
become serial data inputs, and DOUT0 and DOUT1 remain as
serial data outputs under the control of the FORMATx pins. For
the AD7768-4 the DIN pin is the daisy chain serial data input
pin and DOUT0 is the serial data output pin.
AD7768
START
MCLK
As soon as settled data is available on any channel, the device
outputs data from all channels. The contents of Bit 6 of the channel
header status bits indicates whether the data is fully settled.
The period before the data is settled on all channels (tSETTLE) is
shown in Figure 103. After the data has settled on all channels,
DRDY is asserted high and the device outputs the required settled
data on all channels before DRDY is asserted low. If the user configures the same filter and decimation rate on each ADC, the data is
settled for all channels on the first DRDY output frame, which
avoids a period of unsettled data prior to the settled data and
ensures that all data is output at the same time on all ADCs. The
device then waits for another SYNC_IN signal before outputting
more data.
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
DOUT6 DOUT7
SYNC_IN
SYNC_OUT
DRDY
DOUT0
DOUT1
DSP/
FPGA
IOVDD
AD7768
START
MASTER
CLOCK
MCLK
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
DOUT6 DOUT7
Because all the ADCs are sampling continuously, one-shot mode
affects the sampling theory of the AD7768/AD7768-4. Particularly,
a user periodically sending a SYNC_IN pulse to the device is a
form of subsampling of the ADC output. The subsampling occurs
at the rate of the SYNC_IN pulses. The SYNC_IN pulse must be
synchronous with the master clock to ensure coherent sampling
and to reduce the effects of jitter on the frequency response.
SYNC_IN
SYNC_OUT
DRDY
DNC
DNC
DOUT0
DOUT1
IOVDD
AD7768
START
MCLK
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
DOUT6 DOUT7
Daisy-Chaining
SYNC_IN
SYNC_OUT
DRDY
DNC
DNC
DOUT0
DOUT1
14001-099
Data Interface: One-Shot Conversion Operation
Figure 104. Daisy-Chaining Multiple AD7768 Devices
Daisy-chaining devices allows numerous devices to use the
same data interface lines by cascading the outputs of multiple
ADCs from separate AD7768/AD7768-4 devices. Only one
Figure 104 shows an example of daisy-chaining AD7768 devices,
when FORMATx = 01. In this case, the DOUT1 and DOUT0
pins of the AD7768 devices are cascaded to the DOUT6 and
DOUT7 pins of the next device in the chain. Data readback is
Rev. A | Page 66 of 99
Data Sheet
AD7768/AD7768-4
analogous to clocking a shift register where data is clocked on the
rising edge of DCLK.
The scheme operates by passing the output data of the DOUT0
and DOUT1 pins of an AD7768 upstream device to the DOUT6
and DOUT7 inputs of the next AD7768 device downstream in the
chain. The data then continues through the chain until it is
clocked onto the DOUT0 and DOUT1 pins of the final downstream device in the chain.
The devices in the chain must be synchronized by using one of
the following methods:
•
•
Applying a synchronous signal to the SYNC_IN pin of all
devices in the chain
By routing the SYNC_OUT pin of the first device to the
SYNC_IN pin of that same device and to the SYNC_IN
pins of all other devices in the chain and applying an
asynchronous signal to the START input.
Issuing an SPI_SYNC command over the SPI control
interface.
Figure 104 shows the configuration where an asynchronous
signal is applied to the START pin, and the SYNC_OUT pin of
the first device is connected to the SYNC_IN pins of all devices
in the chain
Daisy chaining can be achieved in a similar manner on the
AD7768 and AD7768-4 when using only the DOUT0 pin. In
this case, only Pin 21 of the AD7768/AD7768-4 is used as the
serial data input pin.
In a daisy-chained system of AD7768/AD7768-4 devices, two
successive synchronization pulses must be applied to guarantee that
all ADCs are synchronized. Two synchronization pulses are also
required in a system of more than one AD7768/AD7768-4 device
sharing a single MCLK signal, where the DRDY pin of only one
device is used to detect new data.
An important consideration for daisy-chaining more than two
AD7768/AD7768-4 devices is synchronization. The basic
provision for synchronizing multiple devices is that each device
is clocked with the same base MCLK signal.
The AD7768/AD7768-4 offer three options to allow ease of system
synchronization. Choosing between the options depends on the
system, but is determined by whether the user can supply a
synchronization pulse that is truly synchronous with the base
MCLK signal.
If the user cannot provide a signal that is synchronous to the
base MCLK signal, one of the following two methods can be
employed:
•
Apply a START pulse to the first AD7768 or AD7768-4
device. The first AD7768 or AD7768-4 device samples the
asynchronous START pulse and generates a pulse on
SYNC_OUT of the first device related to the base MCLK
signal for distribution locally.
Use synchronization over SPI (only available in SPI control
mode) to write a synchronization command to the first
AD7768 or AD7768-4 device. Similarly to the START pin
method, the SPI sync generates a pulse on SYNC_OUT of
the first device related to the base MCLK signal for
distribution locally.
•
In both cases, route the SYNC_OUT pin of the first device to
the SYNC_IN pin of that same device and to the SYNC_IN pins
of all other devices that are to be synchronized (see Figure 105).
The SYNC_OUT pins of the other devices must remain open
circuit. Tie all unused START pins to a Logic 1 through pull-up
resistors.
AD7768/
AD7768-4
The maximum DCLK frequency that can be used when daisychaining devices is a function of the AD7768/AD7768-4 timing
specifications (t4, t8, and t11 in Table 3 and Table 5) and any timing
differences between the AD7768/AD7768-4 devices due to layout
and spacing of devices on the PCB.
MCLK
DIGITAL FILTER
SYNC_IN
Use the following formula to aid in determining the maximum
operating frequency of the interface:
f MAX
START
SYNCHRONIZATION
LOGIC
SYNC_OUT
DRDY
DOUT0
DOUT1
DSP/
FPGA
MASTER
CLOCK
IOVDD
1
=
2 × (t 11 + t 4 + t 8 + t P + t SKEW )
AD7768/
AD7768-4
MCLK
where:
fMAX is the maximum useable DCLK frequency.
t11, t4, and t8 are the AD7768/AD7768-4 timing specifications
(see Table 3 and Table 5).
tP is the maximum propagation delay of the data between
successive AD7768/AD7768-4 devices in the chain.
tSKEW is the maximum skew in the MCLK signal seen by any pair of
AD7768/AD7768-4 devices in the chain.
START
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
SYNC_IN
SYNC_OUT
DRDY
DNC
DNC
14001-303
•
Synchronization
Figure 105. Synchronizing Multiple AD7768/AD7768-4 Devices Using
SYNC_OUT
Rev. A | Page 67 of 99
AD7768/AD7768-4
Data Sheet
The following is an example of how the CRC works for foursample mode (see Figure 107):
If the user can provide a signal that is synchronous to the base
MCLK, this signal can be applied directly to the SYNC_IN pin.
Route the signal from a star point and connect it directly to the
SYNC_IN pin of each AD7768/AD7768-4 device (see Figure 106).
The signal is sampled on the rising MCLK edge; setup and hold
times are associated with the SYNC_IN input are relative to the
AD7768/AD7768-4 MCLK rising edge.
1.
2.
3.
In this case, tie the START pin to Logic 1 through a pull-up
resistor; SYNC_OUT is not used and can remain open circuit.
4.
IOVDD
AD7768/
AD7768-4
MCLK
START
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
SYNC_IN
5.
DRDY
DOUT0
DOUT1
DSP/
FPGA
It is possible to have channels outputting at different rates (for
example decimation by 32 on Channel 0 and decimation by 64 on
Channel 1). In such cases, the CRC header still appears across all
channels at the same time, that is, at every fourth DRDY pulse after
a synchronization. For the channels operating at a relatively slower
ODR, the CRC is still calculated and emitted every 4 or 16 DRDY
cycles, even if this means that the nulled data is included.
Therefore, a CRC is calculated for only nulled samples or for a
combination of nulled samples and actual conversion data.
IOVDD
MCLK
START
SYNCHRONIZATION
LOGIC
DIGITAL FILTER
DRDY
DOUT0
DOUT1
14001-304
AD7768/
AD7768-4
SYNC_IN
After a synchronization pulse is applied to the
AD7768/AD7768-4, the CRC register is cleared to 0xFF.
The next four 24-bit conversion data samples (N to N + 3)
for a given channel stream into the CRC calculation.
For the first three samples that are output after the
synchronization pulse (N to N + 2), the header contains
the normal status bits.
For the fourth sample after the synchronization pulse (N +
3), the 8-bit CRC is sent out instead of the normal header
status bits, followed by the sample conversion data. This
CRC calculation includes the conversion data that is output
immediately after the CRC header.
The CRC register is then cleared back to 0xFF and the
cycle begins again for the fifth to eighth samples after the
synchronization pulse.
Figure 106. Synchronizing Multiple AD7768/AD7768-4 Devices Using Only
SYNC_IN
The AD7768/AD7768-4 use a CRC polynomial to calculate the
CRC message. The 8-bit CRC polynomial used is x8 + x2 + x + 1.
CRC Check on Data Interface
To generate the checksum, the data is left shifted by eight bits to
create a number ending in eight 1s.
The AD7768/AD7768-4 deliver 32 bits per channel as standard,
which by default consists of 8 status header bits and 24 bits of
data.
The polynomial is aligned such that its MSB is adjacent to the
leftmost Logic 1 of the data. An exclusive OR (XOR) function is
applied to the data to produce a new, shorter number. The polynomial is again aligned such that its MSB is adjacent to the leftmost
Logic 1 of the new result, and the procedure is repeated. This
process repeats until the original data is reduced to a value less
than the polynomial. This is the 8-bit checksum.
The header bits default per the description in Table 33. However,
there is also the option to employ a CRC check on the ADC
conversion data. This functionality is available only when operating
in SPI control mode. The function is controlled by CRC_SELECT
in the interface configuration register (Register 0x07). When
employed, the CRC message is calculated internally by the
AD7768/AD7768-4 on a per channel basis. The CRC then
replaces the 8-bit header every four samples or every 16 samples.
DOUT0
N–1
HEADER N
DATA N
HEADER N + 1
DATA N + 1
HEADER N + 2
DATA N + 2
CRC
DATA N + 3
8 BITS
24 BITS
8 BITS
24 BITS
8 BITS
24 BITS
8 BITS
24 BITS
Figure 107. CRC 4-Bit Stream
Rev. A | Page 68 of 99
14001-100
DRDY
Data Sheet
AD7768/AD7768-4
Table 35. Wideband Filter SYNC_IN to Settled Data
Power
Mode
Fast
Median
Eco
Filter Type
Group A
Group B
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Wideband Wideband
Decimation Factor
Group A Group B
32
Unused
64
Unused
128
Unused
256
Unused
512
Unused
1024
Unused
32
32
32
64
32
128
32
256
32
512
32
1024
64
32
128
32
256
32
512
32
1024
32
32
Unused
64
Unused
128
Unused
256
Unused
512
Unused
1024
Unused
32
32
32
64
32
128
32
256
32
512
32
1024
64
32
128
32
256
32
512
32
1024
32
32
Unused
64
Unused
128
Unused
256
Unused
512
Unused
1024
Unused
32
32
32
64
32
128
32
256
32
512
32
1024
64
32
128
32
256
32
512
32
1024
32
Delay from First MCLK
Rise After SYNC_IN Rise
to First DRDY Rise
MCLK Periods
336
620
1187
2325
4601
9153
758
758
758
758
758
758
759
760
762
782
806
656
1225
2359
4635
9187
18,291
820
820
820
820
820
820
822
824
844
836
852
2587
4855
9391
18,495
36,703
73,119
2587
2587
2587
2587
2587
2587
2587
2587
2587
2587
2587
Rev. A | Page 69 of 99
Delay from First MCLK Rise After SYNC_IN
Rise to Earliest Settled Data DRDY Rise
Group A
8400
16,748
33,443
66,837
133,625
267,201
8822
8822
8822
8822
8822
8822
17,015
33,528
66,938
133,646
267,302
16,784
33,481
66,871
133,659
267,235
534,387
16,948
16,948
16,948
16,948
16,948
16,948
33,590
66,872
133,708
267,332
534,612
67,099
133,879
267,439
534,591
1,068,895
2,137,503
67,099
67,099
67,099
67,099
67,099
67,099
134,683
267,803
535,067
1,069,595
2,137,627
MCLK Periods
Group B
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
8822
17,014
33,526
66,934
133,622
267,253
8823
8824
8826
8846
8870
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
16,948
33,588
66,868
133,684
267,316
534,580
16,950
16,952
16,972
16,964
16,980
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
67,099
134,683
267,803
535,067
1,069,595
2,137,627
67,099
67,099
67,099
67,099
67,099
AD7768/AD7768-4
Data Sheet
Table 36. Sinc5 Filter SYNC_IN to Settled Data1
Power
Mode
Fast
Median
Eco
1
Filter Type
Group A
Group B
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Decimation Factor
Group A
Group B
32
Unused
64
Unused
128
Unused
256
Unused
512
Unused
1024
Unused
32
32
32
64
32
128
32
256
32
512
32
1024
64
32
1024
32
32
Unused
64
Unused
128
Unused
256
Unused
512
Unused
1024
Unused
32
32
32
64
32
128
32
256
32
512
32
1024
64
32
1024
32
32
Unused
64
Unused
128
Unused
256
Unused
512
Unused
1024
Unused
32
32
32
64
32
128
32
256
32
512
32
1024
64
32
1024
32
Delay from First MCLK
Rise After SYNC_IN Rise
to First DRDY Rise
MCLK Periods
199
327
583
1095
2119
4167
199
199
199
199
199
199
199
199
383
639
1151
2175
4223
8319
383
383
383
398
398
398
383
398
1487
2511
4559
8655
16,847
33,231
1487
1487
1487
1487
1487
1487
1487
1487
Delay from First MCLK Rise After SYNC_IN
Rise to Earliest Settled Data DRDY Rise
Group A
MCLK Periods
839
1607
3143
6215
12359
24,647
839
839
839
839
839
839
1607
24,647
1663
3199
6271
12,415
24,703
49,279
1663
1663
1663
1663
1663
1663
3199
49,279
6607
12,751
25,039
49,615
98,767
197,071
6607
6607
6607
6607
6607
6607
12,751
197,071
This table is based on default internal clock divide settings of MCLK/4 in fast mode, MCLK/8 in median mode, and MCLK/32 in eco mode.
Rev. A | Page 70 of 99
Group B
MCLK Periods
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
839
1607
3143
6215
12,359
24,647
839
839
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
1663
3199
6271
12,415
24,703
49,279
1663
1663
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
6607
12,751
25,039
49,615
98,767
197,071
6607
6607
Data Sheet
AD7768/AD7768-4
FUNCTIONALITY
GPIO FUNCTIONALITY
GPIO PINS
FILTER/GPIO4 11
The AD7768/AD7768-4 have additional GPIO functionality
when operated in SPI mode. This fully configurable mode
allows the device to operate five GPIOs. The GPIOx pins can be
set as inputs or outputs (read or write) on a per pin basis.
MODE0/GPIO0 12
MODE1/GPIO1 13
MODE2/GPIO2 14
MODE3/GPIO3 15
ST0/CS 16
14001-101
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DEC1/SDI
ST1/SCLK
DEC0/SDO
17 18 19 20 21 22 23 24 25
In write mode, these GPIO pins can be used to control other
circuits such as switches, multiplexers, buffers, over the same
SPI interface as the AD7768/AD7768-4. Sharing the SPI interface
in this way allows the user to use a lower overall number of data
lines from the controller compared to a system where multiple
control signals are required. This sharing is especially useful in
systems where reducing the number of control lines across an
isolation barrier is important. See Figure 108 and Figure 109 for
details of the GPIO pin options available on the AD7768 and
AD7768-4, respectively.
TO DSP/FPGA
Figure 108. AD7768 GPIO Functionality
GPIO PINS
FILTER/GPIO4 11
Similarly, a GPIO read is a useful feature because it allows a
peripheral device to send information to the input GPIO and
then this information can be read from the SPI interface of the
AD7768/AD7768-4.
MODE0/GPIO0 12
MODE1/GPIO1 13
MODE2/GPIO2 14
MODE3/GPIO3 15
ST0/CS 16
DOUT2
14001-305
TO DSP/FPGA
DOUT3
DNC
DNC
DIN
DNC/DGND
DEC0/SDO
SCLK
DEC1/SDI
17 18 19 20 21 22 23 24 25
Figure 109. AD7768-4 GPIO Functionality
Configuration control and readback of the GPIOx pins are set
in Register 0x0E, Register 0x0F, and Register 0x10 (see Table 49,
Table 50, and Table 51 for more information for the AD7768, and
Table 75, Table 76, and Table 77 for the AD7768-4).
Rev. A | Page 71 of 99
AD7768/AD7768-4
Data Sheet
AD7768 REGISTER MAP DETAILS (SPI CONTROL)
AD7768 REGISTER MAP
See Table 63 and the AD7768-4 Register Map Details (SPI Control) section for the AD7768-4 register map and register functions.
Table 37. Detailed AD7768 Register Map
Reg.
0x00
0x01
0x02
0x03
0x08
Name
Channel standby
Channel Mode A
Channel Mode B
Channel mode
select
POWER_MODE
General
configuration
Data control
Interface
configuration
BIST control
0x09
Device status
0x0A
0x0B
0x0C
0x0D
0x0E
Revision ID
Reserved
Reserved
Reserved
GPIO control
0x0F
GPIO write data
0x10
0x11
GPIO read data
Precharge Buffer 1 CH3_PREBUF_
NEG_EN
Precharge Buffer 2 CH7_PREBUF_
NEG_EN
Positive reference CH7_REFP_
precharge buffer BUF
Negative reference CH7_REFN_
precharge buffer
BUF
Channel 0 offset
0x04
0x05
0x06
0x07
0x12
0x13
0x14
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
Channel 1 offset
Channel 2 offset
Channel 3 offset
Channel 4 offset
Channel 5 offset
Channel 6 offset
Channel 7 offset
Bit 7
CH_7
Bit 6
CH_6
Bit 3
CH_3
FILTER_TYPE_A
FILTER_TYPE_B
CH_3_MODE
Bit 2
CH_2
CH_7_MODE
Bit 5
Bit 4
CH_5
CH_4
Unused
Unused
CH_6_MODE
CH_5_MODE CH_4_MODE
SLEEP_MODE
Unused
Unused
Reserved
LVDS_ENABLE
Reserved
Unused
Unused
SPI_SYNC
POWER_MODE
RETIME_EN VCM_PD
Unused
Unused
SINGLE_SHOT_EN
CH_2_MODE
Unused
CRC_SELECT
Unused
Unused
UGPIO_
ENABLE
Unused
Unused
Unused
CH3_PREBUF_
POS_EN
CH7_PREBUF_
POS_EN
CH6_REFP_
BUF
CH6_REFN_
BUF
CH2_PREBUF_
NEG_EN
CH6_PREBUF_
NEG_EN
CH5_REFP_
BUF
CH5_REFN_
BUF
CHIP_ERROR
NO_CLOCK_
ERROR
Bit 1
CH_1
DEC_RATE_A
DEC_RATE_B
CH_1_MODE
Bit 0
CH_0
Reset
0x00
0x0D
0x0D
0x00
RW
RW
RW
RW
RW
MCLK_DIV
VCM_VSEL
0x00
0x08
RW
RW
SPI_RESET
DCLK_DIV
0x80
0x0
RW
RW
0x0
RW
0x0
R
CH_0_MODE
RAM_BIST_
START
RAM_BIST_PASS RAM_BIST_
RUNNING
REVISION_ID
Reserved
Reserved
Reserved
GPIOE4_FILTER GPIOE3_MODE3
0x06
0x00
0x00
0x00
GPIOE2_MODE2 GPIOE1_MODE1 GPIO0_MODE0 0x00
R
R
R
R
RW
GPIO4_WRITE
GPIO3_WRITE
GPIO2_WRITE
GPIO1_WRITE
GPIO0_WRITE
0x00
RW
GPIO4_READ
CH2_PREBUF_
POS_EN
CH6_PREBUF_
POS_EN
CH4_REFP_BUF
GPIO3_READ
CH1_PREBUF_
NEG_EN
CH5_PREBUF_
NEG_EN
CH3_REFP_BUF
GPIO2_READ
CH1_PREBUF_
POS_EN
CH5_PREBUF_
POS_EN
CH2_REFP_BUF
GPIO1_READ
CH0_PREBUF_
NEG_EN
CH4_PREBUF_
NEG_EN
CH1_REFP_BUF
0x00
0xFF
R
RW
0xFF
RW
0x00
RW
CH4_REFN_BUF
CH3_REFN_BUF
CH2_REFN_BUF
CH1_REFN_BUF
GPIO0_READ
CH0_PREBUF_
POS_EN
CH4_PREBUF_
POS_EN
CH0_REFP_
BUF
CH0_REFN_
BUF
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
CH0_OFFSET_MSB
CH0_OFFSET_MID
CH0_OFFSET_LSB
CH1_OFFSET_MSB
CH1_OFFSET_MID
CH1_OFFSET_LSB
CH2_OFFSET_MSB
CH2_OFFSET_MID
CH2_OFFSET_LSB
CH3_OFFSET_MSB
CH3_OFFSET_MID
CH3_OFFSET_LSB
CH4_OFFSET_MSB
CH4_OFFSET_MID
CH4_OFFSET_LSB
CH5_OFFSET_MSB
CH5_OFFSET_MID
CH5_OFFSET_LSB
CH6_OFFSET_MSB
CH6_OFFSET_MID
CH6_OFFSET_LSB
CH7_OFFSET_MSB
CH7_OFFSET_MID
CH7_OFFSET_LSB
Rev. A | Page 72 of 99
Data Sheet
Reg.
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
Name
Channel 0 gain
AD7768/AD7768-4
Bit 7
Bit 6
Bit 5
Bit 4
Channel 1 gain
Channel 2 gain
Channel 3 gain
Channel 4 gain
Channel 5 gain
Channel 6 gain
Channel 7 gain
Channel 0 sync
offset
Channel 1 sync
offset
Channel 2 sync
offset
Channel 3 sync
offset
Channel 4 sync
offset
Channel 5 sync
offset
Channel 6 sync
offset
Channel 7 sync
offset
Diagnostic receiver CH7_RX
(Rx)
Diagnostic mux
Unused
control
Modulator delay
control
Chop control
CH6_RX
CH5_RX
GRPB_SEL
CH4_RX
Bit 3
CH0_GAIN_MSB
CH0_GAIN_MID
CH0_GAIN_LSB
CH1_GAIN_MSB
CH1_GAIN_MID
CH1_GAIN_LSB
CH2_GAIN_MSB
CH2_GAIN_MID
CH2_GAIN_LSB
CH3_GAIN_MSB
CH3_GAIN_MID
CH3_GAIN_LSB
CH4_GAIN_MSB
CH4_GAIN_MID
CH4_GAIN_LSB
CH5_GAIN_MSB
CH5_GAIN_MID
CH5_GAIN_LSB
CH6_GAIN_MSB
CH6_GAIN_MID
CH6_GAIN_LSB
CH7_GAIN_MSB
CH7_GAIN_MID
CH7_GAIN_LSB
CH0_SYNC_OFFSET
Bit 2
Bit 1
Bit 0
Reset RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0x00
RW
CH1_SYNC_OFFSET
0x00
RW
CH2_SYNC_OFFSET
0x00
RW
CH3_SYNC_OFFSET
0x00
RW
CH4_SYNC_OFFSET
0x00
RW
CH5_SYNC_OFFSET
0x00
RW
CH6_SYNC_OFFSET
0x00
RW
CH7_SYNC_OFFSET
0x00
RW
0x00
RW
0x00
RW
0x02
RW
CH3_RX
CH2_RX
Unused
CH1_RX
CH0_RX
GRPA_SEL
Unused
CLK_MOD_DEL_EN
Reserved
Unused
GRPA_CHOP
GRPB_CHOP
Rev. A | Page 73 of 99
0x0A RW
AD7768/AD7768-4
Data Sheet
CHANNEL STANDBY REGISTER
Address: 0x00, Reset: 0x00, Name: Channel Standby
Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register.
When a channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result
output of 24 zeros.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also
disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is
also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7768.
Table 38. Bit Descriptions for Channel Standby
Bits
7
Bit Name
CH_7
Settings
0
1
6
CH_6
0
1
5
CH_5
0
1
4
CH_4
0
1
3
CH_3
0
1
2
CH_2
0
1
1
CH_1
0
1
0
CH_0
0
1
Description
Channel 7
Enabled
Standby
Channel 6
Enabled
Standby
Channel 5
Enabled
Standby
Channel 4
Enabled
Standby
Channel 3
Enabled
Standby
Channel 2
Enabled
Standby
Channel 1
Enabled
Standby
Channel 0
Enabled
Standby
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
CHANNEL MODE A REGISTER
Address: 0x01, Reset: 0x0D, Name: Channel Mode A
Two mode options are available on the AD7768 ADCs. The channel modes are defined by the contents of the Channel Mode A and
Channel Mode B registers. Each mode is then mapped as desired to the required ADC channel. Channel Mode A and Channel Mode B
allow different filter types and decimation rates to be selected and mapped to any of the ADC channels.
When different decimation rates are selected, the AD7768 output a data ready signal at the fastest selected decimation rate. Any channel
that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero
and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output:
Header and Data section).
Rev. A | Page 74 of 99
Data Sheet
AD7768/AD7768-4
Table 39. Bit Descriptions for Channel Mode A
Bits
3
Bit Name
FILTER_TYPE_A
Settings
0
1
[2:0]
DEC_RATE_A
000
001
010
011
100
101
110
111
Description
Filter selection
Wideband filter
Sinc5 filter
Decimation rate selection
×32
×64
×128
×256
×512
×1024
×1024
×1024
Reset
0x1
Access
RW
0x5
RW
Reset
0x1
Access
RW
0x5
RW
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
CHANNEL MODE B REGISTER
Address: 0x02, Reset: 0x0D, Name: Channel Mode B
Table 40. Bit Descriptions for Channel Mode B
Bits
3
Bit Name
FILTER_TYPE_B
Settings
0
1
[2:0]
DEC_RATE_B
000
001
010
011
100
101
110
111
Description
Filter selection
Wideband filter
Sinc5 filter
Decimation rate selection
×32
×64
×128
×256
×512
×1024
×1024
×1024
CHANNEL MODE SELECT REGISTER
Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.
Table 41. Bit Descriptions for Channel Mode Select
Bits
7
Bit Name
CH_7_MODE
Settings
0
1
6
CH_6_MODE
0
1
5
CH_5_MODE
0
1
4
CH_4_MODE
0
1
3
CH_3_MODE
0
1
Description
Channel 7
Mode A
Mode B
Channel 6
Mode A
Mode B
Channel 5
Mode A
Mode B
Channel 4
Mode A
Mode B
Channel 3
Mode A
Mode B
Rev. A | Page 75 of 99
AD7768/AD7768-4
Bits
2
Bit Name
CH_2_MODE
Data Sheet
Settings
0
1
1
CH_1_MODE
0
1
0
CH_0_MODE
0
1
Description
Channel 2
Mode A
Mode B
Channel 1
Mode A
Mode B
Channel 0
Mode A
Mode B
Reset
0x0
Access
RW
0x0
RW
0x0
RW
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
Reset
0x0
Access
RW
POWER MODE SELECT REGISTER
Address: 0x04, Reset: 0x00, Name: POWER_MODE
Table 42. Bit Descriptions for POWER_MODE
Bits
7
Bit Name
SLEEP_MODE
Settings
0
1
[5:4]
POWER_MODE
00
10
11
3
LVDS_ENABLE
0
1
[1:0]
MCLK_DIV
00
10
11
Description
In sleep mode, many of the digital clocks are disabled and all of the ADCs
are disabled. The analog LDOs are not disabled.
The AD7768 SPI is live and is available to the user. Writing to this bit brings
the AD7768 out of sleep mode again.
Normal operation.
Sleep mode.
Power mode. The power mode bits control the power mode setting for
the bias currents used on all ADCs on the AD7768. The user can select the
current consumption target to meet the application. The power modes of
fast, median, and eco give optimum performance when mapped to the
correct MCLK division setting. These power mode bits do not control the
MCLK division of the ADCs. See the MCLK_DIV bits for control of the
division of the MCLK input.
Eco mode.
Median mode.
Fast mode.
LVDS clock.
LVDS input clock disabled.
LVDS input clock enabled.
MCLK division. The MCLK division bits control the divided ratio between
the MCLK applied at the input to the AD7768 and the clock used by each
of the ADC modulators. The appropriate division ratio depends on the
following factors: power mode, decimation rate, and the base MCLK
available in the system. See the Clocking, Sampling Tree, and Power Scaling
section for more information on setting MCLK_DIV correctly.
MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for eco mode.
MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.
MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.
GENERAL DEVICE CONFIGURATION REGISTER
Address: 0x05, Reset: 0x08, Name: General Configuration
Table 43. Bit Descriptions for General Configuration
Bits
5
Bit Name
RETIME_EN
Settings
0
1
Description
SYNC_OUT signal retime enable bit.
Disabled: normal timing of SYNC_OUT.
Enabled: SYNC_OUT signal derived from alternate MCLK
edge.
Rev. A | Page 76 of 99
Data Sheet
Bits
4
AD7768/AD7768-4
Bit Name
VCM_PD
Settings
0
1
[1:0]
VCM_VSEL
00
01
10
11
Description
VCM buffer power-down.
Enabled: VCM buffer normal mode.
Powered down: VCM buffer powered down.
VCM voltage. These bits select the output voltage of the
VCM pin. This voltage is derived from the AVDD1 supply
and can be output as half of that AVDD1 voltage, or other
fixed voltages, with respect to AVSS. The VCM voltage
output is associated with the Channel 0 circuitry. If
Channel 0 is put into standby mode, the VCM voltage
output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used
externally to the AD7768.
(AVDD1 − AVSS)/2 V.
1.65 V.
2.5 V.
2.14 V.
Reset
0x0
Access
RW
0x0
RW
DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER
Address: 0x06, Reset: 0x80, Name: Data Control
Table 44. Bit Descriptions for Data Control
Bits
7
Bit Name
SPI_SYNC
Settings
0
1
4
SINGLE_SHOT_EN
0
1
[1:0]
SPI_RESET
00
01
10
11
Description
Software synchronization of the AD7768. This command has the same effect as
sending a signal pulse to the START pin. To operate the SPI_SYNC, the user must
write to this bit two separate times. First, write a zero, putting SPI_SYNC low, and
then write a 1 to set SPI_SYNC logic high again. The SPI_SYNC command is recognized after the last rising edge of SCLK in the SPI instruction where the SPI_SYNC
bit is changed from low to high. The SPI_SYNC command is then output synchronous to the AD7768 MCLK on the SYNC_OUT pin. The user must connect the
SYNC_OUT signal to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be
routed to the SYNC_IN pins of other AD7768 devices, allowing larger channel
count simultaneous sampling systems. As per any synchronization pulse seen by
the SYNC_IN pin, the digital filters of the AD7768 are reset. The full settling time
of the filters must elapse before data is output on the data interface. In a daisychained system of AD7768 devices, two successive synchronization pulses must
be applied to guarantee that all ADCs are synchronized. Two synchronization
pulses are also required in a system of more than one AD7768 device sharing a
single MCLK signal, where the DRDY pin of only one device is used to detect new
data.
Change to SPI_SYNC low.
Change to SPI_SYNC high.
One-shot mode. Enables one-shot mode. In one-shot mode, the AD7768 output
a conversion result in response to a SYNC_IN rising edge.
Disabled.
Enabled.
Soft reset. These bits allow a full device reset over the SPI port. Two successive
commands must be received in the correct order to generate a reset: first, write
0x03 to the soft reset register, and then write 0x02 to the soft reset register. This
sequence causes the digital core to reset and all registers return to their default
values. Following a soft reset, if the SPI master sends a command to the AD7768,
the devices respond on the next frame to that command with an output of
0x0E00.
No effect.
No effect.
Second reset command.
First reset command.
Rev. A | Page 77 of 99
Reset
0x1
Access
RW
0x0
RW
0x0
RW
AD7768/AD7768-4
Data Sheet
INTERFACE CONFIGURATION REGISTER
Address: 0x07, Reset: 0x0, Name: Interface Configuration
Table 45. Bit Descriptions for Interface Configuration
Bits
[3:2]
Bit Name
CRC_SELECT
Settings
00
01
10
11
[1:0]
DCLK_DIV
00
01
10
11
Description
CRC select. These bits allow the user to implement a CRC on the data
interface. When selected, the CRC replaces the header every fourth or 16th
output sample depending on the CRC option chosen. There are two
options for the CRC; both use the same polynomial: x8 + x2 + x + 1. The
options offer the user the ability to reduce the duty cycle of the CRC
calculation by performing it less often: in the case of having it every 16th
sample or more often in the case of every fourth conversion. The CRC is
calculated on a per channel basis and it includes conversion data only.
No CRC. Status bits with every conversion.
Replace the header with CRC message every 4 samples.
Replace the header with CRC message every 16 samples.
Replace the header with CRC message every 16 samples.
DCLK divider. These bits control division of the DCLK clock used to clock
out conversion data on the DOUTx pins. The DCLK signal is derived from
the MCLK applied to the AD7768. The DCLK divide mode allows the user
to optimize the DCLK output to fit the application. Optimizing the DCLK
per application depends on the requirements of the user. When the
AD7768 are using the highest capacity output on the fewest DOUTx pins,
for example, running in decimate by 32 using the DOUT0 and DOUT1
pins, the DCLK must equal the MCLK; thus, in this case, choosing the no
division setting is the only way the user can output all the data within the
conversion period. There are other cases, however, when the ADC may be
running in fast mode with high decimation rates, or in median or eco
mode where the DCLK does not need to run at the same speed as MCLK.
In these cases, the DCLK divide allows the user to reduce the clock speed
and makes routing and isolating such signals easier.
Divide by 8.
Divide by 4.
Divide by 2.
No division.
Reset
0x0
Access
RW
0x0
RW
Reset
0x0
Access
RW
DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER
Address: 0x08, Reset: 0x0, Name: BIST Control
Table 46. Bit Descriptions for BIST Control
Bits
0
Bit Name
RAM_BIST_START
Settings
0
1
Description
RAM BIST. Filter RAM BIST is a built in self test of the internal RAM. Normal
ADC conversion is disrupted when this test is run. A synchronization pulse
is required after this test is complete to resume normal ADC operation.
The test can be run at intervals depending on user preference. The status
and result of the RAM BIST is available in the device status register; see the
RAM_BIST_PASS and RAM_BIST_RUNNING bits in Table 47.
Off.
Begin RAM BIST.
Rev. A | Page 78 of 99
Data Sheet
AD7768/AD7768-4
STATUS REGISTER
Address: 0x09, Reset: 0x0, Name: Device Status
Table 47. Bit Descriptions for Device Status
Bits
3
Bit Name
CHIP_ERROR
Settings
0
1
2
NO_CLOCK_ERROR
0
1
1
RAM_BIST_PASS
0
1
0
RAM_BIST_RUNNING
0
1
Description
Chip error. Chip error is a global error flag that is output within the
status byte of each ADC conversion output. The following bits lead to
the chip error bit being set to logic high: CRC check on internally hard
coded settings after power-up does not pass; XOR check on the internal
memory does not pass (this check runs continuously in the background);
and clock error is detected on power-up.
No error present.
Error has occurred.
External clock check. This bit indicates whether the externally applied
MCLK is detected correctly. If the MCLK is not applied correctly to the
ADC at power-up, this bit is set and the DCLK frequency is approximately
16 MHz. If this bit is set, the chip error bit is set to logic high in the
status bits of the data output headers, and the conversion results are
output as all zeros regardless of the analog input voltages applied to
the ADC channels.
MCLK detected.
No MCLK detected.
BIST pass/fail. RAM BIST result status. This bit indicates the result of the
most recent RAM BIST. The result is latched to this register and is only
cleared by a device reset.
BIST failed or not run.
BIST passed.
BIST status. Reading back the value of this bit allows the user to poll
when the BIST test has finished.
BIST not running.
BIST running.
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
REVISION IDENTIFICATION REGISTER
Address: 0x0A, Reset: 0x06, Name: Revision ID
Table 48. Bit Descriptions for Revision ID
Bits
[7:0]
Bit Name
REVISION_ID
Description
ASIC revision. 8-bit ID for revision details.
Reset
0x06
Access
R
GPIO CONTROL REGISTER
Address: 0x0E, Reset: 0x00, Name: GPIO Control
Table 49. Bit Descriptions for GPIO Control
Bits
7
Bit Name
UGPIO_ENABLE
Setting
0
1
4
GPIOE4_FILTER
0
1
Description
User GPIO enable. The GPIOx pins are dual-purpose and can be operated only
when the device is in SPI control mode. By default, when the AD7768 are powered
up in SPI control mode, the GPIOx pins are disabled. This bit is a universal enable/
disable for all GPIOx input/outputs. The direction of each general-purpose pin
is determined by Bits[4:0] of this register.
GPIO Disabled.
GPIO Enabled.
GPIO4 Direction. This bit assigns the direction of GPIO4 as either an input or an
output. For SPI control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin.
Input.
Output.
Rev. A | Page 79 of 99
Reset
0x0
Access
RW
0x0
RW
AD7768/AD7768-4
Bits
3
Bit Name
GPIOE3_MODE3
Data Sheet
Setting
0
1
2
GPIOE2_MODE2
0
1
1
GPIOE1_MODE1
0
1
0
GPIO0_MODE0
0
1
Description
GPIO3 Direction. This bit assigns the direction of GPIO3 as either an input or
an output. For SPI control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin.
Input.
Output.
GPIO2 Direction. This bit assigns the direction of GPIO2 as either an input or an
output. For SPI control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin.
Input.
Output.
GPIO1 Direction. This bit assigns the direction of GPIO1 as either an input or an
output. For SPI control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin.
Input.
Output.
GPIO0 Direction. This bit assigns the direction of GPIO0 as either an input or
an output. For SPI control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin.
Input.
Output.
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
GPIO WRITE DATA REGISTER
Address: 0x0F, Reset: 0x00, Name: GPIO Write Data
This register writes the values to be set on each of the general-purpose pins when selected as general-purpose outputs. Each bit, from
Bits[4:0], maps directly to the GPIOx pins.
Table 50. Bit Descriptions for GPIO Write Data
Bits
4
3
2
1
0
Bit Name
GPIO4_WRITE
GPIO3_WRITE
GPIO2_WRITE
GPIO1_WRITE
GPIO0_WRITE
Description
GPIO4/FILTER
GPIO3/MODE3
GPIO2/MODE2
GPIO1/MODE1
GPIO0/MODE0
Reset
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
GPIO READ DATA REGISTER
Address: 0x10, Reset: 0x00, Name: GPIO Read Data
This register reads back the value of the logic input level at the general-purpose pins when selected to operate as general-purpose inputs.
Each bit, from Bits[4:0], maps directly to the GPIO0 to GPIO4 pins.
Table 51. Bit Descriptions for GPIO Read Data
Bits
4
3
2
1
0
Bit Name
GPIO4_READ
GPIO3_READ
GPIO2_READ
GPIO1_READ
GPIO0_READ
Description
GPIO4/FILTER
GPIO3/MODE3
GPIO2/MODE2
GPIO1/MODE1
GPIO0/MODE0
Reset
Access
0x0
0x0
0x0
0x0
0x00
R
R
R
R
R
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3
Address: 0x11, Reset: 0xFF, Name: Precharge Buffer 1
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 7 of this register, the user must write 0x01 to the register. This clears Bit 7 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.
Table 52. Bit Descriptions for Precharge Buffer 1
Bits
7
Bit Name
CH3_PREBUF_NEG_EN
Settings
0
1
Rev. A | Page 80 of 99
Description
Off
On
Reset
0x1
Data Sheet
Bits
6
Bit Name
CH3_PREBUF_POS_EN
5
CH2_PREBUF_NEG_EN
4
CH2_PREBUF_POS_EN
3
CH1_PREBUF_NEG_EN
2
CH1_PREBUF_POS_EN
1
CH0_PREBUF_NEG_EN
0
CH0_PREBUF_POS_EN
AD7768/AD7768-4
Settings
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Reset
0x1
0x1
0x1
0x1
0x1
0x1
0x1
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7
Address: 0x12, Reset: 0xFF, Name: Precharge Buffer 2
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 7 of this register, the user must write 0x01 to the register. This clears Bit 7 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.
Table 53. Bit Descriptions for Precharge Buffer 2
Bits
7
Bit Name
CH7_PREBUF_NEG_EN
6
CH7_PREBUF_POS_EN
5
CH6_PREBUF_NEG_EN
4
CH6_PREBUF_POS_EN
3
CH5_PREBUF_NEG_EN
2
CH5_PREBUF_POS_EN
1
CH4_PREBUF_NEG_EN
0
CH4_PREBUF_POS_EN
Settings
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Reset
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x13, Reset: 0x00, Name: Positive Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference positive input to each of the ADCs from Channel 0 to Channel 7.
Table 54. Bit Descriptions for Positive Reference Precharge Buffer
Bits
7
Bit Name
CH7_REFP_BUF
6
CH6_REFP_BUF
5
CH5_REFP_BUF
Settings
0
1
0
1
0
1
Rev. A | Page 81 of 99
Description
Off
On
Off
On
Off
On
Reset
0x0
0x0
0x0
AD7768/AD7768-4
Bits
4
Bit Name
CH4_REFP_BUF
3
CH3_REFP_BUF
2
CH2_REFP_BUF
1
CH1_REFP_BUF
0
CH0_REFP_BUF
Data Sheet
Settings
0
1
0
1
0
1
0
1
0
1
Description
Off
On
Off
On
Off
On
Off
On
Off
On
Reset
0x0
0x0
0x0
0x0
0x0
NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 7.
Table 55. Bit Descriptions for Negative Reference Precharge Buffer
Bits
7
Bit Name
CH7_REFN_BUF
6
CH6_REFN_BUF
5
CH5_REFN_BUF
4
CH4_REFN_BUF
3
CH3_REFN_BUF
2
CH2_REFN_BUF
1
CH1_REFN_BUF
0
CH0_REFN_BUF
Settings
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers are 24-bit, signed twos complement registers for channel
offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital
output by −4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by −133 LSBs. As offset adjustment
occurs before gain adjustment, the ratio of 4/3 changes linearly with gain adjustment via the CHx_GAIN_x registers. After a reset or power
cycle, the register values revert to the default factory setting.
Table 56. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
MSB
0x1E
0x21
0x24
0x27
0x2A
0x2D
0x30
0x33
Address
Mid
0x1F
0x22
0x25
0x28
0x2B
0x2E
0x31
0x34
LSB
0x20
0x23
0x26
0x29
0x2C
0x2F
0x32
0x35
Name
Channel 0 offset
Channel 1 offset
Channel 2 offset
Channel 3 offset
Channel 4 offset
Channel 5 offset
Channel 6 offset
Channel 7 offset
Description
Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total)
Rev. A | Page 82 of 99
MSB
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset
Mid
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
LSB
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
RW
RW
RW
RW
Data Sheet
AD7768/AD7768-4
GAIN REGISTERS
Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and
LSB. Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The
user may overwrite the gain register setting however, after a reset or power cycle, the gain register values revert to the hard coded
programmed factory setting.
Table 57. Per Channel 24-Bit Gain Registers, 3 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
MSB
0x36
0x39
0x3C
0x3F
0x42
0x45
0x48
0x4B
Address
Mid
0x37
0x3A
0x3D
0x40
0x43
0x46
0x49
0x4C
LSB
0x38
0x3B
0x3E
0x41
0x44
0x47
0x4A
0x4D
Name
Channel 0 gain
Channel 1 gain
Channel 2 gain
Channel 3 gain
Channel 4 gain
Channel 5 gain
Channel 6 gain
Channel 7 gain
Description
Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 4 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 5 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 6 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 7 gain registers: upper, middle, and lower bytes (24 bits in total)
MSB
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
Reset
Mid
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
LSB
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
Access
RW
RW
RW
RW
RW
RW
RW
RW
SYNC PHASE OFFSET REGISTERS
The AD7768 have one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on
each of the channels relative to the synchronization edge received on the SYNC_IN pin. See the Sync Phase Offset Adjustment section for
details on the use of this function.
Table 58. Per Channel 8-Bit Sync Phase Offset Registers
Address
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
Name
Channel 0 sync offset
Channel 1 sync offset
Channel 2 sync offset
Channel 3 sync offset
Channel 4 sync offset
Channel 5 sync offset
Channel 6 sync offset
Channel 7 sync offset
Description
Channel 0 sync phase offset register
Channel 1 sync phase offset register
Channel 2 sync phase offset register
Channel 3 sync phase offset register
Channel 4 sync phase offset register
Channel 5 sync phase offset register
Channel 6 sync phase offset register
Channel 7 sync phase offset register
Reset
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
RW
RW
RW
RW
ADC DIAGNOSTIC RECEIVE SELECT REGISTER
Address: 0x56, Reset: 0x00, Name: Diagnostic Rx
The AD7768 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can
be converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive (Rx) for each
channel and set each bit in this register to 1.
The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input
precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally.
Table 59. Bit Descriptions for Diagnostic Rx
Bits
7
Bit Name
CH7_RX
Settings
0
1
6
CH6_RX
0
1
5
CH5_RX
0
1
Description
Channel 7
Not in use
Receive
Channel 6
Not in use
Receive
Channel 5
Not in use
Receive
Rev. A | Page 83 of 99
Reset
0x0
Access
RW
0x0
RW
0x0
RW
AD7768/AD7768-4
Bits
4
Bit Name
CH4_RX
Data Sheet
Settings
0
1
3
CH3_RX
0
1
2
CH2_RX
0
1
1
CH1_RX
0
1
0
CH0_RX
0
1
Description
Channel 4
Not in use
Receive
Channel 3
Not in use
Receive
Channel 2
Not in use
Receive
Channel 1
Not in use
Receive
Channel 0
Not in use
Receive
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADC DIAGNOSTIC CONTROL REGISTER
Address: 0x57, Reset: 0x00, Name: Diagnostic Mux Control
The AD7768 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can
be converted to verify the correct operation of the ADC channel. This register controls the voltage that is applied to each of the ADC
channels for the diagnostic. There are three input voltage options that the user can select. The voltage selected is mapped to the channels based
on which mode (Mode A or Mode B) they belong to, which is set according to the channel mode select register (Register 0x03).
Set Bits[7:0] to 1 in the ADC diagnostic receive select register, then select the voltage check desired for the channels on Mode A and the
channels on Mode B through Bits[2:0] and Bits[6:4], respectively.
Table 60. Bit Descriptions for Diagnostic Mux Control
Bits
[6:4]
Bit Name
GRPB_SEL
Settings
000
011
100
101
[2:0]
GRPA_SEL
000
011
100
101
Description
Mux B.
Off.
Positive full-scale ADC check. A voltage close to positive full scale is
applied internally to the ADC channel.
Negative full-scale ADC check. A voltage close to negative (or minus) full
scale is applied internally to the ADC channel.
Zero-scale ADC check. A voltage close to 0 V is applied internally to the
ADC channel.
Mux A.
Off.
Positive full-scale ADC check. A voltage close to positive full scale is
applied internally to the ADC channel.
Negative full-scale ADC check. A voltage close to negative (or minus) full
scale is applied internally to the ADC channel.
Zero-scale ADC check. A voltage close to 0 V is applied internally to the
ADC channel.
Rev. A | Page 84 of 99
Reset
0x0
Access
RW
0x0
RW
Data Sheet
AD7768/AD7768-4
MODULATOR DELAY CONTROL REGISTER
Address: 0x58, Reset: 0x02, Name: Modulator Delay Control
Table 61. Bit Descriptions for Modulator Delay Control
Bits
[3:2]
[1:0]
Bit Name
CLK_MOD_DEL_EN
Settings
00
01
10
11
10
Reserved
Description
Enable delayed modulator clock.
Disabled delayed clock for all channels.
Enable delayed clock for Channel 0 to Channel 3 only on the AD7768.
Enable delayed clock for Channel 4 to Channel 7 only on AD7768.
Enable delayed clock for all channels.
Not a user option. Must be set to 0x2.
Reset
0x0
Access
RW
0x2
RW
Reset
0x2
Access
RW
0x2
RW
CHOPPING CONTROL REGISTER
Address: 0x59, Reset: 0x0A, Name: Chop Control
Table 62. Bit Descriptions for Chop Control
Bits
[3:2]
Bit Name
GRPA_CHOP
Settings
01
10
[1:0]
GRPB_CHOP
01
10
Description
Group A chopping
Chop at fMOD/8
Chop at fMOD/32
Group B chopping
Chop at fMOD/8
Chop at fMOD/32
Rev. A | Page 85 of 99
AD7768/AD7768-4
Data Sheet
AD7768-4 REGISTER MAP DETAILS (SPI CONTROL)
AD7768-4 REGISTER MAP
Table 63. Detailed AD7768-4 Register Map
Reg.
0x00
0x01
0x02
0x03
0x08
Name
Channel standby
Channel Mode A
Channel Mode B
Channel mode
select
POWER_MODE
General
configuration
Data control
Interface
configuration
BIST control
0x09
Device status
0x0A
0x0B
0x0C
0x0D
0x0E
Revision ID
Reserved
Reserved
Reserved
GPIO control
0x0F
GPIO write data
Unused
0x10
0x11
GPIO read data
Precharge Buffer 1
Unused
0x12
Precharge Buffer 2
0x13
Positive reference
precharge buffer
Negative reference
precharge buffer
Channel 0 offset
0x04
0x05
0x06
0x07
0x14
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
Channel 1 offset
Reserved
Reserved
Channel 2 offset
Channel 3 offset
Reserved
Reserved
Channel 0 gain
Bit 7
Bit 6
Reserved
SLEEP_MODE
Unused
Unused
Reserved
SPI_SYNC
Bit 5
Bit 4
Unused
Unused
Unused
CH_3_MODE CH_2_MODE
POWER_MODE
RETIME_EN VCM_PD
Unused
Unused
Bit 3
Bit 2
CH_3
CH_2
FILTER_TYPE_A
FILTER_TYPE_B
Reserved
LVDS_ENABLE
Reserved
SINGLE_SHOT_EN
Unused
Unused
Unused
CRC_SELECT
Unused
Unused
UGPIO_
ENABLE
Unused
CHIP_ERROR
Reserved
Reset
0x00
0x0D
0x0D
0x00
RW
RW
RW
RW
RW
MCLK_DIV
VCM_VSEL
0x00
0x08
RW
RW
SPI_RESET
DCLK_DIV
0x80
0x0
RW
RW
0x0
RW
0x0
R
CH_0_MODE
RAM_BIST_
START
RAM_BIST_PASS RAM_BIST_
RUNNING
0x06
0x00
0x00
0x00
GPIOE2_MODE2 GPIOE1_MODE1 GPIO0_MODE0 0x00
R
R
R
R
RW
GPIO4_WRITE
GPIO3_WRITE
GPIO2_WRITE
GPIO4_READ
GPIO3_READ
GPIO2_READ
CH1_PREBUF_
CH1_PREBUF_
NEG_EN
POS_EN
CH3_PREBUF_
CH3_PREBUF_
NEG_EN
POS_EN
Reserved
Reserved
CH3_REFP_
BUF
CH3_REFN_
BUF
Bit 0
CH_0
REVISION_ID
Reserved
Reserved
Reserved
GPIOE4_FILTER GPIOE3_MODE3
Reserved
Reserved
NO_CLOCK_
ERROR
Bit 1
CH_1
DEC_RATE_A
DEC_RATE_B
CH_1_MODE
CH2_REFP_BUF
CH2_REFN_BUF
CH0_OFFSET_MSB
CH0_OFFSET_MID
CH0_OFFSET_LSB
CH1_OFFSET_MSB
CH1_OFFSET_MID
CH1_OFFSET_LSB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH2_OFFSET_MSB
CH2_OFFSET_MID
CH2_OFFSET_LSB
CH3_OFFSET_MSB
CH3_OFFSET_MID
CH3_OFFSET_LSB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH0_GAIN_MSB
CH0_GAIN_MID
CH0_GAIN_LSB
Rev. A | Page 86 of 99
Reserved
GPIO1_WRITE
GPIO0_WRITE
0x00
RW
GPIO1_READ
CH0_PREBUF_
NEG_EN
CH2_PREBUF_NE
G_EN
CH1_REFP_BUF
GPIO0_READ
CH0_PREBUF_
POS_EN
CH2_PREBUF_
POS_EN
CH0_REFP_
BUF
CH0_REFN_
BUF
0x00
0xFF
R
RW
0xFF
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
CH1_REFN_BUF
0xXX RW
Data Sheet
Reg.
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
Name
Channel 1 gain
AD7768/AD7768-4
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Channel 2 gain
Channel 3 gain
Reserved
Reserved
Channel 0 sync
offset
Channel 1 sync
offset
Reserved
Reserved
Channel 2 sync
offset
Channel 3 sync
offset
Reserved
Reserved
Diagnostic Rx
Diagnostic mux
control
Modulator delay
control
Chop control
Reserved
Unused
CH3_RX
CH2_RX
GRPB_SEL
Bit 3
CH1_GAIN_MSB
CH1_GAIN_MID
CH1_GAIN_LSB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH2_GAIN_MSB
CH2_GAIN_MID
CH2_GAIN_LSB
CH3_GAIN_MSB
CH3_GAIN_MID
CH3_GAIN_LSB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH0_SYNC_OFFSET
Bit 2
Bit 1
Bit 0
Reset RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0x00
RW
CH1_SYNC_OFFSET
0x00
RW
Reserved
Reserved
CH2_SYNC_OFFSET
0x00
0x00
0x00
RW
RW
RW
CH3_SYNC_OFFSET
0x00
RW
Reserved
Reserved
0x00
0x00
0x00
0x00
RW
RW
RW
RW
0x02
RW
Reserved
Unused
CH1_RX
GRPA_SEL
CH0_RX
Unused
CLK_MOD_DEL_EN
Reserved
Unused
GRPA_CHOP
GRPB_CHOP
Rev. A | Page 87 of 99
0x0A RW
AD7768/AD7768-4
Data Sheet
CHANNEL STANDBY REGISTER
Address: 0x00, Reset: 0x00, Name: Channel Standby
Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register.
When a channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result
output of 24 zeros.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also
disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768-4.
The crystal excitation circuitry is associated with the Channel 2 circuitry. If Channel 2 is put into standby mode, the crystal circuitry is
also disabled for maximum power savings. Channel 2 must be enabled while the external crystal is used on the AD7768-4.
Table 64. Bit Descriptions for Channel Standby
Bits
3
Bit Name
CH_3
Settings
0
1
2
CH_2
0
1
1
CH_1
0
1
0
CH_0
0
1
Description
Channel 3
Enabled
Standby
Channel 2
Enabled
Standby
Channel 1
Enabled
Standby
Channel 0
Enabled
Standby
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
CHANNEL MODE A REGISTER
Address: 0x01, Reset: 0x0D, Name: Channel Mode A
Two mode options are available on the AD7768-4 ADCs. The channel modes are defined by the contents of the Channel Mode A and
Channel Mode B registers. Each mode is then mapped as desired to the required ADC channel. Mode A and Mode B allow different filter
types and decimation rates to be selected and mapped to any of the ADC channels.
When different decimation rates are selected, the AD7768-4 output a data ready signal at the fastest selected decimation rate. Any channel
that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero
and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output:
Header and Data section).
Table 65. Bit Descriptions for Channel Mode A
Bits
3
Bit Name
FILTER_TYPE_A
Settings
0
1
[2:0]
DEC_RATE_A
000
001
010
011
100
101
110
111
Description
Filter selection
Wideband filter
Sinc5 filter
Decimation rate selection
×32
×64
×128
×256
×512
×1024
×1024
×1024
Rev. A | Page 88 of 99
Reset
0x1
Access
RW
0x5
RW
Data Sheet
AD7768/AD7768-4
CHANNEL MODE B REGISTER
Address: 0x02, Reset: 0x0D, Name: Channel Mode B
Table 66. Bit Descriptions for Channel Mode B
Bits
3
Bit Name
FILTER_TYPE_B
Settings
0
1
[2:0]
DEC_RATE_B
000
001
010
011
100
101
110
111
Description
Filter selection
Wideband filter
Sinc5 filter
Decimation rate selection
×32
×64
×128
×256
×512
×1024
×1024
×1024
Reset
0x1
Access
RW
0x5
RW
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
Reset
0x0
Access
RW
CHANNEL MODE SELECT REGISTER
Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.
Table 67. Bit Descriptions for Channel Mode Select
Bits
5
Bit Name
CH_3_MODE
Settings
0
1
4
CH_2_MODE
0
1
1
CH_1_MODE
0
1
0
CH_0_MODE
0
1
Description
Channel 3
Mode A
Mode B
Channel 2
Mode A
Mode B
Channel 1
Mode A
Mode B
Channel 0
Mode A
Mode B
POWER MODE SELECT REGISTER
Address: 0x04, Reset: 0x00, Name: POWER_MODE
Table 68. Bit Descriptions for POWER_MODE
Bits
7
Bit Name
SLEEP_MODE
Settings
0
1
Description
In sleep mode, many of the digital clocks are disabled and all of the ADCs
are disabled. The analog LDOs are not disabled.
The AD7768-4 SPI is live and is available to the user. Writing to this bit
brings the AD7768-4 out of sleep mode again.
Normal operation.
Sleep mode.
Rev. A | Page 89 of 99
AD7768/AD7768-4
Bits
[5:4]
Bit Name
POWER_MODE
Data Sheet
Settings
00
10
11
3
LVDS_ENABLE
0
1
[1:0]
MCLK_DIV
00
10
11
Description
Power mode. The power mode bits control the power mode setting for
the bias currents used on all ADCs on the AD7768-4. The user can select
the current consumption target to meet the application. The power
modes of fast, median, and eco give optimum performance when
mapped to the correct MCLK division setting. These power mode bits do
not control the MCLK division of the ADCs. See the MCLK_DIV bits for
control of the division of the MCLK input.
Eco.
Median.
Fast.
LVDS clock.
LVDS input clock disabled.
LVDS input clock enabled.
MCLK division. The MCLK division bits control the divided ratio between
the MCLK applied at the input to the AD7768-4 and the clock used by
each of the ADC modulators. The appropriate division ratio depends on
the following factors: power mode, decimation rate, and the base MCLK
available in the system. See the Clocking, Sampling Tree, and Power Scaling
section for more information on setting MCLK_DIV correctly.
MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for eco mode.
MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.
MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.
Reset
0x0
Access
RW
0x0
RW
0x0
RW
GENERAL DEVICE CONFIGURATION REGISTER
Address: 0x05, Reset: 0x08, Name: General Configuration
Table 69. Bit Descriptions for General Configuration
Bits
5
Bit Name
RETIME_EN
Settings
0
1
4
3
[1:0]
VCM_PD
Reserved
VCM_VSEL
0
1
1
00
01
10
11
Description
SYNC_OUTsignal retime enable bit.
Disabled: normal timing of SYNC_OUT.
Enabled: SYNC_OUT signal derived from alternate MCLK edge.
VCM buffer power-down.
Enabled: VCM buffer normal mode.
Powered down: VCM buffer powered down.
Not a user option. This bit must be set to 1.
VCM voltage. These bits select the output voltage of the VCM pin. This voltage is
derived from the AVDD1 supply and can be output as half of that AVDD1 voltage, or
other fixed voltages, with respect to AVSS. The VCM voltage output is associated
with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage
output is also disabled for maximum power savings. Channel 0 must be enabled
while VCM is being used externally to the AD7768-4.
(AVDD1 − AVSS)/2 V.
1.65 V.
2.5 V.
2.14 V.
Rev. A | Page 90 of 99
Reset
0x0
Access
RW
0x0
RW
0x1
0x0
RW
RW
Data Sheet
AD7768/AD7768-4
DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER
Address: 0x06, Reset: 0x80, Name: Data Control
Table 70. Bit Descriptions for Data Control
Bits
7
Bit Name
SPI_SYNC
Settings
0
1
4
SINGLE_SHOT_EN
0
1
[1:0]
SPI_RESET
00
01
10
11
Description
Software synchronization of the AD7768-4. This command has the same
effect as sending a signal pulse to the START pin. To operate the SPI_SYNC,
the user must write to this bit two separate times. First, write a zero,
putting SPI_SYNC low, and then write a 1 to set SPI_SYNC logic high
again. The SPI_SYNC command is recognized after the last rising edge of
SCLK in the SPI instruction where the SPI_SYNC bit is changed from low to
high. The SPI_SYNC command is then output synchronous to the AD7768-4
MCLK on the SYNC_OUT pin. The user must connect the SYNC_OUT signal
to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be routed to
the SYNC_IN pins of other AD7768-4 devices, allowing larger channel
count simultaneous sampling systems. As per any synchronization pulse
seen by the SYNC_IN pin, the digital filters of the AD7768-4 are reset. The
full settling time of the filters must elapse before data is output on the
data interface. In a daisy-chained system of AD7768-4 devices, two
successive synchronization pulses must be applied to guarantee that all
ADCs are synchronized. Two synchronization pulses are also required in a
system of more than one AD7768-4 device sharing a single MCLK signal,
where the DRDY pin of only one device is used to detect new data.
Change to SPI_SYNC low.
Change to SPI_SYNC high.
One-shot mode. Enables one-shot mode. In one-shot mode, the AD7768-4
output a conversion result in response to a SYNC_IN rising edge.
Disabled.
Enabled.
Soft reset. These bits allow a full device reset over the SPI port. Two
successive commands must be received in the correct order to generate a
reset: first, write 0x03 to the soft reset register, and then write 0x02 to the
soft reset register. This sequence causes the digital core to reset and all
registers return to their default values. Following a soft reset, if the SPI
master sends a command to the AD7768-4, the devices respond on the
next frame to that command with an output of 0x0E00.
No effect.
No effect.
Second reset command.
First reset command.
Reset
0x1
Access
RW
0x0
RW
0x0
RW
Reset
0x0
Access
RW
INTERFACE CONFIGURATION REGISTER
Address: 0x07, Reset: 0x0, Name: Interface Configuration
Table 71. Bit Descriptions for Interface Configuration
Bits
[3:2]
Bit Name
CRC_SELECT
Settings
00
01
10
11
Description
CRC select. These bits allow the user to implement a CRC on the data
interface. When selected, the CRC replaces the header every fourth or 16th
output sample depending on the CRC option chosen. There are two
options for the CRC; both use the same polynomial: x8 + x2 + x + 1. The
options offer the user the ability to reduce the duty cycle of the CRC
calculation by performing it less often: in the case of having it every 16th
sample or more often in the case of every fourth conversion. The CRC is
calculated on a per channel basis and it includes conversion data only.
No CRC. Status bits with every conversion.
Replace the header with CRC message every 4 samples.
Replace the header with CRC message every 16 samples.
Replace the header with CRC message every 16 samples.
Rev. A | Page 91 of 99
AD7768/AD7768-4
Bits
[1:0]
Bit Name
DCLK_DIV
Data Sheet
Settings
00
01
10
11
Description
DCLK divider. These bits control division of the DCLK clock used to clock
out conversion data on the DOUTx pins. The DCLK signal is derived from
the MCLK applied to the AD7768-4. The DCLK divide mode allows the user
to optimize the DCLK output to fit the application. Optimizing the DCLK
per application depends on the requirements of the user. When the
AD7768-4 are using the highest capacity output on the fewest DOUTx
pins, for example, running in decimate by 32 using the DOUT0 and
DOUT1 pins, the DCLK must equal the MCLK; thus, in this case, choosing
the no division setting is the only way the user can output all the data
within the conversion period. There are other cases, however, when the
ADC may be running in fast mode with high decimation rates, or in
median or eco mode where the DCLK does not need to run at the same
speed as MCLK. In these cases, the DCLK divide allows the user to reduce
the clock speed and makes routing and isolating such signals easier.
Divide by 8.
Divide by 4.
Divide by 2.
No division.
Reset
0x0
Access
RW
Reset
0x0
Access
RW
Reset
0x0
Access
R
0x0
R
DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER
Address: 0x08, Reset: 0x0, Name: BIST Control
Table 72. Bit Descriptions for BIST Control
Bits
0
Bit Name
RAM_BIST_START
Settings
0
1
Description
RAM BIST. Filter RAM BIST is a built in self test of the RAM storage of the
coefficients used by the digital filter. Normal ADC conversion is disrupted
when this test is run. A synchronization pulse is required after this test is
complete to resume normal ADC operation. The test can be run at
intervals depending on user preference. The status and result of the RAM
BIST is available in the device status register; see the RAM_BIST_PASS and
RAM_BIST_RUNNING bits in Table 73.
Off.
Begin RAM BIST.
STATUS REGISTER
Address: 0x09, Reset: 0x0, Name: Device Status
Table 73. Bit Descriptions for Device Status
Bits
3
Bit Name
CHIP_ERROR
Settings
0
1
2
NO_CLOCK_ERROR
0
1
Description
Chip error. Chip error is a global error flag that is output within the
status byte of each ADC conversion output. The following bits lead to
the chip error bit being set to logic high: CRC check on internally hard
coded settings after power-up does not pass; XOR check on the memory
map does not pass (this check runs continuously in the background);
and clock error is detected on power-up.
No error present.
Error has occurred.
External clock check. This bit indicates whether the externally applied
MCLK is detected correctly. If the MCLK is not applied correctly to the
ADC at power-up, this bit is set and the DCLK frequency is approximately
16 MHz. If this bit is set, the chip error bit is set to logic high in the
status bits of the data output headers, and the conversion results are
output as all zeros regardless of the analog input voltages applied to
the ADC channels.
MCLK detected.
No MCLK detected.
Rev. A | Page 92 of 99
Data Sheet
Bits
1
AD7768/AD7768-4
Bit Name
RAM_BIST_PASS
Settings
0
1
0
RAM_BIST_RUNNING
0
1
Description
BIST pass/fail. RAM BIST result status. This bit indicates the result of the
most recent RAM BIST. The result is latched to this register and is only
cleared by a device reset.
BIST failed or not run.
BIST passed.
BIST status. Reading back the value of this bit allows the user to poll
when the BIST test has finished.
BIST not running.
BIST running.
Reset
0x0
Access
R
0x0
R
REVISION IDENTIFICATION REGISTER
Address: 0x0A, Reset: 0x06, Name: Revision ID
Table 74. Bit Descriptions for Revision ID
Bits
[7:0]
Bit Name
REVISION_ID
Description
ASIC revision. 8-bit ID for revision details.
Reset
0x06
Access
R
GPIO CONTROL REGISTER
Address: 0x0E, Reset: 0x00, Name: GPIO Control
Table 75. Bit Descriptions for GPIO Control
Bits
7
Bit Name
UGPIO_ENABLE
Setting
0
1
4
GPIOE4_FILTER
0
1
3
GPIOE3_MODE3
0
1
2
GPIOE2_MODE2
0
1
1
GPIOE1_MODE1
0
1
0
GPIO0_MODE0
0
1
Description
User GPIO enable. The GPIOx pins are dual-purpose and can be operated only
when the device is in SPI control mode. By default, when the AD7768-4 are
powered up in SPI control mode, the GPIOx pins are disabled. This bit is a universal
enable/ disable for all GPIOx input/outputs. The direction of each generalpurpose pin is determined by Bits[4:0] of this register.
GPIO Disabled.
GPIO Enabled.
GPIO4 Direction. This bit assigns the direction of GPIO4 as either an input or an
output. For SPI control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin.
Input.
Output.
GPIO3 Direction. This bit assigns the direction of GPIO3 as either an input or
an output. For SPI control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin.
Input.
Output.
GPIO2 Direction. This bit assigns the direction of GPIO2 as either an input or an
output. For SPI control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin.
Input.
Output.
GPIO1 Direction. This bit assigns the direction of GPIO1 as either an input or an
output. For SPI control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin.
Input.
Output.
GPIO0 Direction. This bit assigns the direction of GPIO0 as either an input or
an output. For SPI control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin.
Input.
Output.
Rev. A | Page 93 of 99
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
AD7768/AD7768-4
Data Sheet
GPIO WRITE DATA REGISTER
Address: 0x0F, Reset: 0x00, Name: GPIO Write Data
This register writes the values to be set on each of the general-purpose pins when selected as general-purpose outputs. Each bit, from
Bits[4:0], maps directly to the GPIOx pins.
Table 76. Bit Descriptions for GPIO Write Data
Bits
4
3
2
1
0
Bit Name
GPIO4_WRITE
GPIO3_WRITE
GPIO2_WRITE
GPIO1_WRITE
GPIO0_WRITE
Description
GPIO4/FILTER
GPIO3/MODE3
GPIO2/MODE2
GPIO1/MODE1
GPIO0/MODE0
Reset
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
GPIO READ DATA REGISTER
Address: 0x10, Reset: 0x00, Name: GPIO Read Data
This register reads back the value of the logic input level at the general-purpose pins when selected to operate as general-purpose inputs.
Each bit, from Bits[4:0], maps directly to the GPIO0 to GPIO4 pins.
Table 77. Bit Descriptions for GPIO Read Data
Bits
4
3
2
1
0
Bit Name
GPIO4_READ
GPIO3_READ
GPIO2_READ
GPIO1_READ
GPIO0_READ
Description
GPIO4/FILTER
GPIO3/MODE3
GPIO2/MODE2
GPIO1/MODE1
GPIO0/MODE0
Reset
Access
0x0
0x0
0x0
0x0
0x00
R
R
R
R
R
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1
Address: 0x11, Reset: 0xFF, Name: Precharge Buffer 1
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 7 of this register, the user must write 0x01 to the register. This clears Bit 7 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.
Table 78. Bit Descriptions for Precharge Buffer 1
Bits
3
Bit Name
CH1_PREBUF_NEG_EN
2
CH1_PREBUF_POS_EN
1
CH0_PREBUF_NEG_EN
0
CH0_PREBUF_POS_EN
Settings
0
1
0
1
0
1
0
1
Rev. A | Page 94 of 99
Description
Off
On
Off
On
Off
On
Off
On
Reset
0x1
0x1
0x1
0x1
Data Sheet
AD7768/AD7768-4
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3
Address: 0x12, Reset: 0xFF, Name: Precharge Buffer 2
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 7 of this register, the user must write 0x01 to the register. This clears Bit 7 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.
Table 79. Bit Descriptions for Precharge Buffer 2
Bits
3
Bit Name
CH3_PREBUF_NEG_EN
2
CH3_PREBUF_POS_EN
1
CH2_PREBUF_NEG_EN
0
CH2_PREBUF_POS_EN
Settings
0
1
0
1
0
1
0
1
Description
Off
On
Off
On
Off
On
Off
On
Reset
0x1
0x1
0x1
0x1
POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x13, Reset: 0x00, Name: Positive Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference positive input to each of the ADCs from Channel 0 to Channel 3.
Table 80. Bit Descriptions for Positive Reference Precharge Buffer
Bits
5
Bit Name
CH3_REFP_BUF
4
CH2_REFP_BUF
1
CH1_REFP_BUF
0
CH0_REFP_BUF
Settings
0
1
0
1
0
1
0
1
Description
Off
On
Off
On
Off
On
Off
On
Reset
0x0
0x0
0x0
0x0
NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 3.
Table 81. Bit Descriptions for Negative Reference Precharge Buffer
Bits
5
Bit Name
CH3_REFN_BUF
4
CH2_REFN_BUF
1
CH1_REFN_BUF
0
CH0_REFN_BUF
Settings
0
1
0
1
0
1
0
1
Rev. A | Page 95 of 99
Description
Off
On
Off
On
Off
On
Off
On
Reset
0x0
0x0
0x0
0x0
AD7768/AD7768-4
Data Sheet
OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers are 24-bit, signed twos complement registers for channel
offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital
output by −4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by −133 LSBs. As offset adjustment
occurs before gain adjustment, the ratio of 4/3 changes linearly with gain adjustment via the CHx_GAIN_x registers. After a reset or power
cycle, the register values revert to the default factory setting.
Table 82. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
MSB
0x1E
0x21
0x2A
0x2D
Address
Mid
0x1F
0x22
0x2B
0x2E
LSB
0x20
0x23
0x2C
0x2F
Name
Channel 0 offset
Channel 1 offset
Channel 2 offset
Channel 3 offset
Description
Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total)
Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total)
MSB
0x00
0x00
0x00
0x00
Reset
Mid
0x00
0x00
0x00
0x00
LSB
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
GAIN REGISTERS
Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and
LSB. Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The
user may overwrite the gain register setting however, after a reset or power cycle, the gain register values revert to the hard coded
programmed factory setting.
Table 83. Per Channel 24-Bit Gain Registers, 3 8-Bit Registers for Each Channel, Split Up as MSB, MID, and LSB
MSB
0x36
0x39
0x42
0x45
Address
Mid
0x37
0x3A
0x43
0x46
LSB
0x38
0x3B
0x44
0x47
Name
Channel 0 gain
Channel 1 gain
Channel 2 gain
Channel 3 gain
Description
Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total)
Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total)
MSB
0xXX
0xXX
0xXX
0xXX
Reset
Mid
0xXX
0xXX
0xXX
0xXX
LSB
0xXX
0xXX
0xXX
0xXX
Access
RW
RW
RW
RW
SYNC PHASE OFFSET REGISTERS
The AD7768-4 have one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on
each of the channels relative to the synchronization edge received on the SYNC_IN pin. See the Sync Phase Offset Adjustment section for
details on the use of this function.
Table 84. Per Channel 8-Bit Sync Phase Offset Registers
Address
0x4E
0x4F
0x52
0x53
Name
Channel 0 sync offset
Channel 1 sync offset
Channel 2 sync offset
Channel 3 sync offset
Description
Channel 0 sync phase offset register
Channel 1 sync phase offset register
Channel 2 sync phase offset register
Channel 3 sync phase offset register
Reset
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
ADC DIAGNOSTIC RECEIVE SELECT REGISTER
Address: 0x56, Reset: 0x00, Name: Diagnostic Rx
The AD7768-4 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which
can be converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive (Rx) for each
channel and set each bit in this register to 1.
The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input
precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally.
Table 85. Bit Descriptions for Diagnostic Rx
Bits
5
Bit Name
CH3_RX
Settings
0
1
Description
Channel 3
Not in use
Receive
Reset
0x0
Rev. A | Page 96 of 99
Access
RW
Data Sheet
Bits
4
Bit Name
CH2_RX
AD7768/AD7768-4
Settings
0
1
1
CH1_RX
0
1
0
CH0_RX
0
1
Description
Channel 2
Not in use
Receive
Channel 1
Not in use
Receive
Channel 0
Not in use
Receive
Reset
0x0
Access
RW
0x0
RW
0x0
RW
ADC DIAGNOSTIC CONTROL REGISTER
Address: 0x57, Reset: 0x00, Name: Diagnostic Mux Control
The AD7768-4 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which
can be converted to verify the correct operation of the ADC channel. This register controls the voltage that is applied to each of the ADC
channels for the diagnostic. There are three input voltage options that the user can select. The voltage selected is mapped to the channels based
on which mode (Mode A or Mode B) they belong to, which is set according to the channel mode select register (Register 0x03).
Set Bits[7:0] to 1 in the ADC diagnostic receive select register, then select the voltage check desired for the channels on Mode A and the
channels on Mode B through Bits[2:0] and Bits[6:4], respectively.
Table 86. Bit Descriptions for Diagnostic Mux Control
Bits
[6:4]
Bit Name
GRPB_SEL
Settings
000
011
100
101
[2:0]
GRPA_SEL
000
011
100
101
Description
Mux B.
Off.
Positive full-scale ADC check. A voltage close to positive full scale is
applied internally to the ADC channel.
Negative full-scale ADC check. A voltage close to negative (or minus) full
scale is applied internally to the ADC channel.
Zero-scale ADC check. A voltage close to 0 V is applied internally to the
ADC channel.
Mux A.
Off.
Positive full-scale ADC check. A voltage close to positive full scale is
applied internally to the ADC channel.
Negative full-scale ADC check. A voltage close to negative (or minus) full
scale is applied internally to the ADC channel.
Zero-scale ADC check. A voltage close to 0 V is applied internally to the
ADC channel.
Reset
0x0
Access
RW
0x0
RW
Reset
0x0
Access
RW
0x2
RW
MODULATOR DELAY CONTROL REGISTER
Address: 0x58, Reset: 0x02, Name: Modulator Delay Control
Table 87. Bit Descriptions for Modulator Delay Control
Bits
[3:2]
[1:0]
Bit Name
CLK_MOD_DEL_EN
Reserved
Settings
00
01
10
11
10
Description
Enable delayed modulator clock.
Disabled delayed clock for all channels.
Enable delayed clock for Channel 0 and Channel 1 only on the AD7768-4.
Enable delayed clock for Channel 2 and Channel 3 only on the AD7768-4.
Enable delayed clock for all channels.
Not a user option. Must be set to 0x2.
Rev. A | Page 97 of 99
AD7768/AD7768-4
Data Sheet
CHOPPING CONTROL REGISTER
Address: 0x59, Reset: 0x0A, Name: Chop Control
Table 88. Bit Descriptions for Chop Control
Bits
[3:2]
Bit Name
GRPA_CHOP
Settings
01
10
[1:0]
GRPB_CHOP
01
10
Description
Group A chopping
Chop at fMOD/8
Chop at fMOD/32
Group B chopping
Chop at fMOD/8
Chop at fMOD/32
Rev. A | Page 98 of 99
Reset
0x2
Access
RW
0x2
RW
Data Sheet
AD7768/AD7768-4
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
VIEW A
16
33
32
17
VIEW A
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 110. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7768BSTZ
AD7768BSTZ-RL7
AD7768BSTZ-RL
AD7768-4BSTZ
AD7768-4BSTZ-RL7
AD7768-4BSTZ-RL
EVAL-AD7768FMCZ
EVAL-AD7768-4FMCZ
EVAL-SDP-CH1Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
AD7768-4 Evaluation Board
Controller Board
Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14001-0-3/16(A)
Rev. A | Page 99 of 99
Package Option
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
ST-64-2
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