TI1 BQ2012SN-D107G4 Gas gauge ic with slow-charge control Datasheet

Not Recommended For New Designs
bq2012
Gas Gauge IC With
Slow-Charge Control
Features
General Description
means of controlling charge based
on the battery's charge state.
➤ Conservative and repeatable
measurement of available charge
in rechargeable batteries
The bq2012 Gas Gauge IC is intended for battery-pack or in-system
installation to maintain an accurate
record of available battery charge.
The IC monitors a voltage drop
across a sense resistor connected in
series between the negative battery
terminal and ground to determine
charge and discharge activity of the
battery.
Nominal available charge may be directly indicated using a five- or sixsegment LED display. These segments are used to graphically indicate nominal available charge.
➤ Charge control output
➤ Designed for battery pack integration
-
120µA typical standby current
(self-discharge estimation mode)
-
Small size enables implementations in as little as 1 2
square inch of PCB
➤ Integrate within a system or as a
stand-alone device
-
Display capacity via singlewire serial communication
port or direct drive of LEDs
➤ Measurements compensated for
current and temperature
Self-discharge of NiMH and NiCd
batteries is estimated based on an
internal timer and temperature sensor. Compensations for battery temperature and rate of charge or discharge are applied to the charge,
discharge, and self-discharge calculations to provide available charge
information across a wide range of
operating conditions. Battery capacity is automatically recalibrated, or
“learned,” in the course of a discharge cycle from full to empty.
➤ 16-pin narrow SOIC
The bq2012 includes a charge control output that, when used with
other full-charge safety termination
methods, can provide a cost-effective
Pin Connections
Pin Names
➤ Self-discharge compensation using internal temperature sensor
LCOM
LCOM
1
16
VCC
SEG1/PROG1
2
15
REF
SEG2/PROG2
3
14
CHG
SEG3/PROG3
4
13
DQ
SEG4/PROG4
5
12
EMPTY
SEG5/PROG5
6
11
SB
SEG6/PROG6
7
10
DISP
VSS
8
9
LED common output
SEG1/PROG1 LED segment 1/
program 1 input
SEG2/PROG2 LED segment 2/
program 2 input
SEG3/PROG3 LED segment 3/
program 3 input
SEG4/PROG4 LED segment 4/
program 4 input
The bq2012 supports a simple
single-line bidirectional serial link to
an external processor (common
ground). The bq2012 outputs battery
information in response to external
commands over the serial link.
Internal registers include available
charge, temperature, capacity, battery
ID, battery status, and programming
pin settings. To support subassembly
testing, the outputs may also be controlled. The external processor may
also overwrite some of the bq2012 gas
gauge data registers.
The bq2012 may operate directly
from three or four cells. With the
REF output and an external transistor, a simple, inexpensive regulator
can be built to provide VCC across a
greater number of cells.
REF
Voltage reference output
CHG
Charge control output
DQ
Serial communications
input/output
EMPTY
Empty battery indicator
output
SB
Battery sense input
DISP
Display control input
SR
Sense resistor input
VCC
3.0–6.5V
VSS
System ground
SR
16-Pin Narrow SOIC
PN201201.eps
SEG5/PROG5 LED segment 5/
program 5 input
SEG6/PROG6 LED segment 6/
program 6 input
9/96 B
1
Not Recommended For New Designs
bq2012
SR
Pin Descriptions
LCOM
The voltage drop (VSR) across the sense resistor RS is monitored and integrated over
time to interpret charge and discharge activity. The SR input is tied to the high side of
the sense resistor. VSR < VSS indicates discharge, and VSR > VSS indicates charge. The
effective voltage drop (VSRO) as seen by the
bq2012 is VSR + VOS (see Table 5).
LED common output
Open-drain output switches VCC to source
current for the LEDs. The switch is off during initialization to allow reading of the soft
pull-up or pull-down program resistors.
LCOM is also high impedance when the display is off.
SEG1–
SEG6
DISP
LED display segment outputs (dual function with PROG1–PROG6)
Programmed full count selection inputs
(dual function with SEG1–SEG2)
These three-level input pins define the programmed full count (PFC) thresholds described in Table 2.
PROG3–
PROG4
SB
Gas gauge rate selection inputs (dual
function with SEG3–SEG4)
Self-discharge rate selection (dual function with SEG5)
EMPTY
Display mode selection (dual function
with SEG6)
DQ
This three-level pin defines the display operation shown in Table 1.
CHG
Battery empty output
This open-drain output becomes highimpedance on detection of a valid end-ofdischarge voltage (VEDVF) and is low following
the next application of a valid charge.
This three-level input pin defines the selfdischarge compensation rate shown in Table 1.
PROG6
Secondary battery input
This input monitors the single-cell voltage
potential through a high-impedance resistive divider network for end-of-discharge
voltage (EDV) thresholds, maximum charge
voltage (MCV), and battery removed.
These three-level input pins define the scale
factor described in Table 2.
PROG5
Display control input
DISP high disables the LED display. DISP
tied to VCC allows PROGX to connect directly
to VCC or VSS instead of through a pull-up or
pull-down resistor. DISP floating allows the
LED display to be active during a valid
charge or during discharge if the NAC register is updated at a rate equivalent to VSRO ≤
-4mV. DISP low activates the display. See
Table 1.
Each output may activate an LED to sink
the current sourced from LCOM.
PROG1–
PROG2
Sense resistor input
Serial I/O pin
This is an open-drain bidirectional pin.
REF
Charge control output
Voltage reference output for regulator
REF provides a voltage reference output for
an optional micro-regulator.
This open-drain output becomes active low
when charging is allowed. Valid charging
conditions are described in the Charge Control section.
2
VCC
Supply voltage input
VSS
Ground
Not Recommended For New Designs
bq2012
Figure 1 shows a typical battery pack application of the
bq2012 using the LED display capability as a chargestate indicator. The bq2012 can be configured to display
capacity in either a relative or an absolute display mode.
The relative display mode uses the last measured discharge capacity of the battery as the battery “full” reference. The absolute display mode uses the programmed
full count (PFC) as the full reference, forcing each segment of the display to represent a fixed amount of
charge. A push-button display feature is available for
momentarily enabling the LED display.
Functional Description
General Operation
The bq2012 determines battery capacity by monitoring
the amount of charge input to or removed from a rechargeable battery. The bq2012 measures discharge and
charge currents, estimates self-discharge, monitors the
battery for low-battery voltage thresholds, and compensates for temperature and charge/discharge rates. The
charge measurement is made by monitoring the voltage
across a small-value series sense resistor between the
negative battery terminal and ground. The available
battery charge is determined by monitoring this voltage
over time and correcting the measurement for the environmental and operating conditions.
The bq2012 monitors the charge and discharge currents
as a voltage across a sense resistor (see RS in Figure 1).
A filter between the negative battery terminal and the
SR pin may be required if the rate of change of the battery current is too great.
R1
1M
bq2012
Gas Gauge IC
Q1
ZVNL110A
REF
LCOM
SEG1/PROG1
VCC
C1
0.1 F
SB
VCC
SEG2/PROG2
SEG3/PROG3
DISP
SEG4/PROG4
SR
VCC
RB1
RB2
SEG5/PROG5
SEG6/PROG6
RS
VSS
EMPTY
CHG
DQ
Charger
Indicates optional.
Directly connect to VCC across 3 or 4 cells (3 to 4.8V nominal,should not
exceed 6.5V) with a resistor and a Zener diode to limit voltage during charge.
Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells.
The value of R1 depends on the number of cells.
Load
Programming resistors (6 max.) and ESD-protection diodes are not shown.
R-C on SR may be required (application-specific), where the R
should not exceed 100k.
FG201201.eps
Figure 1. Battery Pack Application Diagram—LED Display
3
Not Recommended For New Designs
bq2012
available over the serial port in 10°C increments as
shown below:
Voltage Thresholds
In conjunction with monitoring VSR for charge/discharge
currents, the bq2012 monitors the single-cell battery potential through the SB pin. The single-cell voltage potential is determined through a resistor/divider network
per the following equation:
TMPGG (hex)
Temperature Range
0x
< -30°C
RB1
= N −1
RB2
1x
-30°C to -20°C
2x
-20°C to -10°C
3x
-10°C to 0°C
4x
0°C to 10°C
5x
10°C to 20°C
6x
20°C to 30°C
7x
30°C to 40°C
8x
40°C to 50°C
9x
50°C to 60°C
Ax
60°C to 70°C
Bx
70°C to 80°C
Cx
> 80°C
where N is the number of cells, RB1 is connected to the
positive battery terminal, and RB2 is connected to the
negative battery terminal. The single-cell battery voltage is monitored for the end-of-discharge voltage (EDV)
and for maximum cell voltage (MCV). EDV threshold
levels are used to determine when the battery has
reached an “empty” state, and the MCV threshold is used
for fault detection during charging.
Two EDV thresholds for the bq2012 are fixed at:
EDV1 (early warning) = 1.05V
EDVF (empty) = 0.95V
If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of VSB, until the next valid charge.
During discharge and charge, the bq2012 monitors VSR
for various thresholds. These thresholds are used to
compensate the charge and discharge rates. Refer to the
count compensation section for details. EDV monitoring
is disabled if VSR ≤ -250mV typical and resumes 1 2 second after VSR > -250mV.
Layout Considerations
EMPTY Output
The bq2012 measures the voltage differential between
the SR and VSS pins. VOS (the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:
The EMPTY output switches to high impedance when
VSB < VEDF and remains latched until a valid charge occurs. The bq2012 also monitors VSB relative to VMCV,
2.25V. VSB falling from above VMCV resets the device.
Reset
The bq2012 recognizes a valid battery whenever VSB is
greater than 0.1V typical. VSB rising from below 0.25V
or falling from above 2.25V resets the device. Reset can
also be accomplished with a command over the serial
port as described in the Register Reset section.
Temperature
The bq2012 internally determines the temperature in
10°C steps centered from -35°C to +85°C. The temperature steps are used to adapt charge and discharge rate
compensations, self-discharge counting, and available
charge display translation. The temperature range is
4
■
The capacitors (SB and VCC) should be placed as
close as possible to the SB and VCC pins, respectively,
and their paths to VSS should be as short as possible.
A high-quality ceramic capacitor of 0.1µf is
recommended for VCC.
■
The sense resistor (RS) should be as close as possible
to the bq2012.
■
The R-C on the SR pin should be located as close as
possible to the SR pin. The maximum R should not
exceed 100K.
Not Recommended For New Designs
bq2012
1.
Gas Gauge Operation
Last Measured Discharge (LMD) or learned
battery capacity:
The operational overview diagram in Figure 2 illustrates
the operation of the bq2012. The bq2012 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge currents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.
LMD is the last measured discharge capacity of the
battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV1. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register.
The LMD also serves as the 100% reference threshold used by the relative display mode.
The main counter, Nominal Available Charge (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).
2.
Programmed Full Count (PFC) or initial battery capacity:
The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2012 adapts its capacity determination based on the
actual conditions of discharge.
The initial LMD and gas gauge rate values are programmed by using PROG1–PROG4. The PFC also
provides the 100% reference for the absolute display mode. The bq2012 is configured for a given application by selecting a PFC value from Table 2.
The correct PFC may be determined by multiplying
the rated battery capacity in mAh by the sense resistor value:
The battery’s initial capacity is equal to the programmed
full count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold
during subsequent charges. This approach allows the
gas gauge to be charger-independent and compatible
with any type of charge regime.
Inputs
PFC (mVh)
Selecting a PFC slightly less than the rated capacity for absolute mode provides capacity above the
full reference for much of the battery’s life.
Charge
Current
Discharge
Current
Self-Discharge
Timer
Rate and
Temperature
Compensation
Rate and
Temperature
Compensation
Temperature
Compensation
+
Main Counters
and Capacity
Reference (LMD)
Battery capacity (mAh) * sense resistor (Ω) =
+
-
Nominal
Available
Charge
(NAC)
<
Last
Measured
Discharged
(LMD)
Temperature Step,
Other Data
Temperature
Translation
Outputs
Chip-Controlled
Available Charge
LED Display
Serial
Port
Figure 2. Operational Overview
5
+
Discharge
Count
Qualified Register
(DCR)
Transfer
FG201002.eps
Not Recommended For New Designs
bq2012
Select:
Example: Selecting a PFC Value
PFC = 33792 counts or 211mVh
PROG1 = float
PROG2 = float
PROG3 = float
PROG4 = low
PROG5 = float
PROG6 = float
Given:
Sense resistor = 0.1Ω
Number of cells = 6
Capacity = 2200mAh, NiCd battery
Current range = 50mA to 2A
Absolute display mode
Serial port only
Self-discharge = C 64
Voltage drop over sense resistor = 5mV to 200mV
The initial full battery capacity is 211mVh
(2110mAh) until the bq2012 “learns” a new capacity with a qualified discharge from full to EDV1.
Therefore:
2200mAh * 0.1Ω = 220mVh
Table 1. bq2012 Programming
Pin
Connection
PROG5
Self-Discharge Rate
PROG6
Display Mode
DISP
Display State
H
Self-discharge disabled
NAC = PFC on reset
LED disabled
64
Absolute
LED enabled on discharge when
VSRO < -4mV or during a valid charge
47
Relative
LED on
Z
NAC
L
NAC
Note:
PROG5 and PROG6 states are independent.
Table 2. bq2012 Programmed Full Count mVh Selections
PROGx
Programmed
Full
Count
(PFC)
PROG3 = H
PROG4 = L
PROG4 = Z
1
2
-
-
-
Scale =
1/80
Scale =
1/160
Scale =
1/320
Scale =
1/640
H
H
49152
614
307
154
H
Z
45056
563
282
H
L
40960
512
256
Z
H
36864
461
Z
Z
33792
422
Z
L
30720
384
L
H
27648
346
173
86.4
43.2
21.6
10.8
mVh
L
Z
25600
320
160
80.0
40.0
20.0
10.0
mVh
L
L
22528
282
141
70.4
35.2
17.6
8.8
mVh
90
45
22.5
11.25
5.56
2.8
mV
VSR is equivalent to 2
counts/sec. (nom.)
PROG3 = Z
PROG3 = L PROG3 = H PROG3 = Z
PROG3 = L
Units
Scale =
1/1280
Scale =
1/2560
mVh/
count
76.8
38.4
19.2
mVh
141
70.4
35.2
17.6
mVh
128
64.0
32.0
16.0
mVh
230
115
57.6
28.8
14.4
mVh
211
106
53.0
26.4
13.2
mVh
192
96.0
48.0
24.0
12.0
mVh
6
Not Recommended For New Designs
bq2012
3.
Nominal Available Charge (NAC):
Charge Control
NAC counts up during charge to a maximum
value of LMD and down during discharge and
self-discharge to 0. NAC is reset to 0 on initialization (PROG6 = Z or low) and on reaching EDV1. NAC
is set to PFC on initialization if PROG6 = high. To
prevent overstatement of charge during periods of
overcharge, NAC stops incrementing when NAC =
LMD.
4.
Charge control is provided by the CHG output. This
output is asserted continuously when:
NAC < 0.94 * LMD and
0.95V < VSB < 2.25V and
0°C < Temp < 50°C and
BRM = 0
This output is asserted at a 1 16 duty cycle (low for 0.5 sec
and high for 7.5 sec) when the above conditions are not
met and:
Discharge Count Register (DCR):
The DCR counts up during discharge independent
of NAC and could continue increasing after NAC
has decremented to 0. DCR stops counting when
EDV1 is reached. Prior to NAC = 0 (empty battery),
both discharge and self-discharge increment the
DCR. After NAC = 0, only discharge increments the
DCR. The DCR resets to 0 when NAC = LMD. The
DCR does not roll over but stops counting when it
reaches FFFFh.
NAC < LMD and
0.95V < VSB < 2.25V and
Temp < 50°C and
BRM = 0
This output is also asserted at a 1 16 duty cycle (low for 0.5 sec
and high for 7.5 sec) for a 2-hour top-off period after:
NAC = LMD and
Temp < 50°C and
0.95V < VSB < 2.25V and
BRM = 0
The DCR value becomes the new LMD value on the
first charge after a valid discharge to VEDV1 if:
No valid charge initiations (charges greater than
256 NAC counts; where VSRO > VSRQ) occurred during the period between NAC = LMD and EDV1 detected.
This output is inactive when:
NAC = LMD (after a 2-hour top-off period) or
Temp > 50°C or
VSB < 0.95V or
VSB > 2.25V or
BRM = 1
The self-discharge count is not more than 4096
counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).
The temperature is ≥ 0°C when the EDV1 level is
reached during discharge.
The top-off timer (2 hours) is reset to allow another topoff after the battery is discharged to 0.8 * LMD (PROG6
= L) or 0.8 * PFC (PROG6 = Z or H).
The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.
Caution: The charge control output (CHG) should
be used with other forms of charge termination
such as ∆T/∆t and -∆V.
Charge Counting
Charge activity is detected based on a positive voltage
on the VSR input. If charge activity is detected, the
bq2012 increments NAC at a rate proportional to VSRO
(VSR + VOS) and, if enabled, activates the LED display if
the rate is equivalent to VSRO > 4mV. Charge actions increment the NAC after compensation for charge rate
and temperature.
If charge terminates due to maximum temperature, the
battery temperature must fall typically 10°C below 50°C
before the charge output becomes active again.
Discharge Counting
All discharge counts where VSRO < VSRD cause the NAC
register to decrement and the DCR to increment. Exceeding the fast discharge threshold (FDQ) if the rate is
equivalent to VSRO < -4mV activates the display, if enabled. The display becomes inactive after VSRO rises
above -4mV. V SRD is a programmable threshold as
described in the Digital Magnitude Filter section. The
default value for VSRD is -300µV.
The bq2012 determines charge activity sustained at a
continuous rate equivalent to VSRO > VSRQ. A valid
charge equates to sustained charge activity greater than
256 NAC counts. Once a valid charge is detected, charge
counting continues until VSRO falls below VSRQ. VSRQ is
a programmable threshold as described in the Digital
Magnitude Filter section. The default value for VSRQ is
375µV.
7
Not Recommended For New Designs
bq2012
Where N = Number of 10°C steps below 10°C and
-150mV < V SR < 0.
Self-Discharge Estimation
The bq2012 continuously decrements NAC and increments
DCR for self-discharge based on time and temperature.
The self-discharge count rate is programmed to be a nominal 1 64 * NAC or 1 47 * NAC per day or disabled as selected
by PROG5. This is the rate for a battery whose temperature is between 20°–30°C. The NAC register cannot be
decremented below 0.
For example:
T > 10°C : Nominal compensation, N = 0
0°C < T < 10°C: N = 1 (i.e., 1.0 becomes 1.05)
-10°C < T < 0°C: N = 2 (i.e., 1.0 becomes 1.10)
-20°C < T < -10°C: N = 3 (i.e., 1.0 becomes 1.15)
Count Compensations
-20°C < T < -30°C: N = 4 (i.e., 1.0 becomes 1.20)
The bq2012 determines fast charge when the NAC updates at a rate of ≥2 counts/sec. Charge and discharge are
compensated for temperature and charge/discharge
rate before updating the NAC and/or DCR. Self-discharge estimation is compensated for temperature before updating the NAC or DCR.
Self-Discharge Compensation
The self-discharge compensation is programmed for a
nominal rate of 1 64 * NAC or 1 47 * NAC per day. This is
the rate for a battery within the 20–30°C temperature
range (TMPGG = 6x). This rate varies across 8 ranges
from <10°C to >70°C, doubling with each higher temperature step (10°C). See Table 3.
Charge Compensation
Two charge efficiency compensation factors are used for
trickle charge and fast charge. Fast charge is defined as
a rate of charge resulting in ≥ 2 NAC counts/sec (≥ 0.15C
to 0.32C depending on PFC selections; see Table 2). The
compensation defaults to the fast charge factor until the
actual charge rate is determined.
Table 3. Self-Discharge Compensation
Temperature
Step
Temperature adapts the charge rate compensation factors
over three ranges between nominal, warm, and hot temperatures. The compensation factors are shown below.
Charge
Temperature
Trickle Charge
Compensation
Fast Charge
Compensation
<30°C
0.80
0.95
30–40°C
0.75
0.90
> 40°C
0.65
0.80
Typical Rate
PROG5 = Z
< 10°C
NAC
10–20°C
NAC
20–30°C
NAC
30–40°C
NAC
40–50°C
NAC
50–60°C
NAC
PROG5 = L
NAC
256
188
NAC
128
NAC
64
NAC
32
NAC
16
NAC
8
94
47
23 .5
11 .8
5 .88
Digital Magnitude Filter
The bq2012 has a programmable digital filter to eliminate
charge and discharge counting below a set threshold. The default setting is -0.30mV for VSRD and +0.38mV for VSRQ. The
proper digital filter setting can be calculated using the following
equation. Table 4 shows typical digital filter settings.
Discharge Compensation
Corrections for the rate of discharge are made by adjusting
an internal discharge compensation factor. The discharge
factor is based on the dynamically measured VSR. The
compensation factors during discharge are:
VSRD (mV) = -45 / DMF
VSRQ (mV) = -1.25 * VSRD
Approximate
VSR Threshold
Discharge
Compensation
Factor
Efficiency
VSR > -150 mV
1.00
100%
VSR < -150 mV
1.05
95%
Table 4. Typical Digital Filter Settings
DMF
75
100
150 (default)
175
200
Temperature compensation during discharge also takes place.
At lower temperatures, the compensation factor increases by
0.05 for each 10°C temperature range below 10°C.
Compensation factor = 1.0 + (0.05 * N)
8
DMF
Hex.
4B
64
96
AF
C8
VSRD
(mV)
-0.60
-0.45
-0.30
-0.26
-0.23
VSRQ
(mV)
0.75
0.56
0.38
0.32
0.28
Not Recommended For New Designs
bq2012
The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using
either polled or interrupt processing. Data input from the
bq2012 may be sampled using the pulse-width capture
timers available on some microcontrollers.
Error Summary
Capacity Inaccurate
The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value includes the error between the programmed full capacity
and the actual capacity. This error is present until a
valid discharge occurs and LMD is updated (see DCR description). The other cause of LMD error is battery
wear-out. As the battery ages, the measured capacity
must be adjusted to account for changes in actual battery
capacity.
Communication is normally initiated by the host processor sending a BREAK command to the bq2012. A
BREAK is detected when the DQ pin is driven to a
logic-low state for a time, tB or greater. The DQ pin
should then be returned to its normal ready-high logic
state for a time, tBR. The bq2012 is now ready to receive
a command from the host processor.
A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description) and is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges.
The return-to-one data bit frame consists of three distinct sections. The first section is used to start the
transmission by either the host or the bq2012 taking the
DQ pin to a logic-low state for a period, tSTRH,B. The
next section is the actual data transmission, where the
data should be valid by a period, tDSU, after the negative
edge used to start communication. The data should be
held for a period, tDV, to allow the host or bq2012 to
sample the data bit.
Current-Sensing Error
Table 5 illustrates the current-sensing error as a function of VSR. A digital filter eliminates charge and discharge counts to the NAC register when VSRO (VSR +
VOS) is between VSRQ and VSRD.
The final section is used to stop the transmission by returning the DQ pin to a logic-high state by at least a period,
tSSU, after the negative edge used to start communication.
The final logic-high state should be held until a period, tSV, to
allow time to ensure that the bit transmission was stopped
properly. The timings for data and break communication are
given in the serial communication timing specification and
illustration sections.
Communicating With the bq2012
The bq2012 includes a simple single-pin (DQ plus return) serial data interface. A host processor uses the interface to access various bq2012 registers. Battery characteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2012 should be pulled up by the host system, or may
be left floating if the serial interface is not used.
Communication with the bq2012 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication sequence to read the bq2012 NAC register.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2012.
The command directs the bq2012 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.
bq2012 Registers
The bq2012 command and status registers are listed in
Table 6 and described in the following sections.
Table 5. Current-Sensing Error as a Function of VSR
Symbol
Parameter
Typical
Maximum
Units
Notes
INL
Integrated non-linearity
error
±2
±4
%
Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.
INR
Integrated nonrepeatability error
±1
±2
%
Measurement repeatability given
similar operating conditions.
9
Not Recommended For New Designs
bq2012
Table 6. bq2012 Command and Status Registers
Control Field
Symbol
Register
Name
Loc.
(hex)
Read/
Write
7(MSB)
6
5
4
3
2
1
0(LSB)
CMDR
Command
register
00h
Write
W/R
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FLGS1
Primary
status flags
register
01h
Read
CHGS
BRP
BRM
CI
VDQ
CHG
EDV1
EDVF
02h
Read
TMP3
TMP2
TMP1
TMP0
GG3
GG2
GG1
GG0
Temperature
TMPGG and gas gauge
register
NACH
Nominal
available
charge high
byte register
03h
R/W
NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
NACL
Nominal
available
charge low
byte register
17h
Read
NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
BATID
Battery
identification
register
04h
R/W
BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
LMD
Last measured discharge register
05h
R/W
LMD7
LMD6
LMD5
LMD4
LMD3
LMD2
LMD1
LMD0
FLGS2
Secondary
status flags
register
06h
Read
CR
DR2
DR1
DR0
n/u
n/u
n/u
OVLD
PPD
Program pin
pull-down
register
07h
Read
n/u
n/u
PPD6
PPD5
PPD4
PPD3
PPD2
PPD1
PPU
Program pin
pull-up register
08h
Read
n/u
n/u
PPU6
PPU5
PPU4
PPU3
PPU2
PPU1
CPI
Capacity
inaccurate
count register
09h
Read
CPI7
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
CPI0
DMF
Digital magnitude filter
register
0ah
R/W
DMF7
DMF6
DMF5
DMF4
DMF3
DMF2
DMF1
DMF0
RST
Reset register
39h
Write
RST
0
0
0
0
0
0
0
Note:
n/u = not used
10
Not Recommended For New Designs
bq2012
Written by Host to bq2012
CMDR = 03h
LSB
MSB
Break 1 1 0 0 0 0 0 0
Received by Host to bq2012
NAC = 65h
LSB
MSB
1 0 1 0 011 0
DQ
TD201201.eps
Figure 3. Typical Communication With the bq2012
The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when VSRO > VSRQ. A VSRO of less than VSRQ or
discharge activity clears CHGS.
Command Register (CMDR)
The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2012.
The CMDR register contains two fields:
■
W/R bit
■
Command address
The CHGS values are:
FLGS1 Bits
The W/R bit of the command register is used to select
whether the received command is for a read or a write
function.
7
6
5
4
3
2
1
0
CHGS
-
-
-
-
-
-
-
Where CHGS is:
The W/R values are:
0
Either discharge activity detected or VSRO <
VSRQ
1
VSRO > VSRQ
CMDR Bits
7
6
5
4
3
2
1
0
W/R
-
-
-
-
-
-
-
The battery replaced flag (BRP) is asserted whenever
the potential on the SB pin (relative to VSS), VSB, falls
from above the maximum cell voltage, MCV (2.25V), or
rises above 0.1V. The BRP flag is also set when the
bq2012 is reset (see the RST register description). BRP
is reset when either a valid charge action increments
NAC to be equal to LMD, or a valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies
that the device has been reset.
Where W/R is:
0
The bq2012 outputs the requested register
contents specified by the address portion of
CMDR.
1
The following eight bits should be written
to the register specified by the address portion of CMDR.
The BRP values are:
The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.
FLGS1 Bits
CMDR Bits
7
-
6
5
AD6 AD5
4
AD4
3
AD3
2
AD2
1
0
AD1
AD0
(LSB)
7
6
5
4
3
2
1
0
-
BRP
-
-
-
-
-
-
Where BRP is:
Primary Status Flags Register (FLGS1)
The read-only FLGS1 register (address=01h) contains
the primary bq2012 flags.
11
0
Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted
1
VSB dropping from above MCV, VSB rising
from below 0.1V, or a serial port initiated
reset has occurred
Not Recommended For New Designs
bq2012
Where VDQ is:
The battery removed flag (BRM) is asserted whenever
the potential on the SB pin (relative to VSS) rises above
MCV or falls below 0.1V. The BRM flag is asserted until
the condition causing BRM is removed.
The BRM values are:
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
BRM
-
-
-
-
-
0
SDCR ≥ 4096, subsequent valid charge action detected, or EDV1 is asserted with the
temperature less than 0°C
1
On first discharge after NAC = LMD
The charge control flag, CHG, is asserted whenever
the CHG pin is asserted (see the charge control section
on page 7 for a description of the CHG pin function).
The CHG values are:
Where BRM is:
0
0.1V < VSB < 2.25V
1
0.1 V > VSB or VSB > 2.25V
7
-
The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2012 is reset. The flag is cleared
after an LMD update.
FLGS1 Bits
6
5
4
3
2
1
0
-
-
-
CI
-
-
-
-
1
FLGS1 Bits
4
3
2
CHG
1
-
0
-
0
When the CHG pin is asserted active low,
signifying that the bq2012 is in a state to
allow charge activity.
1
When the CHG pin is high-impedance, signifying that no charge activity should take
place.
The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG1, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has
been detected.
Where CI is:
0
5
-
Where CHG is:
The CI values are:
7
6
-
When LMD is updated with a valid full discharge
The EDV1 values are:
After the 64th valid charge action with no
LMD updates
7
-
The valid discharge flag (VDQ) is asserted when the
bq2012 is discharged from NAC = LMD. The flag remains set until either LMD is updated or one of three
actions that can clear VDQ occurs:
■
The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.
■
A valid charge action sustained at VSRO > VSRQ for at
least 256 NAC counts.
■
The EDV1 flag was set at a temperature below 0°C
5
4
3
2
1
0
-
-
-
-
VDQ
-
-
-
FLGS1 Bits
4
3
-
2
-
1
EDV1
0
-
0
Valid charge action detected, VSB ≥ 1.05V
1
VSB < 1.05V providing that OVLD=0 (see
FLGS2 register description)
The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EMPTY pin is also forced to a high-impedance state on
assertion of EDV1. The host system may pull EMPTY
high, which may be used to disable circuitry to prevent
deep-discharge of the battery.
FLGS1 Bits
6
5
-
Where EDV1 is:
The VDQ values are:
7
6
-
12
Not Recommended For New Designs
bq2012
The EDVF values are:
Table 7. Temperature Register Translation
FLGS1 Bits
7
6
5
4
3
2
1
0
TMP3
TMP2
TMP1
TMP0
-
-
-
-
-
-
-
EDVF
0
0
0
0
T < -30°C
0
0
0
1
-30°C < T < -20°C
Where EDVF is:
Temperature
0
0
1
0
-20°C < T < -10°C
0
Valid charge action detected, VSB ≥ 0.95V
0
0
1
1
-10°C < T < 0°C
1
VSB < 0.95V providing that OVLD=0 (see
FLGS2 register description)
0
1
0
0
0°C < T < 10°C
0
1
0
1
10°C < T < 20°C
Temperature and Gas Gauge Register
(TMPGG)
0
1
1
0
20°C < T < 30°C
0
1
1
1
30°C < T < 40°C
1
0
0
0
40°C < T < 50°C
1
0
0
1
50°C < T < 60°C
1
0
1
0
60°C < T < 70°C
1
0
1
1
70°C < T < 80°C
1
1
0
0
T > 80°C
The read-only TMPGG register (address=02h) contains
two data fields. The first field contains the battery temperature. The second field contains the available charge
from the battery.
TMPGG Temperature Bits
7
6
5
TMP3 TMP2
4
TMP1 TMP0
3
2
1
-
-
-
0
The adjustment between > 0°C and -20°C < T < 0°C has
a 10°C hysteresis.
The bq2012 contains an internal temperature sensor.
The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient.
Nominal Available Charge Registers
(NACH/NACL)
The read/write NACH high-byte register (address=03h)
and the read-only NACL low-byte register (address=17h)
are the main gas gauging register for the bq2012. The
NAC registers are incremented during charge actions and
decremented during discharge and self-discharge actions.
The correction factors for charge/discharge efficiency are
applied automatically to NAC.
The temperature register contents may be translated as
shown in Table 7.
The bq2012 calculates the available charge as a function
of NAC, temperature, and a full reference, either LMD
or PFC. The results of the calculation are available via
the display port or the gas gauge field of the TMPGG
register. The register is used to give available capacity
in 1 16 increments from 0 to 15 16.
On reset, if PROG6 = Z or low, NACH and NACL are
cleared to 0; if PROG6 = high, NACH = PFC and NACL
= 0. When the bq2012 detects a valid EDV1, NACH and
NACL are reset to 0. Writing to the NAC registers affects
the available charge counts and, therefore, affects the
bq2012 gas gauge operation. Do not write the NAC registers to a value greater than LMD.
TMPGG Gas Gauge Bits
7
6
5
4
3
2
1
0
-
-
-
-
GG3
GG2
GG1
GG0
Battery Identification Register (BATID)
The gas gauge display and the gas gauge portion of the
TMPGG register are adjusted for cold temperature dependencies. A piece-wise correction is performed as follows:
The read/write BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as
VCC is greater than 2V. The contents of BATID have no
effect on the operation of the bq2012. There is no default setting for this register.
Temperature
Available Capacity Calculation
> 0°C
NAC / “Full Reference”
-20°C < T < 0°C
0.75 * NAC / “Full Reference”
Last Measured Discharge Register (LMD)
< -20°C
0.5 * NAC / “Full Reference”
LMD is a read/write register (address=05h) that the
bq2012 uses as a measured full reference. The bq2012
adjusts LMD based on the measured discharge capacity
13
Not Recommended For New Designs
bq2012
of the battery from full to empty. In this way the
bq2012 updates the capacity of the battery. LMD is set
to PFC during a bq2012 reset.
DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to VSS. The rate at which
this measurement is made varies with device activity.
Secondary Status Flags Register (FLGS2)
Program Pin Pull-Down Register (PPD)
The read-only FLGS2 register (address=06h) contains
the secondary bq2012 flags.
The read-only PPD register (address=07h) contains some of
the programming pin information for the bq2012. The segment drivers, SEG1–6, have a corresponding PPD register
location, PPD1–6. A given location is set if a pull-down resistor has been detected on its corresponding segment
driver. For example, if SEG1 and SEG4 have pull-down
resistors, the contents of PPD are xx001001.
The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.
The CR values are:
Program Pin Pull-Up Register (PPU)
The read-only PPU register (address=08h) contains the
rest of the programming pin information for the
bq2012. The segment drivers, SEG1–6, have a corresponding PPU register location, PPU1–6. A given location is set if a pull-up resistor has been detected on its corresponding segment driver. For example, if SEG3 and
SEG6 have pull-up resistors, the contents of PPU are
xx100100.
FLGS2 Bits
7
6
5
4
3
2
1
0
CR
-
-
-
-
-
-
-
Where CR is:
0
When charge rate falls below 2 counts/sec
1
When charge rate is above 2 counts/sec
PPD/PPU Bits
8
The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency factors are used. The time to change CR varies due to the
user-selectable count rates.
7
6
5
4
3
2
1
-
-
PPU6 PPU5 PPU4 PPU3 PPU2 PPU1
-
-
PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
The discharge rate flags, DR2–0, are bits 6–4.
7
-
Capacity Inaccurate Count Register (CPI)
FLGS2 Bits
5
4
3
DR1
DR0
-
6
DR2
2
-
1
-
The read-only CPI register (address=09h) is used to indicate the number of times a battery has been charged
without an LMD update. Because the capacity of a rechargeable battery varies with age and operating conditions, the bq2012 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.
0
They are used to determine the current discharge regime as follows:
DR2
DR1
DR0
VSR (V)
0
0
0
VSR > -150mV
0
0
1
VSR < -150mV
The CPI register is incremented every time a valid
charge is detected if NAC < 0.94 * LMD. When NAC ≥
0.94 * LMD, the CPI register increments on the first
valid charge; CPI does not increment again for a valid
charge until NAC is discharged below 0.94 * LMD. This
prevents continuous trickle charging from incrementing
CPI if self-discharge decrements NAC. The CPI register
increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI
register is reset whenever an update of the LMD register is performed, and the CI flag is also cleared.
The overload flag (OVLD) is asserted when a discharge
overload is detected, VSR < -250mV. OVLD remains asserted as long as the condition persists and is cleared
when VSR > -250mV. The overload condition is used to
stop sampling of the battery terminal characteristics for
end-of-discharge determination. Sampling is re-enabled
0.5 secs after the overload condition is removed.
FLGS2 Bits
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
OVLD
14
Not Recommended For New Designs
bq2012
In absolute mode, each segment represents a fixed
amount of charge, based on the initial PFC. In absolute
mode, each segment represents 20% of the PFC, with
the sixth segment representing “overfull” (charge above
the PFC). As the battery wears out over time, it is possible for the LMD to be below the initial PFC. In this
case, all of the LEDs may not turn on, representing the
reduction in the actual battery capacity.
Digital Magnitude Filter (DMF)
The read-write DMF register (address = 0ah) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different values into this register, the limits of VSRD and VSRQ can be
adjusted.
Note: Care should be taken when writing to this register. A VSRD and VSRQ below the specified VOS may adversely affect the accuracy of the bq2012. Refer to Table
4 for recommended settings for the DMF register.
The capacity display is also adjusted for the present battery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
not affect the NAC register. The temperature adjustments are detailed in the TMPGG register description.
Reset Register (RST)
When DISP is tied to VCC, the SEG1–6 outputs are inactive. When DISP is left floating, the display becomes active whenever the NAC registers are counting at a rate
equivalent to VSRO < -4mV or VSRO > VSRQ. When
pulled low, the segment outputs become active immediately. A capacitor tied to DISP allows the display to remain active for a short period of time after activation by
a push-button switch.
The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. By
writing the RST register contents from 00h to 80h, a
bq2012 reset is performed. Setting any bit other than the
most-significant bit of the RST register is not allowed,
and results in improper operation of the bq2012.
Resetting the bq2012 sets the following:
■
LMD = PFC
■
CPI, VDQ, NACH, and NACL = 0
■
CI and BRP = 1
The segment outputs are modulated as two banks of
three, with segments 1, 3, and 5 alternating with segments 2, 4, and 6. The segment outputs are modulated
at approximately 100Hz with each segment bank active
for 30% of the period.
Note: NACH = PFC when PROG6 = H.
SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables
the display output.
Display
The bq2012 can directly display capacity information using low-power LEDs. If LEDs are used, the program
pins should be resistively tied to VCC or VSS for a program high or program low, respectively.
Microregulator
The bq2012 can operate directly from three or four cells.
To facilitate the power supply requirements of the
bq2012, an REF output is provided to regulate an external low-threshold n-FET. A micropower source for the
bq2012 can be inexpensively built using the FET and an
external resistor; see Figure 1.
The bq2012 displays the battery charge state in either
absolute or relative mode. In relative mode, the battery
charge is represented as a percentage of the LMD. Each
LED segment represents 20% of the LMD. The sixth
segment is not used.
15
Not Recommended For New Designs
bq2012
Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
Unit
Notes
VCC
Relative to VSS
-0.3
7.0
V
All other pins
Relative to VSS
-0.3
7.0
V
REF
Relative to VSS
-0.3
8.5
V
Current limited by R1 (see Figure 1)
VSR
Relative to VSS
TOPR
Operating temperature
Note:
-0.3
7.0
V
Minimum 100Ω series resistor should
be used to protect SR in case of a
shorted battery (see the bq2012 application note for details).
0
70
°C
Commercial
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
VEDVF
Final empty warning
0.93
0.95
0.97
V
SB
VEDV1
First empty warning
1.03
1.05
1.07
V
SB
VSR1
Discharge compensation threshold
-120
-150
-180
mV
SR, VSR + VOS (see
note 2)
VORD
Overload threshold
-230
-250
-280
mV
SR, VSR + VOS
VSRO
SR sense range
-300
-
+2000
mV
SR, VSR + VOS
375
-
-
µV
VSR + VOS (see note 1)
-
-
-300
µV
VSR + VOS (see note 1)
2.20
2.25
2.30
V
VSRQ
Valid charge
VSRD
Valid discharge
VMCV
Maximum single-cell voltage
VBR
Battery removed/replaced
Notes:
1. Default value; value set in DMF register. VOS is affected by PC board layout. Proper layout
guidelines should be followed for optimal performance. See “LayoutConsiderations.”
2. Proper threshold measurements require VCC to be more than 1.5V greater than the desired signal
value.
SB
-
0.1
0.25
V
SB pulled low
2.20
2.25
2.30
V
SB pulled high
16
Not Recommended For New Designs
bq2012
DC Electrical Characteristics (TA = TOPR)
Symbol
Parameter
VCC
Supply voltage
VOS
Offset referred to VSR
VREF
Minimum
Typical
Maximum
Unit
Notes
VCC excursion from < 2.0V to ≥
3.0V initializes the unit.
3.0
4.25
6.5
V
-
±50
±150
µV
DISP = VCC
Reference at 25°C
5.7
6.0
6.3
V
IREF = 5µA
Reference at -40°C to +85°C
4.5
-
7.5
V
IREF = 5µA
RREF
Reference input impedance
2.0
5.0
-
MΩ
VREF = 3V
-
90
135
µA
VCC = 3.0V
ICC
Normal operation
-
120
180
µA
VCC = 4.25V
-
170
250
µA
VCC = 6.5V
-
-
2.4
V
VSB
Battery input
RSBmax
SB input impedance
10
-
-
MΩ
0 < VSB < VCC
IDISP
DISP input leakage
-
-
5
µA
VDISP = VSS
ILCOM
LCOM input leakage
-0.2
-
0.2
µA
DISP = VCC
RDQ
Internal pulldown
500
-
-
KΩ
VSR
Sense resistor input
-0.3
-
2.0
V
RSR
SR input impedance
VIH
Logic input high
VIL
Logic input low
VIZ
Logic input Z
VOLSL
10
-
-
MΩ
VCC - 0.2
-
-
V
VSR < VSS = discharge;
VSR > VSS = charge
-200mV < VSR < VCC
PROG1–PROG6
-
-
VSS + 0.2
V
PROG1–PROG6
float
-
float
V
PROG1–PROG6
SEGX output low, low VCC
-
0.1
-
V
VCC = 3V, IOLS ≤ 1.75mA
SEG1–SEG6
VOLSH
SEGX output low, high VCC
-
0.4
-
V
VCC = 6.5V, IOLS ≤ 11.0mA
SEG1–SEG6
VCC = 3V, IOHLCOM = -5.25mA
VOHLCL
LCOM output high, low VCC
VCC - 0.3
-
-
V
VOHLCH
LCOM output high, high VCC
VCC - 0.6
-
-
V
IIH
PROG1-6 input high current
-
1.2
-
µA
IIL
PROG1-6 input low current
IOHLCOM LCOM source current
IOLS
SEGX sink current
IOL
Open-drain sink current
VCC = 6.5V, IOHLCOM = -33.0mA
VPROG = VCC/2
-
1.2
-
µA
VPROG = VCC/2
-33
-
-
mA
At VOHLCH = VCC - 0.6V
-
-
11.0
mA
At VOLSH = 0.4V
At VOL = VSS + 0.3V
DQ, EMPTY, CHG
-
-
5.0
mA
IOL ≤ 5mA, DQ, EMPTY
VOL
Open-drain output low
-
-
0.5
V
VIHDQ
DQ input high
2.5
-
-
V
DQ
VILDQ
DQ input low
-
-
0.8
V
DQ
RPROG
Soft pull-up or pull-down resistor value (for programming)
-
-
200
KΩ
PROG1–PROG6
RFLOAT
Float state external impedance
-
5
-
MΩ
PROG1–PROG6
Note:
All voltages relative to VSS.
17
Not Recommended For New Designs
bq2012
Serial Communication Timing Specification
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYCH
Cycle time, host to bq2012
3
-
-
ms
tCYCB
Cycle time, bq2012 to host
3
-
6
ms
tSTRH
Start hold, host to bq2012
5
-
-
ns
tSTRB
Start hold, bq2012 to host
500
-
-
µs
tDSU
Data setup
-
-
750
µs
tDH
Data hold
750
-
-
µs
tDV
Data valid
1.50
-
-
ms
tSSU
Stop setup
-
-
2.25
ms
tSH
Stop hold
700
-
-
µs
tSV
Stop valid
2.95
-
-
ms
tB
Break
3
-
-
ms
tBR
Break recovery
1
-
-
ms
Note:
Notes
See note
The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation.
DQ may be left floating if the serial interface is not used.
Serial Communication Timing Illustration
DQ
(R/W "1")
DQ
(R/W "0")
tSTRH
tSTRB
tDH
tDSU
tDV
tSH
tSSU
DQ
(BREAK)
tSV
tCYCH, tCYCB, tB
tBR
TD201002.eps
18
Not Recommended For New Designs
bq2012
16-Pin SOIC Narrow (SN)
16-Pin SN (0.150" SOIC)
Inches
D
B
e
E
H
A
C
A1
Millimeters
Dimension
A
Min.
Max.
Min.
Max.
0.060
0.070
1.52
1.78
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.18
0.25
D
0.385
0.400
9.78
10.16
E
0.150
0.160
3.81
4.06
e
0.045
0.055
1.14
1.40
H
0.225
0.245
5.72
6.22
L
0.015
0.035
0.38
0.89
.004
L
Data Sheet Revision History
Change No.
Page No.
1
7
Note:
Description
Addition to Table 2
Nature of Change
Added bottom row
Change 1 = Sept. 1996 B changes from July 1994.
Ordering Information
bq2012
Temperature Range:
blank = Commercial (0 to +70°C)
Package Option:
SN = 16-pin narrow SOIC
Device:
bq2012 Gas Gauge IC
19
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ2012SN-D107
NRND
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2012
D107
BQ2012SN-D107G4
NRND
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2012
D107
BQ2012SN-D107TR
NRND
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2012
D107
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ2012SN-D107TR
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ2012SN-D107TR
SOIC
D
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
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