ON ASM3P1819NF.08.SR Low power mobile vga emi reduction ic Datasheet

ASM3P1819N
Product Preview
Low Power Mobile VGA EMI
Reduction IC
Description
The ASM3P1819N is a versatile spread spectrum frequency
modulator designed specifically for a wide range of input clock
frequencies from 20 to 40 MHz. The ASM3P1819N can generate an
EMI reduced clock from crystal, ceramic resonator, or system clock.
The ASM3P1819N reduces electromagnetic interference (EMI) at
the clock source, allowing a system wide EMI reduction for all the
down stream clocks and data dependent signals. The ASM3P1819N
allows significant system cost savings by reducing the number of
circuit board layers, ferrite beads, shielding, and other passive
components that are traditionally required to pass EMI regulations.
The ASM3P1819N modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, thereby decreasing the
peak amplitude of its harmonics. This results in a significantly lower
system EMI compared to the typical narrow band signal produced by
oscillators and most clock generators.
Lowering EMI by increasing a signal’s bandwidth is called “spread
spectrum clock generation”. The ASM3P1819N uses the most
efficient and optimized modulation profile approved by the FCC and
is implemented by using a proprietary all digital method.
Applications
The ASM3P1819N is targeted towards EMI management for
memory and LVDS interfaces in mobile graphic chipsets and
high−speed digital applications such as PC peripheral devices,
consumer electronics and embedded controller system.
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SOIC−8
S SUFFIX
CASE 751BD
TSSOP−8
T SUFFIX
CASE 948AL
PIN CONFIGURATION
XIN
1
XOUT
VSS
VDD
NC
PD#
ModOUT
REF
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Features
• FCC Approved Method of EMI Attenuation
• Provides up to 15 dB EMI Reduction
• Generates a Low EMI Spread Spectrum Clock and a Non−spread
•
•
•
•
•
•
•
•
•
•
•
•
Reference Clock of the Input Frequency
Optimized for Frequency Range from 20 MHz to 40 MHz
Internal Loop Filter Minimizes External Components and Board Space
Down Spread Deviation: −1.25%
Low Inherent Cycle−to−Cycle Jitter
3.3 V Operating Voltage
CMOS/TTL Compatible Inputs and Outputs
Low Power CMOS Design
Supports Notebook VGA and Other LCD Timing Controller
Applications
Power Down Function for Mobile Application
Products are Available for Industrial Temperature Range
Available in 8 pin SOIC and TSSOP Packages
These are Pb−Free Devices
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. P2
1
Publication Order Number:
ASM3P1819N/D
ASM3P1819N
PD#
PLL
Modulation
XIN
XOUT
VDD
Crystal
Oscillator
Frequency
Divider
Phase
Detector
Feedback
Divider
Loop
Filter
Output
Divider
VCO
REF
ModOUT
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
Pin Name
Type
Description
1
XIN
I
Connect to externally generated Clock signal or Crystal.
2
VSS
P
Ground Connection. Connect to system ground.
3
NC
−
No Connect.
4
ModOUT
O
Spread spectrum clock output.
5
REF
O
Non−modulated Reference clock output of the input frequency.
6
PD#
I
Power down control pin. Pull LOW to enable Power−Down mode. This pin has an internal pull−up resistor.
7
VDD
P
Connect to +3.3 V.
8
XOUT
I
Connect to crystal. No connect if externally generated clock signal is used.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Unit
Voltage on any pin with respect to Ground
−0.5 to +4.6
V
Storage temperature
−65 to +125
°C
TA
Operating temperature
−40 to +85
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
KV
VDD, VIN
TSTG
TDV
Parameter
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. OUTPUT FREQUENCY AND MODULATION RATE
Input Frequency Range (MHz)
Output Frequency Range (MHz)
Modulation Rate
Spread Deviation (%)
20 to 40
20 to 40
Input Frequency / 512
−1.25
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2
ASM3P1819N
Table 4. DC ELECTRICAL CHARACTERISTICS
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)
Max
Unit
VIL
Input Low voltage
Parameter
VSS − 0.3
0.8
V
VIH
Input High voltage
2.0
VDD + 0.3
V
IIL
Input Low current
−20.0
mA
IIH
Input High current
1.0
mA
Symbol
Min
Typ
IXOL
XOUT Output low current @ 0.4 V, VDD = 3.3 V
3
mA
IXOH
XOUT Output high current @ 2.5 V, VDD = 3.3 V
3
mA
VOL
Output Low voltage VDD = 3.3 V, IOL = 20 mA
VOH
Output High voltage VDD = 3.3 V, IOH = 20 mA
ICC
Dynamic Supply current
3.3 V and 10 pF probe loading
IDD
Static Supply current
4.5
mA
Operating Voltage
3.3
V
Power up time (First locked clock cycle after power up)
0.18
mS
50
W
VDD
tON
ZOUT
0.4
2.5
V
7.1
fIN − min
Clock Output impedance
V
26.9
fIN − max
mA
Table 5. AC ELECTRICAL CHARACTERISTICS
Symbol
fIN
fOUT
Parameter
Min
Typ
Max
Unit
Input Frequency
20
40
MHz
Output Frequency
20
40
MHz
tLH (Note 1)
Output Rise time (Measured from 0.8 V to 2.0 V)
tHL (Note 1)
Output Fall time (Measured from 2.0 V to 0.8 V)
tJC
Jitter (Cycle to Cycle)
tD
Output Duty cycle
0.69
0.66
−200
45
1. tLH and tHL are measured into a capacitive load of 15 pF.
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3
nS
50
nS
200
pS
55
%
ASM3P1819N
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.15
0.90
e
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
1.05
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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4
ASM3P1819N
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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5
ASM3P1819N
Table 6. ORDERING INFORMATION
Part Number
Marking
Package Type
Temperature
ASM3P1819NF−08−ST
3P1819NF
8−Pin SOIC, Tube, Pb Free
Commercial
ASM3P1819NF−08−SR
3P1819NF
8−Pin SOIC, Tape and Reel, Pb Free
Commercial
ASM3P1819NG−08−ST
3P1819NG
8−Pin SOIC, Tube, Green
Commercial
ASM3P1819NG−08−SR
3P1819NG
8−Pin SOIC, Tape and Reel, Green
Commercial
ASM3I1819NF−08−ST
3I1819NF
8−Pin SOIC, Tube, Pb Free
Industrial
ASM3I1819NF−08−SR
3I1819NF
8−Pin SOIC, Tape and Reel, Pb Free
Industrial
ASM3I1819NG−08−ST
3I1819NG
8−Pin SOIC, Tube, Green
Industrial
ASM3I1819NG−08−SR
3I1819NG
8−Pin SOIC, Tape and Reel, Green
Industrial
ASM3P1819NF−08−TT
3P1819NF
8−Pin TSSOP, Tube, Pb Free
Commercial
ASM3P1819NF−08−TR
3P1819NF
8−Pin TSSOP, Tape and Reel, Pb Free
Commercial
ASM3P1819NG−08−TT
3P1819NG
8−Pin TSSOP, Tube, Green
Commercial
ASM3P1819NG−08−TR
3P1819NG
8−Pin TSSOP, Tape and Reel, Green
Commercial
ASM3I1819NF−08−TT
3I1819NF
8−Pin TSSOP, Tube, Pb Free
Industrial
ASM3I1819NF−08−TR
3I1819NF
8−Pin TSSOP, Tape and Reel, Pb Free
Industrial
ASM3I1819NG−08−TT
3I1819NG
8−Pin TSSOP, Tube, Green
Industrial
ASM3I1819NG−08−TR
3I1819NG
8−Pin TSSOP, Tape and Reel, Green
Industrial
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
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ASM3P1819N/D
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