AD ADUM150N High robustness to radiated and conducted noise Datasheet

FUNCTIONAL BLOCK DIAGRAMS
High common-mode transient immunity: 100 kV/μs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals (pending)
UL recognition: 3000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
CQC certification per GB4943.1-2011
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, narrow-body SOIC package
VDD1 1
VDD2
ENCODE
DECODE
15 VOA
VIB 3
ENCODE
DECODE
14
VOB
VIC 4
ENCODE
DECODE
13
VOC
VID 5
ENCODE
DECODE
12
VOD
VIE 6
ENCODE
DECODE
11
VOE
NIC 7
10
NIC
GND1 8
9
GND2
ADuM151N
16
VDD2
VIA 2
ENCODE
DECODE
15
VOA
VIB 3
ENCODE
DECODE
14
VOB
VIC 4
ENCODE
DECODE
13
VOC
VID 5
ENCODE
DECODE
12
VOD
VOE 6
DECODE
ENCODE
11
VIE
NIC 7
10
NIC
GND1 8
9
GND2
14531-002
VDD1 1
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
Figure 2. ADuM151N Functional Block Diagram
VDD1 1
GENERAL DESCRIPTION
The ADuM150N/ADuM151N/ADuM152N1 are 5-channel
digital isolators based on Analog Devices, Inc., iCoupler®
technology. Combining high speed, complementary metal-oxide
semiconductor (CMOS) and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as
optocoupler devices and other integrated couplers. The
maximum propagation delay is 13 ns with a pulse width
distortion of less than 4.5 ns at 5 V operation. Channel to
channel matching of propagation delay is tight at 4.0 ns
maximum.
1
16
Figure 1. ADuM150N Functional Block Diagram
APPLICATIONS
The ADuM150N/ADuM151N/ADuM152N data channels are
independent and are available in a variety of configurations
with a withstand voltage rating of 3.0 kV rms (see the Ordering
Guide). The devices operate with the supply voltage on either
side ranging from 1.7 V to 5.5 V, providing compatibility with
lower voltage systems as well as enabling voltage translation
functionality across the isolation barrier.
ADuM150N
VIA 2
14531-001
FEATURES
ADuM152N
16
VDD2
VIA 2
ENCODE
DECODE
15
VOA
VIB 3
ENCODE
DECODE
14
VOB
VIC 4
ENCODE
DECODE
13
VOC
VOD 5
DECODE
ENCODE
12
VID
VOE 6
DECODE
ENCODE
11
VIE
NIC 7
10
NIC
GND1 8
9
GND2
14531-003
Data Sheet
3.0 kV RMS 5-Channel Digital Isolators
ADuM150N/ADuM151N/ADuM152N
Figure 3. ADuM152N Functional Block Diagram
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available by which the outputs transition to a predetermined state when the input power supply is not applied.
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. 0
Document Feedback
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Technical Support
www.analog.com
ADuM150N/ADuM151N/ADuM152N
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 12
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 13
General Description ......................................................................... 1
ESD Caution................................................................................ 13
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ......................... 14
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 17
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 19
Electrical Characteristics—5 V Operation................................ 3
Applications Information .............................................................. 20
Electrical Characteristics—3.3 V Operation ............................ 5
PCB Layout ................................................................................. 20
Electrical Characteristics—2.5 V Operation ............................ 7
Propagation Delay Related Parameters ................................... 20
Electrical Characteristics—1.8 V Operation ............................ 9
Jitter Measurement ..................................................................... 20
Insulation and Safety Related Specifications .......................... 11
Insulation Lifetime ..................................................................... 20
Package Characteristics ............................................................. 11
Outline Dimensions ....................................................................... 22
Regulatory Information ............................................................. 11
Ordering Guide .......................................................................... 22
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 12
REVISION HISTORY
8/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Symbol
Min
PW
6.6
150
4.8
tPHL, tPLH
PWD
7.2
0.5
1.5
tPSK
VIH
VIL
Output Voltage
Logic High
VOH
Logic Low
VOL
Max
Unit
Test Conditions/Comments
13
4.5
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
6.1
tPSKCD
tPSKOD
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM150N
Typ
0.5
0.5
490
70
4.0
4.5
0.7 ×
VDDx
ns
ns
ps p-p
ps rms
Between any two units at the
same temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
V
0.3 ×
VDDx
V
V
V
IOx2 = −20 µA, VIx = VIxH3
IOx2 = −4 mA, VIx = VIxH3
0.1
0.4
+10
V
V
µA
IOx2 = 20 µA, VIx = VIxL4
IOx2 = 4 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
2.54
3.34
16.8
3.57
3.70
4.56
27.5
4.90
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.79
3.20
14.2
7.08
4.09
4.22
23
11.1
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.91
2.95
11.1
10.5
4.11
4.15
19.5
16.7
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
Inputs switching, 50% duty cycle
IDDI (D)
IDDO (D)
0.01
0.02
VDDx
VDDx −
0.2
0.0
0.2
+0.01
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
II
VDDx − 0.1
VDDx − 0.4
−10
ADuM151N
ADuM152N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Rev. 0 | Page 3 of 22
mA/Mbps
mA/Mbps
ADuM150N/ADuM151N/ADuM152N
Parameter
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity7
Symbol
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
Data Sheet
Min
Typ
Max
Unit
1.6
1.5
0.1
V
V
V
tR/tF
|CMH|
75
2.5
100
ns
kV/µs
|CML|
75
100
kV/µs
Test Conditions/Comments
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, or E.
3
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
2
Table 2. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM150N
Supply Current Side 1
Supply Current Side 2
ADuM151N
Supply Current Side 1
Supply Current Side 2
ADuM152N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
9.63
3.61
14.6
5.61
10.9
5.36
17.1
8.50
16.0
11.1
24.0
19.0
mA
mA
IDD1
IDD2
8.51
5.28
13.7
8.95
9.85
6.89
16.1
11.5
15.0
12.3
23.3
20.0
mA
mA
IDD1
IDD2
7.08
6.83
11.6
10.5
8.56
8.35
13.9
12.8
13.7
13.4
20.4
20.6
mA
mA
Rev. 0 | Page 4 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM150N
Symbol
Min
PW
6.6
150
4.8
tPHL, tPLH
PWD
Typ
6.8
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
14
4.5
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.5
tPSKCD
tPSKOD
0.7
0.7
580
120
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
4.0
4.5
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx2 = −20 µA, VIx = VIxH3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 µA, VIx = VIxL4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.36
3.20
16.5
3.43
3.52
4.42
27.2
4.76
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.61
3.05
14.0
6.91
3.91
4.07
22.8
10.9
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.74
2.79
10.9
10.3
3.94
3.99
19.3
16.5
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
Inputs switching, 50% duty cycle
IDDI (D)
IDDO (D)
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
0.01
0.01
mA/Mbps
mA/Mbps
1.6
1.5
0.1
V
V
V
VOL
II
−10
ADuM151N
ADuM152N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Rev. 0 | Page 5 of 22
ADuM150N/ADuM151N/ADuM152N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity7
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, or E.
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
2
3
Table 4. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM150N
Supply Current Side 1
Supply Current Side 2
ADuM151N
Supply Current Side 1
Supply Current Side 2
ADuM152N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
9.36
3.45
14.3
5.45
10.4
5.03
16.6
8.23
14.6
10.2
22.6
18.1
mA
mA
IDD1
IDD2
8.26
5.09
13.5
8.76
9.41
6.55
15.7
11.2
13.9
11.4
22.2
19.1
mA
mA
IDD1
IDD2
6.84
6.60
11.3
10.3
8.12
7.94
13.5
12.4
12.7
12.6
19.4
19.8
mA
mA
Rev. 0 | Page 6 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM150N
Symbol
Min
PW
6.6
150
5.0
tPHL, tPLH
PWD
Typ
7.0
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
14
5.0
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
6.8
tPSKCD
tPSKOD
0.7
0.7
800
190
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
5.0
5.0
ns
ns
ps p-p
ps rms
Between any two units at the
same temperature, voltage, load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx2 = −20 µA, VIx = VIxH3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 µA, VIx = VIxL4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.28
3.13
16.4
3.34
3.44
4.35
27.1
4.67
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1) 6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.52
2.97
13.9
6.83
3.82
3.99
22.7
10.8
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.66
2.71
10.8
10.2
3.86
3.91
19.2
16.4
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
Inputs switching, 50% duty cycle
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
VDDxUV+
VDDxUV−
VDDxUVH
1.6
1.5
0.1
V
V
V
VOL
II
−10
ADuM151N
ADuM152N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Rev. 0 | Page 7 of 22
ADuM150N/ADuM151N/ADuM152N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity7
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, or E.
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
2
3
Table 6. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM150N
Supply Current Side 1
Supply Current Side 2
ADuM151N
Supply Current Side 1
Supply Current Side 2
ADuM152N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
9.25
3.35
14.2
5.35
10.2
4.58
16.4
7.78
14.0
8.61
22.0
16.5
mA
mA
IDD1
IDD2
8.14
4.98
13.4
8.65
9.14
6.14
15.4
10.8
13.1
10.1
21.4
17.8
mA
mA
IDD1
IDD2
6.74
6.48
11.2
10.2
7.80
7.56
13.2
12.0
11.8
11.5
18.5
18.7
mA
mA
Rev. 0 | Page 8 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM150N
Symbol
Min
PW
6.6
150
5.8
tPHL, tPLH
PWD
Typ
8.7
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
15
5.0
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.0
tPSKCD
tPSKOD
0.7
0.7
470
70
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
5.0
5.0
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx2 = −20 µA, VIx = VIxH3
IOx2 = −2 mA, VIx = VIxH3
IOx2 = 20 µA, VIx = VIxL4
IOx2 = 2 mA, VIx = VIxL4
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.19
3.07
16.3
3.28
3.35
4.29
27.0
4.61
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.44
2.91
13.7
6.75
3.74
3.93
22.5
10.7
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.58
2.64
10.7
10.1
3.78
3.84
19.1
16.3
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
Inputs switching, 50% duty cycle
IDDI (D)
IDDO (D)
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
0.01
0.01
mA/Mbps
mA/Mbps
1.6
1.5
0.1
V
V
V
VOL
II
−10
ADuM151N
ADuM152N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Rev. 0 | Page 9 of 22
ADuM150N/ADuM151N/ADuM152N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity7
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
IOx is the Channel x output current, where x = A, B, C, D, or E.
VIxH is the input side logic high.
4
VIxL is the input side logic low.
5
VI is the voltage input.
6
N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models. N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
2
3
Table 8. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM150N
Supply Current Side 1
Supply Current Side 2
ADuM151N
Supply Current Side 1
Supply Current Side 2
ADuM152N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
9.07
3.30
14.0
5.30
10.0
4.55
16.2
7.75
13.8
8.71
21.8
16.4
mA
mA
IDD1
IDD2
7.99
4.89
13.3
8.56
8.98
6.06
15.3
10.7
12.8
10.1
21.1
17.8
mA
mA
IDD1
IDD2
6.62
6.38
11.1
10.1
7.68
7.45
13.1
11.9
11.6
11.5
18.3
18.7
mA
mA
Rev. 0 | Page 10 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see http://www.analog.com/icouplersafety.
Table 9.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L (I01)
Value
3000
4.0
Unit
V rms
mm min
Minimum External Tracking (Creepage)
L (I02)
4.0
mm min
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
4.5
mm min
CTI
25.5
>400
II
μm min
V
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2.2
4.0
75
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 11.
UL (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Single Protection, 3000 V rms
Isolation Voltage
Double Protection, 3000 V rms
Isolation Voltage
File E214100
CSA (Pending)
Approved under CSA Component
Acceptance Notice 5A
VDE (Pending)
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122
CSA 60950-1-07+A1+A2 and IEC
60950-1, second edition, +A1+A2:
Basic insulation at 400 V rms
(565 V peak)
Reinforced insulation at 200 V rms
(283 V peak)
IEC 60601-1 Edition 3.1: basic
insulation (one means of patient
protection (1 MOPP)), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains,
400 V rms secondary (565 V peak)
Reinforced insulation at 300 V rms
mains, 200 V secondary (282 V peak)
File 205078
Reinforced insulation, VIORM =
565 V peak, VIOSM = 6000 V peak
Basic insulation, VIORM = 565 V peak,
VIOSM = 10 kV peak
CQC (Pending)
Certified under
CQC11-471543-2012,
GB4943.1-2011:
Basic insulation at
770 V rms (1089 V peak)
Reinforced insulation at
385 V rms (545 V peak)
File 2471900-4880-0001
File (pending)
1
In accordance with UL 1577, each ADuM150N/ADuM151N/ADuM152N in the R-16 narrow-body (SOIC_N) package is proof tested by applying an insulation test voltage ≥
3600 V rms for 1 sec.
2
In accordance with DIN V VDE V 0884-10, each ADuM150N/ADuM151N/ADuM152N in the R-16 narrow-body (SOIC_N) package is proof tested by applying an insulation
test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
Rev. 0 | Page 11 of 22
ADuM150N/ADuM151N/ADuM152N
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 12.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Surge Isolation Voltage Reinforced
Safety Limiting Values
Unit
VIORM
Vpd (m)
I to IV
I to IV
I to III
40/125/21
2
565
1059
V peak
V peak
848
V peak
678
V peak
VIOTM
VIOSM
4200
10,000
V peak
V peak
VIOSM
6000
V peak
TS
PS
RS
150
1.64
>109
°C
W
Ω
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VPEAK = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VPEAK = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
Maximum value allowed in the event of a
failure (see Figure 4)
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
RECOMMENDED OPERATING CONDITIONS
1.8
1.6
SAFE LIMITING POWER (W)
Characteristic
Vpd (m)
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage Basic
Table 13.
1.4
Parameter
Operating Temperature
Supply Voltages
Input Signal Rise and Fall Times
1.2
1.0
0.8
0.6
0.4
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
14531-004
0.2
0
Symbol
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. 0 | Page 12 of 22
Symbol
TA
VDD1, VDD2
Rating
−40°C to +125°C
1.7 V to 5.5 V
1.0 ms
Data Sheet
ADuM150N/ADuM151N/ADuM152N
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 14.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature
(TA) Range
Supply Voltages (VDD1, VDD2)
Input Voltages (VIA, VIB, VIC, VID, VIE)
Output Voltages (VOA, VOB, VOC, VOD,
VOE)
Average Output Current per Pin3
Side 1 Output Current (IO1)
Side 2 Output Current (IO2)
Common-Mode Transients4
Rating
−65°C to +150°C
−40°C to +125°C
−0.5 V to +7.0 V
−0.5 V to VDDI1 + 0.5 V
−0.5 V to VDDO2 + 0.5 V
ESD CAUTION
−10 mA to +10 mA
−10 mA to +10 mA
−150 kV/μs to +150 kV/μs
1
VDDI is the input side supply voltage.
VDDO is the output side supply voltage.
See Figure 4 for the maximum rated current values for various temperatures.
4
Refers to the common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
2
3
Table 15. Maximum Continuous Working Voltage1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Rating
Constraint
789 V peak
403 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
909 V peak
469 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
558 V peak
285 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Truth Table
Table 16. ADuM150N/ADuM151N/ADuM152N Truth Table (Positive Logic)
VIx Input1, 2
L
H
L
X4
VDDI State2
Powered
Powered
Unpowered
Powered
VDDO State2
Powered
Powered
Powered
Unpowered
Default Low (N0),
VOx Output1, 2, 3
L
H
L
Indeterminate
Default High (N1),
VOx Output1, 2, 3
L
H
H
Indeterminate
1
Test Conditions/Comments
Normal operation
Normal operation
Fail-safe output
Output unpowered
L means low, H means high, and X means don’t care.
VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, or E). VDDI and VDDO refer to the supply voltages on the input and output sides of the given
channel, respectively.
3
N0 refers to the ADuM150N0/ADuM151N0/ADuM152N0 models, N1 refers to the ADuM150N1/ADuM151N1/ADuM152N1 models. See the Ordering Guide section.
4
Input pins (VIx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
2
Rev. 0 | Page 13 of 22
ADuM150N/ADuM151N/ADuM152N
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
VIA 2
15 VOA
VIB 3
14 VOB
ADuM150N
VIE 6
13 VOC
TOP VIEW
(Not to Scale) 12 VOD
11 VOE
NIC 7
10 NIC
VID 5
GND1 8
9
GND2
NOTES
1. NIC = NO INTERNAL CONNECTION.
14531-005
VIC 4
Figure 5. ADuM150N Pin Configuration
Table 17. ADuM150N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VID
VIE
NIC
GND1
GND2
NIC
VOE
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Input E.
No Internal Connection. Leave this pin floating.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
No Internal Connection. Leave this pin floating.
Logic Output E.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. 0 | Page 14 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
VDD1 1
16 VDD2
VIA 2
15 VOA
VIB 3
14 VOB
ADuM151N
VOE 6
13 VOC
TOP VIEW
(Not to Scale) 12 VOD
11 VIE
NIC 7
10 NIC
VID 5
GND1 8
9
GND2
NOTES
1. NIC = NO INTERNAL CONNECTION.
14531-006
VIC 4
Figure 6. ADuM151N Pin Configuration
Table 18. ADuM151N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VID
VOE
NIC
GND1
GND2
NIC
VIE
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Output E.
No Internal Connection. Leave this pin floating.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
No Internal Connection. Leave this pin floating.
Logic Input E.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. 0 | Page 15 of 22
ADuM150N/ADuM151N/ADuM152N
Data Sheet
16 VDD2
VDD1 1
VIA 2
15 VOA
14 VOB
VIB 3
VOE 6
NIC 7
10 NIC
VOD 5
GND1 8
9
GND2
NOTES
1. NIC = NO INTERNAL CONNECTION.
14531-007
ADuM152N
13 VOC
TOP VIEW
(Not to Scale) 12 VID
11 VIE
VIC 4
Figure 7. ADuM152N Pin Configuration
Table 19. ADuM152N Pin Function Descriptions
Pin No.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Mnemonic
VDD1
VIA
VIB
VIC
VOD
VOE
NIC
GND1
GND2
NIC
VIE
VID
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Logic Output E.
No Internal Connection. Leave this pin floating.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
No Internal Connection. Leave this pin floating.
Logic Input E.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
Reference the AN-1109 Application Note for specific layout guidelines.
Rev. 0 | Page 16 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
25
20
20
5
5V
3.3V
2.5V
1.8V
0
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
IDD1 SUPPLY CURRENT (mA)
20
5
5V
3.3V
2.5V
1.8V
0
20
40
60
80
100
120
140
160
DATA RATE (Mbps)
Figure 9. ADuM150N IDD2 Supply Current vs. Data Rate at Various Voltages
60
80
100
DATA RATE (Mbps)
120
140
160
Figure 10. ADuM151N IDD1 Supply Current vs. Data Rate at Various Voltages
20
40
60
80
100
120
140
160
Figure 12. ADuM152N IDD1 Supply Current vs. Data Rate at Various Voltages
IDD2 SUPPLY CURRENT (mA)
40
160
DATA RATE (Mbps)
15
10
5
5V
3.3V
2.5V
1.8V
0
14531-010
20
140
5V
3.3V
2.5V
1.8V
0
5V
3.3V
2.5V
1.8V
0
120
0
20
0
100
5
20
5
80
10
25
10
60
15
25
15
40
Figure 11. ADuM151N IDD2 Supply Current vs. Data Rate at Various Voltages
20
10
20
DATA RATE (Mbps)
25
15
5V
3.3V
2.5V
1.8V
0
25
0
IDD1 SUPPLY CURRENT (mA)
5
0
14531-009
IDD2 SUPPLY CURRENT (mA)
Figure 8. ADuM150N IDD1 Supply Current vs. Data Rate at Various Voltages
10
14531-012
10
15
0
20
40
60
80
100
DATA RATE (Mbps)
120
140
160
14531-013
15
14531-011
IDD2 SUPPLY CURRENT (mA)
25
14531-008
IDD1 SUPPLY CURRENT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 13. ADuM152N IDD2 Supply Current vs. Data Rate at Various Voltages
Rev. 0 | Page 17 of 22
Data Sheet
14
12
12
10
8
6
4
5V
3.3V
2.5V
1.8V
2
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
10
8
6
4
5V
3.3V
2.5V
1.8V
2
0
–40
Figure 14. Propagation Delay, tPLH vs. Temperature at Various Voltages
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
14531-015
PROPAGATION DELAY, tPHL (ns)
14
14531-014
PROPAGATION DELAY, tPLH (ns)
ADuM150N/ADuM151N/ADuM152N
Figure 15. Propagation Delay, tPHL vs. Temperature at Various Voltages
Rev. 0 | Page 18 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
THEORY OF OPERATION
The ADuM150N/ADuM151N/ADuM152N use a high frequency
carrier to transmit data across the isolation barrier using iCoupler
chip scale transformer coils separated by layers of polyimide
isolation. Using an on/off keying (OOK) technique and the
differential architecture shown in Figure 16 and Figure 17, the
ADuM150N/ADuM151N/ADuM152N have very low propagation delay and high speed. Internal regulators and input/output
design techniques allow logic and supply voltages over a wide
range from 1.7 V to 5.5 V, offering voltage translation of 1.8 V,
2.5 V, 3.3 V, and 5 V logic. The architecture is designed for high
common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques.
Figure 16 shows the waveforms for models of the ADuM150N0/
ADuM151N0/ADuM152N0 that have the condition of the failsafe output state equal to low, where the carrier waveform is off
when the input state is low. If the input side is off or not operating,
the fail-safe output state of low sets the output to low. For the
ADuM150N1/ADuM151N1/ADuM152N1 that have a fail-safe
output state of high, Figure 17 illustrates the conditions where the
carrier waveform is off when the input state is high. When the
input side is off or not operating, the fail-safe output state of
high sets the output to high. See the Ordering Guide for the
model numbers that have the fail-safe output state of low or the
fail-safe output state of high.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
14531-016
VOUT
GND2
Figure 16. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
GND2
Figure 17. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Rev. 0 | Page 19 of 22
14531-017
VOUT
ADuM150N/ADuM151N/ADuM152N
Data Sheet
APPLICATIONS INFORMATION
PCB LAYOUT
JITTER MEASUREMENT
The ADuM150N/ADuM151N/ADuM152N digital isolators
require no external interface circuitry for the logic interfaces. Power
supply bypassing is strongly recommended at the input and
output supply pins (see Figure 18). Bypass capacitors are connected
between Pin 1 and Pin 8 for VDD1 and between Pin 9 and Pin 16 for
VDD2. The recommended bypass capacitor value is between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the input power supply pin must not exceed
10 mm.
Figure 20 shows the eye diagram for the ADuM150N/
ADuM151N/ADuM152N. The measurement was taken using
an Agilent 81110A pulse pattern generator at 150 Mbps with
pseudorandom bit sequences (PRBS) 2(n − 1), n = 14, for 5 V
supplies. Jitter was measured with the Tektronix Model 5104B
oscilloscope, 1 GHz, 10 GSPS with the DPOJET jitter and eye diagram analysis tools. The result shows a typical measurement on
the ADuM150N/ADuM151N/ADuM152N with 490 ps p-p jitter.
5
4
VOLTAGE (V)
Figure 18. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
3
2
1
0
–10
–5
0
5
10
TIME (ns)
14531-020
VDD2
VOA
VOB
VOC
VID/VOD
VIE/VOE
NIC
GND2
14531-018
VDD1
VIA
VIB
VIC
VID/VOD
VIE/VOE
NIC
GND1
Figure 20. ADuM150N/ADuM151N/ADuM152N Eye Diagram
See the AN-1109 Application Note for board layout guidelines.
INSULATION LIFETIME
PROPAGATION DELAY RELATED PARAMETERS
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
14531-019
tPLH
50%
Figure 19. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM150N/
ADuM151N/ADuM152N component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM150N/ADuM151N/
ADuM152N components operating under the same conditions.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking,
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation, pollution degree, and material group. The material
group and creepage for the ADuM150N/ADuM151N/ADuM152N
isolators are presented in Table 9.
Rev. 0 | Page 20 of 22
Data Sheet
ADuM150N/ADuM151N/ADuM152N
Testing and modeling have shown that the primary driver of longterm degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the
polyimide materials used in these products, the ac rms voltage
determines the product lifetime.
VRMS = VAC RMS 2 + VDC 2
VAC RMS = VRMS − VDC
2
VDC
TIME
The working voltage across the barrier from Equation 1 is
VRMS = VAC RMS 2 + VDC 2
VRMS = 2402 + 4002
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
(1)
VAC RMS = VRMS 2 − VDC 2
VAC RMS = 4662 − 4002
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
VRMS
VPEAK
Figure 21. Critical Voltage Example
or
2
VAC RMS
14531-021
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
ISOLATION VOLTAGE
Insulation Wear Out
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 15 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 21 and
the following equations.
Note that the dc working voltage limit in Table 15 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
Rev. 0 | Page 21 of 22
ADuM150N/ADuM151N/ADuM152N
Data Sheet
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
0.25 (0.0098)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADuM150N1BRZ
ADuM150N1BRZ-RL7
ADuM150N0BRZ
ADuM150N0BRZ-RL7
ADuM151N1BRZ
ADuM151N1BRZ-RL7
ADuM151N0BRZ
ADuM151N0BRZ-RL7
ADuM152N1BRZ
ADuM152N1BRZ-RL7
ADuM152N0BRZ
ADuM152N0BRZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
No. of
Inputs,
VDD1
Side
5
5
5
5
4
4
4
4
3
3
3
3
No. of
Inputs,
VDD2
Side
0
0
0
0
1
1
1
1
2
2
2
2
Withstand
Voltage
Rating
(kV rms)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14531-0-8/16(0)
Rev. 0 | Page 22 of 22
Fail-Safe
Output
State
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
Package Description
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
16-Lead SOIC_N
16-Lead SOIC_N, 7” Reel
Package
Option
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16
R-16