DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 DS90C185 Low Power 1.8V FPD-Link (LVDS) Serializer Check for Samples: DS90C185 FEATURES DESCRIPTION • • The DS90C185 is a low-power serializer for portable battery-powered applications that reduces the size of the RGB interface between the host GPU and the display. 1 2 • • • • • • • Typical power 50 mW at 75-MHz pclk Drives up to 1400x1050 at 60-Hz (SXGA+) Displays 2.94 Gbps of throughput Two operating modes: 24-bit and 18-bit RGB 25- to 105-MHz Pixel Clock support Single 1.8-V Supply Sleep Mode Spread Spectrum Clock compatibility Small 6mm x 6mm x 0.8mm WQFN package 24-bit RGB plus three video control signals are serialized and translated to LVDS-compatible levels and sent as a 4 data + clock (4D+C) reduced-width LVDS compatible interface. The LVDS Interface is compatible with FPD-Link (1) deserializers and many LVDS based displays. These interfaces are commonly supported in LCD modules with “LVDS” or FPD-Link / FlatLink single-pixel input interfaces. Displays up to 1400x1050 at 60 fps are supported with 24-bpp color depth. 18 bpp may also be supported by a dedicated mode with a 3D+C output. Power dissipation is minimized by the full LVCMOS design and 1.8-V powered core and VDDIO rails. APPLICATIONS • • • • eBooks Media Tablet Devices Netbooks Portable Display Monitors The DS90C185 is offered in the small 48-pin WQFN package and features single 1.8-V supply operation for minimum power dissipation (50 mW typ). System Diagram 24-bit RGB 4 Control Clock 1.8V LVCMOS GPU R7-R0 G7-G0 1.8V DS90C185 FPD-Link SERIALIZER LVDS0+/- FPD-Link 4D+C LVDS DISPLAY MODULE LVDS1+/LVDS2+/- SXGA+ Resolution LVDSC+/B7-B0 LVDS3+/- TCON w/ LVDS Interface HSync VSync DE GPO/CNTL(L/R) CLK PDB 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Functional Block Diagram LVCMOS PARALLEL TO LVDS LVCMOS INPUTS RED GREEN BLUE D0 ± D27 HS VS DE CNTRL (L/R) DATA (LVDS) PLL CLK CLOCK (LVDS) PDB 18B_Mode VOD_SEL RFB DS90C185 - SERIALIZER 2 VDD D8 D7 D6 D5 D4 D3 D2 D1 VOD_SEL D0 PDB 48 47 46 45 44 43 42 41 40 39 38 37 Connection Diagram D9 1 36 TxOUT0- D10 2 35 TxOUT0+ D11 3 34 TxOUT1- D12 4 33 TxOUT1+ D13 5 32 TxOUT2- CLK 6 31 TxOUT2+ D14 7 30 TxCLKOUT- D15 8 29 TxCLKOUT+ D16 9 28 TxOUT3- D17 10 27 TxOUT3+ D18 11 26 18B_MODE D19 12 25 VDDTX DS90C185SQ TOP VIEW DAP = GND 15 16 17 18 19 20 21 22 23 GND D21 D22 D23 D24 D25 D26 D27 RFB 24 14 D20 Submit Documentation Feedback GND 13 VDDPLL (Not to scale) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Table 1. DS90C185 Pin Descriptions Pin Name I/O No. Description 1.8 V LVCMOS VIDEO INPUTS D27-D21, D20, D19-D14, D13-D9, D8-D1, D0 I 22-16, 14, 12-7, 5-1, 47-40, 38 CLK I 6 TxOUT0 –/+, TxOUT1 –/+, TxOUT2 –/+, TxOUT3 –/+, O 36, 34, 32, 28, TxCLK OUT -/+ O 30, 29 Data input pins. This includes: 8 Red, 8 Green, 8 Blue, and 3 video control lines and a general purpose or L/R control bit. Includes pull down. Clock input. Includes pull down. LVDS VIDEO OUTPUTS 35 33 31 27 LVDS Output Data — Expects 100 Ω DC load. LVDS Output Clock — Expects 100 Ω DC load. 1.8 V LVCMOS CONTROL INPUTS R_FB I 23 LVCMOS Ievel programmable strobe select 1 = Rising Edge Clock 0 = Falling Edge Clock — default Includes pull down. 18B_Mode I 26 Mode Configuration Input 1 = 3D+C (18 bit RGB mode) 0 = 4D+C (24 bit RGB mode) — default Includes pull down. VOD_SEL I 39 VOD Select Input 0 = Reduced VOD (lower power) 1 = Normal VOD — default Includes pull down. PDB I 37 Power Down Bar(Sleep) Input 1 = ACTIVE 0 = Sleep State (low power idle) — default Includes pull down. VDD P 48 Digital power input VDDTX P 25 LVDS driver power input PLL power input POWER and GROUND VDDPLL P 13 GND G 15, 24 DAP G Ground pins Connect DAP to ground plane These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 3 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Absolute Maximum Ratings www.ti.com (1) −0.3V to +2.5V Supply Voltage (VDD) LVCMOS Input Voltage −0.5V to (VDD + 0.3V) LVDS Driver Output Voltage −0.3V to (VDD + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec) +260°C Package Derating: θJA 26.6 °C/W above +22°C ESD Ratings HBM >4kV CDM >1.25kV MM (1) >250V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Recommended OperatingConditions Supply Voltage (VDD) Operating Free Air Temperature (TA) Min Nom Max 1.71 1.8 1.89 V −10 +22 +70 °C <90 mVPP Supply Noise Voltage (VDD) Differential Load Impedance 80 Input Clock Frequency 25 4 Submit Documentation Feedback 100 Units 120 Ω 105 MHz Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 0.65 VDD VDD V VIL Low Level Input Voltage GND 0.35 VDD V IIN Input Current –10 ±1 +10 μA VODSEL = H 160 (320) 300 (600) 450 (900) mV (mVP-P) VODSEL = L 115 (230) 180 (360) 300 (600) mV (mVP-P) 50 mV VIN = 0V or VDD = 1.71 V to 1.89 V LVDS DC SPECIFICATIONS VOD Differential Output Voltage RL = 100Ω Figure 3 ΔVOD Change in VOD between complimentary output states VOS Offset Voltage ΔVOS Change in VOS between complimentary output states IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω IOZ Output LVDS Driver Power Down Current PDB = 0V RL = 100Ω 0.8 –45 0.9 1.0 V 50 mV −35 −25 mA ±1 ±10 mA 85 mA SERIALIZER SUPPLY CURRENT IDDT1 Serializer Supply Current Worst Case Checkerboard pattern, RL = 100Ω, 18B_MODE = L, VOD_SEL = H, VDD = 1.89 Figure 1 f = 105 MHz 60 IDDTG Serializer Supply Current 16 Grayscale RL = 100Ω, 18B_MODE = L, VOD_SEL = L, VDD = 1.8 16 Grayscale Pattern f = 75 MHz 31 mA RL = 100Ω, 18B_MODE = L, VOD_SEL = H, VDD = 1.8 16 Grayscale Pattern 41 mA RL = 100Ω, 18B_MODE = H, VOD_SEL = L, VDD = 1.8 16 Grayscale Pattern 28 mA RL = 100Ω, 18B_MODE = H, VOD_SEL = H, VDD = 1.8 16 Grayscale Pattern 36 mA Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 5 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol IDDTP IDDZ 6 Parameter Serializer Supply Current PRBS-7 Conditions RL = 100Ω, 18B_MODE = L, VOD_SEL = L, VDD = 1.8 PRBS-7 Pattern Min f = 75 MHz Figure 11 Typ Max Units 33 mA RL = 100Ω, 18B_MODE = L, VOD_SEL = H, VDD = 1.8 PRBS-7 Pattern 45 mA RL = 100Ω, 18B_MODE = H, VOD_SEL = L, VDD = 1.8 PRBS-7 Pattern 29 mA RL = 100Ω, 18B_MODE = H, VOD_SEL = H, VDD = 1.8 PRBS-7 Pattern 38 mA Serializer Power Down Current 18 Submit Documentation Feedback 200 μA Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units TCIT TxCLK IN Transition Time (Figure 5) 1.0 6.0 ns TCIP TxCLK IN Period (Figure 6) 9.52 T 40 ns TCIH TxCLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min LVDS Low-to-High Transition Time (Figure 4 (1) LHLT LVDS High-to-Low Transition Time (Figure 4 (1) TPPOS0 Transmitter Output Pulse Positions Normalized for Bit 0 TPPOS1 LLHT ) ) Max Units 0.5 ns 0.18 0.5 ns 1 UI Transmitter Output Pulse Positions Normalized for Bit 1 2 UI TPPOS2 Transmitter Output Pulse Positions Normalized for Bit 2 3 UI TPPOS3 Transmitter Output Pulse Positions Normalized for Bit 3 4 UI TPPOS4 Transmitter Output Pulse Positions Normalized for Bit 4 5 UI TPPOS5 Transmitter Output Pulse Positions Normalized for Bit 5 6 UI TPPOS6 Transmitter Output Pulse Positions Normalized for Bit 6 7 UI ΔTPPOS Variation in Transmitter Pulse Position (Bit 6 — Bit 0) TSTC Required TxIN Setup to TxCLK IN THTC Required TxIN Hold to TxCLK IN TCCJ TSD f = 105 MHz Figure 10 Typ 0.18 ±0.06 Figure 6 Cycle to Cycle Jitter f = 105 MHz Serializer Propagation Delay f = 105 MHz Figure 7 TCCS TxOUT Channel to Channel Skew TPLLS Transmitter Phase Lock Loop Set Figure 8 TPPD Transmitter Power Down Delay Figure 9 (2) (1) (2) (1) UI 0 ns 2.5 ns 0.028 0.035 UI 2*TCIP + 10.54 2*TCIP + 13.96 ns 1 ms 100 ns 110 ps Parameter is guaranteed by characterization and is not tested at final test. Parameter is guaranteed by design and is not tested at final test. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 7 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com AC Timing Diagrams T CLK Dx, x = ODD Dx, x = EVEN Falling Edge CLK (RFB = GND) shown NOTE: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS I/O. Figure 1. “Worst Case” Test Pattern Signal Pattern Signal Signal Frequency f PCLK R0 f / 16 R1 f/8 R2 f/4 R3 f/2 R4 Steady State, Low R5 Steady State, Low G0 f / 16 G1 f/8 G2 f/4 G3 f/2 G4 Steady State, Low G5 Steady State, Low B0 f / 16 B1 f/8 B2 f/4 B3 f/2 B4 Steady State, Low B5 Steady State, Low HS Steady State, High VS Steady State, High DE Steady State, High NOTE: Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. NOTE: Figure 1 and Figure 2 show a falling edge data strobe (CLK). Figure 2. “16 Grayscale” Test Pattern - DS90C185 Figure 3. DS90C185 (Transmitter) LVDS Output Load 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 AC Timing Diagrams (continued) Figure 4. DS90C185 (Transmitter) LVDS Transition Times VDD 80% 80% 50% 20% 20% GND TCIT TCIT Figure 5. DS90C185 (Transmitter) Input Clock Transition Time TCIP TCIH TCIL VDD 50% GND VDD VIHmin TSTC VILmax 50% THTC GND Falling Edge CLK shown (RFB = GND) Figure 6. DS90C185 (Transmitter) Setup/Hold and High/Low Times with R_FB pin = GND (Falling Edge Strobe) CLK D0 ± D27 Pixel n-1 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 TSD TxCLKOUT+/TxOUTn+/- Pixel n Pixel n+1 Figure 7. DS90C185 Propagation Delay Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 9 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com AC Timing Diagrams (continued) 1.8V VDD GND VDD CLK GND VDD PDB GND TPLLS TxCLKOUT (Diff.) (LVDS) Figure 8. DS90C185 (Transmitter) Phase Lock Loop Set Time VDD CLK GND VDD PDB 50% GND TPDD TxCLKOUT (Diff.) (LVDS) Figure 9. Transmitter Power Down Delay Cycle N TxCLKOUT TxOUT[3:0]+/- bit 1 n-1 bit 0 n-1 bit 6 n bit 5 n bit 4 n bit 3 n bit 2 n bit 1 n bit 0 n 1UI 2UI 3UI 4UI 5UI 6UI 7UI Figure 10. Transmitter LVDS Output Pulse Position Measurement - DS90C185 60 VODSEL = L, 18B = L VODSEL = H, 18B = L VODSEL = L, 18B = H VODSEL = H, 18B = H 55 IDD (mA) 50 45 40 35 30 25 20 20 40 60 80 100 FREQUENCY (MHz) 120 Figure 11. Typ Current Draw — PRBS-7 Data Pattern 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 LVDS INTERFACE, TFT COLOR DATA RECOMMENDED MAPPING Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is used to ensure compatible mapping for the application. The DS90C185 supports single pixel interfaces with either 24bpp or 18bpp color depths. The DS90C185 provides four LVDS data lines along with an LVDS clock line (4D+C) for the 28 LVCMOS data inputs. The 28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE) and one spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The single pixel 24bpp 4D+C LVDS interface mapping is shown Figure 13. A single pixel 18bpp mode is also supported by utilizing the 18B_MODE pin. In this configuration the TxOUT3 output channel is place in TRI-STATE® to save power. Its respective inputs are ignored. This mapping is shown in Figure 12. TxCLKOUT+/(Diff) Current Cycle TxOUT3+/(SE) TRI-STATE TxOUT2+/(SE) D20 D19 D18 D17 D16 D15 D14 TxOUT1+/(SE) D13 D12 D11 D10 D9 D8 D7 TxOUT0+/(SE) D6 D5 D4 D3 D2 D1 D0 Figure 12. DS90C185 LVDS Map — 18B_MODE = H TxCLKOUT+/(Diff) Current Cycle TxOUT3+/(SE) D27 D26 D25 D24 D23 D22 D21 TxOUT2+/(SE) D20 D19 D18 D17 D16 D15 D14 TxOUT1+/(SE) D13 D12 D11 D10 D9 D8 D7 TxOUT0+/(SE) D6 D5 D4 D3 D2 D1 D0 Figure 13. DS90C185 LVDS Map — 18B_MODE = L COLOR MAPPING INFORMATION A defacto color mapping is shown next. Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is used to ensure compatible mapping for the application. Table 2. 24bpp / MSB on CH3 DS90C187 Input Color Mapping Note D22 R7 MSB D21 R6 D5 R5 D4 R4 D3 R3 D2 R2 D1 R1 D0 R0 LSB Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 11 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Table 2. 24bpp / MSB on CH3 (continued) DS90C187 Input Color Mapping Note D24 G7 MSB D23 G6 D11 G5 D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 LSB D26 B7 MSB D25 B6 D17 B5 D16 B4 D15 B3 D14 B2 D13 B1 D12 B0 D20 DE Data Enable D19 VS Vertical Sync D18 HS Horizontal Sync D27 GP General Purpose Table 3. 24bpp / LSB on CH3 12 DS90C187 Input Color Mapping Note D5 R7 MSB D4 R6 D3 R5 D2 R4 D1 R3 D0 R2 D22 R1 D21 R0 LSB D11 G7 MSB D10 G6 D9 G5 D8 G4 D7 G3 D6 G2 D24 G1 D23 G0 LSB D17 B7 MSB D16 B6 D15 B5 D14 B4 D13 B3 D12 B2 D26 B1 D25 B0 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 Table 3. 24bpp / LSB on CH3 (continued) DS90C187 Input Color Mapping Note D20 DE Data Enable D19 VS Vertical Sync D18 HS Horizontal Sync D27 GP General Purpose Table 4. 18bpp DS90C187 Input Color Mapping Note D5 R5 MSB D4 R4 D3 R3 D2 R2 D1 R1 D0 R0 LSB D11 G5 MSB D10 G4 D9 G3 D8 G2 D7 G1 D6 G0 LSB D17 B5 MSB D16 B4 D15 B3 D14 B2 D13 B1 D12 B0 D20 DE Data Enable D19 VS Vertical Sync D18 HS Horizontal Sync FUNCTIONAL DESCRIPTION DS90C185 converts a wide parallel LVCMOS input bus into FPD-Link LVDS data. The device can be configured to support RGB-888 (24 bit color) or RGB-666 (18 bit color). The DS90C185 has several power saving features including: selectable VOD, 18 bit / 24 bit mode select, and a power down pin control. In each input pixel clock cycle, data from D[27:0] is serialized and driven out on TxOUT[3:0] +/- with TxCLKOUT +/-. If 18B_MODE is LOW, then TxOUT3 +/- is powered down and the corresponding LVCMOS input signals are ignored. The input pixel clock can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 700 Mbps (28 bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits per input clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. TxCLKOUT +/- will operate at the same rate as CLK with a duty cycle ratio of 57:43. Pixel Clock Edge Select (RFB) The RFB pin determines the edge that the input LVCMOS data is latched on. If RFB is HIGH, input data is latched on the RISING EDGE of the pixel clock (CLK). If RFB is LOW, the input data is latched on the FALLING EDGE of the pixel clock. Note: This can be set independently of receiver’s output clock strobe. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 13 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com Table 5. Pixel Clock Edge RFB Result 0 FALLING edge 1 RISING edge Power Management The DS90C185 has several features to assist with managing power consumption. The 18B_MODE pin allows the DS90C185 to power down the unused LVDS driver for RGB-666 (18 bit color) applications. If no clock is applied to the CLK pin, the DS90C185 will enter a low power state. To place the DS90C185 in its lowest power state, the device can be powered down by driving the PDB pin to LOW. Sleep Mode (PDB) The DS90C185 provides a power down feature. When the device has been powered down, current draw through the supply pins is minimized and the PLL is shut down. The LVDS drivers are also powered down with their outputs pulled to GND through 100Ω resistors. Table 6. Power Down Select PDB Result 0 SLEEP Mode (default) 1 ACTIVE (enabled) LVDS Outputs The DS90C185's LVDS drivers are compatible with ANSI/TIA/EIA-644–A LVDS receivers. The LVDS drivers an output a power saving low VOD or a higher VOD to enable longer trace and cable lengths by configuring the VODSEL pin. Table 7. VOD Select VODSEL Result 0 ±180 mV (360mVpp) 1 ±300 mV (600mVpp) For more information regarding the electrical characteristics of the LVDS outputs, refer to the LVDS DC Characteristics and LVDS Switching Specifications. 18 bit / 24 bit Color Mode (18B) The 18B pin can be used to further save power by powering down the 4th LVDS driver in each used bank when the application requires only 18 bit color or 3D+C LVDS. Set the 18B pin to logic HIGH to TRI-STATE® TxOUT3 +/-. For 24 bit color applications this pin should be set to logic LOW. Note that the power down function takes priority over the TRI-STATE® function. Table 8. Color Depth Configurations 18B_Mode Result 0 24bpp, LVDS 4D+C 1 18bpp, LVDS 3D+C LVCMOS Inputs The DS90C185 has 28 data inputs. These inputs are typically used for 24 or 18 bits of RGB video with 1, 2 or 3 video control signal (HS, VS and DE) inputs and one spare bit that can be used for L/R signaling or function as a general purpose bit. All LVCMOS input pins are designed for 1.8V LVCMOS logic. All LVCMOS inputs, including clock, data and configuration pins have an internal pull down resistor to set a default state. If any LVCMOS inputs are unused, they can be left as no connect (NC) or connected to ground. 14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 APPLICATIONS INFORMATION Power Up Sequence The VDD power supply pins do not require a specific power on sequence and can be powered on in any order. However, the PDB pin should only be set to logic HIGH once the power sent to all supply pins is stable. Active clock and data inputs should not be applied to the DS90C185 until all of the input power pins have been powered on, settled to the recommended operating voltage and the PDB pin has be set to logic HIGH. The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended: Power up sequence (DS90C185 PDB input initially LOW): 1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off. 2. Wait for additional 0-200ms to ensure display noise won’t occur. 3. Toggle DS90C185 power down pin to PDB = VIH. 4. Enable video source output; start sending black video data. 5. Send >1ms of black video data; this allows the DS90C185 to be phase locked, and the display to show black data first. 6. Start sending true image data. 7. Enable backlight. Power Down sequence (DS90C185 PDB input initially HIGH): 1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low. 2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for >2 frame times. 3. Set DS90C185 power down pin to PDB = GND. 4. Disable the video output of the video source. 5. Remove power from the LCD panel for lowest system power. Power Supply Filtering The DS90C185 has several power supply pins at 1.8V. It is important that these pins all be connected and properly bypassed. Bypassing should consist of at least one 0.1µF capacitor placed on each pin, with an additional 4.7µF to 22µF capacitor placed on the PLL supply pin (VDDPLL). 0.01µF capacitors are typically recommended for each pin. Additional filtering including ferrite beads may be necessary for noisy systems. It is recommended to place a 0 resistor at the bypass capacitors that connect to each power pin to allow for additional filtering if needed. A large bulk capacitor is recommended at the point of power entry. This is typically in the 50µF to 100µF range. Layout Guidelines Circuit board layout and stack-up for the LVDS serializer devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. This practice is easier to implement in dense pcbs with many layers and may not be practical in simpler boards. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with vias on both ends of the capacitor. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 15 DS90C185 SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 www.ti.com A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the WQFN package is provided in Application Note: AN-1187 (SNOA401). LVDS Interconnect Guidlines See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details. • Use 100Ω coupled differential pairs • Use differential connectors when above 500Mbps • Minimize skew within the pair • Use the S/2S/3S rule in spacings – S = space between the pairs – 2S = space between pairs – 3S = space to LVCMOS signals • Place ground vias next to signal vias when changing between layers • When a signal changes reference planes, place a bypass cap and vias between the new and old reference plane For more tips and detailed suggestions regarding high speed board layout principles, please consult the LVDS Owner's Manual at: http://www.ti.com/lvds 16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 DS90C185 www.ti.com SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013 REVISION HISTORY June 08, 2012 • Fixed typo in Figure 12 for bits D14 and D15 • Fixed typo in Pin Descriptions for VODSEL. VODSEL = 0 reduced swing and VODSEL = 1 normal LVDS swing now match Functional Description explanation February 2013 • Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS90C185 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS90C185SQ/NOPB ACTIVE WQFN NJV 48 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -10 to 70 90C185SQ DS90C185SQE/NOPB ACTIVE WQFN NJV 48 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -10 to 70 90C185SQ DS90C185SQX/NOPB ACTIVE WQFN NJV 48 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -10 to 70 90C185SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90C185SQ/NOPB WQFN NJV 48 DS90C185SQE/NOPB WQFN NJV DS90C185SQX/NOPB WQFN NJV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 48 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C185SQ/NOPB WQFN NJV 48 1000 367.0 367.0 35.0 DS90C185SQE/NOPB WQFN NJV 48 250 210.0 185.0 35.0 DS90C185SQX/NOPB WQFN NJV 48 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NJV0048A SQF48A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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