CY7C1041G CY7C1041GE 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features ■ ■ ■ Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. High speed ❐ tAA = 10 ns / 15 ns Embedded ECC for single-bit error correction[1] Low active and standby currents ❐ Active current: ICC = 38-mA typical ❐ Standby current: ISB2 = 6-mA typical ■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V ■ 1.0-V data retention ■ TTL-compatible inputs and outputs Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. ■ Error indication (ERR) pin to indicate 1-bit error detection and correction All I/Os (I/O0 through I/O15) are placed in a high-impedance state during the following events: ■ Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages ■ The device is deselected (CE HIGH) ■ The control signals (OE, BLE, BHE) are de-asserted Functional Description CY7C1041G and CY7C1041GE are high-performance CMOS fast static RAM devices with embedded ECC. Both devices are offered in single and dual chip-enable options and in multiple pin configurations. The CY7C1041GE device includes an ERR pin that signals an error-detection and correction event during a read cycle. On the CY7C1041GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = HIGH)[1]. See the Truth Table on page 14 for a complete description of read and write modes. The logic block diagram is on page 2. Product Portfolio Product [2] Features and Options (see Pin Configurations on page 4) CY7C1041G(E)18 Single or Dual Chip Enables CY7C1041G(E)30 CY7C1041G(E) Optional ERR pins Power Dissipation Speed Operating ICC, (mA) (ns) Standby, ISB2 (mA) f = fmax 10/15 [3] [3] Typ Max Typ Max Range VCC Range (V) Industrial 1.65 V–2.2 V 15 – 40 2.2 V–3.6 V 10 38 45 4.5 V–5.5 V 10 38 45 6 8 Notes 1. This device does not support automatic write-back on error detection. 2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details. 3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 001-91368 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 2, 2016 CY7C1041G CY7C1041GE Logic Block Diagram – CY7C1041G MEMORY ARRAY ECC DECODER ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 INPUT BUFFER SENSE AMPLIFIERS ECC ENCODER I/O 0‐I/O 7 I/O 8‐I/O 15 A10 A11 A12 A13 A14 A15 A16 A17 COLUMN DECODER BHE WE OE CE 2 CE 1 BLE Logic Block Diagram – CY7C1041GE ECC DECODER M EM ORY ARRAY INPUT BUFFER SENSE AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER ECC ENCODER ERR I/O 0 ‐I/O 7 I/O 8 ‐I/O 15 A10 A11 A12 A13 A14 A15 A16 A17 COLUM N DECODER BH E WE OE BLE Document Number: 001-91368 Rev. *J CE 2 CE 1 Page 2 of 20 CY7C1041G CY7C1041GE Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Loads and Waveforms ....................................... 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 AC Switching Characteristics ......................................... 9 Switching Waveforms .................................................... 10 Truth Table ...................................................................... 14 ERR Output – CY7C1041GE .......................................... 14 Document Number: 001-91368 Rev. *J Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 18 Document Conventions ................................................. 18 Units of Measure ....................................................... 18 Document History Page ................................................. 19 Sales, Solutions, and Legal Information ...................... 20 Worldwide Sales and Design Support ....................... 20 Products .................................................................... 20 PSoC® Solutions ...................................................... 20 Cypress Developer Community ................................. 20 Technical Support ..................................................... 20 Page 3 of 20 CY7C1041G CY7C1041GE Pin Configurations Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable without ERR, CY7C1041G [4], Package/Grade ID: BVXI [6] with ERR, CY7C1041GE [4, 5], Package/Grade ID: BVXI [6] 1 2 BLE OE I/O 0 3 4 5 6 A0 A1 A2 NC BHE A3 A4 CE I/O 1 I/O2 A5 A6 VSS I/O3 A17 VCC I/O4 I/O 6 1 2 A BLE OE I/O8 B I/O0 I/O10 I/O9 C A7 I/O11 VCC D NC A 16 I/O12 VSS E I/O5 A14 A 15 I/O13 I/O14 F I/O 7 NC A12 A 13 WE I/O15 G NC A8 A9 A 10 A 11 NC H Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable without ERR, CY7C1041G [4], Package/Grade ID: BVJXI [6] 1 2 BLE OE I/O8 3 4 5 6 A0 A1 A2 NC BHE A3 A4 CE I/O9 I/O10 A5 A6 VSS I/O11 A17 VCC I/O12 I/O14 3 4 5 6 A0 A1 A2 NC A BHE A3 A4 CE I/O8 B I/O1 I/O2 A5 A6 I/O10 I/O9 C VSS I/O3 A17 A7 I/O11 VCC D VCC I/O4 ERR A16 I/O12 VSS E I/O6 I/O5 A14 A15 I/O13 I/O14 F I/O7 NC A12 A13 WE I/O15 G NC A8 A9 A10 A11 NC H Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable with ERR, CY7C1041GE [4, 5], Package/Grade ID: BVJXI [6] 1 2 A BLE OE I/O0 B I/O8 I/O1 I/O2 C A7 I/O3 VCC NC A16 I/O4 I/O13 A14 A15 I/O15 NC A12 NC A8 A9 3 4 5 6 A0 A1 A2 NC A BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C D VSS I/O11 A17 A7 I/O3 VCC D VSS E VCC I/O12 ERR A16 I/O4 VSS E I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 G A10 A11 NC H NC A8 A9 A10 A11 NC H Notes 4. NC pins are not connected internally to the die. 5. ERR is an output pin. 6. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8] balls are swapped. Document Number: 001-91368 Rev. *J Page 4 of 20 CY7C1041G CY7C1041GE Pin Configurations (continued) Figure 5. 44-pin TSOP II/44-pin SOJ Single Chip Enable with ERR, CY7C1041GE [7, 8] A0 A1 A2 A3 A4 /CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 /WE A5 A6 A7 A8 A9 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 44- pin TSOP II36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 A17 A16 A15 /OE / BHE / BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 ERR A14 A13 A12 A11 A10 Figure 6. 44-pin TSOP II/44-pin SOJ Single Chip Enable without ERR, CY7C1041G [7] A0 A1 A2 A3 A4 /CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 /WE A5 A6 A7 A8 A9 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 44-pin TSOP II 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 A17 A16 A15 /OE /BHE /BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Notes 7. NC pins are not connected internally to the die. 8. ERR is an output pin. Document Number: 001-91368 Rev. *J Page 5 of 20 CY7C1041G CY7C1041GE DC input voltage [9] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ................................... –55 C to +125 C Current into outputs (in LOW state) ............................ 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Operating Range Supply voltage on VCC relative to GND [9] .................. –0.5 V to VCC + 0.5 V DC voltage applied to outputs in HI-Z State [9] ................................... –0.5 V to VCC + 0.5 V Grade Ambient Temperature VCC Industrial –40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the operating range of –40 C to 85 C Parameter VOH Description Output HIGH voltage Min Typ [10] Max 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 1.4 – – 2 – – 2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.2 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – VCC = Min, IOH = –0.1 mA – 0.5 [11] – – – – 0.2 4.5 V to 5.5 V VOL VIH VIL Output LOW voltage Input HIGH voltage Input LOW voltage 10 ns / 15 ns Test Conditions 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA VCC Unit V V 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4 1.4 – VCC + 0.2 [9] [9] 1.65 V to 2.2 V – 2.2 V to 2.7 V – 2 – VCC + 0.3 2.7 V to 3.6 V – 2 – VCC + 0.3 [9] 4.5 V to 5.5 V – 2.2 – VCC + 0.5 [9] –0.2 [9] – 0.4 [9] 1.65 V to 2.2 V – 2.2 V to 2.7 V – –0.3 – 0.6 2.7 V to 3.6 V – –0.3 [9] – 0.8 – [9] – 0.8 – +1 4.5 V to 5.5 V IIX Input leakage current IOZ ICC –0.5 V V A GND < VIN < VCC –1 Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A Operating supply current Max VCC, IOUT = 0 mA, f = 100 MHz CMOS levels f = 66.7 MHz – 38 45 mA – – 40 ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – – 15 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 6 8 mA Notes 9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns. 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V), VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C. 11. This parameter is guaranteed by design and not tested. Document Number: 001-91368 Rev. *J Page 6 of 20 CY7C1041G CY7C1041GE Capacitance Parameter [12] Description CIN Input capacitance COUT I/O capacitance Test Conditions 48-ball VFBGA 44-pin SOJ 10 10 10 pF 10 10 10 pF Test Conditions 48-ball VFBGA 44-pin SOJ Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 31.35 55.37 68.85 C/W 14.74 30.41 15.97 C/W TA = 25 C, f = 1 MHz, VCC = VCC(typ) 44-pin TSOP II Unit Thermal Resistance Parameter [12] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 44-pin TSOP II Unit AC Test Loads and Waveforms Figure 7. AC Test Loads and Waveforms [13] High-Z Characteristics: VCC 50 Output VTH Z0 = 50 R1 Output 30 pF* * Including jig and scope (a) * Capacitive load consists of all components of the test environment (b) All Input Pulses VHIGH GND R2 5 pF* 90% 90% 10% Rise Time: > 1 V/ns 10% Fall Time: > 1 V/ns (c) Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317 R2 1538 351 351 VTH 0.9 1.5 1.5 V VHIGH 1.8 3 3 V Notes 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization. Document Number: 001-91368 Rev. *J Page 7 of 20 CY7C1041G CY7C1041GE Data Retention Characteristics Over the operating range of –40 C to 85 C Parameter VDR Description Conditions Min Max Unit 1 – V – 8 mA 0 – ns VCC > 2.2 V 10 – ns VCC < 2.2 V 15 – ns VCC for data retention [14] ICCDR Data retention current tCDR[15] Chip deselect to data retention time tR[14, 15] Operation recovery time VCC = 1.2 V, CE > VCC – 0.2 V , VIN > VCC – 0.2 V, or VIN < 0.2 V Data Retention Waveform Figure 8. Data Retention Waveform [14] VCC VCC(min) DATA RETENTION MODE VDR = 1.0 V tCDR VCC(min) tR CE Notes 14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s. 15. These parameters are guaranteed by design. Document Number: 001-91368 Rev. *J Page 8 of 20 CY7C1041G CY7C1041GE AC Switching Characteristics Over the operating range of –40 C to 85 C Parameter [16] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tRC Read cycle time 10 – 15 – ns tAA Address to data / ERR valid – 10 – 15 ns tOHA Data / ERR hold from address change 3 – 3 – ns – 10 – 15 ns – 4.5 – 8 ns 0 – 0 – ns – 5 – 8 ns 3 – 3 – ns – 5 – 8 ns 0 – 0 – ns – 10 – 15 ns tACE CE LOW to data / ERR valid tDOE OE LOW to data / ERR valid tLZOE tHZOE OE LOW to low impedance OE HIGH to HI-Z [18, 19] [18, 19] tLZCE CE LOW to low impedance tHZCE CE HIGH to HI-Z [17, 18, 19] tPU [17] CE LOW to power-up [17, 18, 19] [17, 19, 20] [17, 19, 20] tPD CE HIGH to power-down tDBE Byte enable to data valid – 4.5 – 8 ns tLZBE Byte enable to low impedance [19] 0 – 0 – ns – 6 – 8 ns tHZBE Write Cycle Byte disable to HI-Z [19] [20, 21] tWC Write cycle time 10 – 15 – ns tSCE CE LOW to write end [17] 7 – 12 – ns tAW Address setup to write end 7 – 12 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns [18, 19] tLZWE WE HIGH to low impedance 3 – 3 – ns tHZWE WE LOW to HI-Z [18, 19] – 5 – 8 ns tBW Byte Enable to write end 7 – 12 – ns Notes 16. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 7 on page 7, unless specified otherwise. 17. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 18. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Transition is measured 200 mV from steady state voltage. 19. These parameters are guaranteed by design and are not tested. 20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. The minimum write cycle pulse width in Write Cycle No 2 (WE Controlled, OE LOW) should be equal to sum of tsdand tHZWE. Document Number: 001-91368 Rev. *J Page 9 of 20 CY7C1041G CY7C1041GE Switching Waveforms Figure 9. Read Cycle No. 1 of CY7C1041G (Address Transition Controlled) [22, 23] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 10. Read Cycle No. 1 of CY7C1041GE (Address Transition Controlled) [22, 23] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 22. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL. 23. WE is HIGH for the read cycle. Document Number: 001-91368 Rev. *J Page 10 of 20 CY7C1041G CY7C1041GE Switching Waveforms (continued) Figure 11. Read Cycle No. 2 (OE Controlled) [24, 25, 26] ADDRESS tRC CE tPD tHZCE tACE OE t HZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE t HZBE DATAOUT VALID HIGH IMPEDANCE tLZCE tPU VCC SUPPLY CURRENT ISB Notes 24. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 25. WE is HIGH for the read cycle. 26. Address valid prior to or coincident with CE LOW transition. Document Number: 001-91368 Rev. *J Page 11 of 20 CY7C1041G CY7C1041GE Switching Waveforms (continued) Figure 12. Write Cycle No. 1 (CE Controlled) [27, 28, 29] tW C ADDRESS tS A tSC E CE tA W tPW tH A E W E tB W B H E/ BLE O E tHZOE tH D tS D D A T A I /O D A T AI N V A L ID Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [27, 28, 29, 30] tW C ADDRESS tSCE CE tB W BHE / BLE tS A tA W tH A tPW E WE t LZ W E t HZW E D A T A I /O tS D DATA tH D IN V A L ID Notes 27. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 28. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 29. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 30. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. Document Number: 001-91368 Rev. *J Page 12 of 20 CY7C1041G CY7C1041GE Switching Waveforms (continued) Figure 14. Write Cycle No. 3 (BLE or BHE Controlled) [31, 32, 33] tWC ADDRESS t SCE CE tAW tSA tHA tBW BHE / BLE t PWE WE t HZWE tHD tSD t LZWE DATA IN VALID DATA I /O Figure 15. Write Cycle No. 4 (WE Controlled) [31, 32, 33, 34] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 35 DATA IN VALID tHZOE Notes 31. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 32. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 33. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 34. Data I/O is high impedance if OE = VIH. 35. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-91368 Rev. *J Page 13 of 20 CY7C1041G CY7C1041GE Truth Table CE [36] OE WE BLE BHE H X[37] X[37] X[37] X[37] L L H L L L H L L L I/O0–I/O7 I/O8–I/O15 Mode Power HI-Z HI-Z Power down Standby (ISB) L Data out Data out Read all bits Active (ICC) L H Data out HI-Z Read lower bits only Active (ICC) H H L HI-Z Data out Read upper bits only Active (ICC) X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in HI-Z Write lower bits only Active (ICC) L X L H L HI-Z Data in Write upper bits only Active (ICC) L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC) L X X H H HI-Z HI-Z Selected, outputs disabled Active (ICC) ERR Output – CY7C1041GE Output [38] 0 Mode Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. HI-Z Device deselected or outputs disabled or Write operation Notes 36. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 37. The input voltage levels on these pins should be either at VIH or VIL. 38. ERR is an Output pin.If not used, this pin should be left floating Document Number: 001-91368 Rev. *J Page 14 of 20 CY7C1041G CY7C1041GE Ordering Information Speed (ns) 10 Voltage Range Package Diagram Ordering Code 2.2 V–3.6 V CY7C1041GE30-10ZSXI 51-85087 44-pin TSOP II, ERR output CY7C1041G30-10ZSXI 51-85087 44-pin TSOP II CY7C1041GE30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output CY7C1041G30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm) CY7C1041G30-10BVJXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC CY7C1041G30-10VXI 51-85082 44-pin SOJ (400 Mils) CY7C1041GE30-10VXI 51-85082 44-pin SOJ (400 Mils), ERR output 4.5 V–5.5 V CY7C1041G-10ZSXI 15 Package Type (all Pb-free) Operating Range Industrial 51-85087 44-pin TSOP II CY7C1041GE-10ZSXI 51-85087 44-pin TSOP II, ERR output CY7C1041GE-10VXI 51-85082 44-pin SOJ (400 Mils), ERR output CY7C1041G-10VXI 51-85082 44-pin SOJ (400 Mils) 1.65 V–2.2 V CY7C1041G18-15ZSXI 51-85087 44-pin TSOP II CY7C1041G18-15VXI 51-85082 44-pin SOJ (400 Mils) CY7C1041G18-15BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm) Ordering Code Definitions CY 7 C 1 04 1 G E XX - XX XXX I Temperature Range: I = Industrial Pb-free Package Type: XXX = BVX or VX or ZSX or BVJX BVX = 48-ball VFBGA; VX= 44-pin Molded SOJ; ZSX = 44-pin TSOP II; BVJX = 48-ball VFBGA-JEDEC Compliant Speed: XX = 10 ns or 15 ns Voltage Range: 18 = 1.65 V–2.2 V; 30 = 2.2 V–3.6 V; no character = 4.5 V–5.5 V ERR output Single bit error indication Revision Code “G”: Process Technology – 65 nm Data width: 1 = × 16-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-91368 Rev. *J Page 15 of 20 CY7C1041G CY7C1041GE Package Diagrams Figure 16. 44-pin TSOP II (Z44) Package Outline, 51-85087 51-85087 *E Figure 17. 44-pin SOJ (400 Mils) Package Outline, 51-85082 51-85082 *E Document Number: 001-91368 Rev. *J Page 16 of 20 CY7C1041G CY7C1041GE Package Diagrams (continued) Figure 18. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-91368 Rev. *J Page 17 of 20 CY7C1041G CY7C1041GE Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable °C Degrees Celsius CE chip enable MHz megahertz CMOS complementary metal oxide semiconductor A microamperes I/O input/output s microseconds OE output enable mA milliamperes SRAM static random access memory mm millimeters TSOP thin small outline package ns nanoseconds TTL transistor-transistor logic ohms VFBGA very fine-pitch ball grid array % percent WE write enable pF picofarads V volts W watts Document Number: 001-91368 Rev. *J Symbol Unit of Measure Page 18 of 20 CY7C1041G CY7C1041GE Document History Page Document Title: CY7C1041G/CY7C1041GE, 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-91368 Rev. ECN No. Orig. of Change Submission Date *F 4867081 NILE 07/31/2015 Changed status from Preliminary to Final. *G 4876251 NILE 08/07/2015 Updated Ordering Information: Updated part numbers. *H 4968879 NILE 10/16/2015 Fixed typo in bookmarks. *I 5019226 VINI 11/18/2015 Updated Ordering Information: Updated part numbers. *J 5122043 NILE 02/02/2016 Updated Truth Table. Document Number: 001-91368 Rev. *J Description of Change Page 19 of 20 CY7C1041G CY7C1041GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2014-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-91368 Rev. *J Revised February 2, 2016 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 20 of 20