STMicroelectronics AN2846 The serial current limited termination device Datasheet

AN2846
Application note
SCLT3-8 - guidelines for use in industrial automation applications
Introduction
The serial current limited termination device SCLT3-8 provides 8 inputs and supports the
data transfer of the input states through a limited opto-transistor count thanks to the digital
SPI (serial peripheral interface).
The purpose of this document is to:
■
Help designers to use the SCLT3-8 in basic operations and to allow them to use it easily
in their own applications by describing the SCLT3-8 behavior in detail (Refer also to the
SCLT3-8 device datasheet and to the User guide for the evaluation board
STEVAL-IFP000V1.)
■
Provide basic schematic diagrams
■
Provide information on the thermal behavior of the SCLT3-8 device
■
Offer recommendations to achieve robust SCLT3-8 designs to optimize EMI protection in
accordance with industry standards (IEC 61000-4-2, 4-4, 4-5 and 4-6)
February 2010
Doc ID 15130 Rev 1
1/35
www.st.com
Contents
AN2846
Contents
1
Application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Features of the SCLT3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Current-limited inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3
1.4
2
3
1.2.1
Maximum input current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2
Input characteristics (IEC 61131-2 standard) . . . . . . . . . . . . . . . . . . . . . 6
1.2.3
Digital input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.4
Input signal frequency limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.5
Input state monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Monitoring functions and regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1
VCC monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.2
Power loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.3
Overtemperature detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.4
Internal voltage regulator 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.1
Input state register and parity bit generator . . . . . . . . . . . . . . . . . . . . . 14
1.4.2
Data shift register and control shift register . . . . . . . . . . . . . . . . . . . . . . 15
1.4.3
Digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.4
SPI functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.5
SPI timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal dissipation calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1
Forward inputs polarity case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
Reverse polarity on a single input case . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3
Temperature gradient on the SCLT3 and on the board . . . . . . . . . . . . . . 20
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Basic SCLT3-8 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2
Component definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1
4
2/35
Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Isolation management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
Opto-coupler isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2
Magnetic digital isolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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AN2846
Contents
5
SCLT3-8 link configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
Electromagnetic compatibility (EMC) requirements . . . . . . . . . . . . . . 29
6.1
IEC 61000 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
IEC 61000 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3
IEC 61000 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4
6.3.1
Results on input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2
Results on VC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IEC 61000 4-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Application guidelines
AN2846
1
Application guidelines
1.1
Features of the SCLT3-8
The SCLT is an octal input active termination device designed for 24 V DC high density input
modules used in industrial automation. Each channel circuit terminates the connection
between a high side proximity sensor and the I/O module.
The advanced features of the SCLT3-8 compared to the basic CLT3-4BT6 device are:
●
SPI for digital output count reduction
●
Doubling of input terminations: 8 inputs compared to 4
●
Input state monitoring by LEDs from the process section
●
Undervoltage alarm detection of the power bus
●
Power bus loss detection
●
5 V supply source available for external driving circuits like opto-couplers or magnetic
isolators
●
Overtemperature detection
●
Checksum data transmission through SPI for better data transfer integrity
The SCLT3-8 also features an input overvoltage protection. This input protection makes this
device robust against electromagnetic interference as defined in IEC 61000-4-x standards:
ESD, fast transient bursts, and voltage surges.
It is housed in a very low RTH exposed pad, surface mount, HTSS0P38 package to reduce
the circuit board size and the cooling pad.
Figure 1 shows the schematic block diagram for the device.
Figure 1.
Schematic block diagram
IN1
MISO
LD1
8 lines
Input
state
register
/MISO
8 lines
Input
limiters
Shift
Prog.
digital
filters
Shift
SCK
/CS
SPM
MOSI
Parity
bits
gen.
Current
reference
OSC
Oscillator
4 lines
Overtemperature
alarm
Ctrl
shift
register
Power
reset
VDD
Power
supply
Undervoltage
alarm
VCS
4/35
COMS
8/16
Bits
LD8
DVR
VDD
MOSI
8 Lines
IN8
REF
Write
Transfer
logic
protection
and
input current
8 lines
COMP
Data
shift
register
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VDD
VC
AN2846
Application guidelines
The SCLT3-8 has been designed to run with SPI protocol CPHA = 0 and CPOL = 0. The frame
format is 16 bits or 8 bits long according to SPM pin level. When SPM is grounded, 16 bits
are transmitted - 8 input data bits and 8 control bits. When SPM is connected to VDD only
the 8 input data bits are transmitted.
Table 1 defines the significance of the16 bits. Bit 15 is the most significant bit. Detailed SPI
functionality is described in Section 1.4.
Table 1.
16-bit frame definition
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit09
Bit08
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
Bit07
Bit06
Bit05
Bit04
Bit03
Bit02
Bit01
Bit00
/UVA
/OTA
PC1
PC2
PC3
PC4
0
1
Data bits
Control Bits
1.2
Current-limited inputs
1.2.1
Maximum input current setting
All internal bias currents sources and particularly the input current limiter are defined by the
reference resistor connected to pin REF. A 15 kΩ resistor will assure a typical input limited
current of 2.35 mA (see Figure 2). The typical limited input current ILIM is given by the
formula:
I LIM = 30
Figure 2.
·
V BG
( R REF + 1 . 5 k )
with typi cal VBG = 1 . 25 V
Current limiter diagram
ILIM
1 : 20
1 : 1
LED
VBG=1.25V
2
:
3
LED_ON
1.5k
REF
COMs
R
REF =15k
The technology used allows a very low current dispersion according to the different
channels (less than 10%). The reference voltage VBG is also compensated over the junction
temperature range from -25 °C to 150 °C enabling a good stability of the limited current (see
Figure 3).
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Application guidelines
Figure 3.
AN2846
Limited current versus junction temperature
2.6
Ilim (mA)
IN1
Vcc = 24 V, Vi = 11 V
IN2
2.5
IN3
IN4
IN5
2.4
IN6
IN7
2.3
IN8
2.2
Junction temp (°C)
2.1
-25°C
25°C
125°C
150°C
Figure 4 shows the ILIM trend versus RREF. according to the input current setting and
therefore the dissipated power, the SCLT3-8 should be cooled with a sufficient copper heat
sink area (see Section 2)
Figure 4.
Typical limiting input current versus RREF
Ilim (mA)
8.0
Test conditions:
ILIM versus RREF
VCC = 24 V, VI = 24 V
7.0
6.0
5.0
4.0
3.0
RREF (k)
2.0
3
5
3.9
1.2.2
7
9
11
9.1
13
15
15
Input characteristics (IEC 61131-2 standard)
According to the IEC 61131-2 standard and referring to type 3, when the input current is less
than 1.5 mA the output circuit passes all the input current, keeping the monitoring LED off
and transmits a low level state to the input state register.
When the module input voltage VI, taking into account the 2.2 kΩ input resistor, is higher
than 11 V (that is, the SCLT3-8 input voltage VIN is higher than 5 V) the monitoring LED is
on and the circuit transmits a high level state to the input state register.
Figure 5 gives the input characteristics and operating regions of type 3, defined in the
IEC 61131-2 standard, and the typical SCLT3-8 input characteristic.
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AN2846
Application guidelines
Input characteristic according to IEC 61131-2 type 3
VIN (V)
Figure 5.
ON Region
ON
Transition Region
ON
11V
11V
SCLT3-8 (including R IN)
input characteristic
OFF
OFF
OFF Region
5V
5V
OFF
0.1
1.5
IIN (mA)
2.0
ILIMIT
Current limited inputs allow reduced power dissipation into the device as well as reduced
power needed by the external supplies. A typical application circuit schematic is shown in
Figure 31 in the application section.
Figure 6 displays the SCLT3-8 input stage configuration and its typical input threshold
voltages. Low frequency triangular waveform as the input voltage has been used to better
highlight the voltage thresholds. Input current (IIN) and voltage across the LEDs are also
displayed in Figure 6. The VLED wave shape shows clearly the on-off states of the SCLT3-8.
Figure 6.
Input stage
RIN
2.35 mA
VTH
VIN_ON = 9.5 V
V IN_OFF =8.0 V
V
IN
IIN
VI
VI: 2V/div
INPUT STATUS
DIGITAL
FILTER
V IN : 2V/div
I LIM = 2.35 mA
LED
I IN: 1mA/div
V LED
Input stage configuration
Typical input voltage thresholds
With RIN = 2.2 kΩ, the typical VI_ON and VI_OFF threshold voltages are respectively 9.5 V
and 8.5 V, consistent with the 11 V min. and 5 V max specified in the IEC 61131-2 standard.
The hysteresis (1 V) improves the input noise immunity.
The module input thresholds are the results of drop voltage across the input resistor RIN,
into which flows the input current IIN, and the SCLT3-8 input thresholds VTH_ON and
VTH_OFF.
The input current limiter is activated typically when VIN = 3.7 V, before the VTH_ON threshold
is reached.
In all cases the following formula can be applied:
V I = R IN × I IN + VIN
When the input current limiter is activated, the formula becomes:
V I = R IN × I ILIM + V IN
The typical module input threshold voltage can be calculated as follow:
VMath
= R IN × I ILIM
+ VVTH_ON
1.1.5
IN _ONComposer
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Application guidelines
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The proposed RIN value of 2.2 kΩ has been calculated to meet the IEC 61131-2 threshold
requirements. Users can set their own particular application threshold voltages by applying,
in the formula given above, the VIN they want to achieve and find the corresponding RIN
value. Take note, the higher the RIN, the better will be the immunity against voltage surges.
A particular useful application is when an input type 2 is needed. Figure 7 shows the
solution of connecting RIN7 and input RIN8 = 1.5 kΩ in parallel and tuning the ILIM with
RREF = 9.1 kΩ to get 3.5 mA (see Figure 4) in each input branch. Of course corresponding
bits (B14, B15) will be set together at the right state according to the level applied at the
common input. Unused LED outputs must be grounded to maintain the flow of the
current in its corresponding chanel.
Figure 7.
IN7 and IN8 parallel wired for type 2
R IN = 1.5k Ω
R REF= 9.1kΩ
IN1
Type 3 inputs
IN2
RREF
IN3
LED1
IN4
LED2
LED3
Type 2 inputs
IN5
LED4
IN6
LED5
IN7
LED6
IN8
LED7
LED8
The different threshold voltages and the ILIMIT = 7.0 mA are shown in Figure 8 below.
Figure 8.
Threshold voltages - type 2 configuration using two inputs in parallel
V (2V/div)
I
V
I_ON
= 9.9 V
V I_OFF = 8.4 V
V
I
IN
I LIMIT = 7.0mA
(5mA/div)
V
8/35
IN (2V/div)
LED
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AN2846
1.2.3
Application guidelines
Digital input filter
Input parasitic disturbances can be removed by the programmable input digital filter. It is
based on an RC oscillator, a divider and a two step filter (see Figure 9).
Figure 9.
Digital input filter.
IN<1:8>
POR
REF1V Oscillator OSC Divider
OSC period = 1.2 µ s
CKF filter_2step
OUT<1:8>
OSCR
DVR
R OSC = 51 k
The internal capacitor value is typically 10 pF. The oscillator resistor is connected externally
on pin ROSC. The clock divider is set at 8 when the pin DVR is connected to GND or at 64
when it is connected to VDD. The two step filter validates the input voltage when it sees at
least three rising edges as shown in Figure 9. The delay time is between 2 · tOSC and
3 · tOSC. A wide filter time range, tFT, can be set by using the couple ROSC and DVR as
shown in below in Figure 10.
Figure 10. Minimum tFT versus ROSC
600
tFT (µS)
4000
DVR=8
500
DVR=64
3000
400
2000
300
200
1000
100
0
tFT (µS)
Rosc(kΩ)
0
500
1000
Rosc(KΩ)
0
1500
0
500
1000
1500
The user can also choose a particular typical filter time, tFT, by calculating the corresponding
ROSC value from the formula:
Math Composer 1.1.5
t FT
1
1
R OSC =
×
×
-12
2
DVR
23 . 5 × 10
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Application guidelines
1.2.4
AN2846
Input signal frequency limitation
The maximum frequency transmitted trough the current limited inputs is limited by 3 factors:
1.
The input digital filter, which cuts undesirable frequencies. ROSC set to 51 kΩ and
DVR connected to GND ensures that the input signal has to be at a stable level for
more than 20 µs to be taken into account. This allows a maximum input frequency of
25 kHz. It can be reduced to 130 Hz using the combination of ROSC = 1.5 MΩ and DVR
connected to VDD.
2.
The input capacitors CIN are used to increase the EMI immunity filter of the input
signal. RIN = 2.2 kΩ and CIN = 22 nF ensures a 3.2 kHz low pass filter.
3.
The SPI sampling effect - the input states are taken into account at each /CS fall (see
Section 1.4.4). This achieves a sampling of inputs at the /CS frequency, as shown in
Figure 11. The input states will be correctly transmitted if the sampling mode meets the
Shannon equation:
F / CS = 2 • F Input
with F/CS =
1
t /CS
: with t /CS the
/CS
signal period
with F Input = max input frequency
Figure 11. Sampling effect
t INPUT
Low level capture
missed
High level capture
missed
Current limited Input signal
/CS
t /CS
As the /CS period is dependant on the frame length, Table 2 below gives some useful
combinations of SCK frequency signal, frame length and current limited input frequency.
Table 2.
Input frequency versus SCK and length frame
FSCK
0.1
1.0
2.0
MHz
Frame length
8
16
32
64
8
16
32
64
8
16
32
64
bits
t/CS
80
160
320
640
8
16
32
64
4
8
16
32
µs
3.125 1.56
0.78
62.5
31.25
15.6
7.8
125
15.6
kHz
Fcurrent limited input
10/35
6.25
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62.5 31.25
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1.2.5
Application guidelines
Input state monitoring
The state of each of the 8 monitoring LEDs is an image of the 8 filtered input states. All the
monitoring LED cathodes have to be connected to ground. In the on state a current of ILIM
reduced by 0.15 mA is available for each LED. In case of a LED not being used, the LED
output pin must be connected to the ground COMP to allow the input current to flow back to
the ground.
The LEDs must be chosen with a VF voltage less then 2.7 V (at minimum operating
temperature -25 °C).
1.3
Monitoring functions and regulator
1.3.1
VCC monitoring
The power bus voltage connected to VCC is sensed by the VCS pin through a resistor bridge.
The VCS threshold voltage is typically 1.25 V with a hysteresis of 100 mV. Designers can
easily set their own alarm detection voltage by an appropriate resistor bridge (see
Figure 12) using the formula:
VCC _ min = V CS (1 +
RS
R PD
)
Figure 12. UVA comparator
VCC
RS
VDD
VCS
UVA
1ms delay
R PD
VBG =1.25V
COM
For example, the resistor bridge consisting of RS = 1.5 MΩ and RPD = 120 kΩ produces UVA
activation when VCC drops below 17 V. The UVA activation has no effect on SCLT3-8
behavior but the information is transmitted trough the SPI bus by setting bit 7 to low state in
the control bits register (see Figure 13 and Figure 14).
To eliminate any short voltage disturbances that could trigger the UVA, a 1 ms delay circuit
has been inserted in the output line of the UVA comparator.
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Application guidelines
Figure 13.
AN2846
VCC = 24 V, UVA bit not activated
V
CC
Figure 14. VCC = 16 V, UVA bit activated
= 24 V
V
CC
MISO
MISO
SCK
SCK
/CS
/CS
1.3.2
= 16 V
Power loss detection
For a greater voltage drop on VC, a power supply loss detection has been added. This
immediately sets MISO output at low level state when VC is below 8 V, as shown in
Figure 15 and Figure 16. The MCU can then interpret that if all bits are equal to 0, this
means that VC is too low.
Figure 15. Communication stops for VC < 8 V
VC
Figure 16. Communication resumes for
VC > 8.1 V
8.0 V
8.1 V
/CS
/CS
SCK
SCK
MISO
1.3.3
MISO goes to L
MISO
Overtemperature detection
When the junction temperature exceeds 150 °C an overtemperature alarm sets the MISO
bit 6 at low state in the control bits register. The SCLT3-8 remains operational. The MCU
receiving the alarm has to take the corrective actions. The alarm will be reset when the
junction temperature falls below 135 °C.
1.3.4
Internal voltage regulator 5 V
The input of this voltage regulator is internally connected to the VC pin. The voltage
regulator supplies the digital part of the SCLT3-8 and therefore it defines the high digital
level. It also supplies the sourced current available at pin MISO. It can also supply
application needs (such as opto-couplers and micro transformers) through pin VDD. Its total
current capability is 9 mA for a 3% voltage drop on VDD (see Figure 17).
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Application guidelines
Figure 17. Regulator output voltage
5.1
Vdd versus Idd
Vdd (V)
5.0
Vdd -3%
4.9
4.8
4.7
4.6
Idd (mA)
4.5
9.0
Figure 18 shows the schematic diagram of a solution for applications where greater current
is needed. The bypass transistor allows extra current while maintaining a 5 V regulated
voltage (see Figure 19).
Figure 18. VDD booster schematic
Figure 19. Load regulation with VDD booster
R E 2N2907A
VCC
5.100
RC
VDD
IDD
IRC
VDD (V)
VDD
5.050
5.000
SMAJ30A
VDD
VC
VCS
SCLT3
IN1
IN2
IN3
IN4
4.950
4.900
RREF
LED 1
LED 2
LED 3
4.850
IDD (mA)
4.800
0.00
5.00
10.00
15.00
20.00
25.00
The proposed circuit allows a 25 mA current load capability with a VDD regulation <2%. An
additional input protection device, like SMAJ30A, is needed to comply with voltage surges
because RC has to be reduced to limit the voltage drop across it.
The dissipated power in the bypass transistor PZT2N2907A is 550 mW.
Components used:
1.4
●
PZT2N2907A (SOT223 with 1 cm2 copper area)
●
RC = 330 Ω (1/8 W), RE = 51 Ω (1/8 W)
SPI functional description
Three registers (refer to Figure 1) are used to transfer input data and control data to the
16-bit data frame. The data frames are transmitted through four interface signals: /CS, SCK,
MOSI, and MISO.
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Application guidelines
1.4.1
AN2846
Input state register and parity bit generator
After filtering, the 8 input termination states are stored in an 8-bit input state register. Its
content is an image of the filtered input states in real time.
Filtered
Input
states
Input state register
Figure 20. Input state register and parity bit generator.
Parity
bits gen.
8 lines
The SCLT3-8 has been designed to help diagnose incorrect data transmission. The four
parity bits generated by the parity bit generator are computed according to the input states
register content. They are updated each time the input state register content changes.
The parity bit 5 of PC1 register controls the 1 to 8 input data states; PC2-bit 4 controls inputs
5 to 8: PC3-bit 3 controls inputs 1 to 4;PC4-bit 2 controls inputs 3 to 6 according to the logic
equation:.
http://www.mathcomposer.com
PC n = 1 if
INPUTstate = even, 0 if odd.
∑
See example in Figure 21.
The decoding of all the parity bit results will help the microcontroller detect the possible
corrupted pair of bits occurring during the transmission.
1N8
1N7
1N6
1N5
1N4
1N3
1
0
0
1
1
0
PC1
PC2
PC3
PC4
1
2
3
4
Parity
8 lines
Bbits gen.
From
input
8 lines
state
filter
Input state register
Figure 21. Parity bit generation example.
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1N2
0
1N1
1
AN2846
1.4.2
Application guidelines
Data shift register and control shift register
Data and control shift registers are each 8 bits long. At each /CS falling edge all the data is
frozen and the 8 bits of the input states register are transferred to the data shift register (bits
8 to 15) while the control bits, consisting of four parity bits, overtemperature alarm bit,
undervoltage alarm bit and the stop bit, are transferred to the control shift register (bit 0 to
7).
The two last bits (bit 1 and bit 0) are always set respectively to 0 and 1 indicating the end of
data frame except in power loss case where all bits are set to 0.
Bit 15 will be the MSB and Bit 0 the LSB.
Parity
bits gen.
4 lines
Data shift register
Control shift register
8 Lines
8 lines
Input state register
Figure 22. Data and control data shift registers.
Overtemperature
alarm
1.4.3
Undervoltage
alarm
Digital inputs and outputs
These digital pins are involved with the SPI:
●
/CS: Chip select input
●
SCK: Serial clock input
●
MISO: Master-in slave-out output
●
/MISO: complementary MISO state
●
MOSI: Master-out slave-in input (connected to ground when not used)
To improve the immunity of the digital inputs against noise, the digital inputs /CS, SCK and
MOSI have been designed to use a Schmitt trigger configuration. Each input is connected to
VDD through a high impedance pull up resistor to set the input at high level state when no
input signal is applied. Protection diodes are inserted with these pull-up resistors to prevent
the ESD reaching the VDD. The digital input diagram is given in Figure 23.
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Application guidelines
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Figure 23. Digital inputs diagram.
VDD
/CS
SCK
MOSI
COM S
The digital output signal MISO is delivered through a high-Z impedance buffer able to
source or sink 3 mA.
Figure 24. Digital output MOSI
VDD
M1
UVA
M2
EN
MOSI
COM S
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AN2846
1.4.4
Application guidelines
SPI functionality
At the /CS falling edge the following operations are done:
●
The input data states, parity and control bits are frozen and stored in the data and
control shift registers.
●
The MSB (Bit 15) is shifted out first to MISO.
The SCLT3-8 data transfer uses SPI protocol with CPOL = 0, CPHA = 0 conditions. This
means the SCK signal must be at low level state when the /CS is falling (communication
starts). In this case the MSB (bit15) is transferred first from MISO as soon as /CS falls, and
all the remaining bits are transferred at each SCK falling edge.
Figure 25. SCK and /CS synchronization security
/CS
/CS
SCK
SCK
Bit14
MISO
Bit14
MISO
SCK is high when /CS falls
SCK is low when /CS falls
For more flexibility the SPI protocol has been enhanced and takes into account the case
where SCK signal is at high level when /CS falls to low level. In this case, as previously the
MSB will be present at MISO pin at the /CS falling edge but the following bit will be available
only at the second SCK falling edge.
In both cases the rule is: a rising SCK edge must occur after the falling /CS edge to validate
the first SCK falling edge. Otherwise the state change duration of MISO may be too short to
correctly trigger the transmission of the MSB (bit 15) (see Figure 25).
In normal operation the two last bits are 0 and 1 indicating the end of the transmission.
The data transmission runs as long as the /CS is at low state. As soon as /CS returns to
high level, the data transfer is disabled and the MISO output is in high impedance - hi-Z.
When MOSI input is used in daisy chain operation, the inputs are captured at each SCK
rising edge and loaded into the shift register. Loaded data has no effect on the SCLT3-8.
Figure 26. 16-bit transmission example
/CS
SCK
MISO
1 0 1
1
1
1 1
B15
1 1
1
0 0 1
1
B8 B7
Input data bits
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B0
Control bits
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Application guidelines
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Figure 26 shows a 16-bit transmission example when the application is running in good
conditions:
1.4.5
●
Application is correctly supplied: /UVA, Bit 7 not activated
●
SCLT3-8 junction temperature less than 150 °C: /OTA, bit 6 not activated
●
Correct transmission: parity bits in accordance with input states
SPI timing definition
The four SPI signals involved: /CS, SCK, MOSI, MISO are described in Figure 27. A fifth
/MISO pin output signal is also present.
The typical SCK frequency is 1 MHz, but the SCLT3 can run at up to 2 MHz. The other more
important timing parameters are:
●
tD: Delay time. This is the delay time of MISO between SCK falling edge and MISO
change.
●
tS: Set up time. This is the minimum holding time of MOSI input data for its capture
before the SCK rising edge.
●
tH: Holding time. This is the minimum holding time of MOSI input data after the SCK
rising edge for its correct capture.
The most important rules to meet to perform a correct data transmission are:
●
tCL > tD + tS
●
tCH > tH.
Figure 27. SPI timing definition.
tC
/CS
t DT
1
SCK
2
t CL
t LD
16
t CH
t HC
tD
t DIS
MISO
MSBS
LSBS
tA
tS
tH
MOSI
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MSB M
AN2846
Thermal dissipation calculation
2
Thermal dissipation calculation
2.1
Forward inputs polarity case
In reference to the application schematic defined in Figure 31, the dissipated power into the
SCLT3-8 PSCLT can be calculated as following:
Consider the worst case where all inputs are connected to 30 V.
PSCLT = P1 - P2
where:
P1 is the total power delivered by the supplies
P2 is the total power dissipated by the external components
P1 = VCC · (IC + IDD + 8 · ILIM)
External components are: RIN, RC, LEDs, regulator load
Power dissipated by input resistors = 8 · RIN ·ILIM2
Power dissipated by supply resistor = RC · (IC + IDD)2
Power dissipated by LEDs = 8 · VLED · ILED
Power supplied by the VDD linear regulator = VREG · IDD
The PSCLT = 560 mW
Assuming:
VCC = 30 V, ILIM = 2.35 mA, RIN = 2.2 kΩ, RC = 1.0 kΩ, VLED = 2 V, VDD = 5 V, IDD = 7MA.
Note:
The current flowing through the LED is almost the same as ILIMIT. The difference is about
125 µA used to bias the input circuit device.
With the above mentioned conditions and using copper area of 1cm2 as heat sink, the
SCLT3-8 junction temperature will be around 120 °C with an ambient temperature of 85 °C.
Figure 28 below shows the RTH_JA variations versus the heat sink area on a 35 µm FR4
epoxy single side board.
Figure 28. RTH_JA versus copper area
Rth(j-a) (°C/W)
HTSSOP38
SCLT
120
100
80
60
40
20
SCU (mm²)
0
0
20
40
60
80
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100
120
140
160
180
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Thermal dissipation calculation
2.2
AN2846
Reverse polarity on a single input case
Each input resistor can be connected to a reverse polarity down to -30 V. This case
corresponds to a connection mistake or a reverse biasing that is generated by the
demagnetization of a monitored inductive solenoid. The involved input can withstand a high
reverse current up to 20 mA. The corresponding state transmitted is low level. The other
inputs remain operational.
The power dissipated into a reverse polarized input is low, but attention has to be paid to
power dissipation into the input resistor which sustains almost all the reverse voltage.
Pdis_RIN
=
( V I - 0. 7 ) 2
R IN
Pdis_RIN = 390 mW for VIN = - 30 V and R IN = 2.2 k Ω
2.3
Temperature gradient on the SCLT3 and on the board
Figure 29 shows the case top temperature when SCLT3-8 dissipates 600 mW, which
corresponds to maximum supply case with VCC and all module inputs at 32 V. The heat sink
is 100 mm2, and the ambient temperature is 25 °C. In this example the maximum case top
temperature reaches 68 °C. The case top temperature is a good indication of the junction
temperature, which can be estimated using thermal analysis techniques.
Figure 29. Case top temperature
RC = 1.1 kΩ
RIN = 2.2 kΩ
Lens: G1
(Board paint in black)
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Thermal dissipation calculation
Figure 30 shows the temperature gradient of the SCLT3-8 board with the same supply
conditions as above. Almost the totality of the power is concentrated around the SCLT3-8
and its heatsink. No particular temperature hot spot can be detected on the board.
Figure 30. Temperature gradient of the board
Profil 1
Profil 1
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Application circuit
AN2846
3
Application circuit
3.1
Basic SCLT3-8 board description
The basic electrical schematic diagram using a single SCLT3-8 fulfills the requirements
defined in the IEC 6131-2 standard. It is easy to duplicate this configuration to meet more
complex applications using many inputs and several SCLT3-8s.
The major settings are:
●
Type 3 configuration
●
16-bit frame (SPM grounded)
●
16 µs digital input filtering (ROSC = 51 kΩ, DVR grounded)
Figure 31. Type 3 application diagram
33n
DVR
VDD
OSC
51k
470p
SPM
33n
/CS
220
220
1.0k
VC
SCK
1.5M
120k
VCS
MOSI
22n
COMP
/MISO
22n
IN1
MISO
22n
IN2
COMS
22n
IN3
RREF
2.2k
2.2k
J1
COMP
2.2k
IN4
2.2k
COMP
LED1
2.2k
IN5
LED2
2.2k
22n
IN6
LED3
22n
IN7
LED4
IN8
LED5
COMP
LED6
22n
2.2k
2.2k
LED7
SCLT3-8
22/35
LED8
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10n
15k
470p
J2
AN2846
3.2
Application circuit
Component definitions
The reference resistor RREF tolerance gives the accuracy of the input limiters. 1% accuracy
is suggested.
The typical type 3 SCLT3-8 application uses RREF = 15 kΩ and RIN = 2.2 kΩ. Type 2 can be
also achieved as shown in Table 3.
The input MELF resistors are used to sustain high voltages occurring during surge tests.
Table 3.
Type 2 and 3 configurations
Type 3
Type 2
Unit
RREF
15
3.9
kΩ
RIN
2.2
0.75
kΩ
Typical ILIMIT
2.3
6.5
mA
Using type 2, the power dissipated by the SCLT3-8 reaches 1W with VI = VCC = 24 V. A
copper heat sink area of 1 cm2 will set TJ at 150 °C with an ambient temperature of 65 °C.
The RC value has to be chosen with attention. The voltage drop across this resistor is the
product of SCLT3-8 supply current and any load current supplied by VDD: regulator output
current and sourced MISO current. The resulting voltage VC must be in any case above the
8 V activation threshold to avoid a spurious power loss detection. 1 kΩ meets this
requirement and allows 2 kV of voltage surge.
The 22 nF input capacitors are used to improve the noise immunity of the whole module.
Their function is to filter the high frequency electrical noise, and to secure the off state of the
module.
Adding a 33 nF capacitor on VC pin ensures high immunity against electrical noise such as
that described in the IEC 61131-2 standard.
ROSC = 51 kΩ and pin DVR grounded set the input digital filter to eliminate pulse widths
below 20 µs.
A 33 nF capacitor connected on VDD output ensures a good output of the voltage regulator.
The LEDs must be chosen according to their input diode drop voltage. LED outputs can
drive LEDs with forward voltage up to 2.7 V.
Low pass RC filters have been inserted into digital inputs /CS and SCK to improve the
immunity against fast transient bursts. R = 220 Ω and C = 470 pF give a good compromise
between immunity result and SCLT-3 speed which can run up to 1 MHz.
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Application circuit
3.2.1
AN2846
Footprint
The footprint given in Figure 32 allows ground connection optimization of COMP and
COMPS. The 1 cm2 heat sink area defines an RTH-JA of 80 °C/W.
Figure 32. Foot print (not to scale)
0.65
0.4
0.25
3.425
1.35
2.575
5.00
1.30
SCOPPER = 100 mm²
3.50 Copper thickness : 35µm
6.10
8.80
11.35
0.6
0.6
Pin 1
Package footprint
24/35
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Additional copper for extra-cooling
AN2846
4
Isolation management
Isolation management
There are two solutions proposed for galvanic isolation between the SCLT3-8 and the
microcontroller.
Opto-coupler isolation
●
Magnetic digital isolation
Opto-coupler isolation
The first solution is given by opto-couplers which must run at a bit rate compatible with the
SCK frequency and meet SCLT3-8 requirements in terms of consumption.
HCPL4506 or HCPL0466 can be a solution to drive a single SCLT3-8 for a 1 MHz
application.
Figure 33. Single SCLT3-8 and HCPL4506 or 0466
3k Ω
VDD
VCC
VC
/CS
SCK
MOSI
/MISO
MISO
HCPL4506
or 0466
750Ω
/CS
3k Ω
4.1
●
750 Ω
SCK
VDD2
1 kΩ
3 kΩ
MISO
If several SCLT3-8s are used, more current is available through VDD pins to supply the optocouplers. The different outputs VDD can be tied together but, low serial resistors (22 Ω) must
be inserted to balance the different regulated output voltages. The load current is shared
between the two SCLT3s and allows the voltage drop reduction across each RC resistor.
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Isolation management
AN2846
Figure 34 shows two SCLT3s in daisy chain configuration using ACPL-K73L (dual) and
ACPL-W70L (single).
Figure 34. Two daisy-chained SCLT3-8s and ACPL/K73L/W70L
VDD
22Ω
ACPL-K73L
750Ω
750 Ω
VCC
VC
VC
/CS
SCK
MOSI
/MISO
MISO
HCPLK73L
HCPW70L
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SCK
/CS
SCK
MOSI
/MISO
MISO
VDD
VCC
/CS
22 Ω
VDD2
1 kΩ
MISO
ACPL-W70L
Doc ID 15130 Rev 1
AN2846
4.2
Isolation management
Magnetic digital isolator
The second solution is given by digital isolators. The triple-channel digital isolator
ADUM1301 is convenient for such an SCLT3-8 application. The sending channels VIA and
VIB are used for /CS and SCK signals while receiving channel VIC is used for MISO signal.
The VDD pin of SCLT3-8 can easily deliver the typical supply current needed by VDD2, which
is around 2.7 mA at 2 MHz as shown in Figure 35.
Figure 35. Digital isolator
VDD
VCC
VC
/CS
SCK
MOSI
/MISO
MISO
VDD 2
VDD1
GND2
GND1
VOA
VOB
VIA
VIB
VIC
VOC
NC
NC
VE2
VE1
GND2
GND1
ADuM1301
SCLT3 - 8
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SCLT3-8 link configurations
5
AN2846
SCLT3-8 link configurations
Parallel and daisy chain configurations can be implemented using SCLT3-8 or other devices
compatible with a serial peripheral interface.
In parallel mode the microcontroller selects the SCLT-8 with which it wants to communicate
by setting the corresponding /CS to low state as long as the communication lasts. The
microcontroller should be able to control as many /CS pins as SCLT-8s it wants to address.
While in daisy chain configuration the microcontroller commands at the same time all the
SCLT3-8s connected in series. The data must transit from SCLT3-8 to SCLT3-8 going out
from the MISO pin, going in through MOSI pin till reaching the last one connected to the
microcontroller. Considering n SCLT3-8s connected in daisy chain, the microcontroller has
to read n times 16 bits and the communication time is proportional to n times 16 bits.
Figure 36. Daisy-chain configuration
MASTER SPI
Figure 37. Parallel configuration
SCLT1
MASTER SPI
SCLT1
SCK
SCK
SCK
SCK
MISO
MISO
MISO
MISO
MOSI
MOSI
MOSI
MOSI
/CS
/CS1
/CS
/CS1
/CS2
SCLT2
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SCLT2
SCK
SCK
MISO
MISO
MOSI
MOSI
/CS
/CS2
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6
Electromagnetic compatibility (EMC) requirements
Electromagnetic compatibility (EMC) requirements
The SCLT3-8 has been designed to withstand electromagnetic interference as specified in
the IEC 61131-2 standard. This international standard gives all the requirements and
conditions for tests that must be performed on the programmable logic controllers (PLC) and
their associated peripherals. IEC 61000 4-2, 4-4, 4-5 and 4-6 standards define test
methods.
The current limited inputs and supply pins of SCLT3-8 are protected against high voltage
disturbances by a clamping circuits that are grounded to the common pin COMP. Combined
with serial input resistances RIN or RC (see Figure 38). These clamping circuits are effective
against ESD (±8 kV contact), fast transient burt (±2.5 kV), and voltage surge (±1 kV).
Figure 38. Protection clamping circuits
RIN
IN1
IN2
VCC
IN3
VC
Supply
39V
circuit
IN4
IN5
IN6
IN7
COM P
COMS
IN8
39V
39V
39V
39V
Input
39V
circuit
39V
39V
39V
COM P COM S
6.1
IEC 61000 4-2
This standard specifies the behavior of the device when subjected to electrostatic
discharges. The discharges must be applied to operator accessible parts. This means that
these tests have to be performed on each connector pin. The required levels are: air
discharge: ±15 kV, contact discharge: ±8 kV.
The system must continue to operate as intended after the discharge. Temporary
degradation of the performance is acceptable during the test, but the system must recover
by itself after the test (B criterion).
All SCLT3-8 pins are ESD protected.
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Electromagnetic compatibility (EMC) requirements
6.2
AN2846
IEC 61000 4-4
This standard specifies the behavior of the device when subjected to a fast transient burst.
The fast transient burst must be applied on all the input pins of the system. A capacitive
clamp-coupling device is used as described in the IEC 61000-4-4 standard. The required
sustainable burst voltage level is 2.5 kV. The system must continue to operate as intended.
No temporary degradation of the performance is acceptable during the test (A criterion).
New test methodology has been set up to check the frame integrity against fast transient
bursts. The need to monitor each bit level leads to using a scope isolated from the test
bench through optic fibers. The generation of /CS and SCK input signals are also isolated
through the same way as shown in Figure 39. Current and voltage level adaptation is done
through an optical fiber interface (OFI).
Long frames history can be stored in the monitoring scope for an easier detection of
disrupted bits.
The SCLT3-8 immunity has been increased by adding RC filter networks connected on /CS
and SCK input pins. But these RC filters act as low pass filters and limit the maxim data
transfer speed. For example the filter made of R = 220 Ω, C = 470 pF allows a 1 MHz
transmission frequency and ensures device FTB immunity up to 4 kV.
Table 4.
Speed - FTB immunity compromise
RC Values
SCK speed
FTB immunity
220 Ω - 220 pF
2 MHz
3 kV
220 Ω – 470 pF
1 MHz
4 kV
The test configuration is shown in Figure 39.
Figure 39. Two supplies configuration
Bat1
Generator
FTB
generator
Bat2
Capacitive clamp
SCLT3-8
OFI
/CS
SCK
MISO
/CS
SCK
MISO
Fiber optic cable
30/35
Doc ID 15130 Rev 1
OFI
/CS
SCK
MISO
Scope
AN2846
Electromagnetic compatibility (EMC) requirements
Figure 40 shows the output MISO behavior is not disturbed during fast transient bursts. The
FTB signal has been captured through an antenna to observe where the bursts act.
Figure 40. Output MISO behavior during fast transient bursts
+ 4.0 kV
CS
/SCK
FTB
MISO
FTB 200 µs =
= 5 kHz
Figure 41. Test bench
HAEFELY FTB generator
Bat2
SCLT3 board
Bat1
OFI
Capacitive clamp
Fiber
optic
cable
SCLT3 inputs, Gnd
Doc ID 15130 Rev 1
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Electromagnetic compatibility (EMC) requirements
6.3
AN2846
IEC 61000 4-5
This standard specifies the behavior of the device when subjected to voltage surges applied
on all input pins of the system. For all analog inputs, the coupling method is a 42 Ω serial
resistance and a 0.5 µF capacitor. For the DC power line, the coupling is 2 Ω resistor, and
18 µF capacitor. The required voltage surge levels are:
●
1 kV for the input pins with RIN = 2.2 kΩ,
●
2.5 kV for the pin VC when RC = 2.2 kΩ or 1 kV when RC = 500 Ω.
The system must continue to operate as intended. Temporary degradation of the
performance is acceptable during the test, but the system must recover by itself after the
test (B criterion).
6.3.1
Results on input pins
When a positive surge voltage of 1 kV is applied on the input resistor RIN, the input active
clamp protects the SCLT3-8 input and limits the input voltage at 40 V. The input current
reaches 0.45 A.
When a negative voltage surge is applied the input diode is biased in forward mode and the
current is 0.45 mA (see Figure 42)
Figure 42. VIN and IIN behavior
+ 1.0 kV
V surge
Vsurge
0.5kV/div
0.2kV/div
-1.0 kV
0.45A
IIN
0.2A/div
IC
0.2A/div
40V
0.45A
VIN
VC
1V/div
20V/div
Positive voltage surge
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1V
Negative voltage surge
AN2846
6.3.2
Electromagnetic compatibility (EMC) requirements
Results on VC pin
When a positive or negative surge voltage of 1 kV is applied on the supply resistor RC, the
VC active clamp protects the SCLT3-8 input and limits the input voltage at 40 V. The current
reaches 0.45 A.
The wave shapes are similar to the previous ones as shown in Figure 43.
Figure 43. VC behavior with RC = 2.2 kΩ
V surge
-0.5kV/div
+1kV
V surge
-1kV
0.5kV/div
0.45A
IC
IC
0.2A/div
0.2A/div
0.45A
40V
VC
1V/div
VC
20V/div
Negative voltage surge
Positive voltage surge
6.4
1V
IEC 61000 4-6
This standard specifies the behavior of the device when subjected to conducted radio
frequency interference in the range 150 kHz to 80 MHz. The RF signal, 80% modulated by
1 kHz sinusoidal waveform, is injected at the inputs IIN and VCC through a coupling device
network (CDN). The required level defined into IEC 61131-2 is 3 V rms. With these stress
conditions, the system must continue to operate with no loss of function (A criterion).
The test configuration used is shown in Figure 44.
Figure 44. RF test configuration
CWS500C
VCC
-6 dB
VCC
Vi
CDN-AF2
Scope
IN1-8
GND
DUT
Reference plane
SCLT3-8 meets IEC 61000 4-6 and IEC 61311-2 standards requirements. Better immunity
can be obtained by decoupling pin SCK with a 470 pF capacitor.
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Conclusion
7
AN2846
Conclusion
This application note illustrates how designers can maximize SCLT3-8 performances in their
applications especially in the fields of bus controller interface configurations, thermal
behavior and EMI robustness. They will find information that helps them to design new
system boards while saving time.
Designed for digital I/O module in factory automation, the SCLT3-8 is a low-loss EMI-proof
solution showing high usage flexibility. With the SCLT3-8, designers will be able to develop
highly integrated modules interfacing proximity sensors with the following benefits:
●
Reduced pin count
●
Saved space (only 3 isolation devices for SPI)
●
Reduced dissipation
●
No need for additional LED supply
●
Common SPI availability
●
EMI proof
To illustrate its performances and advantages, an evaluation board STEVAL-IFP000V1
using 2 SCLT3-8s configured in daisy chain is available with an optimized layout.
8
Revision history
Table 5.
34/35
Document revision history
Date
Revision
22-Feb-2010
1
Changes
Initial release.
Doc ID 15130 Rev 1
AN2846
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