ON FAN105BM6X Psr quasi-resonant valley switch controller Datasheet

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FAN105BM6X
Offline Primary-Side-Regulation
(PSR) Quasi-Resonant Valley
Switch Controller
FAN105B is offline Primary-Side-Regulation (PSR) PWM controller with
Quasi-Resonant (QR) mode controller to achieved constant-voltage (CV)
and constant-current (CC) control for Travel Adaptor (TA) requirement,
and provide cost-effective, simplified circuit for energy-efficient power
supplies.
www.onsemi.com
MARKING DIAGRAM
FAN105B integrates proprietary operation of energy saving feature at no
load, mWSaver Technology that combines our most energy efficient
process and circuit technologies for power adapter design.
FAN105B can be used in Travel Adapter design by stand-alone or co-work
with secondary-side SR controller FAN6292B. When paired FAN105B with
FAN6292B, both SR and USB Type-C connector are compatible to
achieve higher power and advanced control applications.
PXXEX
- -- -
Features

mWSaver® Technology Provides Ultra-Low Standby
Power Consumption for Energy Star’s 5-Star Level
(<30 mW with HV FET)

Constant-Current (CC) and Constant-Voltage(CV) with
Primary-Side Regulation Eliminates Secondary-Side
Feedback Component


Valley Switch Operation for Highest Average Efficiency

Integrated Dynamic Response Enhanceement(DRE)
Function
Low EMI Emissions and Common Mode Noise
Cycle-by-Cycle Current Limiting





= Year Code
PXX = 5A0 : FAN105BM6X
= 5B0 : FAN105BM6X
E X = Die Run Code
---
= Week Code
PIN CONNECTIONS
Programmable Cable Drop Compensation(CDC) with One
External Resistor
CS
AUX
GND
VS
GATE
VDD
Output Short-Circuit Protection
Scondary side Rectifier Short Detection via Current Sense
Protection(CSP)

Integrated Constant Current Compensation for Precise CC
Regulation





Output Over-Voltage Protection (VSOVP)
Output under-Voltage Protection (VSUVP)
VDD Over-Voltage Protection (VDD OVP)
Internal Thermal-Shutdown Protection (OTP)
Programmable Brown-In and Brown-Out Protection
Typical Applications

···
Travel Adapter for Smart Phones, Feature Phones, and Tablet
PCs
AC-DC Adapters for Portable Devices that Require CV/CC
Control
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
1
ORDERING INFORMATION
Part Number
Operating
Temperature
Range
Package
Packing
Method
FAN105BM6X
-40 ºC ~125ºC
6-Lead,
SOT23
Tap & Reel
For information on tape and reel specifications,
including part orientation and tape sizes,
please refer to our Tape and Reel Packaging
Specifications
Brochure,
BRD8011/D.
Publication Order Number:
FAN105BM6X
Load
Switch
VBUS
Bridge
Lπ
RSN1
+
CDL1
Vac
CDL2
NP
CSN2
NS
Co1
RStart
USB Type-C
Co2
GND
GND
TX1+
RX1+
TX1-
RX1-
VBUS
VBUS
VBUS
CC1
CC1
SBU2
SR MOSFET
DSN1
Fuse
Depletion
MOSFET
DVDD
RLPC1
RLPC2
MOSFET
LPC GATE GND VIN
Rot
CVDD
DR
RCDC
NA
RVS1
AUX
VDD
VS
RVS2
CC2
FAN105B
Optocoupler
RFB
FAN6292B
RGate
Optocoupler
BLD
CC1 /AUX LGATE
VBUS
Gate
CS
D-
D-
D+
SBU1
CC2
VBUS
VBUS
RX2-
TX2-
RX2+
TX2+
GND
GND
CC2
VBUS
CC1
Rcs
GND
D+
VBUS
CC2
CVS
Figure 1. FAN105B Typical Application Schematic
VDD
AUX
VCS-LIM
OCP
S1
TDIS
Internal
Regulator
VDD ON/OFF
DRE Detection
Cable Drop
Compensation
LEB
AR Mode
Protection
CS
OCP
OTP
Brown Out/In
VS OVP/UVP
VDD OVP
Current Monitor
Peak Current
Detection
IVS
VDD
VCS_CTRL
VCS_PK
Diode
Discharge
Detection
TDIS
VS Sample/Hold
PWM
Block
COMI
2.5V
VS
DYN
IO Estimator
EAV
GATE
OSC
Σ
7.5V
COMV
Compensator
VD
No-Load
Control
Maximum
On Time
GND
Valley
Detection
Figure 2.FAN105B Function Block Diagram
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
2
Publication Order Number:
FAN105BM6X
PIN FUNCTION DESCRIPTION
Pin #
Name Description
Current Sense. This pin connects to a current-sense resistor to detect the MOSFET
current for Peak-Current-Mode control for output regulation. The current-sense
information is also used to estimate the output current for CC regulation.
1
CS
2
GND
Ground
3
GATE
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power
MOSFET. The gate driving voltage is internally clamped at 7.5 V.
4
VDD
5
VS
6
AUX
Power Supply. IC operating current and MOSFET driving current are supplied through
this pin. This pin is typically connected to an external VDD capacitor.
Voltage Sense. This pin detects the output voltage information and diode current
discharge time based on the voltage of auxiliary winding. It also senses sink current
through the auxiliary winding to detect input voltage information.
Auxiliary Function. This pin generates one voltage level proportional to output current
to compensate output voltage drop due to cable resistance. The pin is also used for
startup with external HV FET.
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
3
Publication Order Number:
FAN105BM6X
ABSOLUTE MAXIMUM RATINGS (Note 1,2,3,4)
Parameter
Symbol
Min.
Max.
Unit
DC Supply Voltage
VVDD
-0.3
30
V
AUX Pin Input Voltage
VAUX
-0.3
30
V
VS Pin Input Voltage
VVS
-0.3
6.0
V
CS Pin Input Voltage
VCS
-0.3
6.0
V
Power Dissipation (TA=25C)
PD
0.391
mW
TJ
-40
+150
C
TSTG
-60
+150
C
+260
C
Operating Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 Seconds)
Electrostatic Discharge Capability
1.
2.
3.
4.
TL
Human Body Model,
ANSI/ESDA/JEDEC, JESD22_A114
Charged Device Model,
JEDEC:JESD22_C101
>1.5
ESD
kV
>0.5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the
recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
All voltage values, except differential voltages, are given with respect to the GND pin.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Meets JEDEC standards JS-001-2012 and JESD 22-C101.
THERMAL CHARACTERISTICS (Note 5)
Parameter
Symbol
Min.
Max.
Unit
Junction-to-Ambient Thermal Impedance
θJA
242
°C/W
Junction-to-Top Thermal Impedance
θJT
56
°C/W
5.
TA=25°C unless otherwise specified.
RECOMMENDED OPERATING RANGES (Note 6)
Parameter
CS Pin Input Voltage
Symbol
Min.
Max.
Unit
VCS
0
0.8
V
Gate Pin Input Voltage
VGATE
0
8.0
V
VDD Pin Input Voltage
VDD
7.0
25
V
VS Pin Input Voltage
VVS
1.6
3.2
V
AUX Pin Input Voltage
VAUX
5.0
25
V
6. The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance. On Semiconductor does not recommend exceeding
them or designing to Absolute Maximum Ratings.
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
4
Publication Order Number:
FAN105BM6X
ELECTRICAL CHARACTERISTICS
VDD=12 V and TA=-40~85C unless noted
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Turn-On Threshold Voltage
VDD-ON
16.5
17.5
18.5
V
Turn-Off Threshold Voltage
VDD-OFF
6.1
6.5
6.9
V
VDD Over-Voltage-Protection Level
VDD-OVP
26.5
28.0
29.5
V
tD-VDD-OVP
-
120
200
µs
-
20
µA
VDD Section
VDD Over-Voltage-Protection Debounce Time
(8)
Startup Current
IDD-ST
Operating Current
IDD-OP
1
1.4
1.7
mA
IDD-DPGN
375
450
525
µA
Maximum Voltage-Mode QuasiResonant Blanking Frequency
fOSC-BNK-MAX
70
76
82
kHz
Minimum Current-Mode Time-Out
Blankig Frequency
fOSC-BNK-MIN
4.5
5.0
5.5
kHz
fOSC-DPGN
320
420
480
Hz
fOSC-CCM-PRVENT
18
21
24
kHz
Deep Green-Mode Operating Current
Oscillator Section
Deep Green Mode Operating
(8)
Frequency
Minimum CCM Prevention
(7)
Frequency
Over-Temperature Protection Section
Over-Temperature Protection
(7)
Threshold
TOTP-H
120
C
Over-Temperature Protection
(7)
Recovery Threshold
TOTP-L
100
C
Continues on next page…
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
5
Publication Order Number:
FAN105BM6X
ELECTRICAL CHARACTERISTICS
VDD=12 V and TA=-40~85C unless noted
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VVR
2.475
2.500
2.525
V
Voltage Sampling Section
Reference Voltage of Constant
Voltage Feedback
VS Sampling Phase-Shift Resistance
(7)
VS Sampling Phase-Shift
(7)
Capacitance
VS Sampling Blanking Time of High
Level
Io over 100mA
RVS-S/H
300
kΩ
CVS-S/H
5
pF
tVS_BNK-H
1.65
1.80
2.00
µs
VS Sampling Blanking Time at CC
Controlling
tVS_BNK-CC
2.05
2.20
2.35
µs
VS Discharging Time Judgment
(7)
Threshold Voltage
VVS-Offset
150
200
250
mV
ITC
9.0
10.0
11.0
μA
VS Pin Source Current Threshold to
Enable Brown-Out
IVS-BROWN-OUT
260
310
360
μA
Brown-Out De-bounce Time
tD-BROWN-OUT
12
17
22
ms
VS Pin Source Current Threshold to
Enable Brown-In
IVS-BROWN-IN
405
475
545
μA
NBROWN-IN
3
4
5
cycle
Output Over-Voltage-Protection of VS
Sampling threshold
VVS-OVP
2.70
2.80
2.90
V
Output Over-Voltage-Protection
Debounce Cycle Counts
NVS-OVP
3
4
5
Cycle
Output Low Level Under-VoltageProtection of VS Sampling threshold
VVS-UVP
1.50
1.60
1.70
V
Output Under-Voltage Protection
Debounce Time
tVS-UVP
30
40
50
ms
0.4
0.5
0.6
V
2.550
2.600
2.650
V
Voltage Sense Section
Temperature-Independent Bias
Current
Brown-In De-bounce Time
No-Load Control Section
Deep Green Mode Entry Threshold
(7)
Voltage of COMV
VCOMV-CV-DPGN-
Criteria to Enter Deep Green Mode
VVS_EAV_Hi
Deep Green Mode Band-Band Control
High Threshold Voltage
VVS-EAV-H
2.550
V
Deep Green Mode Band-Band Control
Low Threshold Voltage
VVS-EAV-L
2.525
V
ENTRY
Criteria to Exit Deep Green Mode
VVS_EAV_Lo
2.425
2.450
2.475
V
Dynamic Event Trigger Threshold
Voltage in Deep Green Mode
VVS-EAV-DYN
2.375
2.400
2.425
V
Minimum On-time at 264VAC
CGATE=1nF
tON-MIN-264VAC
450
500
550
ns
Minimum On-time at 230VAC
CGATE=1nF
tON-MIN-230VAC
500
550
600
ns
Minimum On-time at 115VAC
CGATE=1nF
tON-MIN-115VAC
1250
1350
1450
ns
Minimum On-time at 90VAC
CGATE=1nF
tON-MIN-90VAC
1500
1650
1800
ns
Continues on next page…
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
6
Publication Order Number:
FAN105BM6X
ELECTRICAL CHARACTERISTICS
VDD=12 V and TA=-40~85C unless noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VCCR
1.19
1.2
1.21
V
Current Feedback Section
Reference Voltage of Constant Current
Feedback
VCS Peak Value Amplifying Gain
(7)
Attenuator ratio of Constant Current
(7)
Feedback Loop
APK
3.9
V/V
AV-CC
1/3.5
V/V
Current Sense Section
Current Limit Threshold Voltage
VCS-LIM
0.70
0.75
0.80
V
GATE Output Turn-Off Delay
(7)
tPD
Leading-Edge Blanking Time
(7)
tLEB
150
200
250
ns
Maximum On-Time
tON-MAX
15
17
20
μs
Gate Output Voltage Low
VGATE-L
0
1.5
V
Internal Gate PMOS Driver ON
VDD-PMOS-ON
7.0
7.5
8.0
V
Internal Gate PMOS Driver OFF
VDD-PMOS-OFF
9.0
9.5
10.0
V
VGATE-CLAMP
7.0
7.5
8.0
V
IDRE-DET
110
140
170
μA
100
ns
GATE Section
Gate Output Clamping Voltage
VDD level higher than 9V
AUX Section
Dynamic Response Enhancement (DRE)
function trigger threshold current at AUX
CDC compensation voltage at internal
reference
RCDC is 330kΩ
VVS-CDC4
0.298 0.320 0.343
V
RCDC is 560kΩ
VVS-CDC3
0.223 0.240 0.257
V
RCDC is 920kΩ
VVS-CDC2
0.149 0.160 0.171
V
RCDC is 1.3MΩ
VVS-CDC1
0.074 0.080 0.086
V
Notes:
7. Guaranteed by Design.
8. TA guaranteed range at 25C
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
7
Publication Order Number:
FAN105BM6X
1.06
1.009
1.04
1.006
VDD-OFF , Normalized
VDD-ON , Normalized
Typical Performance Characteristics
1.02
1.00
0.98
0.96
0.94
1.003
1.000
0.997
0.994
0.991
-40 -30 -15
0
25 50 75 85 100 125
-40 -30 -15 0
Tempeature (°C)
Figure 4.Turn-Off Threshold Voltage (VDD-OFF) vs.
Temperature
1.06
1.3
1.04
1.2
IDD-DPGN , Normalized
IDD-OP , Normalized
Figure 3.Turn-On Threshold Voltage (VDD-ON) vs.
Temperature
1.02
1.00
0.98
0.96
1.1
1.0
0.9
0.8
0.7
0.94
-40 -30 -15 0
-40 -30 -15 0
25 50 75 85 100 125
Figure 5.Operating Supply Current (IDD-OP) vs.
Temperature
Figure 6.Deep Green Mode Operation Current (IDDDPGN) vs. Temperature
1.06
1.04
1.04
f OSC-DPGN , Normalized
1.06
1.02
1.00
0.98
0.96
25 50 75 85 100 125
Tempeature (°C)
Tempeature (°C)
f OSC-BNK-MAX , Normalized
25 50 75 85 100 125
Tempeature (°C)
1.02
1.00
0.98
0.96
0.94
0.94
-40 -30 -15 0
25 50 75 85 100 125
-40 -30 -15 0
Tempeature (°C)
Figure 7.Maximum Operation Frequency of QR
Blanking Time (fOSC-BNK-MAX) vs. Temperature
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
25 50 75 85 100 125
Tempeature (°C)
Figure 8. Deep Green Mode Operation Frequency
(fOSC-DPGN) vs. Temperature
8
Publication Order Number:
FAN105BM6X
1.009
1.009
1.006
1.006
tVS-BNK-H , Normalized
VDD-OFF , Normalized
Typical Performance Characteristics
1.003
1.000
0.997
0.994
1.003
1.000
0.997
0.994
0.991
0.991
-40 -30 -15 0
-40 -30 -15 0
25 50 75 85 100 125
Figure 10.Vs Sampling Blanking Time (tVS-BNK-H) vs.
Temperature
1.009
1.060
1.006
1.040
VVS-UVP , Normalized
VVS-OVP , Normalized
Figure 9.Reference Voltage of CV Feedback (VVR)
vs. Temperature
1.003
1.000
0.997
0.994
1.020
1.000
0.980
0.960
0.940
0.991
-40 -30 -15 0
-40 -30 -15 0
25 50 75 85 100 125
Figure 11.Output Over-Voltage Protection of Vs
sampling Threshold(VVS-OVP) vs. Temperature
Figure 12.Output Under-Voltage of Vs sampling
Threshold(VVS-UVP) vs. Temperature
1.06
1.006
1.04
tON-MIN-264VAC , Normalized
1.009
1.003
1.000
0.997
0.994
0.991
-40 -30 -15 0
1.02
1.00
0.98
0.96
0.94
25 50 75 85 100 125
-40 -30 -15 0
Tempeature (°C)
Figure 13.Current Limit Threshold Voltage(VCS-LIM)
vs. Temperature
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
25 50 75 85 100 125
Tempeature (°C)
Tempeature (°C)
VCS-LIM , Normalized
25 50 75 85 100 125
Tempeature (°C)
Tempeature (°C)
25 50 75 85 100 125
Tempeature (°C)
Figure 14.Minmum Gate Turn On time(tON-MIN-264VAC)
vs. Temperature
9
Publication Order Number:
FAN105BM6X
FAN105BM6X
1.06
1.009
1.04
1.006
IZTC , Normalized
tON-MAX , Normalized
Typical Performance Characteristics
1.02
1.00
0.98
0.96
1.003
1.000
0.997
0.994
0.94
0.991
-40 -30 -15 0
25 50 75 85 100 125
-40 -30 -15
Tempeature (°C)
1.009
1.04
1.006
1.00
0.98
0.96
0.94
-40 -30 -15 0
0.997
0.994
0.991
-40 -30 -15 0
1.04
1.04
IVS-BROWN-OUT, Normalized
VGATE-CLAMP , Normalized
Figure 18.Brown In Threshold Current (IVS-BROWN-IN) vs.
Temperature
1.06
0.98
0.96
0.94
-40 -30 -15 0
25 50 75 85 100 125
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
1.02
1.00
0.98
0.96
0.94
-40 -30 -15
Tempeature (°C)
Figure 19.Clamp Voltage (VGATE-CLAMP) vs.
Temperature
25 50 75 85 100 125
Tempeature (°C)
1.06
1.00
85 100 125
1.000
Tempeature (°C)
1.02
75
1.003
25 50 75 85 100 125
Figure 17.Cable Compensation Level 4 Reference
Voltage(VVS-CDC4) vs. Temperature
50
Figure 16.Dynamic trigger current threshold (IZTC) vs.
Temperature
1.06
1.02
25
Tempeature (°C)
IVS-BROWN-IN , Normalized
VVSCDC4 , Normalized
Figure 15.Maximum Gate Turn On Time (tON-MAX) vs.
Temperature
0
0
25 50 75 85 100 125
Tempeature (°C)
Figure 20.Brown Out Threshold Current (IVS-BROWN-OUT) vs.
Temperature
10
Publication Order Number:
FAN105BM6X
FAN105BM6X
1.060
1.06
1.040
1.04
VDD-OVP , Normalized
tVS-UVP, Normalized
Typical Performance Characteristics
1.020
1.000
0.980
0.960
0.940
1.02
1.00
0.98
0.96
0.94
-40 -30 -15 0
25 50 75 85 100 125
-40 -30 -15
Tempeature (°C)
Figure 21.Blanking time of VSUVP(tVS-UVP) vs.
Temperature
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
0
25 50 75 85 100 125
Tempeature (°C)
Figure 22.VDD Over Voltage Protection Threshold (VDD-OVP)
vs. Temperature
11
Publication Order Number:
FAN105BM6X
FAN105BM6X
When the MOSFET is turned off, the energy stored in the
inductor forces the secondary diode (Dsec) to turn on. While
the diode is conducting, the output voltage (V o), together
with diode forward voltage drop (VF), are applied across the
2
2
secondary-side inductor (LmNs / Np ) and the diode current
(ID) decreases linearly from the peak value (IpkNp/Ns) to
zero. At the end of inductor current discharge time (tDIS), all
the energy stored in the inductor has been delivered to the
output.
Functional Description
FAN105B is an offline PWM and Primary-Side Regulated
(PSR) fly-back controller that can simplify feedback circuit
and secondary side circuit compare to traditional fly-back
converter. In addition, FAN105B detects Quasi-Resonant
valley switching to minimize the switching loss and get
better EMI performance.
When the diode current reaches zero, the transformer
auxiliary winding voltage (VAux) begins to oscillate by the
resonance between the primary-side inductor (Lm) and the
effective capacitor loaded across MOSFET.
FAN105B modulates pulse width and switching frequency
based on feedback signal auxiliary winding signal (VS) and
current sense signal (CS). Extremely accurately Constant
Voltage(CV) with Cable Drop Compensation (CDC) and
Constant Current (CC) could meet strict requirement from
market. The CV and CC output characteristic is shown as
Figure 23. There are 4 levels (80mV - 320mV) choices in
CDC compensation weighting that is easily set via external
SMD resistor.
VO
During the inductor current discharge time, the sum of
output voltage and diode forward-voltage drop is reflected to
the auxiliary winding side as (Vo+VF)  NAux/Ns. Since the
diode forward-voltage drop decreases as current
decreases, the auxiliary winding voltage reflects the output
voltage best at the end of diode conduction time, where the
diode current diminishes to zero. By sampling the winding
voltage at the end of the diode conduction time, the output
voltage information can be obtained. The internal error
amplifier for output voltage regulation (EAV) compares the
sampled voltage with internal precise reference to generate
error voltage (COMV), which determines the duty cycle of
the MOSFET in CV Mode.
Before Cable Compensation
After Cable Compensation
Maximum Specification
Minimum Specification
The output current is obtained by averaging the triangular
output diode current area over a switching cycle as:
IO  I D  AVG 
IO
Figure 23.CV with CDC and CC V/I Curve at the Cable
End
1
N T
 I PK  P  DIS
2
N S TS
(1)
The internal FAN105B circuits identify the peak value of the
drain current with a peak detection circuit and calculate the
output current using the inductor discharge time (tDIS) and
switching period (tS). This output information (EAI) is
compared with internal precise reference to generate error
voltage (COMI), which determines the duty cycle of the
MOSFET in CC Mode. With TRUECURRENT® technique,
constant output current can be precisely controlled.
FAN105B implements DeeP GreeN mode (DPGN) with
lowest switching frequency, limites IC current consumption
(450µA) for excellent system standby power performance.
Furthermore, the system design allowes two kinds of startup
circuit with resistor or high voltage FET.
With a given current sensing resistor, the output current can
be programmed as:
Protections are : over/under voltage protection (VSOVP,
VSUVP), Brown In and Brown Out, cycle by cycle over
current protection(OCP), current sense resistor short
protection, secondary rectifier short protection.
(2)
Basic CV/CC Control Principle
Of the two error voltages, COMV and COMI, the smaller
one determines the duty cycle. During Constant Voltage
regulation, COMV determines the duty cycle while COMI is
saturated to HIGH. During Constant Current regulation,
COMI determines the duty cycle while COMV is saturated to
HIGH.
Figure 24 shows the circuit diagram of a PSR fly-back
converter, FAN105B estimates output current through
primary side peak current from CS, output voltage via
auxiliary winding signal that proportional to secondary side
voltage, the current and voltage sampling are shown in
Figure 25. Generally, Discontinuous Conduction Mode
(DCM) with valley switching operation is preferred for PSR
since it allows better output regulation. The operation
principles of DCM/BCM flyback converter are as follows:
During the MOSFET turn on time (tON), input voltage (VDL) is
applied across the primary-side inductor (Lm). Then
MOSFET current (IDS) increases linearly from zero to the
peak value (Ipk). Meanwhile, the energy is drawn from the
input and stored in the inductor.
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
12
Publication Order Number:
FAN105BM6X
FAN105BM6X
VDL
CDL
NP
RSN1
NS
Dsec
CSN1
as EAV at timing like gray point showed. Base on EAV level
to regulate Pulse width to achieve estimation output voltage.
+
Co
Vo
DSN1
GATE R
Gate
CC
Estimator
EAI
COMI
MOSFET
RCG
CS
GATE
RCS
VCCR
PWM
Control
Block
VVR
VAux
CS
COMV
CV
EAV Estimator
NA
VAuxiliary
RVS1
VS
CVS

RVS2
NA
V BLK
NP
200mV
Figure 24.Simplified PSR Flyback Converter Circuit
IDS (MOSFET Drain-to-Source Current)
VS (With Schottky)
I PK
ID (Diode Current)
I PK 
NP
NS
I o  I D  AVG
VS (With SR control)
tVS-BNK-L
VS (With Schottky)
tON
VO 
VF 
RVS 2
NA

N S RVS 1  RVS 2
RVS 2
NA

 EAV
N S RVS 1  RVS 2
tS
Figure 26.VS sampling with Diode or Synchronous
Rectifier
TON
A leading edge blanking time(tVS-BNK-H/L) start from primary
switch turned off. Most of TA design have VS oscillation
after primary switch turned off, that is caused by the
resonance of leakage inductance and parasistic
capacitance at transformer. In order to avoid VS sampling
procedure get impacted by that ringing, the oscillation
should be settle before settle down before tVS-BNK-L ended as
Figure 26 showed. tDIS is secondary rectifier current
discharging time which recommend better design is longer
than tVS-BNK-H during miimum on time controlling. tDIS is
predictable by following formula:
TDIS
TS
Figure 25.Cycling Current and VS Sampling in DCM
Quasi-Resonant Valley Switch
FAN105B Build-In Quasi-Resonant valley detecting function
and inductor discharging time detecting function. During
MOSFET turn off period, FAN105B checked falling of VVS,
TDIS information will update as falling of VVS checked.
FAN105B keep monitor both VVS and IVS after TDIS
checked. FAN105B maximum period of MOSFET on time
and off time could be reach 45µs, it was depending on
whether valley checked. Quasi-Resonant valley switching
could minimize MOSFET switching loss during switch on,
meanwhile, to eliminate EMI and Common mode switching
component noise. Charger system would be getting better
efficiency than non-valley switching methodology.
(3)
Where parameter : tOFF-DELAY is switch turn off delay time
that level is chaging in differences system criteria, tON-MIN is
minimum turn on time in design that should consider
propagation delay from IC Gate to switch Gate.
Output voltage can be describe by below equation:
Output Voltage Sampling
(4)
VS voltage which is reflected auxiliary winding and
proportional to output voltage. Therefore, It is possible to
regulate output voltage by sensing VS voltage. Figure 26
shown VS sampling waveform with secondary rectifier that
using Schottky diode or Synchronous Rectifier (SR).
Deep Green Mode (DPGN) Operation in CV
mode
FAN105B integrated mWSaver® technology that minimize
current consumption and frequency at DPGN mode is fixed
to minimum switching frequency (fOSC-DPGN) and variable
Pulse width based on VS sampling voltage (EAV).
In order to regulate output voltage in accurately range,
FAN105B build-in VS sampling methodology for signal like
Figure 26 showed, FAN105B samples and hold VS voltage
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
tDIS
13
Publication Order Number:
FAN105BM6X
FAN105BM6X
VVS regulated boundary are between VVS-EAV-H and VVS-EAVL. After exit DPGN, internal regulation reference voltage was
changed to VVR.
Programmable Brown In/ Brown Out
FAN105B implement Brown out and Brown In through high
side resistor setting at VS PIN. In actual system operation,
VS PIN is drain a current (IVS) that proportional to line
voltage during MOSFET turns on. IVS could predict by below
equation:
FAN105B DPGN entry and exit criteria showed as below:
 DPGN entry need to meet both criteria as below:
 Minimum frequency (fOSC-MIN) operation continues over
than NDPGN-Entry switching cycles.
 EAV > VVS-EAV-H(2.550V).
(5)
Operating Current
The operating current in FAN105B is as small as 1.4mA.
The small operating current results in higher efficiency and
reduces the VDD hold-up capacitance requirement. During
DPGN mode, the FAN105B consumption current is reduced
to 450µA, assisting the power supply meet standby power
standard requirements.
 DPGN exit criteria, meet one of below criteria:
 EAV < VVS-EAV-L (2.525V) and maximum on time at
DPGN.
 EAV < VVS-EAV-DYN(2.4V).
During the DPGN mode controlling, FAN105B decreases
the operating current down to 450µA. Therefore, the
standby power could meet international standard
requirement when work with flexible start up circuit,
designer have flexible start up circuit that HV FET or start
up resistor depending on cost and better standby power
consideration
Protections
The FAN105B self-protection includes VDD Over-VoltageProtection (VDD OVP), Internal Chip Over-TemperatureProtection (OTP), VS Over-Voltage Protection (VSOVP), VS
Under-Voltage
Protection
(VSUVP),
CS
pin
Protection(CSP), Brownout and Brown In protection, and
all of protection are implemented as Auto Restart(AR)
mode.
Cable Drop Compensation (CDC)
FAN105B integrates cable drop compensation function and
the compensation weighting is calculated based on tDIS,
current sense voltage (VCS), and CDC setting resistor (RCDC)
needed to between VDD and AUX pin. During startup, as
VDD reached VDD-ON, CDC programming block detects AUX
pin current and determine cable drop compensation
weighting based on current weighting of AUX pin. Once
finished CDC compensation weighting detecting, the
information will stored until shunt-down by protections or
VDD lower than VDD-OFF. The CDC weighting automatic
detected input current during start up. which provides a
constant output voltage at the end of the cable over the
entire load range in CV Mode. The table shows the
compensation weighting with corresponding RCDC setting as
below:
When When an Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop till VDD-OFF and shut-down the system
then all protections are reset. After then VDD will be charged
again by the input AC voltage and once touch V DD-ON then
switching resumes. This is the reason why it is called AutoRestart, resumes switching automatically.
VDD Over-Voltage-Protection(VDD OVP)
When VDD is raised up to higher level by some reasons,
transformer VDD winding turns are too many, load regulation
is not good between transformer winding, VS information is
not available anyhow and so on, and touches VDD-OVP, then
FAN105B stops switching and protects IC from higher VDD
voltage. This is different then output voltage is over than pre
determined level.
CDC Weighting and RCDC Setting
RCDC
Label
VVS Compensation
weighting
1.3MΩ
VVS-CDC1
0.08V
920kΩ
VVS-CDC2
0.16V
560kΩ
VVS-CDC3
0.24V
330kΩ
VVS-CDC4
0.32V
VS Under-Voltage Protection (VSUVP)
FAN105B bulid-in VSUVP function that prevent TA keep
deliver power to phone side when output voltage is under
the set voltage at VS pin. VSUVP has a 40ms de-bounce
time and once VDD touches VDD-ON, during the later 40ms
VSUVP is disabled because VSUVP should not be triggered
during the start up. VSUVP level can be calculated as
below:
(6)
TA designer can easily to set up CDC weighting via choose
RCDC following above table. In the table, resisance of RCDC
is recommended for corresponding compensation level.
Cable drop compensation voltage at output is proportional
to VVS compensation weighting that is internal referce
voltage for CDC compensation.
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
VS Over-Voltage Protection (VSOVP)
The VSOVP is designed to prevent TA output voltage is
over then the rating of used components, like capacitor.
VSOVP has 4 switching cycles of denounce time and that
prevent mis-triggered of VSOVP by switching noise. The
protection level is changed in proportional to the CDC
14
Publication Order Number:
FAN105BM6X
FAN105BM6X
weighting.VSOVP trigger level can be illustrates as
following formula :
VDD
VDD-OVP
VDD-ON
(7)
VDD-OFF
CS pin Protection(CSP)
In order to prevent MOSFET current over than safe
operating area, FAN105B build-in cycle by cycle over
current protection. The protection could protect MOSFET
damaged by saturation current and CS pin sensing error. As
CS PIN signal meet below conditions FAN105B will turn off
Gate immediately. Current Sensing Protection (CSP) criteria
shows as below:

VCS <0.2V after switching turn on 4.5us at low line
or 1.5us at high line.

VCS>1.5V
VGATE,S1
VDD-VAUX
VAUX-CL
Figure 28. Start Up Sequence With AUX Controlling
Dynamic Response Enhancement (DRE) With
AUX
Over-Temperature Protection(OTP)
In order to guarantee FAN105B works within recommended
temperature. FAN105B build-in chip Over-Temperature –
Protection (OTP). As chip junction temperature over
thareshold TOTP-H IC immediately terminated Gate switching
signal untill chip junction termperature recover to TOTP-L.
PSR flyback converter regulates output voltage within
requirement specification through detects VS signal which
proportional to output voltage, However VS signal can only
detects when system switched. In order to get better
standby power performance, the switching frequency is
decreases to quite low frequency, it can not maintaining out
voltage as load suddenly increases from extremely light
load to heavy load during minimum frequency operation.
Therefore, FAN105B build in a Dynamic Response
Enhancement (DRE) function to detects output voltage
dropping immediately when FAN105B pair with FAN6292B.
Figure 29 shows DRE function block. Figure 30 shows
DRE function relative signal working sequence. When
output voltage undershoot is acknowledged via FAN6292B
VIN pin, BLD/AUX pin pull-down current via S2 switch to
inform undershoot to FAN105B via a photo-coupler. Once
FAN105B sensed AUX current higher than IDRE-DET, the
switching frequency is increases immediately.
Start Up Function With AUX
FAN105B supports high voltage start up with HV FET that
can make better standby power and shorter start up time.
Figure 27 shows start up controlling function block. Figure
28 shows start up relative signal sequence with AUX
controlling.
At system power on moment, initial VDD voltage is zero,
internal PMOS switch is turn on and external HV FET also
turn on, CVDD is charged through HV FET till VDD reach
VDD-ON. While Internal PMOS switch S1 turn off and VGS of
HV FET will close to internal clamping voltage (VAUX-CL)
which less than HV FET VGS turn on threshold. Meanwhile
VDD energy supplement is turn to auxiliary winding. The
voltage gap between VDD and VAUX is keep at 5V till
controller shut-down by protection or VDD touching VDD-OFF.
VBUS
NP
NS
Co1
Co2
LGATE
SR Gate
VDD
RAUX
VDL
RStart
AUX
FAN105B
VAUX-CL
VO Drop
Detection
RCDC
No Load
Control
TDIS
TON
VDD
Optocoupler
ROPTO(3.3kΩ)
Leave
Bang-Bang
Control
IAUX
AUX
BLD / AUX
S1
VIN
FAN6292B
±
R
CVDD
± 1V
VDD-ON/ VDD-OFF
S2
Pulse
VIN-AUX
Figure 29. Internal function for Start Up of AUX PIN
Figure 27. Internal function for Start Up of AUX PIN
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
15
Publication Order Number:
FAN105BM6X
FAN105BM6X
VGATE
(FAN105B)
IO
Accurately
Constant
Compensation
Heavy Load
(CC)
FAN105B provides accurate constant current with
universal line voltage range, In order to achieve this
accurately output current regulated, FAN105B build in
circuits that compensate a DC level at CS signal
based on difference line voltage. It could avoid output
current gap of difference line voltage during constand
current controlling. For noise immunity, the
recommendation of CS pin series resistor is 10Ω.
VBUS
VIN-AUX
S2
tAUX-ON
IAUX
Current
tOPTO-DELAY
IDRE-DET
Figure 30.DRE function Detecting Sequency
© Semiconductor Components Industries, LLC, 2017
May 2017- Rev. 1.0
16
Publication Order Number:
FAN105BM6X
REVISIONS
LTR
A
C
2
D
0.15 C A-B
DESCRIPTION
E.C.N.
RELEASE TO DOCUMENT CONTROL
2X
DATE
11/4/2006
5 JULY 07
DWG UPDATED TO CONFORM TO MO178
BY/APP'D
H.ALLEN
L.HUEBENER
SYMM
C
L
2.9
(0.95)
1.9
(0.95)
D
A
(1.00MIN)
1.4
C
D
1.6
2.8
(2.60)
(0.70MIN)
0.15 C D
2X
0.15 C
PIN 1 INDEX AREA
2X 3 TIPS
0.95
B
(1.90)
2X 0.3-0.5
0.20
C A-B D
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.45 MAX
1.30
0.90
0.08
0.22
C
0.15
0.05
6X
0.10
C
R0.10MIN
GAGE PLANE
R0.10MIN
0.25
8°
0°
0.60
0.30
SEATING PLANE
0.60 REF
DETAIL A
NOTES:
A. THIS PACKAGE CONFORMS TO JEDEC MO-178,
VARIATION AB.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
D. DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSIONS.
E. DIMENSIONS AND TOLERANCING AS PER ASME
Y14.5M-1994
F. DRAWING FILE NAME: MA06EREV2
SCALE: 2:1
APPROVALS
DATE
L.HUEBENER
5 JULY 07
H.ALLEN
17 JULY 07
6LD,SOT23,JEDEC
MO-178 VARIATION AB,
1.6MM WIDE
1:1
FORMERLY:
/
NA
N/A
MKT-MA06E
SHEET :
2
1
OF 1
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