CCD47-20 High Performance CCD Sensor FEATURES * 1024 by 1024 1:1 Image Format * Image Area 13.3 x 13.3 mm * Frame Transfer Operation * 13 mm Square Pixels * Symmetrical Anti-static Gate Protection * Very Low Noise Output Amplifiers * Gated Dump Drain on Output Register * 100% Active Area APPLICATIONS * Spectroscopy * Scientific Imaging * Star Tracking * Medical Imaging INTRODUCTION This version of the CCD47-20 is a front-face illuminated, frame transfer CCD sensor with high performance low noise output amplifiers, suitable for use in slow-scan imaging systems. The image area contains a full 1024 by 1024 pixels which are 13 mm square. The output register is split, allowing either or both of the two output amplifiers to be employed, and is provided with a drain and control gate for charge dump purposes. In common with all e2v technologies CCD Sensors, the CCD4720 is available with a fibre-optic window or taper, a UV coating or a phosphor coating for X-ray detection. Other variants of the CCD47-20 include IMO, back-thinned and full-frame devices. Designers are advised to consult e2v technologies should they be considering using CCD sensors in abnormal environments or if they require customised packaging. TYPICAL PERFORMANCE Maximum readout frequency Output responsivity . . . Peak signal . . . . . . Dynamic range (at 20 kHz) . Spectral range . . . . . Readout noise (at 20 kHz) . QE at 700 nm . . . . . . . . . . . . . . . . . . . . . . 5 MHz . . . 4.5 mV/e7 . . . 120 ke7/pixel *60 000:1 400 – 1100 nm . . . 2.0 e7 rms . . . 45 % GENERAL DATA Format Image area . . . . . . . . . 13.3 x 13.3 mm Active pixels (H) . . . . . . . . 1024 (V) . . . . . . . . 1024 Pixel size . . . . . . . . . . 13 x 13 mm Storage area . . . . . . . . . 13.3 x 13.3 mm Pixels (H) . . . . . . . . . . . 1024 (V) . . . . . . . . . . . 1024 Additional pixels are provided in both the image and storage areas for dark reference and over-scanning purposes. Number of output amplifiers . . . . . . . . . . 2 Weight (approx, no window) . . . . . 7.5 g Package Package size . . Number of pins . Inter-pin spacing Window material Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.7 x 42.0 mm . . . . . . . 32 . . . . . 2.54 mm quartz or removable glass . . ceramic DIL array e2v technologies limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU England Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 e-mail: [email protected] Internet: www.e2vtechnologies.com Holding Company: e2v holdings limited e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail: [email protected] # e2v technologies limited 2003 A1A-CCD47-20 Issue 7, April 2003 527/5896 PERFORMANCE Min Peak charge storage (see note 1) Peak output voltage (no binning) Dark signal at 293 K (see notes 2 and 3) Dynamic range (see note 4) Charge transfer efficiency (see note 5): parallel serial Output amplifier responsivity (see note 3) Readout noise at 243 K (see notes 3 and 6): grade 0 and 1 grade 2 Maximum readout frequency (see note 7) Response non-uniformity (std. deviation) Dark signal non-uniformity (std. deviation) (see notes 3 and 8) Typical 80k – – – 120k 540 10k 60 000 – – 3.0 99.9999 99.9993 4.5 – – – – 2.0 3.0 5.0 3 – 1000 Max e7/pixel mV e7/pixel/s – – 20k – – – 6.0 % % mV/e7 4.0 6.0 – 10 rms e7/pixel rms e7/pixel MHz % of mean e7/pixel/s 2000 ELECTRICAL INTERFACE CHARACTERISTICS Electrode capacitances (measured at mid-clock level) Min S1/S1 interphase I1/I1 interphase I1/SS and S1/SS R1/R1 interphase R1/(SS+DG+OD) 1R/SS Output impedance (at typ. operating condition) – – – – – – – 1. Signal level at which resolution begins to degrade. 2. Measured between 233 and 253 K and VSS +9.0 V. Dark signal at any temperature T (kelvin) may be estimated from: Qd/Qd0 = 122T3e76400/T where Qd0 is the dark signal at T = 293 K (20 8C). 3. Test carried out at e2v technologies on all sensors. 4. Dynamic range is the ratio of readout noise to full well capacity measured at 243 K and 20 kHz readout speed. 5. CCD characterisation measurements made using charge generated by X-ray photons of known energy. 6. Measured using a dual-slope integrator technique (i.e. correlated double sampling) with a 20 ms integration period. 7. Readout at speeds in excess of 5 MHz into a 15 pF load can be achieved but performance to the parameters given cannot be guaranteed. 8. Measured between 233 and 253 K, excluding white defects. BLEMISH SPECIFICATION Slipped columns Black spots CCD47-20, page 2 3.5 3.5 4.5 40 60 10 300 White spots NOTES Traps Typical Pixels where charge is temporarily held. Traps are counted if they have a capacity greater than 200 e7 at 243 K. Are counted if they have an amplitude greater than 200 e7. Are counted when they have a signal level of less than 90% of the local mean at a signal level of approximately half fullwell. White column Black column Max – – – – – – – nF nF nF pF pF pF O Are counted when they have a generation rate 25 times the specified maximum dark signal generation rate (measured between 233 and 253 K). The amplitude of white spots will vary in the same manner as dark current, i.e.: Qd/Qd0 = 122T3e76400/T A column which contains at least 21 white defects. A column which contains at least 21 black defects. GRADE 0 1 2 Column defects: black or slipped white Black spots Traps 4200 e7 White spots 0 0 15 1 20 2 0 25 2 30 6 0 100 5 50 Grade 5 Devices which are fully functioning, with image quality below that of grade 2, and which may not meet all other performance parameters. Minimum separation between adjacent black columns . . . . . . . . . 50 pixels Note The effect of temperature on defects is that traps will be observed less at higher temperatures but more may appear below 233 K. The amplitude of white spots and columns will decrease rapidly with temperature. # e2v technologies TYPICAL OUTPUT CIRCUIT NOISE (Measured using clamp and sample) VSS = 9 V VRD = 18 V VOD = 29 V 7 7508 NOISE EQUIVALENT SIGNAL (e7 r.m.s.) 6 5 4 3 2 1 0 10k FREQUENCY (Hz) 50k 100k 500k 1M TYPICAL SPECTRAL RESPONSE (No window) 60 7128 50 QUANTUM EFFICIENCY (%) 40 30 20 10 0 400 500 600 700 800 900 1000 1100 WAVELENGTH (nm) TYPICAL VARIATION OF DARK SIGNAL WITH SUBSTRATE VOLTAGE (Two I1 phases held low) 60 7509 50 DARK SIGNAL (k e7/pixel/s) 40 30 20 TYPICAL RANGE 10 0 0 1 2 3 SUBSTRATE VOLTAGE VSS (V) # e2v technologies 4 5 6 7 8 9 10 11 CCD47-20, page 3 TYPICAL VARIATION OF DARK CURRENT WITH TEMPERATURE 105 7510 104 103 102 DARK CURRENT (e7/pixel/s) 10 1 1071 1072 780 760 PACKAGE TEMPERATURE (8C) 740 720 0 20 40 DEVICE SCHEMATIC 7518 3 DARK REFERENCE ROWS SS 1 32 SS ABD 2 31 ABG I13 3 30 S13 I12 4 29 S12 I11 5 28 S11 IMAGE SECTION 1024 x 1024 ACTIVE PIXELS 13 x 13 mm SS 6 OG 7 26 DG RDL 8 25 RDR 9 24 16 DARK REFERENCE COLUMNS 27 SS OSL 10 23 OSR STORE SECTION 1024(H) x 1033(V) ELEMENTS 13 x 13 mm ODL 11 22 ODR SS 12 21 SS 1RL 13 20 1RR 8 16 16 8 R13L 14 19 R13R R12L 15 18 R12R R11L 16 17 R11R 8 BLANK ELEMENTS CCD47-20, page 4 16 DARK REFERENCE COLUMNS 8 BLANK ELEMENTS # e2v technologies CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS PIN REF DESCRIPTION 1 SS Substrate PULSE AMPLITUDE OR DC LEVEL (V) (See note 9) Min Typical Max 0 9 10 MAXIMUM RATINGS with respect to VSS – 70.3 to +25 V 2 ABD Anti-blooming drain (see note 10) 3 I13 Image area clock 8 12 VOD 15 +20 V 4 I12 Image area clock 8 12 15 +20 V 5 I11 Image area clock 8 12 15 +20 V 6 SS Substrate 0 9 10 – 7 OG Output gate 8 RDL Reset transistor drain (left amplifier) 9 – No connection 10 OSL Output transistor source (left amplifier) 11 ODL Output transistor drain (left amplifier) 1 3 5 +20 V 15 17 19 70.3 to +25 V – – 70.3 to +25 V see note 11 27 29 31 70.3 to +35 V 12 SS Substrate 0 9 10 – 13 1RL Output reset pulse (left amplifier) 8 12 15 +20 V 14 R13L Output register clock (left section) 8 10 15 +20 V 15 R12L Output register clock (left section) 8 10 15 +20 V 16 R11L Output register clock (left section) 8 10 15 +20 V 17 R11R Output register clock (right section) 8 10 15 +20 V 18 R12R Output register clock (right section) 8 10 15 +20 V 19 R13R Output register clock (right section) 8 10 15 +20 V 20 1RR Output reset pulse (right amplifier) 8 12 15 +20 V 21 SS Substrate 0 9 10 – 22 ODR Output transistor drain (right amplifier) 29 31 70.3 to +35 V 23 OSR Output transistor source (right amplifier) 24 – No connection 25 RDR Reset transistor drain (right amplifier) 26 DG Dump gate (see note 12) 27 SS Substrate 0 9 10 – 28 S11 Storage area clock 8 12 15 +20 V 29 S12 Storage area clock 8 12 15 +20 V 30 S13 Storage area clock 8 12 15 +20 V 31 ABG Anti-blooming gate 0 0 5 +20 V 32 SS Substrate 0 9 10 – Maximum voltages between pairs of pin 10 (OSL) to pin 11 (ODL) . pin 22 (ODR) to pin 23 (OSR) . Maximum output transistor current 27 70.3 to +25 V see note 11 – – 15 17 19 70.3 to +25 V – 0 – +20 V pins: . . . . . +15 V . . . . . +15 V . . . . . 10 mA NOTES 9. 10. 11. 12. 13. Readout register clock pulse low levels +1 V; other clock low levels 0+0.5 V. Drain not incorporated, but bias is still necessary. 3 to 5 V below OD. Connect to ground using a 2 to 5 mA current source or appropriate load resistor (typically 5 to 10 kO). Non-charge dumping level shown. For operation in charge dumping mode, DG should be pulsed to 12 + 2 V. All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be required for to optimise performance for critical applications. It should be noted that conditions for optimum performance may differ from device to device. 14. With the R1 connections shown, the device will operate through the left-hand output only. In order to operate from both outputs R11(R) and R12(R) should be reversed. # e2v technologies CCD47-20, page 5 FRAME TRANSFER TIMING DIAGRAM 7511 CHARGE COLLECTION PERIOD 1033 CYCLES I11 I12 I13 Ti 51028 CYCLES S11 S12 S13 SEE DETAIL OF LINE TRANSFER FRAME TRANSFER PERIOD 41 LINE TIME R11 R12 R13 1R OS SEE DETAIL OF OUTPUT CLOCKING READOUT PERIOD DETAIL OF LINE TRANSFER (For output from a single amplifier) 7579 1 /3Ti S11 toi toi S12 tdri twi tdir S13 R11 R12 R13 1R CCD47-20, page 6 # e2v technologies DETAIL OF VERTICAL LINE TRANSFER (Single line dump) 7787 S11 S12 S13 R11 R12 R13 1R DG END OF PREVIOUS LINE READOUT LINE TRANSFER INTO REGISTER DUMP SINGLE LINE FROM REGISTER TO DUMP DRAIN LINE TRANSFER INTO REGISTER START OF LINE READOUT DETAIL OF VERTICAL LINE TRANSFER (Multiple line dump) 7788 S11 S12 S13 R11 R12 R13 1R DG END OF PREVIOUS LINE READOUT # e2v technologies 1ST LINE 2ND LINE 3RD LINE DUMP MULTIPLE LINE FROM REGISTER TO DUMP DRAIN CLEAR READOUT REGISTER LINE TRANSFER INTO REGISTER START OF LINE READOUT CCD47-20, page 7 DETAIL OF OUTPUT CLOCKING 7133A R11 Tr tor R12 R13 twx tdx 1R SIGNAL OUTPUT OUTPUT VALID OS RESET FEEDTHROUGH LINE OUTPUT FORMAT 7512 8 BLANK 15 DARK REFERENCE * 1024 ACTIVE OUTPUTS * 15 DARK REFERENCE 8 BLANK RECOMMENDED D.C. CLAMP TIME * = Partially shielded transition elements CLOCK TIMING REQUIREMENTS Symbol Ti twi tri tfi toi tdir tdri Tr trr tfr tor twx trx, tfx tdx Description Image clock period Image clock pulse width Image clock pulse rise time (10 to 90%) Image clock pulse fall time (10 to 90%) Image clock pulse overlap Delay time, S1 stop to R1 start Delay time, R1 stop to S1 start Output register clock cycle period Clock pulse rise time (10 to 90%) Clock pulse fall time (10 to 90%) Clock pulse overlap Reset pulse width Reset pulse rise and fall times Delay time, 1R low to R13 low Min 2 1 0.1 tri (tri+tfi)/2 1 1 200 50 trr 20 30 0.2twx 30 Typical Max 5 2.5 0.5 0.5 0.5 2 1 1000 0.1Tr 0.1Tr 0.5trr 0.1Tr 0.5trr 0.5Tr see note see note 0.2Ti 0.2Ti 0.2Ti see note see note see note 0.3Tr 0.3Tr 0.1Tr 0.3Tr 0.1Tr 0.8Tr 15 15 15 15 15 ms ms ms ms ms ms ms ns ns ns ns ns ns ns NOTES 15. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times. 16. To minimise dark current, two of the I1 clocks should be held low during integration. I1 timing requirements are identical to S1 (as shown above). CCD47-20, page 8 # e2v technologies OUTPUT CIRCUIT 7516A RD R13 1R S12 (SEE NOTE 17) OD OG OS OUTPUT EXTERNAL LOAD (SEE NOTE 18) SS SS 0V NOTES 17. The amplifier has a DC restoration circuit which is internally activated whenever S12 is high. 18. Not critical; can be a 2 to 5 mA constant current supply or an appropriate load resistor. # e2v technologies CCD47-20, page 9 OUTLINE (All dimensions without limits are nominal) A 7522 D M 32 17 IMAGE AREA N C E B 16 1 PIN 1 INDICATOR F RECESSED TEMPORARY COVERGLASS L IMAGE PLANE G H J PITCH Ref Millimetres A B C D E 42.00 + 0.42 22.73 + 0.26 16.60 + 0.25 3.64 + 0.37 22.86 + 0.25 + 0.051 0.254 7 0.025 5.0 + 0.5 0.457 + 0.051 2.54 + 0.13 38.1 1.65 + 0.50 13.3 13.3 F K CCD47-20, page 10 G H J K L M N # e2v technologies ORDERING INFORMATION HANDLING CCD SENSORS Options include: CCD sensors, in common with most high performance MOS IC devices, are static sensitive. In certain cases a discharge of static electricity may destroy or irreversibly degrade the device. Accordingly, full antistatic handling precautions should be taken whenever using a CCD sensor or module. These include:- * Temporary Quartz Window * Permanent Quartz Window * Temporary Glass Window * Permanent Glass Window * Working at a fully grounded workbench Operator wearing a grounded wrist strap Fibre-optic Coupling * * UV Coating * All receiving socket pins to be positively grounded * X-ray Phosphor Coating * Unattended CCDs should not be left out of their conducting foam or socket. * For further information on the performance of these and other options, please contact e2v technologies. Evidence of incorrect handling will invalidate the warranty. All devices are provided with internal protection circuits to the gate electrodes (pins 3, 4, 5, 7, 13, 14, 15, 16, 17, 18, 19, 20, 26, 28, 29, 30, 31) but not to the other pins. HIGH ENERGY RADIATION Device parameters may begin to change if subject to an ionising dose of greater than 104 rads. Certain characterisation data are held at e2v technologies. Users planning to use CCDs in a high radiation environment are advised to contact e2v technologies. TEMPERATURE LIMITS Min Typical Max Storage . . . . . . . 73 – 373 K Operating . . . . . . . 73 243 323 K Operation or storage in humid conditions may give rise to ice on the sensor surface on cooling, causing irreversible damage. Maximum device heating/cooling . . . . 5 K/min Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. # e2v technologies Printed in England CCD47-20, page 11