Revision 16 IGLOO PLUS Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/O Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode Low Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode • Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode Feature Rich • 30 k to 125 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 212 User I/Os Reprogrammable Flash Technology • • • • • 130-nm, 7-Layer Metal, Flash-Based CMOS Process Instant On Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)† • FlashLock® Designed to Secure FPGA Contents High-Performance Routing Hierarchy • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—4 Banks per Chip on All IGLOO® PLUS Devices • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V • Selectable Schmitt Trigger Inputs • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Small-Footprint Packages across the IGLOO PLUS Family Clock Conditioning Circuit (CCC) and PLL† • Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except ×18)† • Segmented, Hierarchical Routing and Clock Structure Table 1 • IGLOO PLUS Product Family IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 30,000 60,000 125,000 Typical Equivalent Macrocells 256 512 1,024 VersaTiles (D-flip-flops) System Gates 792 1,584 3,120 Flash*Freeze Mode (typical, µW) 5 10 16 RAM Kbits (1,024 bits) – 18 36 4,608-Bit Blocks – 4 8 Secure (AES) ISP – Yes Yes FlashROM Kbits 1 1 1 – 1 1 6 18 18 Integrated PLL in CCCs VersaNet Globals 1 2 I/O Banks Maximum User I/Os Package Pins CS VQ 4 4 4 120 157 212 CS201, CS289 VQ128 CS201, CS289 VQ176 CS281, CS289 Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. † The AGLP030 device does not support this feature. December 2012 © 2012 Microsemi Corporation I IGLOO PLUS Low Power Flash FPGAs I/Os Per Package 1 IGLOO PLUS Devices AGLP030 AGLP060 Package AGLP125 Single-Ended I/Os CS201 120 157 – CS281 – – 212 CS289 120 157 212 VQ128 101 – – VQ176 – 137 – Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of singleended user I/Os available is reduced by one. Table 2 • IGLOO PLUS FPGAs Package Size Dimensions Package CS201 CS281 CS289 VQ128 VQ176 8×8 10 × 10 14 × 14 14 × 14 20 × 20 Nominal Area (mm2) 64 100 196 196 400 Pitch (mm) 0.5 0.5 0.8 0.4 0.4 Height (mm) 0.89 1.05 1.20 1.0 1.0 Length × Width (mm/mm) IGLOO PLUS Device Status IGLOO PLUS Device Status AGLP030 Production AGLP060 Production AGLP125 Production II R evis i o n 16 IGLOO PLUS Low Power Flash FPGAs IGLOO PLUS Ordering Information AGLP125 V2 _ CS G 289 Y I Application (Temperature Range) Blank = Commercial (0°C to +70°C ambient temperature) I = Industrial (–40°C to +85°C ambient temperature) PP = Pre-Production ES = Engineering Sample (room temperature only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type = CS Chip Scale Package (0.5 mm and 0.8 mm pitches) VQ = Very Thin Quad Flat Pack (0.4 mm pitch) Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number AGLP030 = 30,000 System Gates AGLP060 = 60,000 System Gates AGLP125 = 125,000 System Gates Notes: 1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly. 2. "G" indicates RoHS-compliant packages. R ev i si o n 1 6 III IGLOO PLUS Low Power Flash FPGAs Temperature Grade Offerings Package AGLP030 AGLP060 AGLP125 CS201 C, I C, I – CS281 – – C, I CS289 C, I C, I C, I VQ128 C, I – – VQ176 – C, I – Notes: 1. C = Commercial temperature range: 0°C to 70°C ambient temperature. 2. I = Industrial temperature range: –40°C to 85°C ambient temperature. Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/company/contact/default.aspx. IV Revision 16 IGLOO PLUS Low Power Flash FPGAs Table of Contents IGLOO PLUS Device Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 IGLOO PLUS DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 Pin Descriptions and Packaging Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-4 3-5 3-5 3-5 Package Pin Assignments VQ128 VQ176 CS201 CS281 CS289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 R ev i si o n 1 6 V 1 – IGLOO PLUS Device Family Overview General Description The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-low power mode that consumes as little as 5 µW while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, low power, single-chip solution that is Instant On. IGLOO PLUS is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212 user I/Os. The AGLP030 devices have no PLL or RAM support. Flash*Freeze Technology The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode. IGLOO PLUS devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state, tristate, or set as HIGH or LOW. The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS devices the best fit for portable electronics. Flash Advantages Low Power IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA. R ev i si o n 1 6 1 -1 IGLOO PLUS Device Family Overview Security Nonvolatile, flash-based IGLOO PLUS devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO PLUS devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO PLUS devices (except AGLP030) utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of security in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO PLUS devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO PLUS devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO PLUS devices with AES-based security provide a high level of protection for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Security, built into the FPGA fabric, is an inherent component of the IGLOO PLUS family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO PLUS family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. An IGLOO PLUS device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO PLUS FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. The IGLOO PLUS devices can be operated with a 1.2 V or 1.5 V single-voltage supply for core and I/Os, eliminating the need for additional supplies while minimizing total power consumption. Instant On Flash-based IGLOO PLUS devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The Instant On feature of flash-based IGLOO PLUS devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO PLUS device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO PLUS devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO PLUS flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 µs), and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from external memory components; instead, it retains all necessary information to resume operation immediately. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based IGLOO PLUS devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industrystandard AES algorithm. 1- 2 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs The IGLOO PLUS family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO PLUS family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO PLUS flashbased FPGAs. Once it is programmed, the flash cell configuration element of IGLOO PLUS FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO PLUS family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130 nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO PLUS family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO PLUS architecture provides granularity comparable to standard-cell ASICs. The IGLOO PLUS device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4): • Flash*Freeze technology • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory† • Extensive CCCs and PLLs† • Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO PLUS core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC® family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. † The AGLP030 device does not support PLL or SRAM. R ev i si o n 1 6 1 -3 IGLOO PLUS Device Family Overview Bank 0 Bank 1 Bank 3 CCC* RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 1 Bank 3 VersaTile Bank 2 Note: *Not supported by AGLP030 devices Figure 1-1 • IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and AGLP125) Flash*Freeze Technology The IGLOO PLUS device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pullup or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 µW in this mode. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned. Flash*Freeze Mode Control IGLOO PLUS FPGA Flash*Freeze Pin Figure 1-2 • 1- 4 IGLOO PLUS Flash*Freeze Mode R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs VersaTiles The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The IGLOO PLUS VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop with clear or set • Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Enable D-Flip-Flop with Clear or Set Data Y CLK D-FF Y D-FF Enable CLR Figure 1-3 • VersaTile Configurations User Nonvolatile FlashROM IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • Secure key storage for secure communications algorithms • Asset management/tracking • Date stamping • Version management The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in AGLP030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The IGLOO PLUS development software solutions, Libero® System-on-Chip (SoC) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. R ev i si o n 1 6 1 -5 IGLOO PLUS Device Family Overview SRAM and FIFO IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL. The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz • Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz • 2 programmable delay types for clock skew minimization • Clock frequency synthesis (for PLL only) Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). • Output duty cycle = 50% ± 1.5% or better (for PLL only) • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) • Maximum acquisition time is 300 µs (for PLL only) • Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only) • Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps × 250 MHz / fOUT_CCC Global Clocking IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO PLUS FPGAs support many different I/O standards. The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The configuration of these banks determines the I/O standards supported. 1- 6 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Each I/O module contains several input, output, and output enable registers. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support IGLOO PLUS devices support JEDEC-defined wide range I/O operation. IGLOO PLUS devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-4 on page 1-8). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated R ev i si o n 1 6 1 -7 IGLOO PLUS Device Family Overview Figure 1-4 • I/O States During Programming Window 6. Click OK to return to the FlashPoint – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. 1- 8 R ev isio n 1 6 2 – IGLOO PLUS DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O buffer supply voltage –0.3 to 3.75 V –0.3 V to 3.6 V V Storage temperature –65 to +150 °C Junction temperature +125 °C 1 I/O input voltage VI TSTG 2 TJ 2 Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. R ev i si o n 1 6 2 -1 IGLOO PLUS DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions1,2 Symbol Parameter Commercial Industrial Units 0 to +70 –40 to +85 °C 0 to + 85 –40 to +100 °C 1.425 to 1.575 1.425 to 1.575 V 1.14 to 1.575 1.14 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V 1.425 to 1.575 1.425 to 1.575 V 1.14 to 1.575 1.14 to 1.575 V 1.2 V DC supply voltage5 1.14 to 1.26 1.14 to 1.26 V 1.2 V DC wide range supply voltage5 1.14 to 1.575 1.14 to 1.575 V 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V wide range DC supply voltage9 2.7 to 3.6 2.7 to 3.6 V 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V TA Ambient temperature TJ Junction temperature2 VCC3 1.5 V DC core supply voltage 4 1.2 V–1.5 V wide range core voltage VJTAG JTAG DC voltage VPUMP7 Programming voltage 5,6 Programming mode Operation VCCPLL 8 Analog power supply (PLL) 1.5 V DC core supply voltage 4 1.2 V–1.5 V wide range core voltage5 VCCI Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank. 4. For IGLOO® PLUS V5 devices 5. For IGLOO PLUS V2 devices only, operating at VCCI VCC. 6. All IGLOO PLUS devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using V2 devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming. 7. VPUMP can be left floating during operation (not programming mode). 8. VCCPLL pins should be tied to VCC pins. See the Pin Descriptions chapter of the IGLOO PLUS FPGA Fabric User’s Guide for further information. 9. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation. Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature 1 Programming Cycles Program Retention (biased/unbiased) Maximum Storage Temperature TSTG (°C) 2 Maximum Operating Junction Temperature TJ (°C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Product Grade Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2- 2 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-4 • Overshoot and Undershoot Limits 1 Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 2.7 V or less 10% 1.4 V 5% 1.49 V 3V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V VCCI 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOO PLUS device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. IGLOO PLUS I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. R ev i si o n 1 6 2 -3 IGLOO PLUS DC and Switching Characteristics PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes Low and/or the output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOO PLUS Device Family User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Figure 2-1 • 2- 4 Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels R ev isio n 1 6 VCCI IGLOO PLUS Low Power Flash FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V Figure 2-2 • Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels R ev i si o n 1 6 2 -5 IGLOO PLUS DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction temperature is 100°C. EQ 2 shows a sample calculation of the maximum operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 1.46 W ja (C/W) 20.5°C/W EQ 2 Table 2-5 • Package Thermal Resistivities ja Package Type Pin Count jc Still Air 200 ft./ min. 500 ft./ min. Units Chip Scale Package (CSP) CS201 TBD TBD TBD TBD C/W CS281 TBD TBD TBD TBD C/W CS289 TBD TBD TBD TBD C/W VQ128 TBD TBD TBD TBD C/W VQ176 TBD TBD TBD TBD C/W Very Thin Quad Flat Package (VQFP) Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Junction Temperature (°C) Array Voltage VCC (V) –40°C 0°C 25°C 70°C 85°C 100°C 1.425 0.934 0.953 0.971 1.000 1.007 1.013 1.5 0.855 0.874 0.891 0.917 0.924 0.929 1.575 0.799 0.816 0.832 0.857 0.864 0.868 2- 6 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) For IGLOO PLUS V2, 1.2 V DC Core Supply Voltage Junction Temperature (°C) Array Voltage VCC (V) –40°C 0°C 25°C 70°C 85°C 100°C 1.14 0.963 0.975 0.989 1.000 1.007 1.011 1.2 0.853 0.865 .0877 0.893 0.893 0.897 1.26 0.781 0.792 0.803 0.813 0.819 0.822 Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage. Microsemi recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • Power Supply State per Mode Power Supply Configurations Modes/Power Supplies VCC VCCPLL VCCI VJTAG VPUMP Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off No Flash*Freeze On On On On On/off/floating Note: Off: Power Supply level = 0 V Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* Typical (25°C) Core Voltage AGLP030 AGLP060 AGLP125 Units 1.2 V 4 8 13 µA 1.5 V 6 10 18 µA Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode* ICCI Current Core Voltage AGLP030 AGLP060 AGLP125 Units VCCI = 1.2 V (per bank) Typical (25°C) 1.2 V 1.7 1.7 1.7 µA VCCI = 1.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.8 1.8 1.8 µA VCCI = 1.8 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.9 1.9 1.9 µA VCCI = 2.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.2 2.2 2.2 µA VCCI = 3.3 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.5 2.5 2.5 µA Note: *IDD = NBANKS * ICCI R ev i si o n 1 6 2 -7 IGLOO PLUS DC and Switching Characteristics Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode Typical (25°C) Core Voltage AGLP030 AGLP060 AGLP125 Units 1.2 V / 1.5 V 0 0 0 µA Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 Core Voltage AGLP030 1.2 V 6 10 13 µA 1.5 V 16 20 28 µA VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) 1.2 V 1.7 1.7 1.7 µA VCCI / VJTAG = 1.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.8 1.8 1.8 µA VCCI / VJTAG = 1.8 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.9 1.9 1.9 µA VCCI / VJTAG = 2.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.2 2.2 2.2 µA VCCI / VJTAG = 3.3 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.5 2.5 2.5 µA ICCA AGLP060 AGLP125 Units Current 2 Typical (25°C) ICCI or IJTAG Current Notes: 1. IDD = NBANKS * ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC, VCCPLL, and VPUMP currents. 2- 8 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings VCCI (V) Dynamic Power PAC9 (µW/MHz) 1 3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.26 3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.95 3.3 16.26 3.3 V LVCMOS Wide Range2 – Schmitt Trigger 3.3 18.95 2.5 V LVCMOS 2.5 4.59 2.5 V LVCMOS – Schmitt Trigger 2.5 6.01 1.8 V LVCMOS 1.8 1.61 1.8 V LVCMOS – Schmitt Trigger 1.8 1.70 1.5 V LVCMOS (JESD8-11) 1.5 0.96 1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.90 1.2 0.55 Single-Ended 3.3 V LVCMOS Wide Range 2 3 1.2 V LVCMOS 1.2 V LVCMOS3 – Schmitt Trigger 1.2 V LVCMOS Wide 1.2 0.47 Range3 1.2 0.55 3 1.2 0.47 1.2 V LVCMOS Wide Range – Schmitt Trigger Notes: 1. PAC9 is the total dynamic power measured on VCCI. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC. Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 CLOAD (pF) VCCI (V) Dynamic Power PAC10 (µW/MHz)2 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 127.11 3.3 V LVCMOS Wide Range3 5 3.3 127.11 2.5 V LVCMOS 5 2.5 70.71 1.8 V LVCMOS 5 1.8 35.57 1.5 V LVCMOS (JESD8-11) 5 1.5 24.30 5 1.2 15.22 5 1.2 15.22 Single-Ended 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range 4 Notes: 1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PAC10 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC. R ev i si o n 1 6 2 -9 IGLOO PLUS DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Device Specific Dynamic Power (µW/MHz) Parameter Definition AGLP125 AGLP060 AGLP030 PAC1 Clock contribution of a Global Rib 4.489 2.696 0.0001 PAC2 Clock contribution of a Global Spine 1.991 1.962 3.499 PAC3 Clock contribution of a VersaTile row 1.510 1.523 1.537 PAC4 Clock contribution of a VersaTile used as a sequential module 0.153 0.151 0.151 PAC5 First contribution of a VersaTile used as a sequential module 0.029 0.029 0.029 PAC6 Second contribution of a VersaTile used as a sequential module 0.323 0.323 0.323 PAC7 Contribution of a VersaTile used as a combinatorial module 0.280 0.300 0.278 PAC8 Average contribution of a routing net 1.097 1.081 1.130 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-13 on page 2-9. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14 on page 2-9. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.70 Note: 1. There is no Center Global Rib present in AGLP030, and thus it starts directly at the spine resulting in 0µW/MHz. 2- 10 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Device-Specific Static Power (mW) Parameter Definition AGLP125 AGLP060 AGLP030 PDC1 Array static power in Active mode See Table 2-12 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-9 on page 2-7 PDC4 Static PLL contribution PDC5 Bank quiescent power (VCCI-dependent) 1.841 See Table 2-12 on page 2-8 Notes: 1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in Libero SoC software. Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Device-Specific Dynamic Power (µW/MHz) Parameter Definition AGLP125 AGLP060 AGLP030 PAC1 Clock contribution of a Global Rib 2.874 1.727 0.0001 PAC2 Clock contribution of a Global Spine 1.264 1.244 2.241 PAC3 Clock contribution of a VersaTile row 0.963 0.975 0.981 PAC4 Clock contribution of a VersaTile used as a sequential module 0.098 0.096 0.096 PAC5 First contribution of a VersaTile used as a sequential module 0.018 0.018 0.018 PAC6 Second contribution of a VersaTile used as a sequential module 0.203 0.203 0.203 PAC7 Contribution of a VersaTile used as a combinatorial module 0.160 0.170 0.158 PAC8 Average contribution of a routing net 0.679 0.686 0.748 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-13 on page 2-9 PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14 on page 2-9 PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.10 Note: 1. There is no Center Global Rib present in AGLP030, and thus it starts directly at the spine resulting in 0µW/MHz. R ev i si o n 1 6 2- 11 IGLOO PLUS DC and Switching Characteristics Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Device-Specific Static Power (mW) Parameter Definition AGLP125 AGLP060 AGLP030 PDC1 Array static power in Active mode See Table 2-12 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-9 on page 2-7 PDC4 Static PLL contribution PDC5 Bank quiescent power (VCCI-dependent) 0.901 See Table 2-12 on page 2-8 Notes: 1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in Libero SoC software. Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on page 2-14. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on page 2-14. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric User's Guide. 2- 12 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric User's Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14. FCLK is the global clock signal frequency. RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on page 2-14. R ev i si o n 1 6 2- 13 IGLOO PLUS DC and Switching Characteristics PLL Contribution—PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – … – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. 2- 14 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVCMOS 2.5 V Output Drive Strength = 12 mA High Slew Rate Y tPD = 1.40 ns tPD = 0.89 ns tDP = 1.62 ns I/O Module (Non-Registered) Combinational Cell Y tDP = 1.62 ns tPD = 1.98 ns I/O Module (Non-Registered) Combinational Cell I/O Module (Registered) Y tPY = 1.06 ns Input LVCMOS 2.5 V D LVTTL Output drive strength = 12 mA High slew rate tPD = 1.24 ns Q I/O Module (Non-Registered) Combinational Cell Y tICLKQ = 0.63 ns tISUD = 0.18 ns LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 2.07 ns tPD = 0.86 ns Input LVTTL Clock Register Cell tPY = 0.85 ns D Combinational Cell Y Q I/O Module (Non-Registered) tPY = 1.15 ns Figure 2-3 • I/O Module (Registered) Register Cell D Q D tPD = 0.87 ns tCLKQ = 0.80 ns tSUD = 0.84 ns LVCMOS 1.5 V LVTTL Output drive strength = 8 mA High slew rate tDP = 1.70 ns Q tDP = 1.62 ns tCLKQ = 0.80 ns tSUD = 0.84 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.85 ns tPY = 0.85 ns LVTTL 3.3 V Output drive strength = 12 mA High slew rate tOCLKQ = 0.89 ns tOSUD = 0.18 ns Timing Model Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices R ev i si o n 1 6 2- 15 IGLOO PLUS DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (R) tPY (F) VCC 50% DIN GND Figure 2-4 • 2- 16 50% tDIN tDIN (R) (F) Input Buffer Timing Model and Delays (example) R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT tDOUT (R) D 50% VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-5 • tDP (F) Output Buffer Model and Delays (example) R ev i si o n 1 6 2- 17 IGLOO PLUS DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% tEOUT (F) 50% E tEOUT (R) VCC 50% EOUT tZL PAD 50% 50% tHZ Vtrip tZH VCCI 90% VCCI Vtrip VOL VCC D VCC E 50% tEOUT (R) 50% tEOUT (F) VCC EOUT PAD 50% tZLS VOH Vtrip Figure 2-6 • 2- 18 50% 50% tZHS Vtrip VOL Tristate Output Buffer Timing Model and Delays (example) R ev i sio n 1 6 50% tLZ 10% VCCI IGLOO PLUS Low Power Flash FPGAs Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings I/O Standard Equiv. Software Default Drive Drive Strength Slew Min. Strength Option2 Rate V VIL VIH VOL VOH IOL1 IOH1 mA mA Max. V Min. V Max. V Max. V Min. V 3.3 V LVTTL / 12 mA 3.3 V LVCMOS 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 V LVCMOS 100 µA Wide Range3 12 mA High –0.3 0.8 2 3.6 0.2 VDD 3 0.2 0.1 0.1 2.5 V LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 V LVCMOS 8 mA 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 1.5 V LVCMOS 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 1.2 V LVCMOS4 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 2 mA High –0.3 0.3 * VCCI 0.1 0.1 1.2 V LVCMOS 100 µA Wide Range4,5 0.7 * VCCI 3.6 0.1 VCCI – 0.1 Notes: 1. Currents are measured at 85°C junction temperature. 2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. R ev i si o n 1 6 2- 19 IGLOO PLUS DC and Switching Characteristics Table 2-22 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL3 IIH4 IIL3 IIH4 DC I/O Standards µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 10 10 15 15 10 10 15 15 10 10 15 15 1.5 V LVCMOS 5 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 5 Notes: 1. 2. 3. 4. Commercial range (0°C < TA < 70°C) Industrial range (–40°C < TA < 85°C) IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to IGLOO PLUS V2 devices operating at VCCI ³ VCC. 2- 20 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-23 • Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 3.3 V LVCMOS Wide Range 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 1.2 V LVCMOS 0.60 V 1.2 V LVCMOS Wide Range 0.60 V Table 2-24 • I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—High to Z tZH Enable to Pad delay through the Output Buffer—Z to High tLZ Enable to Pad delay through the Output Buffer—Low to Z tZL Enable to Pad delay through the Output Buffer—Z to Low tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to High tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to Low R ev i si o n 1 6 2- 21 IGLOO PLUS DC and Switching Characteristics 12 mA 12 mA High 5 pF – 0.97 1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56 ns Units 2.5 V LVCMOS tHZ ns tLZ 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 tZH 0.97 tZL 100 µA 12 mA High 5 pF – tE O U T 3.3 V LVCMOS Wide Range2 tPYS ns tPY tDP 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 tDIN tDOUT 0.97 Capacitive Load (pF) – Slew Rate 12 mA 12 mA High 5 pF Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS I/O Standard External Resistor () Equivalent Software Default Drive Strength Option1 Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V 1.8 V LVCMOS 8 mA 8 mA High 5 pF – 0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns 1.5 V LVCMOS 4 mA 4 mA High 5 pF – 0.97 2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57 ns Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 22 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Units tHZ tLZ tZH tZL tE O U T tPYS tPY) tDIN tDP tDOUT External Resistor () Capacitive Load (pF) Slew Rate Equivalent Software Default Drive Strength Option1 Drive Strength I/O Standard Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High 5 pF – 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns 3.3 V LVCMOS Wide Range2 100 µA 12 mA High 5 pF – 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns 2.5 V LVCMOS 12 mA 12 mA High 5 pF – 0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns 1.8 V LVCMOS 8 mA 8 mA High 5 pF – 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns 1.5 V LVCMOS 4 mA 4 mA High 5 pF – 0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns 1.2 V LVCMOS 2 mA 2 mA High 5 pF – 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns 1.2 V LVCMOS Wide Range3 100 µA 2 mA High 5 pF – 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 23 IGLOO PLUS DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-27 • Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 2-28 • I/O Output Buffer Maximum Resistances 1 Standard 3.3 V LVTTL / 3.3V LVCMOS 3.3 V LVCMOS Wide Range RPULL-DOWN () 2 RPULL-UP () 3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75 100 µA 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range Drive Strength 4 Same as equivalent software default drive 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 2 mA 200 224 4 mA 100 112 2 mA 157.5 163.8 100 µA 157.5 163.8 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS model on the Microsemi SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec 4. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC. 2- 24 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 K 45 K 10 K 45 K 3.3 V (wide range I/Os) 10 K 45 K 10 K 45 K 2.5 V 11 K 55 K 12 K 74 K 1.8 V 18 K 70 K 17 K 110 K 1.5 V 19 K 90 K 19 K 140 K 1.2 V 25 K 110 K 25 K 150 K 1.2 V (wide range I/Os) 19 K 110 K 19 K 150 K Notes: 1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN) Table 2-30 • I/O Short Currents IOSH/IOSL 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 109 103 100 µA Same as equivalent software default drive 2 mA 18 16 4 mA 18 16 6 mA 37 32 8 mA 37 32 12 mA 74 65 2 mA 11 9 4 mA 22 17 6 mA 44 35 8 mA 44 35 2 mA 16 13 4 mA 33 25 2 mA 26 20 100 µA 26 20 Note: *TJ = 100°C R ev i si o n 1 6 2- 25 IGLOO PLUS DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-31 • Duration of Short Circuit Event before Failure Temperature Time before Failure –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-32 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL/LVCMOS (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (100°C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis. 20 years (100°C) Input Buffer Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2- 26 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 • Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max. mA3 Max. mA3 µA4 µA4 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-7 • 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-35 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. R ev i si o n 1 6 2- 27 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA Drive Strength STD 0.97 3.94 0.18 0.85 1.15 0.66 4.02 3.46 1.82 1.87 ns 6 mA STD 0.97 3.20 0.18 0.85 1.15 0.66 3.27 2.94 2.04 2.27 ns 8 mA STD 0.97 3.20 0.18 0.85 1.15 0.66 3.27 2.94 2.04 2.27 ns 12 mA STD 0.97 2.72 0.18 0.85 1.15 0.66 2.78 2.57 2.20 2.53 ns 16 mA STD 0.97 2.72 0.18 0.85 1.15 0.66 2.78 2.57 2.20 2.53 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.97 2.36 0.18 0.85 1.15 0.66 2.41 1.90 1.82 1.98 ns 6 mA STD 0.97 1.96 0.18 0.85 1.15 0.66 2.01 1.56 2.04 2.38 ns 8 mA STD 0.97 1.96 0.18 0.85 1.15 0.66 2.01 1.56 2.04 2.38 ns 12 mA STD 0.97 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 ns 16 mA STD 0.97 1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Applies to 1.2 V DC Core Voltage Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 4.56 0.19 0.99 1.37 0.67 4.63 3.98 2.26 2.57 ns 6 mA STD 0.98 3.80 0.19 0.99 1.37 0.67 3.96 3.45 2.49 2.98 ns 8 mA STD 0.98 3.80 0.19 0.99 137 0.67 3.86 3.45 2.49 2.98 ns 12 mA STD 0.98 3.31 0.19 0.99 1.37 0.67 3.36 3.07 2.65 3.25 ns 16 mA STD 0.98 3.31 0.19 0.99 1.37 0.67 3.36 3.07 2.65 3.25 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 2.92 0.19 0.99 1.37 0.67 2.97 2.38 2.25 2.70 ns 6 mA STD 0.98 2.52 0.19 0.99 1.37 0.67 2.56 2.03 2.49 3.11 ns 8 mA STD 0.98 2.52 0.19 0.99 1.37 0.67 2.56 2.03 2.49 3.11 ns 12 mA STD 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns 16 mA STD 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns Drive Strength Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray 2- 28 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs 3.3 V LVCMOS Wide Range Table 2-40 • Minimum and Maximum DC Input and Output Levels Equivalent Software Default Drive 3.3 V LVCMOS Strength Wide Range Option1 Drive Strength VIH VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Min. Max. V V Max. V Min. V µA Max. µA4 Max. µA4 µA5 µA5 VIL Min. V Max. V µA 100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25 27 10 10 100 µA 4 mA –0.3 0.8 2 3.6 0.4 VDD – 0.2 100 100 25 27 10 10 100 µA 6 mA –0.3 0.8 2 3.6 0.4 VDD – 0.2 100 100 51 54 10 10 100 µA 8 mA –0.3 0.8 2 3.6 0.4 VDD – 0.2 100 100 51 54 10 10 100 µA 12 mA –0.3 0.8 2 3.6 0.4 VDD – 0.2 100 100 103 109 10 10 100 µA 16 mA –0.3 0.8 2 3.6 0.4 VDD – 0.2 100 100 103 109 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V CCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. Table 2-41 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. R ev i si o n 1 6 2- 29 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-42 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 4 mA STD 0.97 5.85 0.18 1.18 1.64 0.66 5.86 5.05 2.57 2.57 ns 100 µA 6 mA STD 0.97 4.70 0.18 1.18 1.64 0.66 4.72 4.27 2.92 3.19 ns 100 µA 8 mA STD 0.97 4.70 0.18 1.18 1.64 0.66 4.72 4.27 2.92 3.19 ns 100 µA 12 mA STD 0.97 3.96 0.18 1.18 1.64 0.66 3.98 3.70 3.16 3.59 ns 100 µA 16 mA STD 0.97 3.96 0.18 1.18 1.64 0.66 3.98 3.70 3.16 3.59 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-43 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 4 mA STD 0.97 3.39 0.18 1.18 1.64 0.66 3.41 2.69 2.57 2.73 ns 100 µA 6 mA STD 0.97 2.79 0.18 1.18 1.64 0.66 2.80 2.17 2.92 3.36 ns 100 µA 8 mA STD 0.97 2.79 0.18 1.18 1.64 0.66 2.80 2.17 2.92 3.36 ns 100 µA 12 mA STD 0.97 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 ns 100 µA 16 mA STD 0.97 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. Applies to 1.2 V DC Core Voltage 2- 30 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-44 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 4 mA STD 0.98 6.68 0.19 1.32 1.92 0.67 6.68 5.74 3.13 3.47 ns 100 µA 6 mA STD 0.98 5.51 0.19 1.32 1.92 0.67 5.51 4.94 3.48 4.11 ns 100 µA 8 mA STD 0.98 5.51 0.19 1.32 1.92 0.67 5.51 4.94 3.48 4.11 ns 100 µA 12 mA STD 0.98 4.75 0.19 1.32 1.92 0.67 4.75 4.36 3.73 4.52 ns 100 µA 16 mA STD 0.98 4.75 0.19 1.32 1.92 0.67 4.75 4.36 3.73 4.52 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-45 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 4 mA STD 0.98 4.16 0.19 1.32 1.92 0.67 4.16 3.32 3.12 3.66 ns 100 µA 6 mA STD 0.98 3.54 0.19 1.32 1.92 0.67 3.54 2.79 3.48 4.31 ns 100 µA 8 mA STD 0.98 3.54 0.19 1.32 1.92 0.67 3.54 2.79 3.48 4.31 ns 100 µA 12 mA STD 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns 100 µA 16 mA STD 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 1 6 2- 31 IGLOO PLUS DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. Table 2-46 • Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max. mA3 Max. mA3 µA4 µA4 2 16 18 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 65 74 10 10 2 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-8 • 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-47 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. 2- 32 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-48 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA Drive Strength STD 0.97 4.44 0.18 1.06 1.22 0.66 4.53 4.15 1.80 1.70 ns 6 mA STD 0.97 3.61 0.18 1.06 1.22 0.66 3.69 3.50 2.05 2.18 ns 8 mA STD 0.97 3.61 0.18 1.06 1.22 0.66 3.69 3.50 2.05 2.18 ns 12 mA STD 0.97 3.07 0.18 1.06 1.22 0.66 3.14 3.03 2.22 2.48 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-49 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.97 2.41 0.18 1.06 1.22 0.66 2.47 2.22 1.79 1.77 ns 6 mA STD 0.97 1.99 0.18 1.06 1.22 0.66 2.04 1.75 2.04 2.25 ns 8 mA STD 0.97 1.99 0.18 1.06 1.22 0.66 2.04 1.75 2.04 2.25 ns 12 mA STD 0.97 1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56 ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Applies to 1.2 V DC Core Voltage Table 2-50 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 5.04 0.19 1.19 1.40 0.67 5.12 4.65 2.22 2.36 ns 6 mA STD 0.98 4.19 0.19 1.19 1.40 0.67 4.25 3.98 2.48 2.85 ns 8 mA STD 0.98 4.19 0.19 1.19 1.40 0.67 4.25 3.98 2.48 2.85 ns 12 mA STD 0.98 3.63 0.19 1.19 1.40 0.67 3.69 3.50 2.66 3.16 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 2.96 0.19 1.19 1.40 0.67 3.00 2.67 2.22 2.46 ns 6 mA STD 0.98 2.52 0.19 1.19 1.40 0.67 2.56 2.18 2.47 2.95 ns 8 mA STD 0.98 2.52 0.19 1.19 1.40 0.67 2.56 2.18 2.47 2.95 ns 12 mA STD 0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns Drive Strength Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. R ev i si o n 1 6 2- 33 IGLOO PLUS DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-52 • Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL Drive Strength Min., V 2 mA –0.3 Max., V VIH Min., V VOL Max., V Max., V 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VOH IOL IOH Min., V IOSL IOSH IIL1 IIH2 mA mA Max., mA3 Max., mA3 µA4 µA4 VCCI – 0.45 2 2 9 11 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10 6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 35 44 10 10 8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 35 44 10 10 8 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-9 • 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-53 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. 2- 34 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-54 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 5.89 0.18 1.00 1.43 0.66 6.01 5.43 1.78 1.30 ns 4 mA STD 0.97 4.82 0.18 1.00 1.43 0.66 4.92 4.56 2.08 2.08 ns 6 mA STD 0.97 4.13 0.18 1.00 1.43 0.66 4.21 3.96 2.30 2.46 ns 8 mA STD 0.97 4.13 0.18 1.00 1.43 0.66 4.21 3.96 2.30 2.46 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-55 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.97 2.82 0.18 1.00 1.43 0.66 2.88 2.78 1.78 1.35 ns 4 mA STD 0.97 2.30 0.18 1.00 1.43 0.66 2.35 2.11 2.08 2.15 ns 6 mA STD 0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns 8 mA STD 0.97 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Applies to 1.2 V DC Core Voltage Table 2-56 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 6.43 0.19 1.12 1.61 0.67 6.54 5.93 2.19 1.88 ns 4 mA STD 0.98 5.33 0.19 1.12 1.61 0.67 5.41 5.03 2.50 2.68 ns 6 mA STD 0.98 4.61 0.19 1.12 1.61 0.67 4.69 4.41 2.72 3.07 ns 8 mA STD 0.98 4.61 0.19 1.12 1.61 0.67 4.69 4.41 2.72 3.07 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-57 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 3.30 0.19 1.12 1.61 0.67 3.34 3.21 2.19 1.93 ns 4 mA STD 0.98 2.76 0.19 1.12 1.61 0.67 2.79 2.51 2.50 2.76 ns 6 mA STD 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns 8 mA STD 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns Drive Strength Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. R ev i si o n 1 6 2- 35 IGLOO PLUS DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-58 • Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Max. V Min. V Max. mA mA mA3 Max. mA3 Drive Strength Min. V Max. V Min. V Max. V 2 mA –0.3 0.35 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA –0.3 0.35 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-10 • AC Loading Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. 2- 36 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-60 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA Drive Strength STD 0.97 6.07 0.18 1.16 1.62 0.66 6.19 5.53 2.13 2.02 ns 4 mA STD 0.97 5.24 0.18 1.16 1.62 0.66 5.34 4.81 2.37 2.47 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-61 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA Drive Strength STD 0.97 2.65 0.18 1.16 1.62 0.66 2.71 2.43 2.13 2.11 ns 4 mA STD 0.97 2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57 ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Applies to 1.2 V DC Core Voltage Table 2-62 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 6.57 0.19 1.26 1.80 0.67 6.68 6.01 2.54 2.59 ns 4 mA STD 0.98 5.72 0.19 1.26 1.80 0.67 5.81 5.27 2.79 3.05 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-63 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 3.08 0.19 1.26 1.80 0.67 3.13 2.82 2.53 2.68 ns 4 mA STD 0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns Drive Strength Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. R ev i si o n 1 6 2- 37 IGLOO PLUS DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-64 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS1 VIL VIH Drive Strength Min. V Max. V Min. V Max. V 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Max. V Min. V mA mA Max. mA4 Max. mA4 µA5 µA5 20 26 10 10 0.25 * VCCI 0.75 * VCCI 2 2 Notes: 1. Applicable to IGLOO nano V2 devices operating at VCCI VCC. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. Datapath R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS R=1k Test Point Enable Path Test Point 5 pF 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-11 • AC Loading Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) CLOAD (pF) 1.2 0.6 5 0 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-66 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.98 8.27 0.19 1.57 2.34 0.67 7.94 6.77 3.00 3.11 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-67 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. 2- 38 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs 1.2 V LVCMOS Wide Range Table 2-68 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS Wide Range1 VIL Equivalent Software Default Drive Drive Strength Min. Strength Option2 V 100 µA 2 mA Max. V VIH Min. V –0.3 0.35 * VCCI 0.65 * VCCI Max. V 3.6 VOL VOH IOL IOH IOSL IOSH IIL3 IIH4 Max. V Min. V Max. Max mA mA mA5 mA5 µA6 µA6 0.25 * VCCI 0.75 * VCCI 2 2 20 26 10 10 Notes: 1. Applicable to V2 devices only. 2. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 6. Currents are measured at 85°C junction temperature. 7. Software default selection highlighted in gray. Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 1.2 0.6 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. R ev i si o n 1 6 2- 39 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-70 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Equivalent Software Default Drive Drive Strength Strength Option1 100 µA 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.98 8.27 0.19 1.57 2.34 0.67 7.94 6.77 3.00 3.11 ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-71 • 1.2 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Equivalent Software Default Drive Drive Strength Strength Option1 100 µA 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. 2- 40 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs I/O Register Specifications Fully Registered I/O Buffers with Asynchronous Preset INBUF Preset L DOUT Data_out C D Q DFN1P1 E Y PRE F Core Array D Q DFN1P1 TRIBUF PRE INBUF Data Pad Out D EOUT CLKBUF CLK H I A PRE J D Q DFN1P1 Data Input I/O Register with: Active High Preset Positive-Edge Triggered INBUF D_Enable CLK CLKBUF Data Output Register and Enable Output Register with: Active High Preset Postive-Edge Triggered Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset R ev i si o n 1 6 2- 41 IGLOO PLUS DC and Switching Characteristics Table 2-72 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-12 on page 2-41 for more information. 2- 42 R ev i sio n 1 6 H, DOUT L, DOUT H, EOUT I, EOUT I, H IGLOO PLUS Low Power Flash FPGAs Fully Registered I/O Buffers with Asynchronous Clear D CC Q DFN1C1 EE Data_out FF D Q DFN1C1 TRIBUF INBUF Data Core Array Pad Out DOUT Y EOUT CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD D Q DFN1C1 Data Input I/O Register with Active High Clear Positive-Edge Triggered INBUF CLKBUF D_Enable CLK CLR Data Output Register and Enable Output Register with Active High Clear Positive-Edge Triggered Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear R ev i si o n 1 6 2- 43 IGLOO PLUS DC and Switching Characteristics Table 2-73 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-13 on page 2-43 for more information. 2- 44 R ev i sio n 1 6 HH, DOUT LL, DOUT HH, EOUT II, EOUT II, HH II, HH IGLOO PLUS Low Power Flash FPGAs Input Register tICKMPWH tICKMPWL CLK 50% 50% 1 50% 50% 50% 0 tIWPRE Preset 50% 50% tIHD tISUD Data 50% 50% tIRECPRE tIREMPRE 50% 50% 50% tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 2-14 • Input Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-74 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.41 ns tISUD Data Setup Time for the Input Data Register 0.32 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.57 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.57 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 45 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-75 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.66 ns tISUD Data Setup Time for the Input Data Register 0.43 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.86 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.86 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 46 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD Data_out 1 50% 50% 0 tOWPRE Preset tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tORECCLR tOREMCLR 50% 50% tOPRE2Q 50% DOUT 50% tOCLR2Q 50% tOCLKQ Figure 2-15 • Output Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-76 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.66 ns tOSUD Data Setup Time for the Output Data Register 0.33 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.88 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 47 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-77 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 1.03 ns tOSUD Data Setup Time for the Output Data Register 0.52 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.22 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.31 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 48 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Output Enable Register tOECKMPWH tOECKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOESUD tOEHD D_Enable 1 50% 0 50% tOEWPRE tOEREMPRE tOERECPRE 50% 50% 50% Preset tOEWCLR 50% Clear tOEPRE2Q EOUT 50% 50% tOERECCLR tOEREMCLR 50% 50% tOECLR2Q 50% tOECLKQ Figure 2-16 • Output Enable Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-78 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.68 ns tOESUD Data Setup Time for the Output Enable Register 0.33 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.84 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.91 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 49 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-79 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units 1.06 ns tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register 0.52 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.25 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.36 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 50 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/ E Macro Library Guide. A A B A OR2 Y AND2 A Y B B B XOR2 A B C Y A A B C NOR2 B A A Y INV NAND3 A MAJ3 B Y NAND2 XOR3 Y Y 0 MUX2 B Y Y 1 C S Figure 2-17 • Sample of Combinatorial Cells R ev i si o n 1 6 2- 51 IGLOO PLUS DC and Switching Characteristics tPD Fanout = 4 A Net NAND2 or Any Combinatorial Logic Length = 1 VersaTile B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell A Net Length = 1 VersaTile B NAND2 or Any Combinatorial Logic Y NAND2 or Any Combinatorial Logic Y NAND2 or Any Combinatorial Logic Y A Net Length = 1 VersaTile B A Net Length = 1 VersaTile B VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) tPD OUT (FR) 50% tPD (RF) GND Figure 2-18 • Timing Model and Waveforms 2- 52 Y R ev i sio n 1 6 50% IGLOO PLUS Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-80 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 0.72 ns Y=A·B tPD 0.86 ns Y = !(A · B) tPD 1.00 ns Y=A+B tPD 1.26 ns NOR2 Y = !(A + B) tPD 1.16 ns XOR2 Y = A B tPD 1.46 ns MAJ3 Y = MAJ(A, B, C) tPD 1.47 ns XOR3 Y = A B C tPD 2.12 ns MUX2 Y = A !S + B S tPD 1.24 ns AND3 Y=A·B·C tPD 1.40 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-81 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 1.26 ns Y=A·B tPD 1.46 ns Y = !(A · B) tPD 1.78 ns Y=A+B tPD 2.47 ns NOR2 Y = !(A + B) tPD 2.17 ns XOR2 Y = A B tPD 2.62 ns MAJ3 Y = MAJ(A, B, C) tPD 2.66 ns XOR3 Y = A B C tPD 3.77 ns MUX2 Y = A !S + B S tPD 2.20 ns AND3 Y=A·B·C tPD 2.49 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 1 6 2- 53 IGLOO PLUS DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOO PLUS library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Data D Q Out Data En DFN1 CLK D Out Q DFN1E1 CLK PRE Data D Q Out En DFN1C1 CLK CLK CLR Figure 2-19 • Sample of Sequential Cells 2- 54 Data R ev i sio n 1 6 D Q DFI1E1P1 Out IGLOO PLUS Low Power Flash FPGAs tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data EN PRE 50% tRECPRE tREMPRE 50% 50% 50% CLR tPRE2Q 50% tREMCLR tRECCLR tWCLR Out 50% 50% 0 tWPRE tHE 50% 50% tHD 50% tSUE 50% 50% 50% 50% tCLR2Q 50% 50% tCLKQ Figure 2-20 • Timing Model and Waveforms Timing Characteristics 1.5 V DC Core Voltage Table 2-82 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 0.89 ns tSUD Data Setup Time for the Core Register 0.81 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 0.73 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.60 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.62 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.56 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 55 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-83 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 1.61 ns tSUD Data Setup Time for the Core Register 1.17 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 1.29 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.87 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.89 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.46 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.46 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.95 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.95 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 56 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Global Resource Characteristics AGLP125 Clock Tree Topology Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing. The global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125 device. It is used to drive all D-flip-flops in the device. Central Global Rib VersaTile Rows CCC Global Spine Figure 2-21 • Example of Global Tree Use in an AGLP125 Device for Clock Routing R ev i si o n 1 6 2- 57 IGLOO PLUS DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-61. Table 2-84 to Table 2-89 on page 2-60 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.5 V DC Core Voltage Table 2-84 • AGLP030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.21 1.42 ns tRCKH Input High Delay for Global Clock 1.23 1.49 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.18 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.15 ns tRCKSW Maximum Skew for Global Clock 0.27 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-85 • AGLP060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.32 1.62 ns tRCKH Input High Delay for Global Clock 1.34 1.72 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.18 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.15 ns tRCKSW Maximum Skew for Global Clock 0.38 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 58 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-86 • AGLP125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.36 1.71 ns tRCKH Input High Delay for Global Clock 1.39 1.82 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.18 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.15 ns tRCKSW Maximum Skew for Global Clock 0.43 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-87 • AGLP030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.80 2.09 ns tRCKH Input High Delay for Global Clock 1.88 2.27 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 1 6 2- 59 IGLOO PLUS DC and Switching Characteristics Table 2-88 • AGLP060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 2.02 2.43 ns tRCKH Input High Delay for Global Clock 2.09 2.65 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.56 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-89 • AGLP125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 2.08 2.54 ns tRCKH Input High Delay for Global Clock 2.15 2.77 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.62 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 60 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-90 • IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Parameter Min. 0.75 Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Typ. 1.5 Clock Conditioning Circuitry Input Frequency fIN_CCC 1, 2 Max. Units 250 MHz 250 MHz 3 360 Number of Programmable Values in Each Programmable Delay Block ps 32 Serial Clock (SCLK) for Dynamic PLL4,5 Input Cycle-to-Cycle Jitter (peak magnitude) 100 MHz 1 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms LockControl = 0 2.5 ns Tracking Jitter6 LockControl = 1 1.5 ns 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 1.25 15.65 ns Delay Range in Block: Programmable Delay 2 1, 2 0.469 15.65 ns Output Duty Cycle Delay Range in Block: Fixed Delay 1, 2 3.5 ns Maximum Peak-to-Peak Period Jitter7,8,9 VCO Output Peak-to-Peak Period Jitter FCCC_OUT7 SSO 2 SSO 4 SSO 8 SSO 16 0.75 MHz to 50 MHz 0.50% 0.60% 0.80% 1.20% 50 MHz to 250 MHz 2.50% 4.00% 6.00% 12.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help associated with the core for more information. 4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 5. The AGLP030 device does not support a PLL. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 8. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate, VCC/VCCPLL = 1.425 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 9. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within ±200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO PLUS FPGA Fabric User’s Guide. R ev i si o n 1 6 2- 61 IGLOO PLUS DC and Switching Characteristics Table 2-91 • IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 0.75 Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Typ. 1, 2 580 Max. Units 160 MHz 160 MHz 3 Number of Programmable Values in Each Programmable Delay Block ps 32 4,5 Serial Clock (SCLK) for Dynamic PLL 60 MHz Input Cycle-to-Cycle Jitter (peak magnitude) .25 ns LockControl = 0 300 µs LockControl = 1 6.0 ms LockControl = 0 4 ns LockControl = 1 3 ns Acquisition Time Tracking Jitter 6 Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 2.3 20.86 ns Delay Range in Block: Programmable Delay 2 1, 2 0.863 20.86 ns Delay Range in Block: Fixed Delay 1, 2 5.7 ns Maximum Peak-to-Peak Period Jitter7,8,9 VCO Output Peak-to-Peak Period Jitter FCCC_OUT7 SSO 2 SSO 4 SSO 8 SSO 16 0.75 MHz to 50 MHz 0.50% 1.20% 2.00% 3.00% 50 MHz to 160 MHz 2.50% 5.00% 7.00% 15.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.2 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the online help associated with the core for more information. 4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions.For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 5. The AGLP030 device does not support PLL. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 8. Measurements are done with LVTTL 3.3 V, 8 mA, I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 9. SSO are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ±200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO PLUS FPGA Fabric User’s Guide 2- 62 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-22 • Peak-to-Peak Jitter Definition R ev i si o n 1 6 2- 63 IGLOO PLUS DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM512X18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-23 • RAM Models 2- 64 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 [R|W]ADDR A1 A2 tBKS tBKH BLK tENS tENH WEN tCKQ1 DOUT|RD Dn D0 D1 D2 tDOH1 Figure 2-24 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK t AS tAH A1 A0 [R|W]ADDR A2 tBKS tBKH BLK tENH tENS WEN tCKQ2 DOUT|RD Dn D0 D1 tDOH2 Figure 2-25 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18. R ev i si o n 1 6 2- 65 IGLOO PLUS DC and Switching Characteristics tCYC tCKH tCKL CLK tAS tAH A0 [R|W]ADDR A1 A2 tBKS tBKH BLK tENS tENH WEN tDS DI0 DIN|WD tDH DI1 D2 Dn DOUT|RD Figure 2-26 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK tAS tAH A0 ADDR A1 A2 tBKS tBKH BLK tENS WEN tDS DI0 DIN DOUT (pass-through) DOUT (pipelined) tDH DI1 Dn DI2 DI0 DI1 DI0 Dn Figure 2-27 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 only. 2- 66 R ev i sio n 1 6 DI1 IGLOO PLUS Low Power Flash FPGAs tCYC tCKH tCKL CLK RESET tRSTBQ DOUT|RD Dm Dn Figure 2-28 • RAM Reset R ev i si o n 1 6 2- 67 IGLOO PLUS DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-92 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.68 ns tENH REN, WEN hold time 0.13 ns tBKS BLK setup time 1.37 ns tBKH BLK hold time 0.13 ns tDS Input data (DIN) setup time 0.59 ns tDH Input data (DIN) hold time 0.30 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 2.94 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.55 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 1.51 ns tC2CWWL1 Address collision clk-to-clk delay for reliable write after write on same address – applicable 0.29 to closing edge ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address – 0.24 applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address – 0.40 applicable to opening edge ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) ns RESET Low to data out Low on DOUT (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 ns tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz 1.72 Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 68 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-93 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.61 ns tENH REN, WEN hold time 0.07 ns tDS Input data (WD) setup time 0.59 ns tDH Input data (WD) hold time 0.30 ns tCKQ1 Clock High to new data valid on RD (output retained) 3.51 ns tCKQ2 Clock High to new data valid on RD (pipelined) 1.43 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address – 0.21 applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address – 0.25 applicable to opening edge ns tRSTBQ RESET Low to data out Low on RD (flow-through) 1.72 ns RESET Low to data out Low on RD (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 ns tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 69 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-94 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tAS Address setup time 1.28 ns tAH Address hold time 0.25 ns tENS REN, WEN setup time 1.25 ns tENH REN, WEN hold time 0.25 ns tBKS BLK setup time 2.54 ns tBKH BLK hold time 0.25 ns tDS Input data (DIN) setup time 1.10 ns tDH Input data (DIN) hold time 0.55 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 5.51 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 4.77 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 2.82 ns tC2CWWL1 Address collision clk-to-clk delay for reliable write after write on same address – applicable to closing edge 0.30 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.32 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address – applicable to opening edge 0.44 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 3.21 ns RESET Low to data out Low on DOUT (pipelined) 3.21 ns tREMRSTB RESET removal 0.93 ns tRECRSTB RESET recovery 4.94 ns tMPWRSTB RESET minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 70 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Table 2-95 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Std. Units tAS Address setup time Description 1.28 ns tAH Address hold time 0.25 ns tENS REN, WEN setup time 1.13 ns tENH REN, WEN hold time 0.13 ns tDS Input data (WD) setup time 1.10 ns tDH Input data (WD) hold time 0.55 ns tCKQ1 Clock High to new data valid on RD (output retained) 6.56 ns tCKQ2 Clock High to new data valid on RD (pipelined) 2.67 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.29 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address – applicable to opening edge 0.36 ns tRSTBQ RESET Low to data out Low on RD (flow through) 3.21 ns RESET Low to data out Low on RD (pipelined) 3.21 ns tREMRSTB RESET removal 0.93 ns tRECRSTB RESET recovery 4.94 ns tMPWRSTB RESET minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 71 IGLOO PLUS DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-29 • FIFO Model 2- 72 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs Timing Waveforms tCYC RCLK tENH tENS REN tBKH tBKS RBLK tCKQ1 RD (flow-through) Dn D0 D1 D2 D0 D1 tCKQ2 RD (pipelined) Dn Figure 2-30 • FIFO Read tCYC WCLK tENS tENH WEN WBLK tBKS tBKH tDS WD DI0 tDH DI1 Figure 2-31 • FIFO Write R ev i si o n 1 6 2- 73 IGLOO PLUS DC and Switching Characteristics RCLK/ WCLK tMPWRSTB tRSTCK RESET tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-32 • FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Figure 2-33 • FIFO EMPTY Flag and AEMPTY Flag Assertion 2- 74 R ev i sio n 1 6 Dist = AEF_TH MATCH (EMPTY) IGLOO PLUS Low Power Flash FPGAs tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-34 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) RCLK MATCH (EMPTY) NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA (Address Counter) WCLK MATCH (FULL) NO MATCH 1st Rising Edge After 1st Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH – 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-36 • FIFO FULL Flag and AFULL Flag Deassertion R ev i si o n 1 6 2- 75 IGLOO PLUS DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-96 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. Units tENS REN, WEN Setup Time 1.66 ns tENH REN, WEN Hold Time 0.13 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (WD) Setup Time 0.63 ns tDH Input Data (WD) Hold Time 0.20 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.77 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 1.50 ns tRCKEF RCLK High to Empty Flag Valid 2.94 ns tWCKFF WCLK High to Full Flag Valid 2.79 ns tCKAF Clock High to Almost Empty/Full Flag Valid 10.71 ns tRSTFG RESET Low to Empty/Full Flag Valid 2.90 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 10.60 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 1.68 ns RESET Low to Data Out Low on RD (pipelined) 1.68 ns tREMRSTB RESET Removal 0.51 ns tRECRSTB RESET Recovery 2.68 ns tMPWRSTB RESET Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency for FIFO 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 76 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-97 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. Units tENS REN, WEN Setup Time 3.44 ns tENH REN, WEN Hold Time 0.26 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (WD) Setup Time 1.30 ns tDH Input Data (WD) Hold Time 0.41 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 5.67 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 3.02 ns tRCKEF RCLK High to Empty Flag Valid 6.02 ns tWCKFF WCLK High to Full Flag Valid 5.71 ns tCKAF Clock High to Almost Empty/Full Flag Valid 22.17 ns tRSTFG RESET Low to Empty/Full Flag Valid 5.93 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 21.94 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 3.41 ns RESET Low to Data Out Low on RD (pipelined) 3.41 ns tREMRSTB RESET Removal 1.02 ns tRECRSTB RESET Recovery 5.48 ns tMPWRSTB RESET Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency for FIFO 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 1 6 2- 77 IGLOO PLUS DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-37 • Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-98 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. Units tSU Address Setup Time 0.57 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 17.58 ns FMAX Maximum Clock Frequency 15 MHz Std. Units 1.2 V DC Core Voltage Table 2-99 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description tSU Address Setup Time 0.59 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 30.94 ns FMAX Maximum Clock Frequency 10 MHz 2- 78 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details. Timing Characteristics 1.5 V DC Core Voltage Table 2-100 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Std. Units tDISU Test Data Input Setup Time Description 1.00 ns tDIHD Test Data Input Hold Time 2.00 ns tTMSSU Test Mode Select Setup Time 1.00 ns tTMDHD Test Mode Select Hold Time 2.00 ns tTCK2Q Clock to Q (data out) 8.00 ns tRSTB2Q Reset to Q (data out) 25.00 ns FTCKMAX TCK Maximum Frequency 15 MHz tTRSTREM ResetB Removal Time 0.58 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-101 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.50 ns tDIHD Test Data Input Hold Time 3.00 ns tTMSSU Test Mode Select Setup Time 1.50 ns tTMDHD Test Mode Select Hold Time 3.00 ns tTCK2Q Clock to Q (data out) 11.00 ns tRSTB2Q Reset to Q (data out) 30.00 ns FTCKMAX TCK Maximum Frequency 9.00 MHz tTRSTREM ResetB Removal Time 1.18 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 6 2- 79 IGLOO PLUS DC and Switching Characteristics 2- 80 R ev i sio n 1 6 3 – Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V for IGLOO PLUS V5 devices, and 1.2 V or 1.5 V for IGLOO PLUS V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. For IGLOO PLUS V2 devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are four I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device. • 1.5 V for IGLOO PLUS V5 devices • 1.2 V or 1.5 V for IGLOO PLUS V2 devices When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed signal FPGAs " chapter of the IGLOO PLUS FPGA Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on IGLOO PLUS devices. R ev i si o n 1 6 3 -1 Pin Descriptions and Packaging VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on IGLOO PLUS devices. VJTAG JTAG Supply Voltage Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage IGLOO PLUS devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: GL • Output buffer is disabled (with tristate value of high impedance) • Input buffer is disabled (with tristate value of high impedance) • Weak pull-up is programmed Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the IGLOO PLUS FPGA Fabric User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure chapter of the IGLOO PLUS FPGA Fabric User’s Guide for an explanation of the naming of global pins. 3- 2 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs FF Flash*Freeze Mode Activation Pin The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS Device Family User’s Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 • Flash*Freeze Pin Location in IGLOO PLUS Devices Package Flash*Freeze Pin CS281 W2 CS201 R4 CS289 U1 VQ128 34 VQ176 47 R ev i si o n 1 6 3 -3 Pin Descriptions and Packaging JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pullup/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2 for more information. Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pulldown resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. 3- 4 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Related Documents IGLOO PLUS Device Family User’s Guide http://www.microsemi.com/soc/documents/IGLOOPLUS_UG.pdf The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical drawings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials are available at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 6 3 -5 4 – Package Pin Assignments VQ128 128 1 128-Pin VQFP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Pin information is in the "Pin Descriptions" chapter of the IGLOO PLUS FPGA Fabric User’s Guide. R ev i si o n 1 6 4 -1 Package Pin Assignments VQ128 VQ128 VQ128 Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function 1 IO119RSB3 36 IO88RSB2 71 IO57RSB1 2 IO118RSB3 37 IO86RSB2 72 VCCIB1 3 IO117RSB3 38 IO84RSB2 73 GND 4 IO115RSB3 39 IO83RSB2 74 IO55RSB1 5 IO116RSB3 40 GND 75 IO54RSB1 6 IO113RSB3 41 VCCIB2 76 IO53RSB1 7 IO114RSB3 42 IO82RSB2 77 IO52RSB1 8 GND 43 IO81RSB2 78 IO51RSB1 9 VCCIB3 44 IO79RSB2 79 IO50RSB1 10 IO112RSB3 45 IO78RSB2 80 IO49RSB1 11 IO111RSB3 46 IO77RSB2 81 VCC 12 IO110RSB3 47 IO75RSB2 82 GDB0/IO48RSB1 13 IO109RSB3 48 IO74RSB2 83 GDA0/IO47RSB1 14 GEC0/IO108RSB3 49 VCC 84 GDC0/IO46RSB1 15 GEA0/IO107RSB3 50 IO73RSB2 85 IO45RSB1 16 GEB0/IO106RSB3 51 IO72RSB2 86 IO44RSB1 17 VCC 52 IO70RSB2 87 IO43RSB1 18 IO104RSB3 53 IO69RSB2 88 IO42RSB1 19 IO103RSB3 54 IO68RSB2 89 VCCIB1 20 IO102RSB3 55 IO66RSB2 90 GND 21 IO101RSB3 56 IO65RSB2 91 IO40RSB1 22 IO100RSB3 57 GND 92 IO41RSB1 23 IO99RSB3 58 VCCIB2 93 IO39RSB1 24 GND 59 IO63RSB2 94 IO38RSB1 25 VCCIB3 60 IO61RSB2 95 IO37RSB1 26 IO97RSB3 61 IO59RSB2 96 IO36RSB1 27 IO98RSB3 62 TCK 97 IO35RSB0 28 IO95RSB3 63 TDI 98 IO34RSB0 29 IO96RSB3 64 TMS 99 IO33RSB0 30 IO94RSB3 65 VPUMP 100 IO32RSB0 31 IO93RSB3 66 TDO 101 IO30RSB0 32 IO92RSB3 67 TRST 102 IO28RSB0 33 IO91RSB2 68 IO58RSB1 103 IO27RSB0 34 FF/IO90RSB2 69 VJTAG 104 VCCIB0 35 IO89RSB2 70 IO56RSB1 105 GND 4- 2 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs VQ128 Pin Number AGLP030 Function 106 IO26RSB0 107 IO25RSB0 108 IO23RSB0 109 IO22RSB0 110 IO21RSB0 111 IO19RSB0 112 IO18RSB0 113 VCC 114 IO17RSB0 115 IO16RSB0 116 IO14RSB0 117 IO13RSB0 118 IO12RSB0 119 IO10RSB0 120 IO09RSB0 121 VCCIB0 122 GND 123 IO07RSB0 124 IO05RSB0 125 IO03RSB0 126 IO02RSB0 127 IO01RSB0 128 IO00RSB0 R ev i si o n 1 6 4 -3 Package Pin Assignments VQ176 1176 176-Pin VQFP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 4 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs VQ176 VQ176 VQ176 Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function 1 GAA2/IO156RSB3 36 IO119RSB3 70 IO89RSB2 2 IO155RSB3 37 GND 71 IO88RSB2 3 GAB2/IO154RSB3 38 VCCIB3 72 IO87RSB2 4 IO153RSB3 39 GEC1/IO116RSB3 73 IO86RSB2 5 GAC2/IO152RSB3 40 GEB1/IO114RSB3 74 IO85RSB2 6 GND 41 GEC0/IO115RSB3 75 IO84RSB2 7 VCCIB3 42 GEB0/IO113RSB3 76 GND 8 IO149RSB3 43 GEA1/IO112RSB3 77 VCCIB2 9 IO147RSB3 44 GEA0/IO111RSB3 78 IO83RSB2 10 IO145RSB3 45 GEA2/IO110RSB2 79 IO82RSB2 11 IO144RSB3 46 NC 80 GDC2/IO80RSB2 12 IO143RSB3 47 81 IO81RSB2 13 VCC FF/GEB2/IO109R SB2 82 GDA2/IO78RSB2 48 GEC2/IO108RSB2 83 GDB2/IO79RSB2 49 IO106RSB2 84 NC 50 IO107RSB2 85 NC 51 IO104RSB2 86 TCK 52 IO105RSB2 87 TDI 53 IO102RSB2 88 TMS 54 IO103RSB2 89 VPUMP 55 GND 90 TDO 56 VCCIB2 91 TRST 57 IO101RSB2 92 VJTAG 58 IO100RSB2 93 GDA1/IO76RSB1 59 IO99RSB2 94 GDC0/IO73RSB1 60 IO98RSB2 95 GDB1/IO74RSB1 61 IO97RSB2 96 GDC1/IO72RSB1 62 IO96RSB2 97 VCCIB1 63 IO95RSB2 98 GND 64 IO94RSB2 99 IO70RSB1 65 IO93RSB2 100 IO69RSB1 66 VCC 101 IO67RSB1 67 IO92RSB2 102 IO66RSB1 68 IO91RSB2 103 IO65RSB1 69 IO90RSB2 104 IO63RSB1 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 IO141RSB3 GFC1/IO140RSB3 GFB1/IO138RSB3 GFB0/IO137RSB3 VCOMPLF GFA1/IO136RSB3 VCCPLF GFA0/IO135RSB3 GND VCCIB3 GFA2/IO134RSB3 GFB2/IO133RSB3 GFC2/IO132RSB3 IO131RSB3 IO130RSB3 IO129RSB3 IO127RSB3 IO126RSB3 IO125RSB3 IO123RSB3 IO122RSB3 IO121RSB3 R ev i si o n 1 6 4 -5 Package Pin Assignments VQ176 VQ176 VQ176 Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function 105 IO62RSB1 140 GBB0/IO32RSB0 175 GAA1/IO01RSB0 106 IO61RSB1 141 GBC0/IO30RSB0 176 GAA0/IO00RSB0 107 GCC2/IO60RSB1 142 IO29RSB0 108 GCB2/IO59RSB1 143 IO28RSB0 109 GCA2/IO58RSB1 144 IO27RSB0 110 GCA0/IO57RSB1 145 VCCIB0 111 GCA1/IO56RSB1 146 GND 112 VCCIB1 147 IO26RSB0 113 GND 148 IO25RSB0 114 GCB0/IO55RSB1 149 IO24RSB0 115 GCB1/IO54RSB1 150 IO23RSB0 116 GCC0/IO53RSB1 151 IO22RSB0 117 GCC1/IO52RSB1 152 IO21RSB0 118 IO51RSB1 153 IO20RSB0 119 IO50RSB1 154 IO19RSB0 120 VCC 155 IO18RSB0 121 IO48RSB1 156 VCC 122 IO47RSB1 157 IO17RSB0 123 IO45RSB1 158 IO16RSB0 124 IO44RSB1 159 IO15RSB0 125 IO43RSB1 160 IO14RSB0 126 VCCIB1 161 IO13RSB0 127 GND 162 IO12RSB0 128 GBC2/IO40RSB1 163 IO11RSB0 129 IO39RSB1 164 IO10RSB0 130 GBB2/IO38RSB1 165 IO09RSB0 131 IO37RSB1 166 VCCIB0 132 GBA2/IO36RSB1 167 GND 133 GBA1/IO35RSB0 168 IO07RSB0 134 NC 169 IO08RSB0 135 GBA0/IO34RSB0 170 GAC1/IO05RSB0 136 NC 171 IO06RSB0 137 GBB1/IO33RSB0 172 GAB1/IO03RSB0 138 NC 173 GAC0/IO04RSB0 139 GBC1/IO31RSB0 174 GAB0/IO02RSB0 4- 6 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS201 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 6 4 -7 Package Pin Assignments CS201 CS201 CS201 Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function A1 NC C6 IO12RSB0 F3 IO119RSB3 A2 IO04RSB0 C7 IO23RSB0 F4 IO111RSB3 A3 IO06RSB0 C8 IO19RSB0 F6 GND A4 IO09RSB0 C9 IO28RSB0 F7 VCC A5 IO11RSB0 C10 IO32RSB0 F8 VCCIB0 A6 IO13RSB0 C11 IO35RSB0 F9 VCCIB0 A7 IO17RSB0 C12 NC F10 VCCIB0 A8 IO18RSB0 C13 GND F12 NC A9 IO24RSB0 C14 IO41RSB1 F13 NC A10 IO26RSB0 C15 IO37RSB1 F14 IO40RSB1 A11 IO27RSB0 D1 IO117RSB3 F15 IO38RSB1 A12 IO31RSB0 D2 IO118RSB3 G1 NC A13 NC D3 NC G2 IO112RSB3 A14 NC D4 GND G3 IO110RSB3 A15 NC D5 IO01RSB0 G4 IO109RSB3 B1 NC D6 IO03RSB0 G6 VCCIB3 B2 NC D7 IO10RSB0 G7 GND B3 IO08RSB0 D8 IO21RSB0 G8 VCC B4 IO05RSB0 D9 IO25RSB0 G9 GND B5 IO07RSB0 D10 IO30RSB0 G10 GND B6 IO15RSB0 D11 IO33RSB0 G12 NC B7 IO14RSB0 D12 GND G13 NC B8 IO16RSB0 D13 NC G14 IO42RSB1 B9 IO20RSB0 D14 IO36RSB1 G15 IO44RSB1 B10 IO22RSB0 D15 IO39RSB1 H1 NC B11 IO34RSB0 E1 IO115RSB3 H2 GEB0/IO106RSB3 B12 IO29RSB0 E2 IO114RSB3 H3 GEC0/IO108RSB3 B13 NC E3 NC H4 NC B14 NC E4 NC H6 VCCIB3 B15 NC E12 NC H7 GND C1 NC E13 NC H8 VCC C2 NC E14 GDC0/IO46RSB1 H9 GND C3 GND E15 GDB0/IO48RSB1 H10 VCCIB1 C4 IO00RSB0 F1 IO113RSB3 H12 IO54RSB1 C5 IO02RSB0 F2 IO116RSB3 H13 GDA0/IO47RSB1 4- 8 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS201 CS201 CS201 Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function H14 IO45RSB1 L15 IO58RSB1 P5 IO87RSB2 H15 IO43RSB1 M1 IO93RSB3 P6 IO86RSB2 J1 GEA0/IO107RSB3 M2 IO92RSB3 P7 IO84RSB2 J2 IO105RSB3 M3 IO97RSB3 P8 IO80RSB2 J3 IO104RSB3 M4 GND P9 IO74RSB2 J4 IO102RSB3 M5 NC P10 IO73RSB2 J6 VCCIB3 M6 IO79RSB2 P11 IO76RSB2 J7 GND M7 IO77RSB2 P12 IO67RSB2 J8 VCC M8 IO72RSB2 P13 IO64RSB2 J9 GND M9 IO70RSB2 P14 VPUMP J10 VCCIB1 M10 IO61RSB2 P15 TRST J12 NC M11 IO59RSB2 R1 NC J13 NC M12 GND R2 NC J14 IO52RSB1 M13 NC R3 IO91RSB2 J15 IO50RSB1 M14 IO55RSB1 R4 FF/IO90RSB2 K1 IO103RSB3 M15 IO56RSB1 R5 IO89RSB2 K2 IO101RSB3 N1 NC R6 IO83RSB2 K3 IO99RSB3 N2 NC R7 IO82RSB2 K4 IO100RSB3 N3 GND R8 IO85RSB2 K6 GND N4 NC R9 IO78RSB2 K7 VCCIB2 N5 IO88RSB2 R10 IO69RSB2 K8 VCCIB2 N6 IO81RSB2 R11 IO62RSB2 K9 VCCIB2 N7 IO75RSB2 R12 IO60RSB2 K10 VCCIB1 N8 IO68RSB2 R13 TMS K12 NC N9 IO66RSB2 R14 TDI K13 IO57RSB1 N10 IO65RSB2 R15 TCK K14 IO49RSB1 N11 IO71RSB2 K15 IO53RSB1 N12 IO63RSB2 L1 IO96RSB3 N13 GND L2 IO98RSB3 N14 TDO L3 IO95RSB3 N15 VJTAG L4 IO94RSB3 P1 NC L12 NC P2 NC L13 NC P3 NC L14 IO51RSB1 P4 NC R ev i si o n 1 6 4 -9 Package Pin Assignments CS201 CS201 CS201 Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function A1 IO150RSB3 C6 IO07RSB0 F3 IO145RSB3 A2 GAA0/IO00RSB0 C7 IO16RSB0 F4 IO147RSB3 A3 GAC0/IO04RSB0 C8 IO21RSB0 F6 GND A4 IO08RSB0 C9 IO28RSB0 F7 VCC A5 IO11RSB0 C10 GBB1/IO33RSB0 F8 VCCIB0 A6 IO15RSB0 C11 GBA1/IO35RSB0 F9 VCCIB0 A7 IO17RSB0 C12 GBB2/IO38RSB1 F10 VCCIB0 A8 IO18RSB0 C13 GND F12 IO47RSB1 A9 IO22RSB0 C14 IO48RSB1 F13 IO45RSB1 A10 IO26RSB0 C15 IO39RSB1 F14 GCC1/IO52RSB1 A11 IO29RSB0 D1 IO146RSB3 F15 GCA1/IO56RSB1 A12 GBC1/IO31RSB0 D2 IO144RSB3 G1* VCOMPLF A13 GBA2/IO36RSB1 D3 IO148RSB3 G2 GFB0/IO137RSB3 A14 IO41RSB1 D4 GND G3 GFC0/IO139RSB3 A15 NC D5 GAB0/IO02RSB0 G4 IO143RSB3 B1 IO151RSB3 D6 GAC1/IO05RSB0 G6 VCCIB3 B2 GAB2/IO154RSB3 D7 IO14RSB0 G7 GND B3 IO06RSB0 D8 IO19RSB0 G8 VCC B4 IO09RSB0 D9 GBC0/IO30RSB0 G9 GND B5 IO13RSB0 D10 GBB0/IO32RSB0 G10 GND B6 IO10RSB0 D11 GBA0/IO34RSB0 G12 IO50RSB1 B7 IO12RSB0 D12 GND G13 GCB1/IO54RSB1 B8 IO20RSB0 D13 GBC2/IO40RSB1 G14 GCC2/IO60RSB1 B9 IO23RSB0 D14 IO51RSB1 G15 GCA2/IO58RSB1 B10 IO25RSB0 D15 IO44RSB1 H1* VCCPLF B11 IO24RSB0 E1 IO142RSB3 H2 GFA1/IO136RSB3 B12 IO27RSB0 E2 IO149RSB3 H3 GFB1/IO138RSB3 B13 IO37RSB1 E3 IO153RSB3 H4 NC B14 IO46RSB1 E4 GAC2/IO152RSB3 H6 VCCIB3 B15 IO42RSB1 E12 IO43RSB1 H7 GND C1 IO155RSB3 E13 IO49RSB1 H8 VCC C2 GAA2/IO156RSB3 E14 GCC0/IO53RSB1 H9 GND C3 GND E15 GCB0/IO55RSB1 H10 VCCIB1 C4 GAA1/IO01RSB0 F1 IO141RSB3 H12 GCB2/IO59RSB1 C5 GAB1/IO03RSB0 F2 GFC1/IO140RSB3 H13 GCA0/IO57RSB1 Note: *Pin numbers G1 and H1 must be connected to ground because a PLL is not supported for AGLP060-CS/G201. 4- 10 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS201 CS201 CS201 Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function H14 IO64RSB1 L15 GDC0/IO73RSB1 P5 IO106RSB2 H15 IO62RSB1 M1 IO122RSB3 P6 IO105RSB2 J1 GFA2/IO134RSB3 M2 IO124RSB3 P7 IO103RSB2 J2 GFA0/IO135RSB3 M3 IO119RSB3 P8 IO99RSB2 J3 GFB2/IO133RSB3 M4 GND P9 IO93RSB2 J4 IO131RSB3 M5 IO125RSB3 P10 IO92RSB2 J6 VCCIB3 M6 IO98RSB2 P11 IO95RSB2 J7 GND M7 IO96RSB2 P12 IO86RSB2 J8 VCC M8 IO91RSB2 P13 IO83RSB2 J9 GND M9 IO89RSB2 P14 VPUMP J10 VCCIB1 M10 IO82RSB2 P15 TRST J12 IO61RSB1 M11 GDA2/IO78RSB2 R1 IO118RSB3 J13 IO63RSB1 M12 GND R2 GEB0/IO113RSB3 J14 IO68RSB1 M13 GDA1/IO76RSB1 R3 GEA2/IO110RSB2 J15 IO66RSB1 M14 GDA0/IO77RSB1 R4 K1 IO130RSB3 M15 GDB0/IO75RSB1 FF/GEB2/IO109RS B2 K2 GFC2/IO132RSB3 N1 IO117RSB3 R5 GEC2/IO108RSB2 K3 IO127RSB3 N2 IO120RSB3 R6 IO102RSB2 K4 IO129RSB3 N3 GND R7 IO101RSB2 K6 GND N4 GEB1/IO114RSB3 R8 IO104RSB2 K7 VCCIB2 N5 IO107RSB2 R9 IO97RSB2 K8 VCCIB2 N6 IO100RSB2 R10 IO88RSB2 K9 VCCIB2 N7 IO94RSB2 R11 IO81RSB2 K10 VCCIB1 N8 IO87RSB2 R12 GDB2/IO79RSB2 K12 IO65RSB1 N9 IO85RSB2 R13 TMS K13 IO67RSB1 N10 GDC2/IO80RSB2 R14 TDI K14 IO69RSB1 N11 IO90RSB2 R15 TCK K15 IO70RSB1 N12 IO84RSB2 L1 IO126RSB3 N13 GND L2 IO128RSB3 N14 TDO L3 IO121RSB3 N15 VJTAG L4 IO123RSB3 P1 GEC0/IO115RSB3 L12 GDB1/IO74RSB1 P2 GEC1/IO116RSB3 L13 GDC1/IO72RSB1 P3 GEA0/IO111RSB3 L14 IO71RSB1 P4 GEA1/IO112RSB3 R ev i si o n 1 6 4- 11 Package Pin Assignments CS281 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 4- 12 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS281 CS281 CS281 Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function A1 GND B18 VCCIB1 E13 IO48RSB0 A2 GAB0/IO02RSB0 B19 IO64RSB1 E14 GBB1/IO60RSB0 A3 GAC1/IO05RSB0 C1 GAB2/IO209RSB3 E15 IO53RSB0 A4 IO09RSB0 C2 IO210RSB3 E16 IO69RSB1 A5 IO13RSB0 C6 IO12RSB0 E18 IO68RSB1 A6 IO15RSB0 C14 IO47RSB0 E19 IO71RSB1 A7 IO18RSB0 C18 IO54RSB0 F1 IO198RSB3 A8 IO23RSB0 C19 GBB2/IO65RSB1 F2 GND A9 IO25RSB0 D1 IO206RSB3 F3 IO201RSB3 A10 VCCIB0 D2 IO208RSB3 F4 IO204RSB3 A11 IO33RSB0 D4 GAA0/IO00RSB0 F5 IO16RSB0 A12 IO41RSB0 D5 GAA1/IO01RSB0 F15 IO50RSB0 A13 IO43RSB0 D6 IO10RSB0 F16 IO74RSB1 A14 IO46RSB0 D7 IO17RSB0 F17 IO72RSB1 A15 IO55RSB0 D8 IO24RSB0 F18 GND A16 IO56RSB0 D9 IO27RSB0 F19 IO73RSB1 A17 GBC1/IO58RSB0 D10 GND G1 IO195RSB3 A18 GBA0/IO61RSB0 D11 IO31RSB0 G2 IO200RSB3 A19 GND D12 IO40RSB0 G4 IO202RSB3 B1 GAA2/IO211RSB3 D13 IO49RSB0 G5 IO08RSB0 B2 VCCIB0 D14 IO45RSB0 G7 GAC2/IO207RSB3 B3 GAB1/IO03RSB0 D15 GBB0/IO59RSB0 G8 VCCIB0 B4 GAC0/IO04RSB0 D16 GBA2/IO63RSB1 G9 IO26RSB0 B5 IO11RSB0 D18 GBC2/IO67RSB1 G10 IO35RSB0 B6 GND D19 IO66RSB1 G11 IO44RSB0 B7 IO21RSB0 E1 IO203RSB3 G12 VCCIB0 B8 IO22RSB0 E2 IO205RSB3 G13 IO51RSB0 B9 IO28RSB0 E4 IO07RSB0 G15 IO70RSB1 B10 IO32RSB0 E5 IO06RSB0 G16 IO75RSB1 B11 IO36RSB0 E6 IO14RSB0 G18 GCC0/IO80RSB1 B12 IO39RSB0 E7 IO20RSB0 G19 GCB1/IO81RSB1 B13 IO42RSB0 E8 IO29RSB0 H1 GFB0/IO191RSB3 B14 GND E9 IO34RSB0 H2 IO196RSB3 B15 IO52RSB0 E10 IO30RSB0 H4 GFC1/IO194RSB3 B16 GBC0/IO57RSB0 E11 IO37RSB0 H5 GFB1/IO192RSB3 B17 GBA1/IO62RSB0 E12 IO38RSB0 H7 VCCIB3 R ev i si o n 1 6 4- 13 Package Pin Assignments CS281 CS281 CS281 Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function H8 VCC K15 IO89RSB1 N4 IO182RSB3 H9 VCCIB0 K16 GND N5 IO161RSB2 H10 VCC K18 IO88RSB1 N7 GEA2/IO164RSB2 H11 VCCIB0 K19 VCCIB1 N8 VCCIB2 H12 VCC L1 GFB2/IO187RSB3 N9 IO137RSB2 H13 VCCIB1 L2 IO185RSB3 N10 IO135RSB2 H15 IO77RSB1 L4 GFC2/IO186RSB3 N11 IO131RSB2 H16 GCB0/IO82RSB1 L5 IO184RSB3 N12 VCCIB2 H18 GCA1/IO83RSB1 L7 IO199RSB3 N13 VPUMP H19 GCA2/IO85RSB1 L8 VCCIB3 N15 IO117RSB2 J1 VCOMPLF L9 GND N16 IO96RSB1 J2 GFA0/IO189RSB3 L10 GND N18 IO98RSB1 J4 VCCPLF L11 GND N19 IO94RSB1 J5 GFC0/IO193RSB3 L12 VCCIB1 P1 IO174RSB3 J7 GFA2/IO188RSB3 L13 IO95RSB1 P2 GND J8 VCCIB3 L15 IO91RSB1 P3 IO176RSB3 J9 GND L16 NC P4 IO177RSB3 J10 GND L18 IO90RSB1 P5 GEA0/IO165RSB3 J11 GND L19 NC P15 IO111RSB2 J12 VCCIB1 M1 IO180RSB3 P16 IO108RSB2 J13 GCC1/IO79RSB1 M2 IO179RSB3 P17 GDC1/IO99RSB1 J15 GCA0/IO84RSB1 M4 IO181RSB3 P18 GND J16 GCB2/IO86RSB1 M5 IO183RSB3 P19 IO97RSB1 J18 IO76RSB1 M7 VCCIB3 R1 IO173RSB3 J19 IO78RSB1 M8 VCC R2 IO172RSB3 K1 VCCIB3 M9 VCCIB2 R4 GEC1/IO170RSB3 K2 GFA1/IO190RSB3 M10 VCC R5 GEB1/IO168RSB3 K4 GND M11 VCCIB2 R6 IO154RSB2 K5 IO19RSB0 M12 VCC R7 IO149RSB2 K7 IO197RSB3 M13 VCCIB1 R8 IO146RSB2 K8 VCC M15 IO122RSB2 R9 IO138RSB2 K9 GND M16 IO93RSB1 R10 IO134RSB2 K10 GND M18 IO92RSB1 R11 IO132RSB2 K11 GND M19 NC R12 IO130RSB2 K12 VCC N1 IO178RSB3 R13 IO118RSB2 K13 GCC2/IO87RSB1 N2 IO175RSB3 R14 IO112RSB2 4- 14 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS281 CS281 Pin Number AGLP125 Function Pin Number AGLP125 Function R15 IO109RSB2 V10 IO133RSB2 R16 GDA1/IO103RSB1 V11 IO127RSB2 R18 GDB0/IO102RSB1 V12 IO123RSB2 R19 GDC0/IO100RSB1 V13 IO120RSB2 T1 IO171RSB3 V14 GND T2 GEC0/IO169RSB3 V15 IO113RSB2 T4 GEB0/IO167RSB3 V16 GDA2/IO105RSB2 T5 IO157RSB2 V17 TDI T6 IO158RSB2 V18 VCCIB2 T7 IO148RSB2 V19 TDO T8 IO145RSB2 W1 GND T9 IO143RSB2 W2 T10 GND FF/GEB2/IO163RSB 2 T11 IO129RSB2 W3 IO155RSB2 T12 IO126RSB2 W4 IO152RSB2 T13 IO125RSB2 W5 IO150RSB2 T14 IO116RSB2 W6 IO147RSB2 T15 GDC2/IO107RSB2 W7 IO142RSB2 T16 TMS W8 IO139RSB2 T18 VJTAG W9 IO136RSB2 T19 GDB1/IO101RSB1 W10 VCCIB2 U1 IO160RSB2 W11 IO128RSB2 U2 GEA1/IO166RSB3 W12 IO124RSB2 U6 IO151RSB2 W13 IO119RSB2 U14 IO121RSB2 W14 IO115RSB2 U18 TRST W15 IO114RSB2 U19 GDA0/IO104RSB1 W16 IO110RSB2 V1 IO159RSB2 W17 GDB2/IO106RSB2 V2 VCCIB3 W18 TCK V3 GEC2/IO162RSB2 W19 GND V4 IO156RSB2 V5 IO153RSB2 V6 GND V7 IO144RSB2 V8 IO141RSB2 V9 IO140RSB2 R ev i si o n 1 6 4- 15 Package Pin Assignments CS289 A1 Ball Pad Corner 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx . 4- 16 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS289 CS289 CS289 Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function A1 IO03RSB0 C4 NC E7 IO06RSB0 A2 NC C5 VCCIB0 E8 IO11RSB0 A3 NC C6 IO09RSB0 E9 IO22RSB0 A4 GND C7 IO13RSB0 E10 IO26RSB0 A5 IO10RSB0 C8 IO15RSB0 E11 VCCIB0 A6 IO14RSB0 C9 IO21RSB0 E12 NC A7 IO16RSB0 C10 GND E13 IO33RSB0 A8 IO18RSB0 C11 IO29RSB0 E14 IO36RSB1 A9 GND C12 NC E15 IO38RSB1 A10 IO23RSB0 C13 NC E16 VCCIB1 A11 IO27RSB0 C14 NC E17 NC A12 NC C15 GND F1 IO111RSB3 A13 NC C16 IO34RSB0 F2 NC A14 GND C17 NC F3 IO116RSB3 A15 NC D1 NC F4 VCCIB3 A16 NC D2 IO119RSB3 F5 IO117RSB3 A17 IO30RSB0 D3 GND F6 NC B1 IO01RSB0 D4 IO02RSB0 F7 NC B2 GND D5 NC F8 IO08RSB0 B3 NC D6 NC F9 IO12RSB0 B4 NC D7 NC F10 NC B5 IO07RSB0 D8 GND F11 NC B6 NC D9 IO20RSB0 F12 NC B7 VCCIB0 D10 IO25RSB0 F13 NC B8 IO17RSB0 D11 NC F14 GND B9 IO19RSB0 D12 NC F15 NC B10 IO24RSB0 D13 GND F16 IO37RSB1 B11 IO28RSB0 D14 IO32RSB0 F17 IO41RSB1 B12 VCCIB0 D15 IO35RSB0 G1 IO110RSB3 B13 NC D16 NC G2 GND B14 NC D17 NC G3 IO113RSB3 B15 NC E1 VCCIB3 G4 NC B16 IO31RSB0 E2 IO114RSB3 G5 NC B17 GND E3 IO115RSB3 G6 NC C1 NC E4 IO118RSB3 G7 GND C2 IO00RSB0 E5 IO05RSB0 G8 GND C3 IO04RSB0 E6 NC G9 VCC R ev i si o n 1 6 4- 17 Package Pin Assignments CS289 CS289 CS289 Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function G10 GND J13 IO43RSB1 L16 NC G11 GND J14 IO51RSB1 L17 NC G12 IO40RSB1 J15 IO52RSB1 M1 NC G13 NC J16 GDC0/IO46RSB1 M2 VCCIB3 G14 IO39RSB1 J17 GDA0/IO47RSB1 M3 IO100RSB3 G15 IO44RSB1 K1 GND M4 IO98RSB3 G16 NC K2 GEB0/IO106RSB3 M5 IO93RSB3 G17 GND K3 IO102RSB3 M6 IO97RSB3 H1 NC K4 IO104RSB3 M7 NC H2 GEC0/IO108RSB3 K5 IO99RSB3 M8 NC H3 NC K6 NC M9 IO71RSB2 H4 IO112RSB3 K7 GND M10 NC H5 NC K8 GND M11 IO63RSB2 H6 IO109RSB3 K9 GND M12 NC H7 GND K10 GND M13 IO57RSB1 H8 GND K11 GND M14 NC H9 GND K12 NC M15 NC H10 GND K13 NC M16 NC H11 GND K14 NC M17 VCCIB1 H12 NC K15 IO53RSB1 N1 NC H13 NC K16 GND N2 NC H14 IO45RSB1 K17 IO49RSB1 N3 IO95RSB3 H15 VCCIB1 L1 IO103RSB3 N4 IO96RSB3 H16 GDB0/IO48RSB1 L2 IO101RSB3 N5 GND H17 IO42RSB1 L3 NC N6 NC J1 NC L4 GND N7 IO85RSB2 J2 GEA0/IO107RSB3 L5 NC N8 IO79RSB2 J3 VCCIB3 L6 NC N9 IO77RSB2 J4 IO105RSB3 L7 GND N10 VCCIB2 J5 NC L8 GND N11 NC J6 NC L9 VCC N12 NC J7 VCC L10 GND N13 IO59RSB2 J8 GND L11 GND N14 NC J9 GND L12 IO58RSB1 N15 GND J10 GND L13 IO54RSB1 N16 IO56RSB1 J11 VCC L14 VCCIB1 N17 IO55RSB1 J12 IO50RSB1 L15 NC P1 IO94RSB3 4- 18 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS289 CS289 Pin Number AGLP030 Function Pin Number AGLP030 Function P2 NC T5 NC P3 GND T6 IO84RSB2 P4 NC T7 IO81RSB2 P5 NC T8 IO76RSB2 P6 IO87RSB2 T9 VCCIB2 P7 IO80RSB2 T10 IO69RSB2 P8 GND T11 IO65RSB2 P9 IO72RSB2 T12 IO64RSB2 P10 IO67RSB2 T13 NC P11 IO61RSB2 T14 GND P12 NC T15 NC P13 VCCIB2 T16 TDI P14 NC T17 TDO P15 IO60RSB2 U1 FF/IO90RSB2 P16 IO62RSB2 U2 GND P17 VJTAG U3 NC R1 GND U4 IO88RSB2 R2 IO91RSB2 U5 IO86RSB2 R3 NC U6 IO82RSB2 R4 NC U7 GND R5 NC U8 IO75RSB2 R6 VCCIB2 U9 IO73RSB2 R7 IO83RSB2 U10 IO68RSB2 R8 IO78RSB2 U11 IO66RSB2 R9 IO74RSB2 U12 GND R10 IO70RSB2 U13 NC R11 GND U14 NC R12 NC U15 NC R13 NC U16 TCK R14 NC U17 VPUMP R15 NC R16 TMS R17 TRST T1 IO92RSB3 T2 IO89RSB2 T3 NC T4 GND R ev i si o n 1 6 4- 19 Package Pin Assignments CS289 CS289 CS289 Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function A1 GAB1/IO03RSB0 C5 VCCIB0 E9 IO22RSB0 A2 NC C6 IO09RSB0 E10 IO26RSB0 A3 NC C7 IO13RSB0 E11 VCCIB0 A4 GND C8 IO15RSB0 E12 NC A5 IO10RSB0 C9 IO21RSB0 E13 GBB1/IO33RSB0 A6 IO14RSB0 C10 GND E14 GBA2/IO36RSB1 A7 IO16RSB0 C11 IO29RSB0 E15 GBB2/IO38RSB1 A8 IO18RSB0 C12 NC E16 VCCIB1 A9 GND C13 NC E17 IO44RSB1 A10 IO23RSB0 C14 NC F1 GFC1/IO140RSB3 A11 IO27RSB0 C15 GND F2 IO142RSB3 A12 NC C16 GBA0/IO34RSB0 F3 IO149RSB3 A13 NC C17 IO39RSB1 F4 VCCIB3 A14 GND D1 IO150RSB3 F5 GAB2/IO154RSB3 A15 NC D2 IO151RSB3 F6 IO153RSB3 A16 NC D3 GND F7 NC A17 GBC0/IO30RSB0 D4 GAB0/IO02RSB0 F8 IO08RSB0 B1 GAA1/IO01RSB0 D5 NC F9 IO12RSB0 B2 GND D6 NC F10 NC B3 NC D7 NC F11 NC B4 NC D8 GND F12 NC B5 IO07RSB0 D9 IO20RSB0 F13 GBC2/IO40RSB1 B6 NC D10 IO25RSB0 F14 GND B7 VCCIB0 D11 NC F15 IO43RSB1 B8 IO17RSB0 D12 NC F16 IO46RSB1 B9 IO19RSB0 D13 GND F17 IO45RSB1 B10 IO24RSB0 D14 GBB0/IO32RSB0 G1 GFC0/IO139RSB3 B11 IO28RSB0 D15 GBA1/IO35RSB0 G2 GND B12 VCCIB0 D16 IO37RSB1 G3 IO144RSB3 B13 NC D17 IO42RSB1 G4 IO145RSB3 B14 NC E1 VCCIB3 G5 IO146RSB3 B15 NC E2 IO147RSB3 G6 IO148RSB3 B16 GBC1/IO31RSB0 E3 GAC2/IO152RSB3 G7 GND B17 GND E4 GAA2/IO156RSB3 G8 GND C1 IO155RSB3 E5 GAC1/IO05RSB0 G9 VCC C2 GAA0/IO00RSB0 E6 NC G10 GND C3 GAC0/IO04RSB0 E7 IO06RSB0 G11 GND C4 NC E8 IO11RSB0 G12 IO48RSB1 4- 20 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS289 CS289 CS289 Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function G13 IO41RSB1 J17 GCA1/IO56RSB1 M4 IO122RSB3 G14 IO47RSB1 K1 GND M5 GEB0/IO113RSB3 G15 IO49RSB1 K2 GFA0/IO135RSB3 M6 GEB1/IO114RSB3 G16 IO50RSB1 K3 GFB2/IO133RSB3 M7 NC G17 GND K4 IO128RSB3 M8 NC H1 VCOMPLF K5 IO123RSB3 M9 IO90RSB2 H2 GFB0/IO137RSB3 K6 IO125RSB3 M10 NC H3 NC K7 GND M11 IO83RSB2 H4 IO141RSB3 K8 GND M12 NC H5 IO143RSB3 K9 GND M13 GDA1/IO76RSB1 H6 GFB1/IO138RSB3 K10 GND M14 GDA0/IO77RSB1 H7 GND K11 GND M15 IO71RSB1 H8 GND K12 IO64RSB1 M16 IO69RSB1 H9 GND K13 IO61RSB1 M17 VCCIB1 H10 GND K14 IO66RSB1 N1 IO119RSB3 H11 GND K15 IO65RSB1 N2 IO120RSB3 H12 GCC1/IO52RSB1 K16 GND N3 GEC0/IO115RSB3 H13 IO51RSB1 K17 GCC2/IO60RSB1 N4 GEA0/IO111RSB3 H14 GCA0/IO57RSB1 L1 GFA2/IO134RSB3 N5 GND H15 VCCIB1 L2 GFC2/IO132RSB3 N6 NC H16 GCA2/IO58RSB1 L3 IO127RSB3 N7 IO104RSB2 H17 GCC0/IO53RSB1 L4 GND N8 IO98RSB2 J1 VCCPLF L5 IO121RSB3 N9 IO96RSB2 J2 GFA1/IO136RSB3 L6 GEC1/IO116RSB3 N10 VCCIB2 J3 VCCIB3 L7 GND N11 NC J4 IO131RSB3 L8 GND N12 NC J5 IO130RSB3 L9 VCC N13 GDB2/IO79RSB2 J6 IO129RSB3 L10 GND N14 NC J7 VCC L11 GND N15 GND J8 GND L12 GDC1/IO72RSB1 N16 GDB0/IO75RSB1 J9 GND L13 GDB1/IO74RSB1 N17 GDC0/IO73RSB1 J10 GND L14 VCCIB1 P1 IO118RSB3 J11 VCC L15 IO70RSB1 P2 IO117RSB3 J12 GCB2/IO59RSB1 L16 IO68RSB1 P3 GND J13 GCB1/IO54RSB1 L17 IO67RSB1 P4 NC J14 IO62RSB1 M1 IO126RSB3 P5 NC J15 IO63RSB1 M2 VCCIB3 P6 IO106RSB2 J16 GCB0/IO55RSB1 M3 IO124RSB3 P7 IO99RSB2 R ev i si o n 1 6 4- 21 Package Pin Assignments CS289 CS289 Pin Number AGLP060 Function Pin Number AGLP060 Function P8 GND T12 IO82RSB2 P9 IO91RSB2 T13 NC P10 IO86RSB2 T14 GND P11 IO81RSB2 T15 NC P12 NC T16 TDI P13 VCCIB2 T17 TDO P14 NC U1 P15 GDA2/IO78RSB2 FF/GEB2/IO109RS B2 P16 GDC2/IO80RSB2 U2 GND P17 VJTAG U3 NC R1 GND U4 IO107RSB2 R2 GEA2/IO110RSB2 U5 IO105RSB2 R3 NC U6 IO101RSB2 R4 NC U7 GND R5 NC U8 IO94RSB2 R6 VCCIB2 U9 IO92RSB2 R7 IO102RSB2 U10 IO87RSB2 R8 IO97RSB2 U11 IO85RSB2 R9 IO93RSB2 U12 GND R10 IO89RSB2 U13 NC R11 GND U14 NC R12 NC U15 NC R13 NC U16 TCK R14 NC U17 VPUMP R15 NC R16 TMS R17 TRST T1 GEA1/IO112RSB3 T2 GEC2/IO108RSB2 T3 NC T4 GND T5 NC T6 IO103RSB2 T7 IO100RSB2 T8 IO95RSB2 T9 VCCIB2 T10 IO88RSB2 T11 IO84RSB2 4- 22 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS289 CS289 CS289 Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function A1 GAB1/IO03RSB0 C5 VCCIB0 E9 IO32RSB0 A2 IO11RSB0 C6 IO17RSB0 E10 IO36RSB0 A3 IO08RSB0 C7 IO23RSB0 E11 VCCIB0 A4 GND C8 IO27RSB0 E12 IO56RSB0 A5 IO19RSB0 C9 IO33RSB0 E13 GBB1/IO60RSB0 A6 IO24RSB0 C10 GND E14 GBA2/IO63RSB1 A7 IO26RSB0 C11 IO43RSB0 E15 GBB2/IO65RSB1 A8 IO30RSB0 C12 IO45RSB0 E16 VCCIB1 A9 GND C13 IO50RSB0 E17 IO73RSB1 A10 IO35RSB0 C14 IO52RSB0 F1 GFC1/IO194RSB3 A11 IO38RSB0 C15 GND F2 IO196RSB3 A12 IO40RSB0 C16 GBA0/IO61RSB0 F3 IO202RSB3 A13 IO42RSB0 C17 IO68RSB1 F4 VCCIB3 A14 GND D1 IO204RSB3 F5 GAB2/IO209RSB3 A15 IO48RSB0 D2 IO205RSB3 F6 IO208RSB3 A16 IO54RSB0 D3 GND F7 IO14RSB0 A17 GBC0/IO57RSB0 D4 GAB0/IO02RSB0 F8 IO20RSB0 B1 GAA1/IO01RSB0 D5 IO07RSB0 F9 IO25RSB0 B2 GND D6 IO10RSB0 F10 IO29RSB0 B3 IO06RSB0 D7 IO18RSB0 F11 IO51RSB0 B4 IO13RSB0 D8 GND F12 IO53RSB0 B5 IO15RSB0 D9 IO34RSB0 F13 GBC2/IO67RSB1 B6 IO21RSB0 D10 IO41RSB0 F14 GND B7 VCCIB0 D11 IO47RSB0 F15 IO75RSB1 B8 IO28RSB0 D12 IO55RSB0 F16 IO71RSB1 B9 IO31RSB0 D13 GND F17 IO77RSB1 B10 IO37RSB0 D14 GBB0/IO59RSB0 G1 GFC0/IO193RSB3 B11 IO39RSB0 D15 GBA1/IO62RSB0 G2 GND B12 VCCIB0 D16 IO66RSB1 G3 IO198RSB3 B13 IO44RSB0 D17 IO70RSB1 G4 IO203RSB3 B14 IO46RSB0 E1 VCCIB3 G5 IO201RSB3 B15 IO49RSB0 E2 IO200RSB3 G6 IO206RSB3 B16 GBC1/IO58RSB0 E3 GAC2/IO207RSB3 G7 GND B17 GND E4 GAA2/IO211RSB3 G8 GND C1 IO210RSB3 E5 GAC1/IO05RSB0 G9 VCC C2 GAA0/IO00RSB0 E6 IO12RSB0 G10 GND C3 GAC0/IO04RSB0 E7 IO16RSB0 G11 GND C4 IO09RSB0 E8 IO22RSB0 G12 IO72RSB1 R ev i si o n 1 6 4- 23 Package Pin Assignments CS289 CS289 CS289 Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function G13 IO64RSB1 J17 GCA1/IO83RSB1 M4 IO172RSB3 G14 IO69RSB1 K1 GND M5 GEB0/IO167RSB3 G15 IO78RSB1 K2 GFA0/IO189RSB3 M6 GEB1/IO168RSB3 G16 IO76RSB1 K3 GFB2/IO187RSB3 M7 IO159RSB2 G17 GND K4 IO179RSB3 M8 IO161RSB2 H1 VCOMPLF K5 IO175RSB3 M9 IO135RSB2 H2 GFB0/IO191RSB3 K6 IO177RSB3 M10 IO128RSB2 H3 IO195RSB3 K7 GND M11 IO121RSB2 H4 IO197RSB3 K8 GND M12 IO113RSB2 H5 IO199RSB3 K9 GND M13 GDA1/IO103RSB1 H6 GFB1/IO192RSB3 K10 GND M14 GDA0/IO104RSB1 H7 GND K11 GND M15 IO97RSB1 H8 GND K12 IO88RSB1 M16 IO96RSB1 H9 GND K13 IO94RSB1 M17 VCCIB1 H10 GND K14 IO95RSB1 N1 IO180RSB3 H11 GND K15 IO93RSB1 N2 IO178RSB3 H12 GCC1/IO79RSB1 K16 GND N3 GEC0/IO169RSB3 H13 IO74RSB1 K17 GCC2/IO87RSB1 N4 GEA0/IO165RSB3 H14 GCA0/IO84RSB1 L1 GFA2/IO188RSB3 N5 GND H15 VCCIB1 L2 GFC2/IO186RSB3 N6 IO156RSB2 H16 GCA2/IO85RSB1 L3 IO182RSB3 N7 IO148RSB2 H17 GCC0/IO80RSB1 L4 GND N8 IO144RSB2 J1 VCCPLF L5 IO173RSB3 N9 IO137RSB2 J2 GFA1/IO190RSB3 L6 GEC1/IO170RSB3 N10 VCCIB2 J3 VCCIB3 L7 GND N11 IO119RSB2 J4 IO185RSB3 L8 GND N12 IO111RSB2 J5 IO183RSB3 L9 VCC N13 GDB2/IO106RSB2 J6 IO181RSB3 L10 GND N14 IO109RSB2 J7 VCC L11 GND N15 GND J8 GND L12 GDC1/IO99RSB1 N16 GDB0/IO102RSB1 J9 GND L13 GDB1/IO101RSB1 N17 GDC0/IO100RSB1 J10 GND L14 VCCIB1 P1 IO174RSB3 J11 VCC L15 IO98RSB1 P2 IO171RSB3 J12 GCB2/IO86RSB1 L16 IO92RSB1 P3 GND J13 GCB1/IO81RSB1 L17 IO91RSB1 P4 IO160RSB2 J14 IO90RSB1 M1 IO184RSB3 P5 IO157RSB2 J15 IO89RSB1 M2 VCCIB3 P6 IO154RSB2 J16 GCB0/IO82RSB1 M3 IO176RSB3 P7 IO152RSB2 4- 24 R ev i sio n 1 6 IGLOO PLUS Low Power Flash FPGAs CS289 CS289 Pin Number AGLP125 Function Pin Number AGLP125 Function P8 GND T12 IO124RSB2 P9 IO132RSB2 T13 IO122RSB2 P10 IO125RSB2 T14 GND P11 IO126RSB2 T15 IO115RSB2 P12 IO112RSB2 T16 TDI P13 VCCIB2 T17 TDO P14 IO108RSB2 U1 P15 GDA2/IO105RSB2 FF/GEB2/IO163RS B2 P16 GDC2/IO107RSB2 U2 GND P17 VJTAG U3 IO151RSB2 R1 GND U4 IO149RSB2 R2 GEA2/IO164RSB2 U5 IO146RSB2 R3 IO158RSB2 U6 IO142RSB2 R4 IO155RSB2 U7 GND R5 IO150RSB2 U8 IO138RSB2 R6 VCCIB2 U9 IO136RSB2 R7 IO145RSB2 U10 IO133RSB2 R8 IO141RSB2 U11 IO129RSB2 R9 IO134RSB2 U12 GND R10 IO130RSB2 U13 IO123RSB2 R11 GND U14 IO120RSB2 R12 IO118RSB2 U15 IO117RSB2 R13 IO116RSB2 U16 TCK R14 IO114RSB2 U17 VPUMP R15 IO110RSB2 R16 TMS R17 TRST T1 GEA1/IO166RSB3 T2 GEC2/IO162RSB2 T3 IO153RSB2 T4 GND T5 IO147RSB2 T6 IO143RSB2 T7 IO140RSB2 T8 IO139RSB2 T9 VCCIB2 T10 IO131RSB2 T11 IO127RSB2 R ev i si o n 1 6 4- 25 5 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet. Revision Revision 16 (December 2012) Changes Page The "IGLOO PLUS Ordering Information" section has been updated to mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43175). III The note in Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to the online help associated with the core (SAR 42566). 2-61, 2-62 Live at Power-Up (LAPU) has been replaced with ’Instant On’. Revision 15 (October 2012) NA Values updated for IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage in Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices and for IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage in Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices (SAR 31988). Also added a new Note to the two tables. 2-10, 2-11 Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40277). N/A Revision 14 (September 2012) The "Security" section was modified to clarify that Microsemi does not support readback of programmed data. 1-2 Revision 13 (June 2012) Figure 2-30 • FIFO Read and Figure 2-31 • FIFO Write have been added (SAR 34843). 2-73 Updated the terminology used in Timing Characteristics in the following tables: Table 2-96 • FIFO and Table 2-97 • FIFO (SAR 38236). 2-76 The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section in the "Pin Descriptions and Packaging" section: "Within the package, the VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI domain" and replaced with “Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet mentions that "VMV pins must be connected to the corresponding VCCI pins" for an ESD enhancement. 3-1 The "In-System Programming (ISP) and Security" section and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 34664). I, 1-2 The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 34724). III Revision 12 (March 2012) The "Specifying I/O States During Programming" section is new (SAR 34695). 1-7 The following sentence was removed from the "Advanced Architecture" section: 1-3 "In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface" (SAR 34684). R ev i si o n 1 6 5 -1 Datasheet Information Revision Revision 12 (continued) Changes Page The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric User's Guide (SAR 34733). 2-12 tDOUT was corrected to tDIN in Figure 2-4 • Input Buffer Timing Model and Delays (example) (SAR 37107). 2-16 The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section (SAR 34887). 2-27 Minimum pulse width High and Low values were added to the tables in the "Global Tree Timing Characteristics" section. The maximum frequency for global clock parameter was removed from these tables because a frequency on the global is only an indication of what the global network can do. There are other limiters such as the SRAM, I/Os, and PLL. SmartTime software should be used to determine the design frequency (SAR 36963). 2-58 Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS CCC/PLL Specification were updated. A note was added to both tables indicating that when the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available (SAR 34820). 2-61, 2-62 The value for serial clock was missing from these tables and has been restored. The value and units for input cycle-to-cycle jitter were incorrect and have been restored. The note to Table 2-90 • IGLOO PLUS CCC/PLL Specification giving specifications for which measurements done was corrected from VCC/VCCPLL = 1.14 V to VCC/VCCPLL = 1.425 V. The Delay Range in Block: Programmable Delay 2 value in Table 2-91 • IGLOO PLUS CCC/PLL Specification was corrected from 0.025 to 0.863 (SAR 37058). Figure 2-28 • Write Access after Read onto Same Address was deleted. Reference was made to a new application note, Simultaneous Read-Write Operations in DualPort SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 34868). The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" tables, Figure 2-32 • FIFO Reset, and the FIFO "Timing Characteristics" tables were revised to ensure consistency with the software names (SAR 35748). Revision 11 (July 2010) 5- 2 2-65, 2-68, 2-74, 2-76 The "Pin Descriptions and Packaging" chapter has been added (SAR 34769). 3-1 Package names used in the "Package Pin Assignments" section were revised to match standards given in Package Mechanical Drawings (SAR 34769). 4-1 The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "IGLOO PLUS Device Status" table indicates the status for each device in the family. N/A The "Reprogrammable Flash Technology" section was revised to add "250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance." I The "I/Os with Advanced I/O Standards" section was revised to add definitions for hot-swap and cold-sparing. 1-6 Conditional statements regarding hot insertion were removed from the description of VI in Table 2-1 • Absolute Maximum Ratings, since all IGLOO PLUS devices are hot insertion enabled. 2-1 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Revision Revision 11 (continued) Changes Page Table 2-2 • Recommended Operating Conditions1,2 was revised. 1.2 V DC wide range supply voltage and 3.3 V wide range supply voltage (SAR 26270) were added for VCCI. VJTAG DC Voltage was revised (SAR 24052). The value range for VPUMP programming voltage for operation was changed from "0 to 3.45" to "0 to 3.6" (SAR 25220). 2-2 Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized 2-6, 2-7 to TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were revised. Table 2-8 • Power Supply State per Mode is new. 2-7 The tables in the "Quiescent Supply Current" section were updated (SARs 24882 and 24112). Some of the table notes were changed or deleted. 2-7 VIH maximum values in tables were updated as needed to 3.6 V (SARs 20990, 79370). N/A The values in the following tables were updated. 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added to the tables where applicable. Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings 2-9 Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 2-9 Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Table 2-22 • Summary of Maximum and Minimum DC Input Levels Table 2-23 • Summary of AC Measuring Points Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V 2-19 2-20 2-21 2-22 Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V 2-23 Table 2-28 • I/O Output Buffer Maximum Resistances 1 2-24 A table note was added to Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices stating the value for PDC4 is the minimum contribution of the PLL when operating at lowest frequency. 2-11, 2-12 Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances was revised, including addition of 3.3 V and 1.2 V LVCMOS wide range. 2-25 The notes defining RWEAK PULL-UP-MAX and RWEAK PULLDOWN-MAX were revised (SAR 21348). Table 2-30 • I/O Short Currents IOSH/IOSL was revised to include data for 3.3 V and 1.2 V LVCMOS wide range (SAR 79353 and SAR 79366). 2-25 Table 2-31 • Duration of Short Circuit Event before Failure was revised to change the maximum temperature from 110°C to 100°C, with an example of six months instead of three months (SAR 26259). 2-26 R ev i si o n 1 6 5 -3 Datasheet Information Revision Revision 11 (continued) Changes Page The tables in the "Single-Ended I/O Characteristics" section were updated. Notes clarifying IIL and IIH were added. 2-27 Tables for 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added (SAR 79370, SAR 79353, and SAR 79366). Notes in the wide range tables state that the minimum drive strength for any LVCMOS 3.3 V (or LVCMOS 1.2 V) software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 25700). The following sentence was deleted from the "2.5 V LVCMOS" section: It uses a 5 V–tolerant input buffer and push-pull output buffer (SAR 24916). 2-32 The tables in the "Input Register" section, "Output Register" section, and "Output 2-45 Enable Register" section were updated. The tables in the "VersaTile Characteristics" through section were updated. 2-56 The following tables were updated in the "Global Tree Timing Characteristics" section: 2-58 Table 2-85 • AGLP060 Global Resource (1.5 V) Table 2-86 • AGLP125 Global Resource (1.5 V) Table 2-88 • AGLP060 Global Resource (1.2 V) 5- 4 Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS CCC/PLL Specification were revised (SAR 79388). VCO output jitter and maximum peak-to-peak jitter data were changed. Three notes were added to the table in connection with these changes. 2-61 Figure 2-28 • Write Access after Write onto Same Address and Figure 2-29 • Write Access after Read onto Same Address were deleted. N/A The tables in the "SRAM", "FIFO" and "Embedded FlashROM Characteristics" sections were updated. 2-68, 2-78 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Revision Revision 10 (Apr 2009) Product Brief v1.5 DC and Switching Characteristics Advance v0.5 Revision 9 (Feb 2009) Product Brief v1.4 Revision 8 (Jan 2009) Changes Page The –F speed grade is no longer offered for IGLOO PLUS devices. References to it have been removed from the document. The speed grade column and note regarding –F speed grade were removed from "IGLOO PLUS Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. III, IV The "Advanced I/O" section was revised to add two bullets regarding support of wide range power supply voltage. I The "I/Os with Advanced I/O Standards" section was revised to add 3.0 V wide range to the list of supported voltages. The "Wide Range I/O Support" section is new. 1-7 The "CS201" pin table was revised to add a note regarding pins G1 and H1. 4-8 Packaging v1.5 Revision 7 (Dec 2008) Product Brief v1.3 A note was added to IGLOO PLUS Devices: "AGLP060 in CS201 does not support the PLL." I Table 2 • IGLOO PLUS FPGAs Package Size Dimensions was updated to change the nominal size of VQ176 from 100 to 400 mm2. II Revision 6 (Oct 2008) Data was revised significantly in the following tables: DC and Switching Characteristics Advance v0.4 Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V 2-22, 2-33 Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Table 2-50 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Revision 5 (Aug 2008) I to IV Product Brief v1.2 The VQ128 and VQ176 packages were added to Table 1 • IGLOO PLUS Product Family, the "I/Os Per Package 1" table, Table 2 • IGLOO PLUS FPGAs Package Size Dimensions, "IGLOO PLUS Ordering Information", and the "Temperature Grade Offerings" table. Packaging v1.4 The "VQ128" package drawing and pin table are new. 4-2 The "VQ176" package drawing and pin table are new. 4-5 As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A Tables have been updated to reflect default values in the software. The default I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O set. N/A Table note 3 was updated in Table 2-2 • Recommended Operating Conditions1,2 to add the sentence, "VCCI should be at the same voltage within a given I/O bank." References to table notes 5, 6, 7, and 8 were added. Reference to table note 3 was removed from VPUMP Operation and placed next to VCC. 2-2 Table 2-4 • Overshoot and Undershoot Limits 1 was revised to remove "as measured on quiet I/Os" from the title. Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. 2-3 Revision 4 (Jul 2008) Product Brief v1.1 DC and Switching Characteristics Advance v0.3 Revision 3 (Jun 2008) DC and Switching Characteristics Advance v0.2 R ev i si o n 1 6 5 -5 Datasheet Information Revision Revision 3 (continued) Changes Page The table note for Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values do not include I/O static contribution. 2-7 The table note for Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode* was updated to remove VJTAG and VCCI and the statement that values do not include I/O static contribution. 2-7 The table note for Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode was updated to remove the statement that values do not include I/O static contribution. 2-8 Note 2 of Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 was updated to include VCCPLL. Table note 4 was deleted. 2-8 Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software 2-9, 2-9 Settings and Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 were updated to remove static power. The table notes were updated to reflect that power was measured on VCCI. Table note 2 was added to Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings. Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices were updated to change the definition for PDC5 from bank static power to bank quiescent power. Table subtitles were added for Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices, Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices, and Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices. 2-11, 2-12 The "Total Static Power Consumption—PSTAT" section was revised. 2-12 Table 2-32 • Schmitt Trigger Input Hysteresis is new. 2-26 The "CS281" package drawing is new. 4-13 The "CS281" table for the AGLP125 device is new. 4-13 Revision 3 (continued) The "CS289" package drawing was incorrect. The graphic was showing the CS281 mechanical drawing and not the CS289 mechanical drawing. This has now been corrected. 4-17 Revision 2 (Jun 2008) The "CS289" table for the AGLP030 device is new. 4-17 Revision 1 (Jun 2008) The "CS289" table for the AGLP060 device is new. 4-20 Packaging v1.1 The "CS289" table for the AGLP125 device is new. 4-23 Packaging v1.3 Packaging v1.2 5- 6 R ev isio n 1 6 IGLOO PLUS Low Power Flash FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOO PLUS Device" table on page II, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. R ev i si o n 1 6 5 -7 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 51700102-16/12.12