ON FCH040N65S3 F155 N-channel superfet mosfet Datasheet

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FCH040N65S3
N-Channel SuperFET® III MOSFET
650 V, 65 A, 40 mΩ
Description
Features
o
SuperFET® III MOSFET is ON Semiconductor’s brand-new
high voltage super-junction (SJ) MOSFET family that is utilizing
charge balance technology for outstanding low on-resistance
and lower gate charge performance. This advanced technology
is tailored to minimize conduction loss, provide superior switching performance, and withstand extreme dv/dt rate. Consequently, SuperFET III MOSFET is very suitable for various
power system for miniaturization and higher efficiency.
• 700 V @ TJ = 150 C
• Typ. RDS(on) = 35.4 mΩ
• Ultra Low Gate Charge (Typ. Qg = 136 nC)
• Low Effective Output Capacitance (Typ. Coss(eff.) = 1154 pF)
• 100% Avalanche Tested
• RoHS Compliant
Applications
• Telecom / Sever Power Supplies
• Industrial Power Supplies
• UPS / Solar
D
G
G
D
S
TO-247
long leads
S
Absolute Maximum Ratings TC = 25oC unless otherwise noted.
Symbol
VDSS
Drain to Source Voltage
VGSS
Gate to Source Voltage
ID
Drain Current
IDM
Drain Current
(Note 1)
162.5
A
EAS
Single Pulsed Avalanche Energy
(Note 2)
358
mJ
IAS
Avalanche Current
(Note 1)
8.1
A
EAR
Repetitive Avalanche Energy
(Note 1)
4.17
mJ
dv/dt
Parameter
FCH040N65S3_F155
650
- DC
±30
- AC
(f > 1 Hz)
- Continuous (TC = 25oC)
65
- Continuous (TC = 100oC)
41
- Pulsed
MOSFET dv/dt
100
Peak Diode Recovery dv/dt
(Note 3)
(TC = 25oC)
PD
Power Dissipation
TJ, TSTG
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds
TL
±30
- Derate Above 25oC
20
Unit
V
V
A
V/ns
417
W
3.33
W/oC
-55 to +150
oC
300
oC
FCH040N65S3_F155
Unit
Thermal Characteristics
Symbol
Parameter
RθJC
Thermal Resistance, Junction to Case, Max.
0.3
RθJA
Thermal Resistance, Junction to Ambient, Max.
40
Semiconductor Components Industries, LLC, 2017
January, 2017, Rev. 1.0
oC/W
Publication Order Number:
FCH040N65S3/D
1
FCH040N65S3 — N-Channel SuperFET® III MOSFET
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Part Number
FCH040N65S3_F155
Top Mark
FCH040N65S3
Package
TO-247 G03
Packing Method
Tube
Reel Size
N/A
Tape Width
N/A
Quantity
30 units
Electrical Characteristics TC = 25oC unless otherwise noted.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VGS = 0 V, ID = 1 mA, TJ = 25°C
650
-
-
V
VGS = 0 V, ID = 1 mA, TJ = 150°C
700
-
-
V
-
0.64
-
V/oC
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ΔBVDSS
/ ΔTJ
Breakdown Voltage Temperature
Coefficient
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Body Leakage Current
o
ID = 10 mA, Referenced to 25 C
VDS = 650 V, VGS = 0 V
-
-
1
VDS = 520 V, TC = 125oC
-
4.5
-
VGS = ±30 V, VDS = 0 V
-
-
±100
μA
nA
On Characteristics
VGS(th)
RDS(on)
Gate Threshold Voltage
VGS = VDS, ID = 6.5 mA
2.5
-
4.5
V
Static Drain to Source On Resistance
-
35.4
40
mΩ
gFS
Forward Transconductance
VGS = 10 V, ID = 32.5 A
VDS = 20 V, ID = 32.5 A
-
46
-
S
VDS = 400 V, VGS = 0 V,
f = 1 MHz
-
4740
-
pF
-
120
-
pF
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Coss(eff.)
Effective Output Capacitance
VDS = 0 V to 400 V, VGS = 0 V
-
1154
-
pF
Coss(er.)
Energy Related Output Capacitance
VDS = 0 V to 400 V, VGS = 0 V
-
171
-
pF
Qg(tot)
Total Gate Charge at 10V
136
-
nC
Gate to Source Gate Charge
VDS = 400 V, ID = 32.5 A,
VGS = 10 V
-
Qgs
-
33
-
nC
Qgd
Gate to Drain “Miller” Charge
ESR
Equivalent Series Resistance
(Note 4)
-
59
-
nC
f = 1 MHz
-
0.7
-
Ω
-
35
-
ns
VDD = 400 V, ID = 32.5 A,
VGS = 10 V, Rg = 3.3 Ω
-
51
-
ns
-
95
-
ns
-
30
-
ns
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
(Note 4)
Drain-Source Diode Characteristics
IS
Maximum Continuous Drain to Source Diode Forward Current
-
-
65
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
-
-
162.5
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 32.5 A
-
-
1.2
V
trr
Reverse Recovery Time
534
-
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 32.5 A,
dIF/dt = 100 A/μs
-
13.6
-
μC
Notes:
1. Repetitive rating: pulse-width limited by maximum junction temperature.
2. IAS = 8.1 A, RG = 25 Ω, starting TJ = 25°C.
3. ISD ≤ 32.5 A, di/dt ≤ 200 A/μs, VDD ≤ 400 V, starting TJ = 25°C.
4. Essentially independent of operating temperature typical characteristics.
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2
FCH040N65S3 — N-Channel SuperFET® III MOSFET
Package Marking and Ordering Information
Figure 1. On-Region Characteristics
200
300
VGS = 10.0V
8.0V
7.0V
6.5V
6.0V
5.5V
100
ID, Drain Current[A]
100
ID, Drain Current[A]
Figure 2. Transfer Characteristics
10
o
150 C
o
25 C
10
o
-55 C
*Notes:
1. 250μs Pulse Test
*Notes:
1. VDS = 20V
2. 250μs Pulse Test
o
2. TC = 25 C
1
0.2
1
10
VDS, Drain-Source Voltage[V]
1
20
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
9
100
IS, Reverse Drain Current [A]
RDS(ON),
Drain-Source On-Resistance [Ω]
0.04
VGS = 10V
VGS = 20V
0.03
0.02
o
150 C
10
1
o
25 C
0.1
*Notes:
1. VGS = 0V
0.01
o
*Note: TC = 25 C
0
60
120
ID, Drain Current [A]
2. 250μs Pulse Test
0.001
0.0
180
Figure 5. Capacitance Characteristics
0.5
1.0
VSD, Body Diode Forward Voltage [V]
1.5
Figure 6. Gate Charge Characteristics
5
10
VGS, Gate-Source Voltage [V]
10
Ciss
4
10
3
10
Coss
2
10
*Note:
1. VGS = 0V
2. f = 1MHz
10
Crss
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1
-1
10
8
VDS = 130V
VDS = 400V
6
4
2
*Note: ID = 32.5A
-1
10
5
6
7
8
VGS, Gate-Source Voltage[V]
1000
0.05
0.01
4
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
0.06
Capacitances [pF]
3
2
1
10
10
VDS, Drain-Source Voltage [V]
0
3
10
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3
0
50
100
Qg, Total Gate Charge [nC]
150
FCH040N65S3 — N-Channel SuperFET® III MOSFET
Typical Performance Characteristics
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
3.0
*Notes:
1. VGS = 0V
2. ID = 10mA
RDS(on), [Normalized]
Drain-Source On-Resistance
BVDSS, [Normalized]
Drain-Source Breakdown Voltage
1.2
1.1
1.0
0.9
0.8
-50
Figure 9. Maximum Safe Operating Area
1.5
1.0
*Notes:
1. VGS = 10V
2. ID = 32.5A
0.5
-50
0
50
100
150
o
TJ, Junction Temperature [ C]
Figure 10. Maximum Drain Current
vs. Case Temperature
80
10μs
100μs
10
ID, Drain Current [A]
ID, Drain Current [A]
2.0
0.0
0
50
100
150
o
TJ, Junction Temperature [ C]
200
100
2.5
1ms
DC
Operation in This Area
is Limited by R DS(on)
1
*Notes:
0.1
o
1. TC = 25 C
60
40
20
o
0.01
2. TJ = 150 C
3. Single Pulse
1
10
100
VDS, Drain-Source Voltage [V]
0
25
1000
Figure 11. Eoss vs. Drain to Source Voltage
30
25
EOSS [μJ]
20
15
10
5
0
0
130
260
390
520
VDS, Drain to Source Voltage [V]
650
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4
50
75
100
125
o
TC, Case Temperature [ C]
150
FCH040N65S3 — N-Channel SuperFET® III MOSFET
Typical Performance Characteristics (Continued)
Figure 12. Transient Thermal Response Curve
o
ZθJC(t), Thermal Response [ C/W]
1
0.5
0.1
0.2
PDM
0.1
t1
0.05
0.01
0.02
0.01
o
1. ZθJC(t) = 0.3 C/W Max.
2. Duty Factor, D= t1/t2
3. TJM - TC = PDM * ZθJC(t)
Single pulse
0.001
-5
10
t2
*Notes:
-4
10
-3
-2
10
10
t1, Rectangular Pulse Duration [sec]
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5
-1
10
0
10
FCH040N65S3 — N-Channel SuperFET® III MOSFET
Typical Performance Characteristics (Continued)
FCH040N65S3 — N-Channel SuperFET® III MOSFET
IG = const.
Figure 13. Gate Charge Test Circuit & Waveform
VDS
RG
V
10V
GS
RL
VDS
90%
VDD
VGS
VGS
DUT
10%
td(on)
tr
t on
td(off)
tf
t off
Figure 14. Resistive Switching Test Circuit & Waveforms
VGS
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
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6
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
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7
FCH040N65S3 — N-Channel SuperFET® III MOSFET
DUT
4.82
E
4.58
15.87
E
15.37
A
B
12.81 E
4.13
3.53
6.85
6.61
3.65
E
3.51
0.254 M
5.58
E
5.34
5.20
4.96
1.35
0.51
13.08 MIN
20.82
E
20.32
1
3
3
1.87
1.53(2X)
3.93
E
3.69
1.60
20.25
E
19.75
2.77
2.43
0.71
0.51
5.56
2.66
2.29
11.12
1.35
1.17
0.254 M
B A M
NOTES: UNLESS OTHERWISE SPECIFIED.
A. PACKAGE REFERENCE: JEDEC TO-247,
ISSUE E, VARIATION AB, DATED JUNE, 2004.
B. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD
FLASH, AND TIE BAR EXTRUSIONS.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
D. DRAWING CONFORMS TO ASME Y14.5 - 1994
E DOES NOT COMPLY JEDEC STANDARD VALUE
F. DRAWING FILENAME: MKT-TO247G03_REV02
1
B A M
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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