ACTIVE-SEMI ACT88320QI101-T Advanced pmu with inrush control and bypass switch Datasheet

ACT88320QI-T
Rev 2.0, 20-Dec-2017
Advanced PMU with Inrush Control and Bypass Switch
BENEFITS and FEATURES
GENERAL DESCRIPTION

Wide input voltage range
o Vin = 2.7V to 5.5V
o Blocking up to 20V

Complete integrated power solution
o One 4A DC/DC Step-Down with Bypass
Mode
o Two 2.5A DC/DC Step-Down Regulators
o Two 200mA LDOs
o High Power Load Switch Gate Driver with
Slew Rate Control

Space Savings
o Fully integrated
o High Fsw = 2.25MHz or 1.125MHz
o Integrated sequencing
The ACT88320 PMIC is an integrated ActivePMU power
management unit. It is highly flexible and can be
reconfigured via I2C for multiple applications without the
need for PCB changes. The low external component
count and high configurability significantly speeds time
to market. Examples of configurable options include
output voltage, startup time, slew rate, system level
sequencing, switching frequency, sleep modes,
operating modes etc. The core of the device includes 3
DC/DC step down converters using integrated power
FETs, and 2 low-dropout regulators (LDOs). Each
regulator can be configured for a wide range of output
voltages through the I2C interface.

ACT88320 is programmed at the factory with a default
configuration. The default settings can be optimized for
a specific design through the I2C interface. Contact the
factory for specific default configurations.
Easy system level design
o Configurable sequencing
o Seamless sequencing with external supplies
o Programmable Reset and Power Good
GPIO’s

Buck 1 Bypass Mode for 3.3V system level
compliance

Highly configurable
o uP interface for status reporting and controllability
o Flexible Sequencing Options
o I2C Interface – 1MHz
o Multiple Sleep Modes
o See ACT88321 for Pushbutton Startup
The ACT88320 includes features that allow flexibility for
all system level configurations. The buck converter can
be reconfigured as a bypass switch. It also contains a
high power load switch controller. It’s external power
supply enable and power good interface allows
seamless sequencing with external power supplies.
The ACT88320 PMIC is available in a 4 x 4 mm 32 pin
QFN package.
APPLICATIONS
•
Solid-State Drives
•
Microcontroller Applications
•
FPGA
•
Personal Navigation Devices
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
1
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Typical Application Diagram
Input Supply 2.7-5.5V
Blocking up to 20V
Over Voltage
Over Current
Protection
Inrush Current
Control
BUCK1 4.0A
BUCK2 2.5A
BUCK3 2.5A
PG
DC/DC
ACT88320
LDO1 200mA
SOC
LDO2 200mA
ENABLE
PWREN
SCL
SDA
nRESET
IRQ
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
2
ACT88320QI-T
Rev 2.0, 20-Dec-2017
FUNCTIONAL BLOCK DIAGRAM
10mΩ
1uF
Input Rail
OVSNS
IO Supply
Supply
OVSNS_M
OVGATE
VIN
VIO
1µF
10µF
FB_B1
PWREN
Vref
Buck1
Controller
SCL
Digital
Controller
SW_B1
1µH
2x22µF
FB_B1
SDA
Digital
Core
nRESET
PGND
VIN
nIRQ
10µF
FB_B2
EN
External
SMPS PG
EXT_EN
Buck2
Controller
EXT_PG
SW_B2
1µH
22µF
FB_B2
PGND
FB_Bx
LSG1
Load_SW1
AGND
Supply
1µF
Vref
Load Switch Gate
Driver
VIN
10µF
AVIN
FB_B3
Vref
Vref
OUT_LDO1
Buck3
Controller
SW_B3
1µH
22µF
FB_B3
1µF
FB
PGND
Vref
ACT88320
OUT_LDO2
1µF
AGND
FB
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
3
ACT88320QI-T
Rev 2.0, 20-Dec-2017
ORDERING INFORMATION
PART NUMBER
VBUCK1
VBUCK2
VBUCK3
VLDO1
VLDO2
VLSWG1
PACKAGE
ACT88320QI101-T
3.3V
1.8V
1.15/0.9V
3.3V
1.8V
OFF
TQFN
4mmx4mm
ACT88320QI103-T
1.2V
1.8V
3.3V
2.5V
3.3V
OFF
TQFN
4mmx4mm
ACT88320QI104-T
0.9V/0.75V
1.2V/1.8V
1.5V/1.35V
OFF
1.8V
ON
TQFN
4mmx4mm
ACT88320QI105-T
1.05V
1.8V
1.5V/1.35V
OFF
1.8V
OFF
TQFN
4mmx4mm
ACT88320QI108-T
3.3V
1.8V
1.15V
3.3V
1.8V
OFF
TQFN
4mmx4mm
A CT883 20QIxx x-T
Product Number
Package Code
Pin Count
Option Code
Tape and Reel
Note 1: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity required.
Note 2: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor
products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
Note 3: Package Code designator “Q” represents QFN
Note 4: Pin Count designator “I” represents 32 pins
Note 5: “xxx” represents the CMI (Code Matrix Index) option. The CMI identifies the IC’s default register settings
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
4
ACT88320QI-T
Rev 2.0, 20-Dec-2017
FB_B3
AGND
LSG1
OUT_LDO1
OUT_LDO2
AVIN
PWREN
FB_B2
PIN CONFIGURATION
32
31
30
29
28
27
26
25
VIN
1
24
VIN
VIN
2
23
VIN
SW_B3
3
22
SW_B2
OVSNS
4
21
PGND
OVSNS_M
5
20
SW_B1
OVGATE
6
19
SW_B1
PGND
7
18
VIN
PGND
8
17
VIN
ACT88320
9
10
11
12
13
14
15
16
SDA
SCL
GPIO4 / DVS
GPIO3 / nIRQ
GPIO1 / nRESET
GPIO2 / EXT_EN
VIO
FB_B1
PGND
Figure 1: Pin Configuration – Top View – QFN44-32
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
5
ACT88320QI-T
Rev 2.0, 20-Dec-2017
PIN DESCRIPTIONS
PIN
NAME
1,2
VIN
DESCRIPTION
Dedicated VIN power input for BUCK3. Connect the BUCK3 input caps directly to these pins
3
SW_B3
Switch Pin for BUCK3 Regulator
4
OVSNS
Analog VIN+ Input. Used to monitor and start inrush control FET
5
OVSNS_M
Analog VIN- Input. Used to monitor current in external resistor (RSNS)
6
OVGATE
7,8
PGND
Gate drive for the inrush control FET. Voltage is typically 8V above VIN which requires a 12V n-ch FET.
9
SDA
I2C Data Input and Output
10
SCL
I2C Clock Input
Power Ground for Buck3. Connect the BUCK3 input caps directly to these pins.
11
GPIO4 / DVS
GPIO. Configured as a dynamic voltage scaling input.
12
GPIO3 / nIRQ
GPIO. Configured as an interrupt (IRQ) open drain output.
13
GPIO1 / nRESET
GPIO. Configured as an nRESET open drain output
14
GPIO2 / EXT_EN
GPIO. Configured as an open drain output to enable an external power supply
15
VIO
16
FB_B1
17, 18
VIN
19, 20
SW_B1
Switch pin for BUCK1 Regulator
21
PGND
Power Ground for BUCK1 and BUCK2. Connect BUCK1 and BUCK2 input caps directly to this pin.
22
SW_B2
23, 24
VIN
25
FB_B2
26
PWREN
Digital input reference voltage. Connect a 1uF capacitor between VIO and AGND
Feedback for BUCK1 regulator. Connect directly to the Buck1 output capacitor.
Dedicated VIN power input for BUCK1. Connect the Buck1 input caps directly to these pins.
Switch Pin for BUCK2 Regulator
Dedicated VIN power input for BUCK2. Connect the BUCK2 input caps directly to these pins.
Feedback for BUCK2 Regulator
Power Enable Digital Input
27
AVIN
28
OUT_LDO2
Dedicated VIN power input for LDO1 & 2 Regulators and Analog VIN Input
Output for LDO2 Regulator
29
OUT_LDO1
Output for LDO1 Regulator
30
LSG1
Output1 Load Switch Gate driver
31
AGND
Analog Ground
32
FB_B3
33
Exposed Pad
Feedback for BUCK3 Regulator
Must be soldered to the top layer ground plane.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
6
ACT88320QI-T
Rev 2.0, 20-Dec-2017
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
UNIT
All Pins to AGND and PGND unless stated otherwise below
-0.3 to 6
V
OVSNS, OVSNS_M to PGND
-0.3 to 22
V
OVGATE to VIN
-0.3 to 13.2
V
VIN to PGND
-0.3 to 6
V
SW_Bx to PGND
-0.3 to VIN + 1
V
PWREN to AGND
-0.3 to AVIN + 0.3
V
GPIOx to AGND
-0.3V to VIO + 0.3
V
FB_Bx to PGND
-0.3 to VIN + 0.3
V
OUTx to PGND
-0.3 to VIN + 0.3
V
AGND to PGND
-0.3 to + 0.3
V
Junction to Ambient Thermal Resistance (Note 2)
26.5
°C/W
Junction to Case Thermal Resistance (Note 2)
13.1
°C/W
Operating Junction Temperature
-40 to 150
°C
Storage Temperature
-55 to 150
°C
Note1: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect
device reliability.
Note2: Measured on Active-Semi Evaluation Kit
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
7
ACT88320QI-T
Rev 2.0, 20-Dec-2017
DIGITAL I/O ELECTRICAL CHARACTERISTICS
(VIO = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
PWREN Input Low
TEST CONDITIONS
MIN
TYP
AVIN = 3.3V
PWREN Input High
AVIN = 3.3V
PWREN Input Low
AVIN = 5V
PWREN Input High
AVIN = 5V
nIRQ, EXT_PG Input Low
VIO = 1.8V
MAX
UNIT
1.6
V
2.1
V
2.2
2.7
V
V
0.4
V
1.0
V
nIRQ, EXT_PG Input High
VIO = 1.8V
nIRQ, EXT_PG Input Low
VIO = 3.3V
1.25
V
nIRQ, EXT_PG Input High
VIO = 3.3V
nIRQ, nRESET, EXT_PG, EXT_EN Leakage Current
Output = 5V
1
µA
nIRQ, EXT_PG Output Low
IOL = 5mA
0.35
V
EXT_EN, nRESET Output Low
IOL = 1mA
0.35
V
nRESET Output High
IOH = 1mA
VIO0.35
V
EXT_EN Output High
IOH = 1mA
VIO0.35
V
2.3
V
PWREN, EXT_PG Deglitch Time (falling)
15
µs
PWREN, EXT_PG Deglitch Time (rising)
10
µs
VIO Operating Range
1.5
Innovative PowerTM
VIN
V
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
8
ACT88320QI-T
Rev 2.0, 20-Dec-2017
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VIO = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Input Supply Voltage Range: AVIN referenced to
AGND
MIN
TYP
2.7
UVLO Threshold Falling
2.5
UVLO Hysteresis
100
System Monitor (SYSMON) Programmable Range
2.7V
OV Threshold Rising
OV Hysteresis
2.6
MAX
UNIT
5.5
V
2.7
V
mV
4.2V
5.5
5.75
6.0
V
100
200
300
mV
Operating Supply Current
All Regulators Disabled
10
µA
Operating Supply Current
All Regulators Enabled but no load
250
µA
Thermal Shutdown
Temperature rising
140
Thermal Shutdown Hysteresis
160
180
30
°C
°C
Power Up Delay after initial VIN
Time from VIN > UVLO threshold to Internal
Power-On Clear (POR)
120
200
µs
Startup Delay after initial VIN
Time from VIN > UVLO threshold to start of
first regulator turning On. (zero delay)
1500
2000
µs
2.25
2.37
MHz
Oscillator Frequency
2.13
VIN UV Interrupt Threshold Falling
Referenced to rising threshold
VIN UV Threshold Rising Programming Range
Rising edge threshold can power up device.
Configurable in 100mV steps.
200
2.7
3
mV
4.2
V
VIN UV Shutdown Threshold Falling
2.6
V
VIN OV Shutdown Threshold Rising
5.75
V
VIN OV Shutdown Threshold Falling
5.5
V
VIN Deglitch Time UV
80
100
120
µs
VIN Deglitch Time OV
160
200
240
µs
1
ms
Transition time from Deep Sleep (DPSLP) State to
Active State
Time from PWREN pin low to high transition to
time when the first regulator turns ON with
minimum turn on delay configuration.
Transition time from Sleep State (SLEEP) to Active
State
Time from I2C command to clear sleep mode
to time when the first regulator turns ON with
minimum turn on delay configuration.
100
Time to first power rail turn off
Time from turn Off event to when the first
power rail turns off with minimum turn off delay
configuration
120
ONDLY=00
ONDLY=01
ONDLY=10
ONDLY=11
0
0.25
0.5
1.0
Startup Delay Programmable Range
µs
200
µs
ms
Turn Off Delay Programmable Range
Configurable in 0.25ms steps
0
7.75
ms
nRESET Programmable Range
Configurable to 20, 40, 60 or 100ms.
20
100
ms
Note 1: All Under-voltage Lockout, Overvoltage measurements are referenced to the AVIN Input and AGND Pins.
Note 2: All POK Under-voltage and Overvoltage measurements are referenced to the VIN Input and GND Pins.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
9
ACT88320QI-T
Rev 2.0, 20-Dec-2017
OVP, INRUSH NMOS SWITCH, ELECTRICAL CHARACTERISITICS
(VIN = 3.3V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Operating Input Voltage Range (VIN)
MIN
TYP
2.7
VIN Input Current
IC Disabled
OVGATE Pull-up Current
OVGATE = 0V
OVGATE Discharge Resistance
Overcurrent Shutdown Threshold
Voltage across current sense resistor
Overcurrent Warning Threshold
Percent of shutdown voltage
Soft-Start Slew Rate
Start up from 0V to 5.0V on OVGATE.
CGate = 1nF
MAX
UNIT
5.5
V
1
µA
10
µA
10
Ω
70
85
100
mV
72.5
80
87.5
%
500
µs
Over Current Deglitch Time
Steady state operation
40
µs
Over Current Blanking Time
Blanking time during power up
85
µs
Retry time after Over Current
42
ms
OVSNS POK Threshold (falling)
2.5
V
OVSNS POK Threshold (rising)
2.7
V
200
mV
OVSNS POK Threshold Hysteresis
100
OVSNS OV Threshold (rising)
6
OVSNS OV Threshold hysteresis
200
Startup Delay
After OVSNS POK to OVGATE rising,
CGate = 1nF
40
Standby Current into OVSNS and OVSNS_M
After OVSNS POK, steady state mode
40
OVSNS = 3.3V
5.4
VOVGATE Voltage (VOVGATE – VIN)
OVSNS = 5V
8
Innovative PowerTM
V
400
mV
µs
50
µA
V
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
10
ACT88320QI-T
Rev 2.0, 20-Dec-2017
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1)
(VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Input Operating Voltage Range
MIN
TYP
MAX
UNIT
2.7
5.5
V
0.6
4.0
V
55
µA
1
µA
Output Voltage Programming Range
See CMI section for programming details
Standby Supply Current, Low Power Mode
Enabled
VOUT_B1 = 103% setpoint, Enabled, VOUT_B1
setpoint = 1.0V, No Load
Shutdown Current
Regulator Disabled
Output Voltage Accuracy
VOUT_B1 = default CMI voltage, continuous
PWM mode
-1
VNOM
1
%
Output Voltage Accuracy
VOUT_B1 = default CMI voltage, PFM mode
-2
VNOM
2
%
Line Regulation
VOUT_B1 = default CMI voltage, PWM Regulation
Load Regulation
VOUT_B1 = at default CM, PWM Regulation
Power Good Threshold
VOUT_B1 Rising
Power Good Hysteresis
VOUT_B1 Falling
Overvoltage Fault Threshold
VOUT_B1 Rising
Overvoltage Fault Hysteresis
VOUT_B1 Falling
Switching Frequency
VOUT_B1 ≥ 20% of VNOM, Configurable
Soft-Start Period Tset
10% to 90% VNOM
40
0.1
%/V
0.1
90
92.5
%/A
95
3
107.5
110
%VNOM
112.5
3
Current Limit, Cycle-by-Cycle
-5%
1.125 /
2.25
%VNOM
%VNOM
%VNOM
+5%
MHz
480
600
µs
4.14
4.6
5.06
A
Current Limit, Shutdown
% compared to Current Limit, cycle-bycycle
112.5
122.5
132.5
%
Current Limit, Warning
% compared to Current Limit, cycle-bycycle
67.5
75
82.5
%
PMOS On-Resistance
ISW = -1A, VIN = 5.0V
40
50
mΩ
NMOS On-Resistance
ISW = 1A, VIN = 5.0V
16
25
mΩ
1
µA
SW Leakage Current
VIN = 5.5V, VSW = 0V
VIN = 5.5V, VSW = 5.5V
Dynamic Voltage Scaling Rate
Output Pull Down Resistance
1
3.50
Enabled when regulator disabled
Innovative PowerTM
4.4
µA
mV/µs
8.75
Ohms
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
11
ACT88320QI-T
Rev 2.0, 20-Dec-2017
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1) –
BYPASS MODE
(VIN = 3.3V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Input Voltage for By-Pass Mode
PMOS On-Resistance
ISW = -1A, VIN = 3.3V, Max=125°C at TJunction
Internal PMOS Current Detection
Triggers Interrupt on IRQ Pin
MIN
TYP
MAX
UNIT
2.7
3.3
3.7
V
0.04
0.06
Ω
3.5
4.0
A
3.0
Internal PMOS Current Detection
Deglitch Time
Internal PMOS Current Shutdown
10
Shuts down after deglitch time and stays off for Off-Time
5.0
5.6
µs
6.2
A
Internal PMOS Current Shutdown
Deglitch Time
5
µs
Internal PMOS Current Shutdown OffTime (Retry time)
14
ms
500
µs
Internal PMOS Soft start
VIN = 3.3V Input, Cout = 47uF, Default setting ISS[1:0]=00
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
12
ACT88320QI-T
Rev 2.0, 20-Dec-2017
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK2-3)
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Input Operating Voltage Range
MIN
TYP
MAX
UNIT
2.7
5.5
V
0.8
3.9875
V
Output Voltage Programming Range
Configurable in 12.5mV steps.
Standby Supply Current, Low Power
Mode Enabled
VOUTx = 103%, Regulator Enabled, No load, VOUTx =
default CMI voltage
35
Shutdown Current
VIN = 5.0V, Regulator Disabled
0.1
1
µA
Output Voltage Accuracy
VOUTx = default CMI voltage, IOUTx = 1A (continuous
PWM mode)
VNOM
1%
V
Line Regulation
VOUTx = default CMI voltage, PWM Regulation
Load Regulation
VOUTx = default CMI voltage, PWM Regulation
Power Good Threshold
VOUTx Rising
Power Good Hysteresis
VOUTx Falling
Overvoltage Fault Threshold
VOUTx Rising
Overvoltage Fault Hysteresis
VOUTx Falling
-1%
µA
0.1
%
0.1
90
92.5
%
95
3
107.5
110
%VNOM
112.5
3
-5%
%VNOM
%VNOM
1.125 /
2.25
+5%
MHz
600
µs
Switching Frequency
VOUTx ≥ 20% of VNOM
Soft-Start Period Tset
10% to 90% VNOM
480
Startup Time
Time from Enable to PG
700
Current Limit, Cycle-by-Cycle
%VNOM
µs
2.7
3.0
3.3
A
Current Limit, Shutdown
% compared to Current Limit, cycle-by-cycle
112.5
122.5
132.5
%
Current Limit, Warning
% compared to Current Limit, cycle-by-cycle
67.5
75
82.5
%
PMOS On-Resistance
ISW_Bx = -500mA, VIN = 5V
80
mΩ
NMOS On-Resistance
ISW_Bx = 500mA, VIN = 5V
50
mΩ
SW Leakage Current
VIN = 5.5V, VSW_Bx = 0 or 0V
1
VIN = 5.5V, VSW_Bx = 0 or 5.5V
1
Dynamic Voltage Scaling Rate
Output Pull Down Resistance
3.50
Enabled when regulator disabled
Innovative PowerTM
9.4
µA
µA
mV/us
20
Ω
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
13
ACT88320QI-T
Rev 2.0, 20-Dec-2017
LDO1-2 ELECTRICAL CHARACTERISTICS
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
Operating Voltage Range LDO1
Output Voltage Range
TEST CONDITIONS
TYP
MAX
UNIT
AVIN (Input Voltage) to the LDO1
2.7
5.5
V
Option 1 Configurable in 9.375mV steps
0.6
2.991
V
Option 2 Configurable in 12.5mV steps
Output Current
Output Voltage Accuracy
AVIN - VLDOx_OUT > 0.4V
Line Regulation
AVIN - VLDOx_OUT > 0.4V
ILDOx_OUT = 1mA
Load Regulation
ILDOx_OUT = 1mA to 100mA,
VLDOx_OUT = default CMI
Power Supply Rejection Ratio
MIN
0.8
3.9875
V
180
200
mA
-1
VNOM
1
%
0.03
0.2
%
0.5
%
f = 1kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1
40.8
dB
f = 10kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1
31.2
dB
f = 2.25MHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1
53.6
dB
Supply Current per Output
Regulator Disabled
Supply Current
Regulator Enabled, No load
1
µA
15
20
µA
µs
Time from soft start “ON” to PGOOD. VLDOx = 1.8V
150
215
300
Time from soft start “ON” to PGOOD. VLDOx = 3.3V
200
275
350
µs
Power Good Threshold
VLDOx_OUT Rising
90
92.5
95
% VNOM
Power Good Hysteresis
VLDOx_OUT Falling
Overvoltage Fault Threshold
VLDOx_OUT Rising
106
110
114
% VNOM
Overvoltage Fault Hysteresis
VLDOx_OUT Falling
Soft-Start Period
3
3
Discharge Resistance
50
Dropout Voltage
ILDOx_OUT = 220mA, VLDOx_OUT = 2.7V
Output Current Limit
ILIM [1:0] = 00
ILIM [1:0] = 01
ILIM [1:0] = 10
ILIM [1:0] = 11
Startup Time
Note 1: AVIN - VLDOx_OUT > 0.4V
% VNOM
-35%
Time from Enable to PG
Innovative PowerTM
% VNOM
125
Ω
150
mV
110
150
210
315
+35%
mA
300
400
µs
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
14
ACT88320QI-T
Rev 2.0, 20-Dec-2017
LOAD SWITCH GATE DRIVER ELECTRICAL CHARACTERISTICS
(VIN = 3.3V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
MIN
TYP
2.7
Maximum Output - Gate Voltage
Gate fully on
Soft-Start Slew Rate
Gate Node rising from 0 to 2V with 1nF output capacitor. (configurable via OVGATE current)
800
400
260
200
OVGATE Pin Pull-up Current
(VOVGATE=0V)
GATE1 SLEW
GATE1 SLEW
GATE1 SLEW
GATE1 SLEW
2.5
5
7.5
10
= 00
= 01
= 10
= 11
Fault Deglitch Time
MAX
UNIT
5.5
V
2*VIN
V
us
µA
µA
µA
µA
10
µs
Gate Discharge Resistance
75
Ω
Startup Delay
75
µs
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
15
ACT88320QI-T
Rev 2.0, 20-Dec-2017
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VIO = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
SCL, SDA Input Low
VIO = 1.8V
SCL, SDA Input High
VIO = 1.8V
SCL, SDA Input Low
VIO = 3.3V
SCL, SDA Input High
VIO = 3.3V
SDA Leakage Current
SDA=5V
SDA Output Low
IOL = 5mA
MIN
TYP
MAX
UNIT
0.4
V
1.25
V
1.0
2.3
V
1
SCL Clock Frequency, fSCL
V
0
µA
0.35
V
1000
kHz
SCL Low Period, tLOW
0.5
µs
SCL High Period, tHIGH
0.26
µs
50
ns
0
ns
ns
SDA Data Setup Time, tSU
SDA Data Hold Time, tHD
(Note1)
Start Setup Time, tST
For Start Condition
260
Stop Setup Time, tSP
For Stop Condition
260
ns
Capacitance on SCL or SDA Pin
SDA Fall Time SDA, Tof
Device requirement
Pulse Width of spikes must be suppressed
on SCL and SDA
0
10
pF
120
ns
50
ns
Note1: Comply with I2C timings for 1MHz operation - “Fast Mode Plus”.
Note2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering Deep Sleep, Sleep,
OVUVFLT, and THERMAL states to clear any transactions that may have been occurring when entering the above states.
Note3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device.
Note4: Device Address is factory configurable to 7’h25, 7’h27, 7’h67, 7’h6B.
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
Stop
condition
Figure 2: I2C Data Transfer
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
16
ACT88320QI-T
Rev 2.0, 20-Dec-2017
SYSTEM CONTROL INFORMATION
There is no timeout function in the I2C packet processing state machine, however, any time the I2C state
machine receives a start bit command, it immediately
resets the packet processing, even if it is in the middle
of a valid packet. The I2C functionality is operational in
all states except RESET.
General
The ACT88320 is a single-chip integrated power management solution designed to power many processors
such as the Silicon Motion SM2258 and SM2259 solid
state drive controllers and the Atmel SAMA5D processors. It integrates three highly efficient buck regulators,
two LDOs, an integrated load bypass switch, and a built
in inrush and overvoltage controller. Its high integration
and high switching frequency result in an extremely
small footprint and lost power solution. It contains a
master controller that manages startup sequencing, timing, voltages, slew rates, sleep states, and fault conditions. I2C configurability allows system level changes
without the need for costly PCB changes. The built-in
load bypass switch enables full sequencing configurability in 3.3V systems.
I2C commands are communicated using the SCL and
SDA pins. SCL is the I2C serial clock input. SDA is the
data input and output. SDA is open drain and must have
a pull-up resistor. Signals on these pins must meet
timing requirements in the Electrical Characteristics
Table.
I2C Registers
The ACT88320 contains an array of internal registers
that contain the IC’s basic instructions for setting up the
IC configuration, output voltages, sequencing, fault
thresholds, fault masks, etc. These registers are what
give the IC its operating flexibility. The two types of
registers are described below.
The ACT88320 master controller monitors all outputs
and reports faults via I2C and hardwired status signals.
Faults can be masked and fault levels and responses
are configurable via I2C.
Many of the ACT88320 pins and functions are configurable. The IC’s default functionality is defined by the default CMI (Code Matrix Index), but much of this functionality can be changed via I2C. Several GPIOs can be
configured as enable inputs, reset outputs, dynamic
voltage (DVS) inputs, LED drivers, etc. The GPIO configuration is specifically defined for each ACT88320 orderable part number. The first part of the datasheet describes basic IC functionality and default pin functions.
The end of the datasheet provides the configuration and
functionality specific to each CMI version. Contact
[email protected] for additional information about
other configurations.
Basic Volatile – These are R/W (Read and Write) and
RO (Read only). After the IC is powered, the user can
modify the R/W register values to change IC
functionality. Changes in functionality include things like
masking certain faults. The RO registers communicate
IC status such as fault conditions. Any changes to these
registers are lost when power is recycled. The default
values are fixed and cannot be changed by the factory
or the end user.
Basic Non-Volatile – These are R/W and RO. After the
IC is powered, the user can modify the R/W register
values to change IC functionality. Changes in
functionality include things like output voltage settings,
startup delay time, and current limit thresholds. Any
changes to these registers are lost when power is
recycled. The default values can be modified at the
factory to optimize IC functionality for specific
applications. Please consult [email protected] for
custom options and minimum order quantities.
I2C Serial Interface
To ensure compatibility with a wide range of systems,
the ACT88320 uses standard I2C commands. The
ACT88320 operates as a slave device, and can be factory configured to one of four 7-bit slave addresses. The
7-bit slave address is followed by an eighth bit, which
indicates whether the transaction is a read-operation or
a write-operation. Refer to each specific CMI for the IC’s
slave address
7-Bit Slave Address
0x25h
0x27h
0x67h
0x6Bh
010 0101b
010 0111b
110 0111b
110 1011b
8-Bit Write
Address
0x4Ah
0x4Eh
0xCEh
0xD6h
When modifying only certain bits within a register, take
care to not inadvertently change other bits.
Inadvertently changing register contents can lead to
unexpected device behavior.
8-Bit Read
Address
0x4Bh
0x4Fh
0xCFh
0xD7h
State Machine
Figure 1 shows the ACT88320 internal state machine.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
17
ACT88320QI-T
Rev 2.0, 20-Dec-2017
RESET State
In the RESET, or “cold” state, the ACT88320 is waiting
for the input voltage on VIN to be within a valid range
defined by the VIN_UV and VIN_OV thresholds. All regulators are off in RESET. All reset outputs are asserted
low. All volatile registers are reset to defaults and NonVolatile registers are reset to programmed defaults. The
IC transitions from RESET to POWER SEQUENCE
START when the input voltage enters the valid range.
The IC transitions from any other state to RESET if the
input voltage drops below the VIN_UV threshold voltage.
It is important to note any transition to RESET returns
all volatile and non-volatile registers to their default
states.
Table 1. SLEEP Mode Truth Table
DPSLP State
The DPSLP state is another low power operating mode
for the operating system. It is intended to be used in a
lower power configuration than the SLEEP mode. It is
similar to the SLEEP state, but DPSLP uses slightly different configurations to enter and exit this mode. Each
output can be programmed to be on or off in the DPSLP
state. This programming can different from the SLEEP
state. The outputs follow their programmed sequencing
delay times when turning on or off as they enter or exit
the DPSLP state. Buck1/2/3 can be programmed to regulate to their VSET0 voltage, VSET1 voltage, or be
turned off in the DPSLP state. Note that same voltage
registers are used for both the SLEEP state and DPSLP
state, so the user must change them before entering
SLEEP or DPSLP if different voltages are required.
LDO1/2 can be programmed to regulate to their VSET0
voltage or can be programmed to be turned off. Note
that LDO1/2 do not have a VSET1 voltage.
POWER SEQUENCE START State
The POWER SEQUENCE START state is a transitional
state while the regulators are starting. The IC does not
operate in this state.
ACTIVE State
The ACTIVE state is the normal operating state when
the input voltage is within the allowable range, all outputs are turned on, and no faults are present.
SLEEP State
The SLEEP state is a low power mode for the operating
system. Each output can be programmed to be on or off
in the SLEEP state. The outputs follow their programmed sequencing delay times when turning on or
off as they enter or exit the SLEEP state. Buck1/2/3 can
be programmed to regulate to their VSET0 voltage,
VSET1 voltage, or be turned off in the SLEEP state.
LDO1/2 can be programmed to regulate to their VSET0
voltage or can be programmed to be turned off. Note
that LDO1/2 do not have a VSET1 voltage.
The IC can enter DPSLP state via I2C registers DPSLP
and DPSLP EN and/or a GPIO input pin. Table 2 shows
the conditions to enter DPSLP state. ACT88320 I2C
stays enabled in DPSLP state. The IC exits the DPSLP
state when the conditions to enter DPSLP state are no
longer present.
If OV, UV, or THERMAL faults occur when in DPSLP
state, the IC resets to the POWER ON/Active state.
The IC can enter SLEEP state via I2C registers SLEEP
and SLEEP EN. Table 1 shows the conditions to enter
SLEEP state. ACT88320 I2C stays enabled in SLEEP
state. The IC exits the SLEEP state when the conditions
to enter SLEEP state are no longer present.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
18
ACT88320QI-T
Rev 2.0, 20-Dec-2017
VIN_OV or VIN_UV in
any state puts the IC in
RESET state
Example for a typical configuration.
Other transitions are possible with factory
programmed configurations.
RESET
Clears all registers and
defaults to original NVM
settings in RESET state
VIN_NOT_OK
UV> VIN > OV
DPSLP
(Deep Sleep)
VIN_OK
UV < VIN < OV
(DPSLP_EN = 1 & PWREN = 0 & DPSLP MODE = 1)
OR
(DPSLP_EN = 1 & PWREN = 0 & DPSLP MODE = 0
& DPSLP Bit = 1)
Clear DPSLP_EN &
SLEEP_EN if set to 1
upon entering OVUV
Fault State
DIS OVUV = 0 &
Mask = 0
Power
Sequence
Start
PWREN = 1
SLEEP Bit = 1 &
SLEEP_EN = 1
SLEEP
OVUV Fault
SLEEP Bit = 0 OR
SLEEP_EN = 0
SLEEP Bit = 1 &
SLEEP_EN = 1
OVUV Fault
Retry Timer
(100ms)
Clear DPSLP_EN &
SLEEP_EN if set to 1
upon entering Thermal
Fault State
Thermal Fault
Cleared
POWER ON
(Active)
Thermal Fault
Thermal Shutdown
Fault & DIS_OTS = 0
Figure 1 PWREN State Machine
the IC into the DPSLP state. While in DPSLP mode, if
there is a fault condition such as system UV or OV or a
thermal fault, the IC resets the DPSLP_EN bit back to 0
when it exits DPSLP mode. This requires PWREN to be
toggled high to set the DPSLP_EN to 1 again and then
toggled back low to enter DPSLP state again. The IC
does not automatically go back into DPSLP state after
exiting the DPSLP state due to fault conditions.
Special consideration is needed for DPSLP state in with
a non-I2C system. When PWREN is first toggled high
after power up, the ACT88320 detects the first rising
transition of PWREN from 0 to 1 and sets the
DPSLP_EN register bit to 1. On the falling transition of
PWREN from 1 to 0, DPSLP state is entered. In a condition when the system is powered up when PWREN =
1, PWREN must be toggled to 0 and back to 1 to set the
DPSLP_EN bit. The next falling PWREN transition puts
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
19
ACT88320QI-T
Rev 2.0, 20-Dec-2017
status of the inputs in Tables 1 and 2. A typical startup
profile is for the system to automatically transition from
RESET to POWER ON when input power is applied.
The typical shutdown sequence is for the system to pull
PWREN low to enter DPSLP.
Sequencing
The ACT88320 provides the end user with extremely
versatile sequencing capability that can be optimized for
many different applications. Each of the five outputs has
four basic sequencing parameters: input trigger, turn-on
delay, turn-off delay, and output voltage. The buck
converters also have softstart time control. Each of
these parameters is controlled via the ICs internal
registers. As an example, the ACT88320QI101-T
sequencing and output voltages are optimized for the
Silicon Motion SM2258 and SM2259 processors. The
specifics for this IC as well as others are detailed at the
end of the datasheet. Contact [email protected]
for custom sequencing configurations. Refer to the
Active-Semi Application Note AN-109, ACT88320Q101
Register Definitions, for full details on the I2C register
map functionality and programming ranges.
Table 2. DPSLP Mode with Truth Table
THERMAL State
In the THERMAL state the chip has exceeded the thermal shutdown temperature. To protect the device, all
the regulators are shut down and the reset pins are asserted low. This state can be disabled by setting register
0x01h bit5 (TMSK) = 1. TMSK prevents the interrupt
from going active, but does not prevent the IC from entering the THERMAL State.
Input trigger. The input trigger for a regulator is the
event that turns that regulator on. Each output can have
a separate input trigger. The input trigger can be the
internal power ok (POK) signal from one of the other
regulators, the internal VIN POK signal, or an external
signal applied to an input pin such as EXT_PG or GPIO.
This flexibility allows a wide range of sequencing
possibilities, including having some of the outputs be
sequenced with external power supply or a control
signal from the host. As an example, if the LDO1 input
trigger is Buck1, LDO1 will not turn on until Buck1 is in
regulation. Input triggers are defined at the factory and
can only be changed with a custom CMI configuration.
The GPIOx outputs can be connected to an internal
power supply’s POK signal and used to trigger external
supplies in the overall sequencing scheme. The GPIOx
inputs can also be connected to an external power
supply’s power good output and used as an input trigger
for an ACT88320 supply.
OVUV FAULT State
In the OVUV FAULT state one of the regulators has exceed an OV level at any time or UV level after the soft
start ramp has completed. All regulators shutdown and
all three reset outputs are asserted low when the IC enters OVUVFLT state. The OVUVFLT state is timed to
retry after 100ms and enter the ACTIVE state. If the OV
or UV condition still exists in the ACTIVE state the IC
returns back to the OVUVFLT state. The cycle continues until the OV or UV fault is removed or the input
power is removed. This state can be disabled by setting
the DIS_OVUV_SHUTDOWN bit high. The IC does not
directly enter OVUVFLT in an overcurrent condition, but
does enter this state due to the resulting UV condition.
Each regulator has an undervoltage fault mask and an
overvoltage fault mask. If the UV or OV fault mask is
active, nIRQ is not asserted in the fault condition. Even
though the fault is masked, the system can still read
each regulators UV and OV. Even though the fault is
masked, the IC still enters the OVUV Fault state.
Turn-on Delay. The turn-on delay is the time between
an input trigger going active and the output starting to
turn on. Each output’s turn-on delay is configured via its
I2C bit ON DELAY. Turn-on delays can be changed after
the IC is powered on, but they are volatile and reset to
the factory defaults when power is recycled.
Startup/Shutdown
The IC automatically transitions from the RESET state
to the POWER SEQUENCE START state when input
power is applied. The IC then transitions to either the
POWER ON, SLEEP, or DPSLP state depending on the
Turn-off Delay. The turn-off delay is the time between
an input trigger going in-active and the output starting to
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
20
ACT88320QI-T
Rev 2.0, 20-Dec-2017
turn off. Each output’s turn-off delay is configured via its
I2C bit OFF DELAY. Turn-off delays can be changed
after the IC is powered on, but they are volatile and reset
to the factory defaults when power is recycled.
DVS can be implemented for all buck converters at one
time via I2C. The user can select from two different
configurations to enter DVS via I2C. Note that DVS is
disabled when EN_DVS_I2C = 0.
Softstart Time. The softstart time is the time it takes an
output to ramp from 10% to 90% of its programmed
voltage. All buck converter softstart times are controlled
by a single I2C bit ALL_BUCKS_FASTER_SS. When
set to 0, the softstart times are 600µs. When set to 1,
the softstart times are 250µs. The default softstart time
can be changed after the IC is powered on, but it is
volatile and resets to the factory defaults when power is
recycled.
1. Enable DVS via a single I2C write to
I2C_DVS_ON bit: With EN_DVS_I2C = 1
and SEL_DVS_IN = 0, the IC enters DVS
when I2C_DVS_ON = 1 and exits DVS
when it equals 0.
2. Enable DVS whenever the IC enters
SLEEP state: With EN_DVS_I2C = 1 and
SEL_DVS_IN = 1, any condition that puts
the IC into SLEEP state also puts the IC
into DVS mode. Note that I2C_DVS_ON bit
does not affect this configuration.
Output Voltage. The output voltage is each regulator’s
desired voltage. Each buck’s output voltage is
programmed via its I2C bits VSET0 and VSET1. The
output regulates to VSET0 in ACTIVE mode. They can
be programmed to regulate to VSET1 in DVS, SLEEP,
and DSPSLP modes. Each LDO has a single register,
VSET, to set its output voltage. Each output’s voltage
can be changed after the IC is powered on, but the new
setting is volatile and is reset to the factory defaults
when power is recycled. Output voltages can be
changed on the fly. If a large output voltage change is
required, it is best to make multiple smaller changes.
This prevents the IC from detecting an instantaneous
over or under voltage condition because the fault
threshold are immediately changed, but the output
takes time to respond.
Note that the IC cannot be configured to enter DVS in
DPSLP state. Table 3 summarizes I2C DVS functionality.
EN_DVS_I2C
SEL_DVS_IN
I2C_DVS_ON
DVS MODE
0
x
x
Off
1
0
0
Off
1
0
1
On
1
1
x
On in SLEEP
state
Table 3. I2C DVS Control
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage
condition does not exceed the current limit setting of the
regulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the
voltage step, slew rate, and load current conditions do
not result in an instantaneous loading that results in a
current limit condition.
Dynamic Voltage Scaling
On-the-fly dynamic voltage scaling (DVS) for the three
buck converters is available via either the I2C interface
or a GPIO. DVS allows systems to save power by
quickly adjusting the microprocessor performance level
when the workload changes. Note that DVS is not a
different operating state. The IC operates in the ACTIVE
state, but just regulates the outputs to a different voltage.
Each buck converter operates at its VOUT0 voltage in
normal operation and operates at its VOUT1 voltage
when the DVS input trigger is active. DVS can be
implemented three ways.
Input Voltage Monitoring (SYSMON)
The ACT88320 monitors the input voltage on the VIN
pins to ensure it is within specified limits for system level
operation. IC “wakes up” and allows I2C communication
when VIN rises above UVLO (~2.7V). However, the outputs do not turn on until VIN rises above the SYSMON
threshold. SYSMON is programmable between 2.7V
and 4.2V. The IC then asserts the nIRQ pin if VIN drops
below SYSMON, but the outputs continue to operate
normally. The IC turns off all outputs if the input voltage
The first method is to individually put each buck
converter in DVS by manually writing a new voltage
regulation setpoint into its VOUT0 register.
DVS can also be implemented for all buck converters at
one time via a single GPIO input. The IC’s specific CMI
determines the specific GPIO used for DVS. This setting
can be modified with a custom CMI.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
21
ACT88320QI-T
Rev 2.0, 20-Dec-2017
drops below UVLO. I2C bit VSYSSTAT = 1 when VIN <
SYSMON and 0 when VIN > SYSMON. This fault can
be masked with I2C bit VSYSMSK.
operation of the interrupt status registers clears the interrupt provided the interrupting condition is removed. If
the interrupting condition is still present, nIRQ stays asserted and the interrupt status bit stay set. The interrupt
status registers are 0x00h, 0x01h, 0x03h, 0x04h, 0x05h,
0xA0h, 0xA6h, and 0xE5h.
Fault Protection
The ACT88320 contains several levels of fault protection, including the following:
The ICs specific CMI determines which GPIOx is used
for the nIRQ pin. nIRQ is an open-drain output and
should be pulled up to an appropriate supply voltage
with a 10kΩ or greater pull-up resistor.
Output Overvoltage
Output Undervoltage
Output Current Limit and short circuit
nRESET
Thermal Warning
The ACT88320 provides a reset function to issue a
master reset to the system CPU/controller. nRESET is
immediately asserted low when either the VIN voltage
is above or below the UV or OV thresholds or any power
supply that is connected to the nRESET functionality
goes below its Power Good threshold. The IC’s specific
CMI configures which power supplies are connected to
the nRESET functionality. After startup, nRESET de-asserts after a programmable delay time when VIN and all
connected power supply outputs are above their respective UVLO thresholds. The reset delay time, 20ms
to 100ms, is controlled by the I2C TRST_DLY register
bits. The IC’s CMI programs the specific GPIOx pin
used for the reset functionality. The CMI also programs
which regulators outputs are monitored for the reset
functionality.
Thermal Shutdown
There are three types of I2C register bits associated with
each fault condition: fault flag bits, fault bits, and mask
bits. The fault flag bits display the real-time fault status.
Their status is valid regardless of whether or not that
fault is masked. The mask bits either block or allow the
fault to affect the fault bit. Each potential fault condition
can be masked via I2C if desired. Any unmasked fault
condition results in the fault bit going high, which asserts
the nIRQ pin. nIRQ is typically active low. The nIRQ pin
only de-asserts after the fault condition is no longer present and the corresponding fault bit is read via I2C. Note
that masked faults can still be read in the fault flag bit.
Refer to Active-Semi Application Note describing the
Register Map for full details on I2C functionality and programming ranges.
EXT_EN
nIRQ (Interrupt)
The ACT88320 provides an external power supply enable function, EXT_EN. EXT_EN is used to control an
external regulator or to provide a control signal to other
system components. It is used as part of the sequencing
profile and can be programmed to have different input
triggers as well as delay times. The IC’s CMI programs
the specific GPIOx pin used for the EXT_EN functionality.
The interrupt function is typically used to drive the interrupt input of the system processor. Many of the
ACT88320's functions support interrupt-generation as a
result of various conditions. These are typically masked
by default, but may be unmasked via the I2C interface.
For more information about the available fault conditions, refer to the appropriate sections of this datasheet.
nIRQ can be triggered from:
EXT_PG
1. Die temperature warning generated
The ACT88320 provides an external input trigger,
EXT_PG, for startup sequencing. EXT_PG can be used
as the startup trigger for one or of the power supplies.
EXT_EN and EXT_PG allow the IC to fully incorporate
one or more external power supplies into the startup sequence. The IC’s CMI programs the specific GPIOx pin
used for the EXT_EN functionality.
2. Any buck regulator exceeding peak current limit
for 16 cycles after soft start or a UV/OV condition.
3. Any LDO regulator exceeding current limit for
more than 16uS after soft start or a UV/OV condition.
Output Under/Over Voltage
4. Input goes above OVP threshold or falls below
the UV threshold.
The ACT88320 monitors the output voltages for under
voltage and over voltage conditions. If an output enters
an UV/OV fault condition, the IC shuts down all outputs
for 100ms and restarts with the programmed power up
If any of these faults occur the nIRQ output is asserted
active low. After nIRQ pin is asserted, an I2C reading
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
22
ACT88320QI-T
Rev 2.0, 20-Dec-2017
sequence. If an output is in current limit, it is possible
that its voltage can drop below the UV threshold which
also shuts down all outputs. If that behavior is not
desired, mask the appropriate fault bit. Each output still
provides its real-time UV/OV fault status via its fault flag,
even if the fault is masked. Masking an OV/UV fault just
prevents the fault from being reported via the IRQ pin.
A UV/OV fault condition pulls the nRESET pin low. Note
that the IC’s specific CMI sets the defaults for which
regulators mask the UV and OV fault conditions.
above the Thermal Shutdown Temperature of typically
160 deg C. A temperature fault shuts down all outputs
unless the fault is masked. Both the fault and the warning can be masked via I2C. The temperature warning
and fault flags still provide real-time status even if the
faults are masked. Masking just prevents the faults from
being reported via the nIRQ pin.
INRUSH CONTROL
When power is applied to the system, the OVSNS pin
checks for under voltage and over voltage. If the input
voltage is within spec, the IC turns on an external NChannel MOSFET, which supplies power to the VIN and
AVIN pins. VIN and AVIN power the IC, the buck converters, and the LDOs. The IC controls the voltage ramp
on VIN to control the inrush current from the input voltage. The gate drive voltage is typically V, which requires
a 12V gate drive FET.
Output Current Limit
The ACT88320 incorporates a three level overcurrent
protection scheme for the buck converters and a single
level scheme for the LDOs. For the buck converters, the
overcurrent current threshold refers to the peak switch
current. The first protection level is when a buck
converter’s peak switch current reaches 75% of the
Cycle-by-Cycle current limit threshold for greater than
16 switching cycles. Under this condition, the IC reports
the fault via the appropriate fault flag bit. If the fault is
unmasked, it asserts the nIRQ pin. The next level is
when the current increases to the Cycle-by-Cycle
threshold. The buck converter limits the peak switch
current in each switching cycle. This reduces the
effective duty cycle and causes the output voltage to
drop, potentially creating an undervoltage condition.
When the overcurrent condition results in an UV
condition, and UV is not masked, the IC turns off all
supplies for 100ms and restarts. The third level is when
the peak switch current reaches 122% of the Cycle-byCycle current limit threshold. This immediately shuts
down the regulator and waits 14ms before restarting.
OVP CONTROL
When over voltage is detected on the OVSNS pin, it
generates a fault condition to shutdown the inrush controller. The overvoltage condition latches VIN output off
until the overvoltage condition is removed. When the input voltage is within specified limits, the IC automatically
restarts. An OVP condition is not reported via I2C.
Input Current Limit
An external sense resistor can be used between
OVSNS and OVSNS_M to detect the input current to
VIN. An overcurrent warning occurs when the voltage
across the sense resistor reaches 72.5% of the current
limit threshold. The current warning asserts nIRQ low.
The current limit warning can be masked with I2C bit INRUSH_ILIM_MSK. An overcurrent condition occurs
when the voltage across the sense resistor reaches the
current limit threshold voltage of 85mV. OVGATE modulates the external MOSFET gate voltage to regulate
the maximum current through the MOSFET and protect
against an overcurrent condition. If the system attempts
to pull more current, the VIN voltage starts to drop. If
VIN drops below the programmed SYSMON setting, the
IC asserts nIRQ.
For LDOs, the overcurrent thresholds are set by each
LDO’s Output Current Limit setting. When the output
current reaches the Current Limit threshold, the LDO
limits the output current. This reduces the output
voltage, creating an undervoltage condition, causing all
supplies to turn off for 100ms before restarting.
The overcurrent fault limits for the buck converters are
adjustable via I2C. LDO current limit is fixed.
Overcurrent fault reporting can be masked via I2C, but
the overcurrent limits are always active and will shut
down the IC when exceeded.
Pin Descriptions
Thermal Warning and Thermal Shutdown
Many of the ACT88320 input and output pins are configurable via CMI configurations. The following descriptions are refer to basic pin functions and capabilities.
Refer to the CMI Options section in the back of the
datasheet for specific pin functionality for each CMI.
The ACT88320 monitors its internal die temperature
and reports a warning via nIRQ when the temperature
rises above the Thermal Interrupt Threshold of typically
135 deg C. It reports a fault when the temperature rises
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
23
ACT88320QI-T
Rev 2.0, 20-Dec-2017
GPIO1 (pin 13). GPIO1 can be programmed for any of
the above functions except the LED drivers. It can be
programmed for both open drain and push-pull.
VIN
VIN pins are the dedicated input power to the buck converters. Buck1 uses pins 17 and 18. Buck2 uses pins 23
and 24. Buck 3 uses pins 1 and 2. Each buck converter
must be bypassed directly to PGND on the top PCB
layer with a 10uF capacitor.
GPIO2 (pin 14). GPIO2 is the same as GPIO1
GPIO3 (pin 12). GPIO3 can be programmed for all the
above functions including the LED drivers. It can be only
be programmed for open drain outputs.
AVIN
AVIN is the input power to the LDOs. It also powers the
IC’s analog circuitry. AVIN must be bypassed directly to
AGND on the top PCB layer with a 1uF ceramic capacitor.
GPIO4 (pin 11). GPIO4 is the same as GPIO3
GPIOx pins can be an input, an open-drain output, or a
push-pull output. They are 5.5V tolerant meaning they
can go to 5.5V even if VIO is less than 5.5V.
OVGATE
SCL, SDA
This pin drives the gate of an external N-ch FET. OVGATE slowly turns on the FET to provide softstart when
power is applied. It quickly turns off the FET in an overvoltage condition. Connect to PGND if the input overvoltage FET is not used.
These are the I2C clock and data pins to the IC. They
have standard I2C functionality.
PGND
The PGND pins are the buck converter power ground
pins. They connect directly to the buck converters’ low
side FETs. Buck1 and Buck2 use pin 21. Buck3 uses
pins 7 and 8. All PGND pins must be connected directly
to the IC’s exposed pad under the IC.
OVSNS, OVSNS_M
These are the positive and negative input current sense
pins. They should be kelvin connected to the input current sense resistor. OVSNS is also the input voltage
sense pin. Connect to PGND if the input overvoltage
FET is not used.
SWx
SWx are the switch nodes for the buck converters. They
connect directly to the buck inductor on the top layer.
VIO
This is the bias supply input to the IC’s digital circuitry.
It powers the GPIO pins. VIO is typically connected to
the VIN pins, but can be powered from a different voltage rail if desired. VIO should be bypassed to PGND
with a 1uF ceramic capacitor.
FB_Bx
These are the feedback pins for the buck regulators.
They should be kelvin connected to the buck output capacitors.
LSG1
PWREN
LSG1 is the load switch FET gate drive pin.
PWREN is a digital input that helps determine if the IC
operates in POWER ON mode or DPSLP mode. Refer
to the DPSLP State section for details.
OUT_LDOx
These are the LDO output pins. Each LDO output must
be bypassed to AGND with a 1uF capacitor.
PWREN is referenced to the AVIN pin, and is 5.5V
tolerant meaning that PWREN can go to 5.5V even if
AVIN is less than 5.5V.
PWREN has a 10us
bidirectional filter to prevent unwanted triggering from
noise.
AGND
AGND is the ground pin for the IC’s analog circuitry and
LDOs. AGND must be connected to the IC’s exposed
pad. The connection between AGND and the exposed
pad should not have high currents flowing through it.
GPIOx
EXPOSED PAD
The ACT88320 has four GPIO pins. Each GPIO is programmed for a specific function by the IC’s CMI. The
available functions are input triggers for sequencing
(EXT_PG), output triggers for sequencing (EXT_EN),
nRESET, nIRQ, DVS, voltage select pins for the voltage
regulators, LED drivers, and GPIO.
The exposed pad is the ICs ground reference. All
ground pins must connect to the exposed pad. It must
be soldered to the PCB.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
24
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Step-down DC/DC Converters
Operating Mode
General Description
By default, all buck converters operate in fixed-frequency PWM mode at medium to heavy loads, then
transition to a proprietary power-saving mode at light
loads in order to save power. Power-save mode reduces conduction losses by preventing the inductor current from going negative.
The ACT88320 contains three fully integrated stepdown converters. Buck1 is a 4A output, while Buck2 and
Buck3 are 2.5A outputs. All buck converters are fixed
frequency, current-mode controlled, synchronous PWM
converters that achieve peak efficiencies of up to 95%.
The buck converters switch at 1.125 or 2.25MHz and
are internally compensated, requiring only three small
external components (Cin, Cout, and L) for operation.
The buck regulators minimize noise in sensitive
applications with the use of a switching phase delay and
offset. Additionally, all regulators are available with a
variety of standard and custom output voltages, and
may be software-controlled via the I2C interface for
systems that require advanced power management
functions.
To further optimize efficiency, a low power mode, LPM,
is available that provides even higher efficiency with
very small load currents. LPM minimizes quiescent current at the expense of slightly larger transient response.
LPM is user controllable and can be enabled and disabled dynamically to allow the customer to optimize the
balance between power consumption and transient response. LPM is enabled when I2C bits DISLPM = 0 and
LP_MODE = 1.
The buck converters can also be forced to operate in
PWM mode at light load by setting I2C bit ForcePWM =
1. This results in slightly lower efficiency at light loads,
but improves transient response.
The ACT88320 buck regulators are highly configurable
and can be quickly and easily reconfigured via I2C. This
allows them to support changes in hardware
requirements without the need for PCB changes.
Examples of I2C functionality are given below:
Synchronous Rectification
Ability to mask individual faults
Buck1/2/3 each feature integrated synchronous rectifiers (or LS FET drivers), maximizing efficiency and minimizing the total solution size and cost by eliminating the
need for external rectifiers.
Dynamically change output voltage
Soft-Start
On/Off control
Buck1/2/3 include internal 600us soft-start ramps which
limit the rate of change of the output voltage, minimizing
input inrush current and ensuring that the output powers
up in a monotonic manner that is independent of loading
on the outputs. This circuitry is effective any time the
regulator is enabled, as well as after responding to a
short-circuit or other fault condition. A single I2C register,
ALL_BUCKS_FASTER_SS, adjusts softstart between
600us when = 0 and 250us when = 1.
Real-time power good, OV, and current limit status
Softstart ramp
Slew rate control
Switching delay and phase control
Low power mode
Overcurrent thresholds
Refer to the Active-Semi Application Note describing the
Register Map for full details on I2C functionality and
programming ranges.
Output Voltage Setting
Buck1/2/3 regulate to the voltage defined by I2C register
VSET0 in normal operation and by VSET1 in DVS mode.
Buck1 can be programmed between 0.6V and 2.991V
in 9.376mV steps.
100% Duty Cycle Operation
Vbuck1=0.6 + VOUTx * 0.009376V
All buck converters are capable of 100% duty cycle operation. During 100% duty cycle operation, the high-side
power MOSFETs are held on continuously, providing a
direct connection from the input to the output (through
the inductor), ensuring the lowest possible dropout voltage in battery powered applications.
Where VOUTx is the decimal equivalent of the value in
each regulator’s I2C VOUTx register. The VOUTx registers contain an unsigned 8-bit binary value. As an example, if Buck 1’s VOUT0 register contains 01000000b
(128 decimal), the output voltage is 1.8V.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
25
ACT88320QI-T
Rev 2.0, 20-Dec-2017
The Buck1 output voltage range can also be configured
to the same range as Buck2/3 via a custom CMI.
POK and Output Fault Interrupt
Each DC/DC features a power-OK status bit, POK,
which can be read by the system microprocessor via the
I2C interface. If an output voltage is lower than the POK
threshold, typically 7% below the programmed regulation voltage, that regulator’s POK bit will be 0.
Buck2/3 are programmable between 0.8V to 3.9875V in
12.5mV steps
Vbuck2 = 0.8V + VOUTx * 0.0125V
Active Semi recommends that the buck converter’s output voltage be kept within +/- 25% of the default output
voltage to maintain accuracy. Voltage changes larger
than +/- 25% may require different factory trim settings
(new CMI) to maintain accuracy.
If a DC/DC's nFLTMSK[ ] bit is set to 1, the ACT88320
will interrupt the processor if the DC/DC's output voltage
falls below the power-OK threshold. In this case, nIRQ
asserts low and remains asserted until either the regulator is turned off or goes back into regulation, and the
POK [ ] bit has been read via I2C.
DVS
Each buck converter supports Dynamic Voltage Scaling
(DVS). In normal operation, each output regulates to the
voltage programmed by its VSET0 I2C register. During
DVS, each output regulates to its VSET1.
Optimizing Noise
Each buck converter contains several features available
via I2C to further optimize functionality. The top P-ch
FET’s turn-on timing can be shifted approximately
110ns from the master clock edge via the PHASE_DELAY I2C bit. It can also be aligned to the rising or falling
clock edge via the PHASE I2C bit.
During the voltage transition between VSET0 to VSET1
and VSET1 to VSET0, the I2C bit FORCEPWM is set to
1 to force the buck converters into PWM mode. This ensures that the output transition to the new voltage level
as quickly as possible. The outputs transition between
the two setpoints at a defined slew rate to minimize inrush currents. Note that VSET0 must be set higher than
VSET1. Violating this requirement results in an OV fault
during DVS.
Minimum On-Time
The ACT88320 minimum on-time is approximately
125ns. If a buck converter’s calculated on-time is less
than 125ns with 2.25MHz operation, then the buck converter must be operated at 1.125MHz. Active Semi will
generate the IC CMIs to ensure that the buck converters
do not run into the minimum on-time limitations. The following equation calculates the on-time.
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage
condition does not exceed the current limit setting of the
regulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the
voltage step, slew rate, and load current conditions do
not result in an instantaneous loading that results in a
current limit condition. See paragraph Dynamic Voltage
Scaling for options to enter and exit DVS.
∗
Where Vout is the output voltage, VIN is the input voltage, and FSW is the switching frequency.
Overcurrent and Short Circuit Protection
Each buck converter provides overcurrent and short circuit protection with built in foldback protection. Overcurrent protection is achieved with cycle-by-cycle current
limiting. The peak current threshold is set by the
ILIM_SET I2C bits.
Enable / Disable Control
During normal operation, each buck may be enabled or
disabled via the I2C interface by writing to that regulator's ON bit. Note that disabling a regulator that is used
as an input trigger to another regulator may or may not
disable the other regulators following it, depending on
the specific CMI settings. Each buck converter has a
load discharge function designed to quickly pull the output voltage to ground when the converter is disabled.
The circuit connects an internal resistor (4.4ohm for
Buck1 and 9.4ohms for Buck2/3) from the output to
PGND when the converter is disabled.
If the peak current reaches 75% of the programmed
threshold for 16 consecutive switching cycles, the IC asserts nIRQ low and changes I2C bit ILIM_WARN = 1,
but continues to operate normally.
If the peak current reaches the programmed threshold,
the IC turns off the power FET for that switching cycle.
If the peak current reaches the threshold 16 consecutive
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
26
ACT88320QI-T
Rev 2.0, 20-Dec-2017
switching cycles, the IC asserts nIRQ low. This condition typically results in shutdown due to an UV condition
due to the shortened switching cycle.
loads. Choose the input capacitor value to keep the
input voltage ripple less than 50mV.
A short circuit condition that results in the peak switch
current being 122.5% of ILIM_SET immediately shuts
down the supply and asserts nIRQ low if the fault bit is
not masked. The supply tries to restart in 14ms. If the
fault condition is not masked, the IC transitions to the
OVUV State, turns off all supplies, and restarts the system in 100ms.
∗
Vripple
∗ 1
∗
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors
smaller than 0805.
A capacitor’s actual capacitance is strongly affected by
its DC bias characteristics. The input capacitor is
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Z5U, or similar dielectrics is not recommended. Input
capacitor placement is critical for proper operation.
Each buck’s input capacitor must be placed as close to
the IC as possible. The traces from VIN to the capacitor
and from the capacitor to PGND should as short and
wide as possible.
The buck converters also have built in current foldback
protection. After softstart is complete, if a short circuit or
overload condition causes the output to go out of regulation for > 28us, the IC reduces the peak-to-peak current limit to 1.5A. This reduces system level power dissipation in short circuit or overload conditions. If the load
current drops low enough to allow the output voltage to
enter regulation with the reduced peak-to-peak current
limit, the output restarts and the IC resets the peak-topeak current limit to the default value
Inductor Selection
If a buck converter reaches overcurrent or short circuit
protection, the status is reported in the ILIM I2C registers. The contents of these registers are latched until
read via I2C. Overcurrent and short circuit conditions
can be masked via the I2C bit ILIM_FLTMSK. The IC’s
specific CMI determines which regulators mask the current limit fault.
The Buck converters utilize current-mode control and a
proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. The ACT88320 is optimized for
operation with 1.0μH inductors, but can be used with
inductor values 1uH to 2.2uH. Choose an inductor with
a low DC-resistance, and avoid inductor saturation by
choosing inductors with DC ratings that exceed the
maximum output current by at least 30%. The following
equation calculates the inductor ripple current.
Compensation
The buck converters utilize current-mode control and a
proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating
range. No compensation design is required; simply follow a few simple guide lines described below when
choosing external components.
∆
∗
1
∗
Where VOUT is the output voltage, VIN is the input voltage,
FSW is the switching frequency, and L is the inductor
value.
Input Capacitor Selection
Each buck converter has a dedicated input pin and
power ground pin. Each buck converter should have a
dedicated input capacitor that is optimally placed to
minimize the power routing loops for each buck
converter. Note that even though each buck converter
has separate inputs, all buck converter inputs must be
connected to the same voltage potential.
Output Capacitor Selection
The ACT88320 is designed to use small, low ESR,
ceramic output capacitors. Buck1 typically requires
2x22uF or a single 47uF output capacitor while Buck2
and Buck3 require a 22uF output capacitor each. In
order to ensure stability, the Buck1 effective
capacitance must be greater than 20uF while Buck2
and Buck3 effective capacitance must be greater than
12uF. The output capacitance can be increased to
reduce output voltage ripple and improve load
transients if needed. Design for an output ripple voltage
Each regulator requires a high quality, low-ESR,
ceramic input capacitor. 10uF capacitors are typically
suitable, but this value can be increased without limit.
Smaller capacitor values can be used with lighter output
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
27
ACT88320QI-T
Rev 2.0, 20-Dec-2017
less than 1% of the output voltage. The following
equation calculates the output voltage ripple as a
function of output capacitance.
VRIPPLE
3. OV is disabled. There is no overvoltage detection circuitry on the output of the bypass switch.
∆
8∗
LDO Converters
∗
General Description
Where ΔIL is the inductor ripple current, FSW is the
switching frequency, and COUT is the output capacitance
after taking DC bias into account.
The ACT88320 contains two fully integrated, 200mA,
low dropout linear regulators (LDO). LDOs have been
optimized to achieve low dropout and high PSRR. The
LDOs can also be configured in load switch mode to
behave like load switches.
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors
smaller than 0805.
The LDOs are require only two small external
components (Cin, Cout) for operation. They ship with
default output voltages that can be modified via the I2C
interface for systems that require advanced power
management functions.
A capacitor’s actual capacitance is strongly affected by
its DC bias characteristics. The output capacitor is
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Z5U, or similar dielectrics are not recommended due to
their wide variation in capacitance over temperature and
voltage ranges.
Soft-Start
Each LDO contains a softstart circuit that limits the rate
of change of the output voltage, minimizing input inrush
current and ensuring that the outputs power up in a
monotonically. This circuitry is effective any time the
LDO is enabled, as well as after responding to a short
circuit or other fault condition. Each LDO’s softstart time
is fixed to 275us.
Buck1 Bypass mode
General Description
Buck1 is configurable as a bypass switch for systems
with a 3.3V bus voltage. The bypass switch provides full
sequencing capability by allowing the 3.3V bus to be
used as the input to the other supplies and still be
properly sequenced to the downstream load. In bypass
mode, the Buck1 P-ch FET acts as a switch and the Nch FET is disabled. The bypass switch turns on the 3.3V
rail with the programmed delay and softstart time.
Output Voltage Setting
The LDOs regulate to the voltage defined by their I2C
registers LDO1_VSET and LDO2_VSET. The LDOs do
not have a second VSET register like the buck converters. The LDOs can be configured with two different output voltage range settings. I2C register bit VREF_CTRL
controls the two settings. This bit is factory set and is
not user configurable.
In bypass mode, the ACT88320 Buck 1 I2C registers are
reconfigured to the following.
1. ILIM bit is the output of the PMOS Current Detection circuit. In an overcurrent condition, ILIM
triggers the nIRQ output. ILIM is latched until
read via I2C. ILIM can be masked with the
ILIM_FLTMSK register.
VREF_CTRL = 0
Vref (V)
Vout Range (V)
Vout Step Size (mV)
2. The UV register bit is reconfigured to the output
of the PMOS Current Shutdown circuit. This is
set to 5.6A typical. If the bypass switch current
exceeds 5.6A, it limits the current which triggers
an under voltage fault condition and moves the
IC into the OVUV FAULT state. This immediately shuts down all regulators including the bypass switch. The system restarts in 100mS, following the programmed startup sequencing.
This fault can be masked with I2C bit UV_FLTMASK. This fault is latched in the UV_REG I2C
bit.
VREF_CTRL = 1
0.8
0.6
0.8 – 3.9875
0.6 – 2.991
12.5
9.375
The following equation determines the LDO output voltages when VREF_CTRL = 0.
VLDOx = 0.8V + LDOx_VSET * 0.0125V
The following equation determines the LDO output voltages when VREF_CTRL = 1.
VLDOx = 0.6V + LDOx_VSET * 0.009375V
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
28
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Active Semi recommends that the LDO’s output voltage
be kept within +/- 25% of the default output voltage to
maintain accuracy. Voltage changes larger than +/- 25%
may require different factory trim settings (new CMI) to
maintain accuracy.
and starts up with default sequencing. Overcurrent and
short circuit conditions can be masked via the I2C bit
ILIMFLTMSK_LDOx. When masked, the LDO still shuts
down or limits current (based on the LDOx_ILIM_SHUTDOWN_DIS bit). In this condition, it does not enter the
OVUVFLT state due to the faults being masked. If it
shuts down, it automatically restarts in 14ms.
Enable / Disable Control
Input Capacitor Selection
During normal operation, each LDO may be enabled or
disabled via the I2C interface by writing to that regulator's ON bit. Note that disabling an LDO that is used as
an input trigger to another regulator may or may not disable the other regulators following it, depending on the
specific CMI settings. Each LDO has a load discharge
function designed to quickly pull the output voltage to
ground when the LDO is disabled. The circuit connects
an internal resistor (50ohm) from the output to AGND
when the LDO is disabled.
The AVIN pins supplies the input power to both LDO.
AVIN requires a high quality, low-ESR, ceramic input
capacitor. A 1uF is typically suitable, but this value can
be increased without limit. The input capacitor is should
be a X5R, X7R, or similar dielectric.
Output Capacitor Selection
Each LDO requires a high quality, low-ESR, ceramic
output capacitor. A 1uF is typically suitable, but this
value can be increased without limit. The input capacitor
is should be a X5R, X7R, or similar dielectric. The LDO
POK and Output Fault Interrupt
Each LDO features a power-OK status bit, POK, which
can be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the POK
threshold, typically 11% below the programmed regulation voltage, that regulator’s POK bit will be 0.
effective output capacitance must be greater than 0.7uF.
LOAD SWITCHES
General Description
If an LDO's nFLTMSK[ ] bit is set to 1, the ACT88320
will interrupt the processor if that LDO’s output voltage
falls below the power-OK threshold. In this case, nIRQ
asserts low and remains asserted until either the LDO
is turned off or goes back into regulation, and the POK
[ ] bit has been read via I2C.
The ACT88320 features a Load Switch gate driver,
LSG1, to power an external n-ch FET. The Load Switch
allows a common power rail to be switched on/off to create a power “island” for system loads. This “island” can
be turned off to minimize power consumption when
those loads are not needed. The Load Switch can also
be incorporated into the ICs startup sequencing with
programmable turn-on and turn-off delay times. It can
also be programed to be turned on or off in SLEEP and
DPSLP states.
Overcurrent and Short Circuit Protection
Each LDO provides overcurrent detection and short circuit protection featuring a current-limit foldback function.
When current limit is reached, the IC can either shut the
output off or limit the output current until the overload
condition is removed. This is controlled by I2C bits
LDOx_ILIM_SHUTDOWN_DIS.
Softstart
The LSG1 incorporates a programmable slew rate to
control the turn-on speed of the external FET. The
LSG1 output consists of a current source to linearly
charge the external FET gate voltage. The slew rate is
controlled via the I2C bits GATE1_SLEW[1:0]. The current source is programmable between 2.5uA and 10uA
in 2.5uA increments. The slew rate is
The overcurrent threshold is set by the ILIM1 and ILIM2
I2C bits. In both an overload and a short circuit condition,
the LDO limits the output current which causes the output voltage to drop. This can result in an undervoltage
fault in addition to the current limit fault. If an LDO load
reaches overcurrent detection threshold, the status is
reported in the ILIM_LDOx I2C registers. The contents
of these registers are latched until read via I2C. When
the current limiting results in a drop in output voltage
that triggers an undervoltage condition, the IC shuts
down all power supplies, asserts nIRQ low, and enters
the UVLOFLT state provided the faults are not masked.
Once in the OVUVFLT state, the IC restarts in 100ms
SLEW
_
Where SLEW is the LSG1 slew rate in V/s, ILSG1 is the
gate drive current in Amps, and CFET_GATE is the external
FET gate capacitance in Farads. Adding a discrete gate
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
29
ACT88320QI-T
Rev 2.0, 20-Dec-2017
capacitor will provide more consistent Load Switch turn
on characteristics.
3. Place the LDO input capacitor close to the AVIN
pin. Connect the capacitor directly to AVIN and
AGND on the top layer.
LSG1 has an active 75 ohm pulldown resistor when disabled to quickly turn off the external FET.
4. The Buck output capacitors should be placed
by the inductor and connected directly to the inductor and ground plane with short and wide
traces. The output capacitor ground should
make a short connection to the input capacitor
ground. If required, use multiple vias.
Current Limit
Because LSG1 only connects to the external FET gate,
Load Switch does not have a current limit function. The
input to the Load Switch should come from an
ACT88320 Buck, LDO, or other current limited source.
5. Each regulator’s FB_Bx should be Kelvin connected to its output capacitor through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. The IC regulates the output voltage to
this Kelvin connection.
Load Switch POK
The load switch internal Power OK, POK, signal can be
used in the sequencing of other power supplies. The
load switch POK signal goes active when the load
switch gate drive voltage at the LSG1 pin is greater than
VIN + 1V and VIN – VOUT < 100mV. Note that the actual load switch may or may not be fully on at this time
depending on the FET used for the load switch or any
additional filtering or delay circuitry connected to LSG1.
6. Connect the PGND and AGND ground pins
must be electrically connected together. Because the AGND ground plane is used for analog, digital, and LDO grounds, it does not need
to be completely isolated from the rest of the
PCB grounds. However, take care to avoid routing the buck converter switching currents
through the analog ground connections.
PC board layout guidance
Proper parts placement and PCB layout are critical to
the operation of switching power supplies. Follow the
following layout guidelines when designing the
ACT88320 PCB. Refer to the Active-Semi ACT88320
Evaluation Kits for layout examples
7. Connect the VIO input capacitor to the AGND
ground pin.
8. Remember that all open drain outputs need
pull-up resistors.
1. Place the buck input capacitors as close as
possible to the IC. Refer to the Pin Descriptions
for each buck converter’s dedicated VIN and
PGND pins. Connect the input capacitors directly to the corresponding VIN and PGND
power ground pin on the top layer. Routing
these traces on the top layer eliminates the
need for vias.
9. Connect the exposed pad directly to the top
layer ground plane. Connect the top layer
ground plane to both internal ground planes
and the PCB backside ground plane with thermal vias. Provide ground plane routing on multiple layers to allow the IC’s heat to flow into the
PCB and then spread radially from the IC. Avoid
cutting the ground planes or adding vias that restrict the radial flow of heat.
2. Minimize the switch node trace length between
each SW_Bx pin and the inductor. Optimal
switch node routing is to run the trace between
the input capacitor’s pads. Using 0805 sized input capacitors is recommended. Avoid routing
sensitive analog signals near these high frequency, high dV/dt traces.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
30
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Typical Operating Characteristics
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
31
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
32
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
33
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
34
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
35
ACT88320QI-T
Rev 2.0, 20-Dec-2017
The following components have been used with the ACT88320.
REFERENCE
DESCRIPTION
MANUFACTURER
Input Capacitor, Buck1
22uF, 10V, X5R
Standard
Input Capacitor, Buck2/3
22uF, 10V, X5R
Standard
Input Capacitor, LDO1/2
1uF, 10V, X5R
Standard
Output Capacitor, Buck1
2x22uF, 10V, X5R
Standard
Output Capacitor, Buck2/3
22uF, 10V, X5R
Standard
Output Capacitor, LDO1/2
1uF, 10V, X5R
Standard
Inductor, Buck1
1uH, 12mΩ
Wurth 74438356010
Inductor, Buck2/3/4
1uH, 63mΩ
Wurth 74438323010
VIO
1uF, 10V, X5R
Standard
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
36
ACT88320QI-T
Rev 2.0, 20-Dec-2017
CMI OPTIONS
This section provides the basic default configuration settings for each available ACT88320 CMI option. IC functionality
in this section supersedes functionality in the main datasheet. Generating the desired functionality for a custom CMI
sometimes requires reassigning internal resources, resulting in removal of base IC functionality. The following sections
attempt to describe any removed functionality from the base IC functionality. The user is required to fully test all required
functionality to ensure the CMI fully meets their requirements.
CMI 101: ACT88320QI101-T
CMI 101 is optimized for SMI SM2258, SM2258XT, SM2259 and SM2259XT processors.
Voltage and Currents
Rail
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DPSLP Mode
Voltage (V)
DVS Voltage
(V)
Current
Limit (A)
Fsw (kHz)
Buck1
3.3
OFF
OFF
3.3
4.6
2250
Buck2
1.8
OFF
OFF
1.8
3.0
2250
Buck3
1.15
0.9
0.9
0.9
3.0
1125
LDO1
3.3
3.3
3.3
3.3
0.315
n/a
LDO2
1.8
1.8
1.8
1.8
0.315
n/a
LS1
n/a
Off
Off
n/a
n/a
n/a
Startup and Sequencing
Rail
Sequence
Order
Sequencing
Input Trigger
StartUp
Delay (us)
Soft-Start
(us)
Shutdown
Delay (us)
Buck1
3
Buck3
500
600
500
Buck2
4
Buck1
500
600
0
Buck3
2
LDO1
500
600
1000
LDO1
1
VIN_UVLO
0
275
2000
LDO2
1
VIN_UVLO
0
215
1500
LS1
off
n/a
0
0
0
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
37
ACT88320QI-T
Rev 2.0, 20-Dec-2017
I2C Address
The ACT88320 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.
GPIO1 (pin 13) - nRESET
GPIO1 is configured as an open drain nRESET. nRESET goes open drain 20ms after Buck3 goes into regulation.
GPIO2 (pin 14) - EXT_EN
GPIO2 is configured as an open drain EXT_EN. EXT_EN goes high 2.5ms after Buck2 goes into regulation. EXT_EN
can be used to sequence on an external supply.
GPIO3 (pin 12) - nIRQ
GPIO3 is configured as an open drain nIRQ.
GPIO4 (pin 11) - DVS
GPIO4 is configured as a DVS input. Pulling the DVS input high makes the ACT88320 operate with normal output
voltages. The buck converters operate with voltages set by their I2C VSET0 registers. Buck3 output is 1.15V. Pulling the
input low makes the IC operate in DVS mode and the buck converters operate with voltages set by their VSET1 registers.
Buck3 output is 0.9V
SLEEP MODE
I2C default settings are SLEEP_MODE=0, SLEEP_EN=0, and SLEEP=0. Refer to the SLEEP State paragraph for details
on how to enter SLEEP Mode.
DPSLP MODE
I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. Refer to the DPSLP State paragraph for
details on how to enter DPSLP Mode.
VSYSMON
VSYSMON = 3.0V
Buck1 Voltage Setting
Buck 1 reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
LDO Voltage Setting
The LDO reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
38
ACT88320QI-T
Rev 2.0, 20-Dec-2017
CMI 103: ACT88320QI103-T
CMI 103 is optimized for the Atmel SAMA5D21 processor.
Voltage and Currents
Rail
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DPSLP Mode
Voltage (V)
DVS Voltage
(V)
Current
Limit (A)
Fsw (kHz)
Buck1
1.2
1.2
1.2
n/a
3
1125
Buck2
1.8
1.8
1.8
n/a
2
2250
Buck3
3.3
3.3
3.3
n/a
2
2250
LDO1
2.5
2.5
2.5
n/a
0.315
n/a
LDO2
3.3
3.3
3.3
n/a
0.315
n/a
LS1
Off
Off
Off
n/a
n/a
n/a
Startup and Sequencing
Rail
Sequence
Order
Sequencing
Input Trigger
StartUp
Delay (us)
Soft-Start
(us)
Shutdown
Delay (us)
Buck1
5
EXT_PG
0
600
500
Buck2
3
LDO2
500
600
500
Buck3
1
VIN_UVLO
0
600
500
LDO1
6
Buck1
500
215
0
LDO2
2
Buck3
500
275
500
LS1
n/a
n/a
n/a
n/a
n/a
External
Supply
4
Buck2
2500
0
0
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
39
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Hardware Configuration
This CMI is intended to have EXT_EN connected directly to EXT_PG. This configuration effectively gives Buck1 a 2.5ms
turn-on delay from Buck2.
I2C Address
The ACT88320 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.
GPIO1 (pin 13) - nRESET
GPIO1 is configured as an open drain nRESET. nRESET goes open drain 60ms after LDO1 goes into regulation.
GPIO2 (pin 14) - EXT_EN
GPIO2 is configured as an open drain EXT_EN. EXT_EN goes high 2.5ms after Buck2 goes into regulation. EXT_EN
can be used to sequence on an external supply. It is intended to be directly connected to EXT_PG to effectively turn on
Buck1 2.5ms after Buck2 turns on.
GPIO3 (pin 12) - nIRQ
GPIO3 is configured as an open drain nIRQ.
GPIO4 (pin 11) – EXT_PG
GPIO4 is configured as an external power good input. EXT_PG is the input trigger for Buck1. It is intended to be
connected directly to EXT_PG to effectively turn on Buck1 2.5ms after Buck2 turns on.
SLEEP MODE
I2C default settings are SLEEP_MODE=0, SLEEP_EN=0, and SLEEP=0. Refer to the SLEEP State paragraph for details
on how to enter SLEEP Mode.
DPSLP MODE
I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. Refer to the DPSLP State paragraph for
details on how to enter DPSLP Mode.
VSYSMON
VSYSMON = 3.0V
Buck1 Voltage Setting
Buck 1 reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
LDO Voltage Setting
The LDO reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
40
ACT88320QI-T
Rev 2.0, 20-Dec-2017
CMI 104: ACT88320QI104-T
CMI 104 is optimized for the Silicon Motion SM2262 and SM2263 ICs. It is designed to operate from a regulated 3.3V
input supply. The ACT88320QI104 powers the Silicon Motion reference design, SM2262_M2_S045A, which is an M.2
2280 form factor solid state disk drive, SSD. The ACT88320QI104 provides all required power rails and helps the user
to validate the full SSD system performance.
Voltage and Currents
Rail
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DPSLP Mode
Voltage (V)
DVS Voltage
(V)
Current
Limit (A)
Fsw (kHz)
Buck1
0.9
0.75
0.75
n/a
4.6
1125
Buck2
1.2/1.8
OFF
OFF
n/a
3
2250
Buck3
1.5/1.35
OFF
OFF
n/a
3
2250
LDO1
OFF
OFF
OFF
n/a
0.315
n/a
LDO2
1.8
1.8
1.8
n/a
0.315
n/a
LS1
ON
OFF
OFF
n/a
n/a
n/a
Startup and Sequencing
Rail
Sequence
Order
Sequencing
Input Trigger
StartUp
Delay (us)
Soft-Start
(us)
Shutdown
Delay (us)
LDO2
1
VIN_UVLO
500
215
0
Buck1
2
LDO2
500
600
0
Buck3
3
Buck1
500
600
0
LS1
4
Buck3
500
n/a
0
Buck2
5
LS1
1000
600
0
LDO1
n/a
n/a
n/a
n/a
n/a
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
41
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Hardware Configuration
Because the SM2262_M2_S045A does not use the inrush control circuitry, the design connects OVSNS, OVSNS_M,
and OVGATE to ground. The inrush circuitry can be used with the ACT88320QI104 by connecting them per the
datasheet guidelines.
Startup
CMI 104 Startup
VIN
LDO2
Buck1
0.5ms
0.5ms
Buck3
0.5ms
LS
1ms
nRESET
20ms
I2C Address
The ACT88320 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.
GPIO1 (pin 13) - nRESET
GPIO1 is configured as an open drain nRESET. nRESET goes open drain 20ms after LDO2 goes into regulation.
GPIO2 (pin 14) – Buck2_VID
GPIO2 is configured as a VID input for Buck2. When Pin 14 = 1, Buck2 = 1.2V. When Pin 14 = 0, Buck2 = 1.8V. This
allows the ACT88320 to put the SM2262 and SM2263 in different power states. Pin 14 can be changed at any time to
change the Buck2 output voltage, but actual usage depends on the application.
GPIO3 (pin 12) – Buck3_VID
GPIO3 is configured as a VID input for Buck3. When Pin 12 = 1, Buck3 = 1.5V. When Pin 12 = 0, Buck2 = 1.35V. This
allows the ACT88320 to put the SM2262 and SM2263 into different power states. Pin 12 can be changed at any time to
change the Buck3 output voltage, but actual application depends on the DDR memory used.
GPIO4 (pin 11) – Buck1_VID
GPIO4 is configured as a VID input for Buck1. When Pin 11 = 1, Buck1 = 0.9V. When Pin 11 = 0, Buck1 = 0.75V. This
allows the ACT88320 to put the SM2262 and SM2263 into different power states. Pin 11 can be changed at any time to
change the Buck1 output voltage, but actual application depends on the DDR memory used.
SLEEP MODE
I2C default settings are SLEEP_MODE=0, SLEEP_EN=0, and SLEEP=0. Refer to the SLEEP State paragraph for details
on how to enter SLEEP Mode.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
42
ACT88320QI-T
Rev 2.0, 20-Dec-2017
DPSLP MODE
I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. Refer to the DPSLP State paragraph for
details on how to enter DPSLP Mode.
VSYSMON
VSYSMON = 3.0V
Buck1 Voltage Setting
Buck 1 reference voltage is 0.6V. This sets the allowable voltage range between 0.6V and 2.991V in 9.376mV steps.
LDO Voltage Setting
The LDO reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
43
ACT88320QI-T
Rev 2.0, 20-Dec-2017
CMI 105: ACT88320QI105-T
CMI 105 is optimized for the Marvell Dean 88SS1074 microprocessor. It is designed to operate from a regulated 3.3V
input supply.
Voltage and Currents
Rail
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DPSLP Mode
Voltage (V)
DVS Voltage
(V)
Current
Limit (A)
Fsw (kHz)
Buck1
1.05
n/a
n/a
n/a
4.6
1125
Buck2
1.2/1.8
n/a
n/a
n/a
3
2250
Buck3
1.5/1.35
n/a
n/a
n/a
3
2250
LDO1
OFF
n/a
n/a
n/a
0.315
n/a
LDO2
1.8
n/a
n/a
n/a
0.315
n/a
LS1
ON
n/a
n/a
n/a
n/a
n/a
Startup and Sequencing
Rail
Sequence
Order
Sequencing
Input Trigger
StartUp
Delay (us)
Soft-Start
(us)
Shutdown
Delay (us)
LDO2
1
VIN_UVLO
500
275
0
Buck1
2
LDO2
500
600
0
Buck2
3
Buck1
500
600
0
Buck3
4
Buck2
1000
600
0
EXT_EN
4
Buck2
0
n/a
0
LS1
n/a
n/a
n/a
n/a
n/a
LDO1
n/a
n/a
n/a
n/a
n/a
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
44
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Hardware Configuration
Because the Marvell Dean 88SS1074 system level configuration does not use the inrush control circuitry, the design
connects OVSNS, OVSNS_M, and OVGATE to ground. The inrush circuitry can be used with the ACT88320QI105 by
connecting them per the datasheet guidelines.
Startup
CMI 105 Startup
VIN
LDO2
0.5ms
Buck1
0.5ms
Buck2
EXT_EN
1ms
Buck3
20ms
nRESET
I2C Address
The ACT88320 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.
GPIO1 (pin 13) - nRESET
GPIO1 is configured as an open drain nRESET. nRESET goes open drain 20ms after LDO2 goes into regulation.
GPIO2 (pin 14) – EXT_EN
GPIO2 is configured as an open drain EXT_EN. EXT_EN goes high immediately after Buck2 goes into regulation.
EXT_EN can be used to sequence on an external supply.
GPIO3 (pin 12) – nIRQ
GPIO3 is configured as an open drain nIRQ.
GPIO4 (pin 11) – Buck3_VID
GPIO4 is configured as a VID input for Buck3. When Pin 11 = 1, Buck3 = 1.5V. When Pin 11 = 0, Buck3 = 1.35V. Pin 11
is intended to be hard wired on the PCB to provide the correct startup for different DDR memory types. In applications
not requiring a fixed DDR voltage, pin 11 can be changed at any time to change the Buck3 output voltage
SLEEP MODE
I2C default settings are SLEEP_MODE=0, SLEEP_EN=0, and SLEEP=0. Refer to the SLEEP State paragraph for details
on how to enter SLEEP Mode.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
45
ACT88320QI-T
Rev 2.0, 20-Dec-2017
DPSLP MODE
I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. Refer to the DPSLP State paragraph for
details on how to enter DPSLP Mode.
VSYSMON
VSYSMON = 3.0V
Buck1 Voltage Setting
Buck1 reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps
LDO Voltage Setting
The LDO reference voltage is 0.8V. This sets the all
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
46
ACT88320QI-T
Rev 2.0, 20-Dec-2017
CMI 108: ACT88320QI108-T
CMI 108 is optimized for the Silicon Motion SM2258. It is designed to operate from a regulated 5V input supply. It is
identical to the ACT88320QI101 except that the default Buck3 SLEEP and DPSLP Mode voltage is 1.15V.
Voltage and Currents
Rail
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DPSLP Mode
Voltage (V)
DVS Voltage
(V)
Current
Limit (A)
Fsw (kHz)
Buck1
3.3
OFF
OFF
3.3
4.6
2250
Buck2
1.8
OFF
OFF
1.8
3
2250
Buck3
1.15
1.15
1.15
1.15
3
1125
LDO1
3.3
3.3
3.3
N/A
0.315
N/A
LDO2
1.8
1.8
1.8
N/A
0.315
N/A
LS1
OFF
OFF
OFF
N/A
0.6
N/A
Startup and Sequencing
Rail
Sequence
Order
Sequencing
Input Trigger
StartUp
Delay (us)
Soft-Start
(us)
Shutdown
Delay (us)
LDO1
1
VIN_UVLO
0
275
2000
LDO2
1
VIN_UVLO
0
215
1500
Buck3
2
LDO1
500
600
1000
Buck1
3
Buck3
500
600
500
Buck2
4
Buck1
500
600
0
LS1
N/A
N/A
0
N/A
0
Hardware Configuration
ACT88320QI108 does not have any special hardware setup considerations.
I2C Address
The ACT88320 7-bit I2C address is 0x25h. Use address 0x4Ah when writing and 0x4Bh when reading.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
47
ACT88320QI-T
Rev 2.0, 20-Dec-2017
Startup
CMI 108 Startup
VIN
LDO1
0.5ms
LDO2
Buck3
Buck1
0.5ms
0.5ms
nRESET
20ms
GPIO1 (pin 13) - nRESET
GPIO1 is configured as an open drain nRESET. nRESET goes open drain 20ms after Buck3 goes into regulation.
GPIO2 (pin 14) – EXT_EN
GPIO2 is configured as an open drain EXT_EN. EXT_EN goes high 2.5ms after Buck2 goes into regulation. EXT_EN
can be used to sequence an external supply.
GPIO3 (pin 12) – nIRQ
GPIO3 is configured as an open drain nIRQ.
GPIO4 (pin 11) – DVS
GPIO4 is configured as a DVS input. Pulling the DVS input high makes the ACT88320 operate in Active mode with
normal output voltages. In Active mode, the buck converters operate with voltages set by their I2C VSET0 registers.
Pulling the DVS input low makes the IC operate in DVS mode. In DVS mode, the buck converters operate with voltages
set by their VSET1 registers.
SLEEP MODE
I2C default settings are SLEEP_MODE=1, SLEEP_EN=0, and SLEEP=0. Refer to the SLEEP State paragraph for details
on how to enter SLEEP Mode.
DPSLP MODE
I2C default settings are DPSLP_MODE=1, DPSLP_EN=0, and DPSLP=0. Refer to the DPSLP State paragraph for
details on how to enter SLEEP Mode.
VSYSMON
VSYSMON = 3.0V
Buck1 Voltage Setting
Buck 1 reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
LDO Voltage Setting
The LDO reference voltage is 0.8V. This sets the allowable voltage range between 0.8V and 3.998V in 12.5mV steps.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
48
ACT88320QI-T
Rev 2.0, 20-Dec-2017
PACKAGE OUTLINE AND DIMENSIONS QFN44-32
Top View
Bottom View
DIMENSION IN
MILLIMETERS
SYMBOL
Side View
MIN
NOM
MAX
A
0.800
0.850
0.900
A1
---
---
0.050
A3
0.203 Ref.
D
3.950
4.000
4.050
E
3.950
4.000
4.050
D2
1.350
1.400
1.450
E2
1.150
1.200
1.250
b
0.150
0.200
0.250
e
Innovative PowerTM
0.400 BSC
L1
0.350
0.400
0.450
L2
1.400
1.450
1.500
aaa
0.10
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
49
ACT88320QI-T
Rev 2.0, 20-Dec-2017
ACT88320 LAND PATTERN
Pin 1
See Active Semi Application note AN-104, QFN PCB Layout Guidelines for more information on generating the
ACT88320 land pattern.
Innovative PowerTM
www.active-semi.com
ActiveSwitcherTM is a trademark of Active-Semi.
Copyright © 2017 Active-Semi, Inc
50