AD AD9051BRSRL-2V 10-bit, 60 msps a-d converter Datasheet

a
FEATURES
60 MSPS Sampling Rate
9.3 Effective Number of Bits at f IN = 10.3 MHz
250 mW Total Power at 60 MSPS
Selectable Input Bandwidth of 50 MHz or 130 MHz
On-Chip T/H and Voltage Reference
Single 5 V Supply Voltage
5 V or 3 V Logic I/O Compatible
Input Range and Output Coding Options Available
APPLICATIONS
Medical Imaging
Digital Communications
Professional Video
Instrumentation
Set-Top Box
GENERAL DESCRIPTION
The AD9051 is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only 5 V and an encode clock to
achieve 60 MSPS sample rates with 10-bit resolution.
10-Bit, 60 MSPS
A/D Converter
AD9051
FUNCTIONAL BLOCK DIAGRAM
BWSEL
5V
GND
IN
OUT
5V
AD9051
AINB
T/H
AIN
SUM
AMP
ENCODE
TIMING
REFERENCE
CIRCUITS
ADC
DAC
DECODE
LOGIC
10
ADC
A 2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on a state-of-the-art BiCMOS
process, the AD9051 is packaged in a space saving surface
mount package (SSOP) and is specified over the industrial temperature range (–40°C to +85°C).
The encode clock is TTL compatible and the digital outputs are
CMOS; both can operate with 5 V/3 V logic. The two-step
architecture used in the AD9051 is optimized to provide the
best dynamic performance available while maintaining low
power consumption.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113
© Analog Devices, Inc., 2010
AD9051BRS/
AD9051BRSZ
AD9051BRS-2V/
AD9051BRSZ-2V
8.76
9.3
9.0
8.8
8.59
9.1
8.8
8.6
53.5
56.5
56
54
52.5
56.5
55
53
54.5
55.5
56.5
55
53.5
56.5
55.5
54
REV. C
AD9051BRS/
AD9051BRSZ
REV. C
AD9051BRS-2V/
AD9051BRSZ-2V
AD9051
EXPLANATION OF TEST LEVELS
Test Level
ABSOLUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
I.
100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND)
Analog Input
Voltage Level
OR
(Out of Range)
Digital Output
MSB . . . LSB
3.126 (3.50)*
2.5
1.874 (1.50)*
Positive Full Scale + 1 LSB
Midscale
Negative Full Scale – 1 LSB
1
0
1
1111111111
0111111111
0000000000
*(BRS-2V Version)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9051 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. C
AD9051
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1, 6, 7, 12, 21, 23
2, 8, 11
3
4
5
9
10
13
GND
VD
VREFOUT
VREFIN
BWSEL
AINB
AIN
ENCODE
14
OR
15
16–19
20, 22
24–27
28
D9 (MSB)
D8–D5
VDD
D4–D1
D0 (LSB)
Ground
Analog 5 V Power Supply
Internal Bandgap Voltage Reference (Nominally 2.5 V)
Input to Reference Amplifier. Voltage reference for ADC is connected here.
Bandwidth Select. NC = 130 MHz nominal. +VD = 50 MHz nominal.
Complementary Analog Input Pin (Analog Input Bar)
Analog Input Pin
Encode Clock Input to ADC. Internal T/H is placed in hold mode (ADC is encoding)
on rising edge of encode signal.
Out of Range Signal. Logic “0” when analog input is in nominal range. Logic “1” when
analog input is out of nominal range.
Most Significant Bit of ADC Output
Digital Output Bits of ADC
Digital Output Power Supply (Only Used by Digital Outputs)
Digital Output Bits of ADC
Least Significant Bit of ADC Output
PIN CONFIGURATION
N
N+1
N+2
N+3
N+4
N+5
AIN
GND 1
28 D0 (LSB)
VD 2
27 D1
VREFOUT 3
26 D2
VREFIN 4
25 D3
BWSEL 5
24 D4
GND 6
GND 7
tA
ENCODE
tPD
DIGITAL
OUTPUTS
23 GND
AD9051
N–5
N–4
N–3
N–2
N–1
AIN 10
19 D5
VD 11
18 D6
GND 12
17 D7
ENCODE 13
16 D8
Figure 1. Timing Diagram
VD
VD
12k⍀
12k⍀
AINB (PIN 9)
15 D9 (MSB)
AIN (PIN 10)
12k⍀
INPUT
BUFFER
ENCODE
(PIN 13)
12k⍀
Analog Input
VDD (PINS 20, 22)
+3V TO +5V
Encode
VD
VREFOUT
(PIN 3)
D0–D9, OR
Output Stage
Figure 2. Equivalent Circuits
REV. C
N
22 VDD
TOP VIEW
VD 8 (Not to Scale) 21 GND
9
20 VDD
AINB
OR 14
t EH t EL
–5–
VREF
AD9051
0
255
250
–1
DISSIPATION – mW
245
BWSEL DISABLED
ADC GAIN – dB
240
235
230
225
–2
–3
BWSEL ENABLED
–4
220
–5
215
210
–6
1
5
15
20
25
30
35
40
45
CLOCK RATE – MSPS
50
55
60
1
TPC 1. Power Dissipation vs. Clock Rate
40
52
80
118
141
ANALOG INPUT FREQUENCY – MHz
201
TPC 4. ADC Gain vs. AIN Frequency
60
59
AIN = 10.3MHz
59
58.5
SNR @ 40MSPS
ENCODE = 40MSPS
58
58
SINAD @ 40MSPS
57.5
56
SNR – dB
SNR/SINAD – dB
57
55
SINAD @ 60MSPS
54
ENCODE = 60MSPS
57
56.5
SNR @ 60MSPS
53
56
52
55.5
51
50
0
10
20
30
40
50
60
FREQUENCY – MHz
70
80
55
–40
90
–20
TPC 2. SNR/SINAD vs. AIN Frequency
0
65
25
45
TEMPERATURE – ⴗC
85
TPC 5. SNR vs. Temperature
–50
60
–55
59
AIN = 10.3MHz
2ND @ 60MSPS
–60
58
3RD @ 40MSPS
57
–65
SNR – dB
dB
–70
2ND @ 40MSPS
–75
3RD @ 60MSPS
–80
56
55
54
–85
53
–90
52
–95
51
–100
50
0
10
20
30
40
50
60
FREQUENCY – MHz
70
80
90
5
TPC 3. Harmonics vs. AIN Frequency
10
20
30
40
ENCODE – MSPS
50
60
70
TPC 6. SNR vs. Clock Rate
–6–
REV. C
AD9051
0
0
–10
AIN = 10.3MHz
ENCODE = 40MSPS
SNR = 58.6dB
SINAD = 57.69dB
–20
–30
–30
–40
–40
dB
dB
–20
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
2.5
5.0
AIN = 15.2MHz
ENCODE = 60MSPS
SNR = 58.29dB
SINAD = 57.23dB
–10
7.5
10
12.5
FREQUENCY – MHz
15
17.5
20
0
TPC 7. FFT Plot 40 MSPS, 10.3 MHz
22.5
26.3
30
AIN = 21.7MHz
ENCODE = 60MSPS
SNR = 57.76dB
SINAD = 56.27dB
–10
–20
–30
–30
–40
–40
dB
dB
11.3
15.0
18.8
FREQUENCY – MHz
0
AIN = 15.2MHz
ENCODE = 40MSPS
SNR = 58.47dB
SINAD = 57.04dB
–20
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
2.5
5.0
7.5
10
12.5
FREQUENCY – MHz
15
17.5
20
0
3.8
7.5
11.3
15.0
18.8
FREQUENCY – MHz
22.5
26.3
30
TPC 11. FFT Plot 60 MSPS, 21.7 MHz
TPC 8. FFT Plot 40 MSPS, 15.2 MHz
0
0
AIN = 10.3MHz
ENCODE = 60MSPS
SNR = 58.15dB
SINAD = 57.25dB
–10
–20
AIN1 = 9.5MHz, –7dBFS
AIN2 = 9.9MHz, –7dBFS
IMD = –65dBc
ENCODE = 60MSPS
–10
–20
–30
–30
–40
–40
–50
dB
dB
7.5
TPC 10. FFT Plot 60 MSPS, 15.2 MHz
0
–10
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
3.8
7.5
11.3
15.0
18.8
FREQUENCY – MHz
22.5
26.3
30
0
3.8
7.5
11.3
15.0
18.8
FREQUENCY – MHz
22.5
TPC 12. Two-Tone IMD
TPC 9. FFT Plot 60 MSPS, 10.3 MHz
REV. C
3.8
–7–
26.3
30
AD9051
6.5
1.2
3V RISING
6
0.8
5.5
tPD – ns
% GAIN ERROR
1.0
0.6
5V FALLING
5
3V FALLING
0.4
5V RISING
4.5
0.2
0
0
10
20
30
40
ENCODE – MSPS
4
–40
60
50
TPC 13. Gain vs. Clock Rate
–20
0
25
45
TEMPERATURE – ⴗC
85
65
TPC 16. tPD vs. Temperature 3 V/5 V
2.51
16
2.50
14
2.49
12
REF VOLTAGE
OFFSET – mV
2.48
10
8
6
4
2.46
2.45
2.44
2
0
VOUT
2.47
2.43
2.42
0
10
20
30
40
ENCODE – MSPS
60
50
TPC 14. Offset vs. Clock Rate
0.1 0.25 0.4 0.55 0.7 0.85 1 1.15 1.3 1.45 1.6 1.75 1.9 2.0
SOURCE CURRENT – mA
TPC 17. Reference Load Regulation
80
60
58
70
56
60
SNR @ 40MSPS
% OCCURRANCE
54
SNR – dB
SNR @ 60MSPS
52
50
48
50
40
30
46
20
44
10
42
40
25
0
30
35
40
55
45
50
DUTY CYCLE – %
60
65
70
75
512
TPC 15. SNR vs. Duty Cycle
513
514
515
CODE
516
517
518
TPC 18. Midscale Histogram (Inputs Tied)
–8–
REV. C
AD9051
THEORY OF OPERATION
140⍀
Refer to the block diagram on the front page.
5V
The AD9051 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 10-bit accuracy at the digital outputs of the converter.
VIN
–0.625V
TO
+0.625V
AD9051
5V
1k⍀
1k⍀
AD820
0.1␮F
Figure 3. Single Supply, Single-Ended, DC-Coupled
AD9051
140⍀
+5V
5V
140⍀
0.1␮F
VIN
–0.625V
TO
+0.625V
USING THE AD9051
3 V System
10
AD9051
AD9631
–5V
The digital input and outputs of the AD9051 can be easily
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of
1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to 5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
9
0.1␮F
Figure 4. Single-Ended, Capacitively-Coupled AD9051
140⍀
+5V
5V
140⍀
VIN
–0.625V
TO
+0.625V
0.1␮F
AD9631
T1-1T
10
AD9051
50⍀
–5V
9
Figure 5. Differentially Driven AD9051 Using Transformer Coupling
The AD830 provides a unique method of providing dc level
shift for the analog input. Using the AD830 allows a great deal
of flexibility for adjusting offset and gain. Figure 6 shows the
AD830 configured to drive the AD9051. The offset is provided
by the internal biasing of the AD9051 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
The analog input of the AD9051 is a differential input buffer
(refer to AD9051 Equivalent Analog Input). The differential
inputs are internally biased at 2.5 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-endedly or differentially (for
best dynamic performance, impedances at AIN and AINB
should match).
VIN
–0.625V
TO
+0.625V
+15V
1
2
3 AD830
4
–5V
Figure 3 shows typical connections for the analog inputs when
using the AD9051 in a dc-coupled system with single-ended
signals. All components are powered from a single 5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9051.
+5V
7
10
AD9051
9
0.1␮F
Figure 6. Level-Shifting with the AD830
AC coupling of the analog inputs of the AD9051 is easily
accomplished. Figure 4 shows capacitive coupling of a singleended signal while Figure 5 shows transformer coupling
differentially into the AD9051.
REV. C
AD9631
0.1␮F
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in
five pipeline delays for the output data. Refer to the AD9051
Timing Diagram.
Analog Input
10
9
At the input, the analog signal is buffered by a high speed
differential buffer and applied to a track-and-hold (T/H) that
holds the analog value present when the unit is strobed with
an ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
The AD9051 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer
to AD9051 Output Stage) with isolated supply pins (Pins 20,
22 VDD). By varying the voltage on the VDD pins, the digital
output levels vary respectively. By connecting Pins 20 and 22 to
the 3 V logic supply, the AD9051 will supply 3 V output
levels. Care should be taken to filter and isolate the output
supply of the AD9051 as noise could be coupled into the
ADC, limiting performance.
5V
140⍀
–9–
AD9051
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9051, which cannot be obtained by using the internal reference. For these applications, an external 2.5 V reference can be
used to connect to Pin 4 of the AD9051. The VREFIN requires
2 µA of drive current.
Overdrive of the Analog Input
Special care was taken in the design of the analog input section
of the AD9051 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 1.875 V to
3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range comparators detect when the analog input signal is out of this range and
the input buffer is clamped. The digital outputs are locked at
their maximum or minimum value (i.e., all “0” or all “1”). This
precludes the digital outputs changing to an invalid value when
the analog input is out of range.
The input range can be adjusted by varying the reference
voltage applied to the AD9051. No appreciable degradation
in performance occurs when the reference is adjusted ± 5%.
The full-scale range of the ADC tracks reference voltage
changes linearly.
The input is protected to one volt outside the power supply
rails. For nominal power (5 V and ground), the analog input
will not be damaged with signals from +5.5 V to –0.5 V.
Timing
The performance of the AD9051 is very insensitive to the duty
cycle of the clock. Pulsewidth variations of as much as ± 15% for
encode rates of 40 MSPS and ± 10% for encode rates of 60 MSPS
will cause no degradation in performance. (See Figure 17, SNR vs.
Duty Cycle.)
The AD9051 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (refer to Figure 1,
Timing Diagram). The length of the output data lines and
loads placed on them should be minimized to reduce transients within the AD9051; these transients can detract from
the converter’s dynamic performance.
Power Dissipation
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 60 MSPS,
analog input is –FS.
As shown in Figure 3, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. The loading
determines the power dissipated in the output stages.
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.
The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to Using the AD9051, 3 V
System). The lower output swings minimize power consumption
as follows: (1/2 CLOAD × VDD2 × Update Rate).
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9051 (Pin 3, VREFOUT). In normal operation the internal
reference is used by strapping together Pins 3 and 4 of the
AD9051. The internal reference has 500 µA of extra drive current that can be used for other circuits.
–10–
REV. C
AD9051
OUTLINE DIMENSIONS
10.50
10.20
9.90
15
28
5.60
5.30
5.00
1
8.20
7.80
7.40
14
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-150-AH
0.95
0.75
0.55
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Figure 7.28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9051BRS
AD9051BRS-2V
AD9051BRSRL
AD9051BRSZ
AD9051BRSZRL
AD9051BRSRL-2V
AD9051BRSZ-2V
AD9051BRSZRL-2V
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
Z = RoHS Compliant Part.
REVISION HISTORY
11/10—Rev. B to Rev. C
Changes to Specifications Section................................................... 2
Deleted Evaluation Board Section ................................................10
Updated Outline Dimensions ........................................................11
Changes to Ordering Guide ...........................................................11
7/01—Rev. A to Rev. B
Edits to ABSOLUTE MAXIMUM RATINGS ............................... 4
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00558-0-11/10(C)
REV. C
–11–
Package Option
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28