CMEDIA CM6533DH Usb 2.0 full-speed compliant Datasheet

CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
DESCRIPTION
FEATURES
The CM6533/CM6533N/CM6533X1/CM6533DH is a
USB 2.0 audio chip built-in 8051 for flexible
applications. With integrated Tri-Colors PWM LED
driver and two (2)-channel ADC/DAC and S/PDIF
interface that makes it suitable for headset,
docking, speaker and microphone applications.
The internal 8051 can also be developed to a lot of
different applications, such as Microsoft™ Lync /
Skype/VoIP device, Android Phone or Tablet/Slate
docking device. The CM6533 /CM6533N /CM6533X1
/CM6533DH is compatible with USB Audio Class 1.0
and USB 2.0 Full-Speed, thus it can plug & play
without any additional software installation on
major operating systems. The internal DAC and
ADC support from 8 ~ 96 KHz sampling rate and
16/24 bits resolution.
 USB 2.0 Full-Speed compliant
The CM6533/CM6533N/CM6533X1/CM6533DH
integrates equalizer on both playback and
recording paths to compensate the frequency
response of microphone and headphone.
 Embedded 1T 8051 with 32K Byte SRAM and 256K Byte
flash(Including 32KB F/W programming size)
The CM6533/CM6533N/CM6533X1/CM6533DH also
integrates 256K Byte flash (Including 32KB F/W
programming size) and crystal but requires few
passive components to make a finish product.
Thus, it can save the total BOM cost and PCB area
can be smaller.
 Master/Slave H/W I2C/SPI/UART control interface for
external audio devices or FLASH access
 USB Audio Class 1.0 compliant
 USB Human Interface Device (HID) Class 1.11 compliant
 Two (2)-channel DAC for audio output interface
 Two (2)-channel ADC for audio input interface
 Supports Digital Microphone interface
 Built-in S/PDIF transmitter
 Built-in Equalizer on both playback and recording paths
 Built-in AGC (Auto Gain Control) on recording path
 Supports dual tone generator
 Supports USB suspend/resume/reset functions
 Supports control, interrupt, bulk, and isochronous data
transfers
 Supports OMTP and CTIA auto switch on a 4-pole jack
 Integrated Tri-Colors PWM LED driver
 Supports embedded oscillator without external crystal
 Built-in 30mW @ R=32 headphone amplifier
 On chip watchdog timer
BLOCK DIAGRAM
Analog Gain
-18 ~ 45dB
(1dB/step)
Digital Gain
-16 ~ 12dB
(1dB/step)
AGC
USB
Interface
ADC
Mux
Microphone In
5-Band EQ
Analog Gain
-30 ~ 33dB
(1dB/step)
Control Bus
32KB SRAM
+12dB
Internal Clock
ROM(4KB)
MCU with
256KB Flash
Digital Gain
-62 ~ 0dB
(1dB/step)
DAC
Analog Gain
-15 ~ 32dB
(1dB/step)
Analog Gain
-44 ~ 0dB (1dB/step)
Speaker/
Heaphone
5-Band EQ
SPDIF Out
GPIO x 12
PWM LED X 3
Uart, I2C, SPI
Page 1 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
Release Notes
Revision
1.0
1.1
Date
2014/07/08
2014/08/05
1.2
2014/09/18
1.3
2014/09/19
1.4
2015/3/30
1.5
2015/08/07
1.6
2015/10/29
Page 2 / 60
Rev.1.6
Description
First release.
Modify F/W volume setting table(CH2.6).
1. Modify Pin descriptions.
2. Modify Pin out diagram.
1. Modify MIC_SWOUT to AO pin.
2. Modify power consumption for 12MHz MCU Clock.
3. Modify Reset diagram of CH6.13.
4. Separate CM6533/CM6533X1/CM6533DH Pin out diagram.
5. Modify flash description: 256K Byte flash(Including 32KB F/W programming
size).
1. Remove Microphone input impedance chart.
2. Add Xear and Dolby software function descriptions.(CH7,CH8)
3. Modify Operating ambient temperature to -15~70 oC.
4. Modify CH5.1 CH5.2 USB Topology chart.
5. Modify Block Diagram (Page1).
6. Add Cap-less cross talk performance.
7. Add CM6533N QFN Package.
1. Modify CH6.7 Digital microphone descriptions.
1. Modify I2C Using Example
2. Modify SPI Using Example
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
TABLE OF CONTENTS
Release Notes .................................................................................................. 2
TABLE OF CONTENTS........................................................................................... 3
1 Description and Overview ............................................................................... 6
2 Features.................................................................................................... 6
2.1
USB Compliance ................................................................................ 6
2.2
Integrated 8051 Microprocessor ............................................................. 6
2.3
Control Interface .............................................................................. 6
2.4
General .......................................................................................... 6
2.5
Audio I/O........................................................................................ 7
3
4
5
6
2.6
General Firmware Volume Setting Value ................................................... 8
2.7
CM6533/CM6533N/CM6533X1/CM6533DH Compared Table .............................. 8
Applications ............................................................................................... 9
Pin Assignment ...........................................................................................10
4.1
CM6533 Pin-out Diagram (LQFP48) .........................................................10
4.2
CM6533N Pin-out Diagram (QFN48) ........................................................11
4.3
CM6533X1 Pin-out Diagram (LQFP48) ......................................................12
4.4
CM6533DH Pin-out Diagram (LQFP48) ......................................................13
4.5
Pin Description ................................................................................14
4.6
Pin Circuit Diagrams ..........................................................................17
USB Audio Topology ......................................................................................18
5.1
CM6533N/CM6533 Headset Topology .......................................................18
5.2
CM6533X1/CM6533DH Headset Topology ..................................................19
Function Description ....................................................................................20
6.1
Playback Equalizer ...........................................................................20
6.1.1
5-band equalizer ........................................................................20
6.1.2
Four (4) Preset EQ Mode................................................................22
6.2
Recording Equalizer ..........................................................................23
6.3
Recording AGC.................................................................................23
6.4
HID Function ...................................................................................25
6.4.1
HID Interrupt in ..........................................................................25
6.4.2
HID get_input_report ...................................................................26
6.4.3
HID set_output_report ..................................................................27
6.5
Vendor Command Definition ................................................................28
6.5.1
Vendor Command Read .................................................................28
6.5.2
Vendor Command Write ................................................................28
6.5.3
USB Vendor Requests....................................................................28
6.5.4
Simple Process of Firmware Update ..................................................29
Page 3 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.6
SPDIF Control Description ...................................................................30
6.6.1
SPDIF Frame Description ...............................................................30
6.6.2
SPDIF Out Channel Status ..............................................................31
6.7
Digital Microphone ............................................................................32
6.8
I2C Interface...................................................................................33
6.8.1
I2C Master Mode .........................................................................33
6.8.2
I2C-Master Read with clk_sync mode .................................................34
6.8.3
I2C Master Device Address and Control Register ....................................34
6.8.4
I2C Master Memory Address Pointer (MAP) Register ................................34
6.8.5
I2C Master Memory Address Pointer (MAP2) Register ...............................34
6.8.6
I2C Master Data Register ...............................................................35
6.8.7
I2C Master Control and Status Register 0 ............................................35
6.8.8
6.8.9
6.8.10
6.8.11
6.8.12
6.8.13
6.8.14
6.8.15
6.8.16
6.9
SPI
I2C Master Control and Status Register 1 ............................................35
I2C Master Download Control and Status Register ..................................36
I2C Master Clock Period Setting Register ............................................37
I2C Slave Mode ...........................................................................38
I2C Slave Data Register .................................................................38
I2C Slave Status Register ...............................................................38
I2C Slave Memory Address Pointer(MAP) Register...................................39
I2C Slave Status Register ...............................................................39
I2C Using Example .......................................................................40
Interface ...................................................................................41
6.9.1
SPI Control Register 0 ...................................................................41
6.9.2
SPI Control Register 1 ...................................................................41
6.9.3
SPI Interrupt .............................................................................42
6.9.4
SPI Control Register 3 ...................................................................42
6.9.5
SPI Using Example .......................................................................43
6.10
GPIO ............................................................................................44
6.10.1 GPO Data Register .......................................................................44
6.10.2 GPI Data Register ........................................................................44
6.10.3 GPIO Direction Control Register .......................................................44
6.10.4 GPIO Interrupt Enable Mask Register .................................................44
7
6.10.5 GPIO Debouncing Register .............................................................44
6.10.6 GPI Remote Choose .....................................................................45
6.10.7 GPIO Pull-up/Down .....................................................................45
6.11
Arbitrary Sine-tone Generator ..............................................................47
6.12
Tri-Colored LED Control Setting ............................................................48
6.13
Reset ............................................................................................49
6.13.1 Watchdog Reset Timer ..................................................................49
CM6533X1 Xear™ Sound Processing....................................................................50
Page 4 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
7.1
8
9
Xear™ Surround Headphone .................................................................50
7.2
Xear™ Software 10 Band Equalizer .........................................................50
7.3
Xear™ Audio Brilliant .........................................................................50
7.4
Xear™ Dynamic Bass ..........................................................................50
7.5
Xear™ Voice Clarity ...........................................................................50
7.6
Xear™ Smart Volume .........................................................................50
7.7
Xear™ Surround Max ..........................................................................50
7.8
Xear™ Magic Voice ............................................................................50
7.9
Xear™ Environmental Noise Cancellation .................................................51
CM6533DH Dolby® and Xear™ Sound Processing ....................................................51
8.1
Dolby® Headphone v2 ........................................................................51
8.2
Dolby® Pro Logic IIx ..........................................................................51
8.3
Xear™ Environment Effect ...................................................................51
8.4
Xear™ Software 10 Band Equalizer .........................................................51
8.5
Xear™ Magic Voice ............................................................................51
Electrical Characteristics ...............................................................................52
9.1
Absolute Maximum Ratings ..................................................................52
9.2
Recommended Operation Conditions ......................................................52
9.3
Power Consumption ..........................................................................52
9.4
DC Characteristics ............................................................................52
9.5
Analog Audio ...................................................................................53
9.6
USB Transceiver ...............................................................................53
9.7
Microphone Bias ...............................................................................53
10
Audio Performance .................................................................................54
10.1
DAC Audio Quality ............................................................................54
10.2
ADC Audio Quality ............................................................................55
10.3
Analog Monitoring / Sidetone (A-A ) Path Audio Quality ................................56
11
Package Dimension .................................................................................57
11.1
Package Dimension of CM6533/6533X1/6533DH .........................................58
11.2
Package Dimension of CM6533N ............................................................59
Page 5 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
1 Description and Overview
The CM6533/CM6533N/CM6533X1/CM6533DH is a USB 2.0 audio chip built-in 8051 for flexible applications. With
integrated Tri-Colors PWM LED driver and two (2)-channel ADC/DAC and S/PDIF interface makes it suitable for
headset, docking, speaker and microphone applications. The internal 8051 can also be developed to a lot of different
applications, such as Microsoft™ Lync/Skype/VoIP device, Android Phone or Tablet/Slate docking device. The
CM6533/CM6533N/CM6533X1/CM6533DH is compatible with USB Audio Class 1.0 and USB 2.0 Full-Speed, thus it can
plug & play without any additional software installation on major operating systems. The internal DAC and ADC
support from 8 ~ 96 KHz sampling rate and 16/24 bits resolution. The hardware of CM6533, CM6533N, CM6533X1 and
CM6533DH are all the same and they only differ in firmware and software.
The CM6533/CM6533N/CM6533X1/CM6533DH integrates equalizer on both playback and recording paths to
compensate the frequency response of microphone and headphone.
The CM6533/CM6533N/CM6533X1/CM6533DH also integrates 256K Byte flash(Including 32KB F/W programming size)
and crystal but requires few passive components to make a finish product. Thus, it can save the total BOM cost and
PCB area can be smaller.
2 Features
2.1 USB Compliance
 USB 2.0 Full-Speed compliant
 USB Audio Class 1.0 compliant
 USB Human Interface Device (HID) Class 1.1 compliant
 Supports USB suspend/resume/reset functions
 Supports control, interrupt, bulk, and isochronous data transfers and overview
2.2 Integrated 8051 Microprocessor
 Embedded 8051 micro-processor to handle the command/protocol transactions
 Embedded 256K Byte SPI Flash(Including 32KB F/W programming size)
 32K Byte RAM for firmware extension and plug-in
 HID interrupts/buttons/functions can be implemented via firmware codes
 Provides maximum hardware configured flexibility with firmware code upgrade
 VID/PID/Product String can program by firmware
2.3 Control Interface
 Master/Slave I2C control interface, bus speed supports 100 and 400kbit/s
 One 4-wire SPI mater/slave interface, bus speed supports from 150k to 12Mbit/s
 12 GPIO pins and firmware programmable
 JTAG debug interface
 GPIOs are configured as HID key and LED indicators
 Tri-Colors PWM LED Driver
2.4 General
 Crystal-less (embedded crystal function)
Page 6 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
 Single 5V power supply (embedded 5V to 1.8V regulator for digital core, 5V to 3.3V regulator for digital IO, 5V to
3.6V regulator for analog codec)
 3.3V digital I/O pads with 5V tolerance
 Industrial standard LQFP-48 package (7x7mm)
2.5 Audio I/O
 Playback Stream:
 Speaker/Headphone

Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/88.2K/96KHz

Supports Bit Length: 16/24bits

Speaker Gain Range (Analog) is -44 ~ 0dB, 1dB/step

DAC Gain Range (Digital) is -62 ~ 0dB, 1dB/step
 S/PDIF transmitter

Sample Rates: 44.1K/48K/88.2K/96KHz

Supports Bit Length: 16/24 bits
 Recording Stream:
 Microphone

Sample Rates: 8K/11.025K/16K/22.05K/32K/44.1K/48K/96KHz

Supports Bit Length: 16/24 bits

Microphone gain range (Analog) is -18 ~ 45dB, 1dB/step

ADC gain range (Digital) is -16 ~ 12dB, 1dB/step
 Stereo Mixer

Mix stereo playback stream and stereo microphone

Stereo Mixer gain range is -30 ~ 33dB, 1dB/step
 A-A path Stream:
 Microphone to playback A-A path

Mix mono microphone input to stereo playback both L/R channel

The Microphone A-A path gain range is -15 ~ 32dB, 1dB/step
**Note 1: A-A path means Analog to Analog Mixer path
**Note 2:
CM6533/CM6533N/CM6533X1/CM6533DH is a USB 2.0 Full Speed audio device. Since bandwidth limitation,
CM6533/CM6533N/CM6533X1/CM6533DH cannot support 96KHz/24bits for playback and capture streams
simultaneously. The possible combinations are shown below:
Playback
Stereo, 96KHz/24bits
Audio Format
Page 7 / 60
Rev.1.6
Stereo, 48kHz/24bits or below
Mono, 96KHz/24bits or below
Capture
Stereo, 48kHz/24bits or below
Mono, 96KHz/24bits or below
96KHz/24bits
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
2.6 General Firmware Volume Setting Value
The CM6533/CM6533N/CM6533X1/CM6533DH is a MCU base USB Audio Device; the default topology is different from
its hardware capability.
Please refer to chapter 5.1 and 5.2 for the CM6533/CM6533N/CM6533X1/CM6533DH default topology while below the
gain volume range.
Device
Speaker
Microphone in recording Volume
Microphone A-A path (playback)
Minimum
-45dB(Mute)
0dB
-15dB(Mute)
Maximum
0dB
+30dB
+22dB
Default
-10dB
+20dB
0dB
dB/Step
1dB
1dB
1dB
2.7 CM6533/CM6533N/CM6533X1/CM6533DH Compared Table
The pin out of CM6533, CM6533N, CM6533X1 and CM6533DH are all the same and they only differ in firmware,
software and package.
Package
Firmware
Jack Detection
Xear™ Surround HP
Dolby® Headphone
Software
CM6533N
QFN48
Optional Jack
Detection
●
---
CM6533
LQFP48
Optional Jack
Detection
●
---
CM6533X1
LQFP48
CM6533DH
LQFP48
--
--
-●
--●
For the detailed firmware and software information, please refer to its corresponding spec.
 Software Functions:
 CM6533X1 Xear™ Sound Processing

Xear™ Surround Headphone

Xear™ Software 10 Band Equalizer

Xear™ Audio Brilliant

Xear™ Dynamic Bass

Xear™ Voice Clarity

Xear™ Smart Volume

Xear™ Surround Max

Xear™ Magic Voice

Xear™ Environmental Noise Cancellation
 CM6533DH Dolby® and Xear™ Sound Processing

Dolby® Headphone v2

Dolby Pro Logic® IIx

Xear™ Environment Effect

Xear™ Software 10 Band Equalizer

Xear™ Magic Voice
Page 8 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
3 Applications
 USB Headset/Gaming Headset
 Microsoft™ Lync/Skype VoIP Headset
 Notebook/Netbook Docking
 Android Phone/Slate Docking
 USB Speaker
 USB Microphone
Page 9 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4 Pin Assignment
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.1 CM6533 Pin-out Diagram (LQFP48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533
43
18
44
17
45
16
46
15
47
14
48
13
10
11
12
1 2 3 4 5 6 7 8 9
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Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.2 CM6533N Pin-out Diagram (QFN48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533N
43
18
44
17
45
16
46
15
47
14
48
13
10
11
12
1 2 3 4 5 6 7 8 9
Page 11 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.3 CM6533X1 Pin-out Diagram (LQFP48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533X1
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
Page 12 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
SPDIF_O
GPIO_8
GPIO_9
GPIO_10
GPIO_11
AV36_DAR
LOUTR
AGND_DAR
LOCOM
AGND_DAL
LOUTL
AV36_DAL
4.4 CM6533DH Pin-out Diagram (LQFP48)
AV42_DA
AVDD50
AVDD36
AGND
MBIASR_SLEEVE
MICR_RING2
MIC_SWOUT
VAG
MBIASL
MICL
VOLADJ
AGND
GPIO_0
PDSW
TEST
I2C_SCLK
I2C_SDAT
VSS
USB_DP
USB_DM
DVDD33
DVDD18
DVDD50
VSS
GPIO_5
GPIO_4
GPIO_3
GPIO_7
GPIO_6
VSS
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_SCK
GPIO_2
GPIO_1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
22
39
21
40
41
20
42
19
CM6533DH
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
Page 13 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4.5 Pin Description
Pin #
Symbol
I/O
7
8
USB_DP
USB_DM
AIO
AIO
9
10
11
22
23
24
25
31
6
12
42
13
21
27
29
DVDD33
DVDD18
DVDD50
AVDD36
AVDD50
AV42_DA
AV36_DAL
AV36_DAR
VSS
VSS
VSS
AGND
AGND
AGND_DAL
AGND_DAR
AO
AO
PWR
AO
PWR
AO
AO
AO
GND
GND
GND
GND
GND
GND
GND
18
MIC_SWOUT
AO
15
19
16
20
17
26
MICL
MICR_RING2
MBIASL
MBIASR_SLEEVE
VAG
LOUTL
AI
AI
AO
AO
AO
AO
28
LOCOM
AO
30
LOUTR
AO
14
VOLADJ
AI
36
SPDIF_O
DO
1
GPIO_0
DIO
48
GPIO_1
DIO
47
GPIO_2
DIO
Page 14 / 60
Rev.1.6
Description
USB2.0 BUS Interface
USB 2.0 data positive (USB D+ signal).
USB 2.0 data negative (USB D- signal).
Power/Ground
Regulator 3.3V output, drive capacity 10mA.
Regulator 1.8V output, no current drive capacity.
5V digital power for 5/3.3/1.8V regulator.
Analog 3.6V regulator for ADC, no current drive capacity.
5V analog power for 4.2/3.6V regulator.
Analog 4.2V regulator for Analog 3.6V regulator, no current drive capacity.
Analog 3.6V regulator for DAC left channel, no current drive capacity.
Analog 3.6V regulator for DAC right channel, no current drive capacity.
Digital Ground.
Digital Ground.
Digital Ground.
Analog Ground.
Analog Ground.
Analog Ground.
Analog Ground.
Audio Interface
Combo jack detect and auto switch, detect combo jack type and switch to
MICR_RING2 or MBIASR_SLEEVE.
Microphone in left channel.
Microphone in right channel or combo jack Ring2 pin input.
Microphone bias (2.75V) for Left channel.
Microphone bias (2.75V) for Right channel or combo jack Sleeve pin input.
Voltage reference cap filter.
Line out left channel.
Line out common reference for cap-less connection.
Suggested connections:
Cap-less: 10uF
None use: floating
Line out right channel.
Analog control voltage input for playback volume control.
SAR ADC digital input range:
SARAD<5:0>
000000:Maxium------27.3mV
111111:Minium-------1.75V
(27.3mV/1step)
S/PDIF I/O
S/PDIF transmitter
SPDIF_O is an output buffer with 8mA Tri-state.
GPIO
General purpose input/output (default Volume Up button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TCK)
General purpose input/output (default Volume Down button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TMS)
General purpose input/output (default Play Mute button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TDI)
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
39
GPIO_3
DIO
38
GPIO_4
DIO
37
GPIO_5
DIO
41
GPIO_6
DIO
40
GPIO_7
DIO
35
GPIO_8
DIO
34
GPIO_9
DIO
33
GPIO_10
DIO
32
GPIO_11
DIO
43
SPI_MISO
DIO
44
SPI_MOSI
DIO
45
SPI_CS0
DIO
46
SPI_SCK
DIO
5
I2C_SDAT
DIO
Page 15 / 60
Rev.1.6
General purpose input/output (default Rec Mute button).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 2 in 1 I/O interface. GPIO / PWM select by firmware.
General purpose input/output (default PWM LED Blue).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 2 in 1 I/O interface. GPIO / PWM select by firmware.
General purpose input/output (default PWM LED Green).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 2 in 1 I/O interface. GPIO / PWM select by firmware.
General purpose input/output (default PWM LED Red).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input. (JTAG-TRST)
General purpose input/output
There are 4 kinds of preset EQ, GPIO7
(JTAG-TDO).
and 8 are used to determine in which
3.3V I/O, 5V tolerance,
mode. The combinations are shown
bidirectional buffer with 8mA
below.
driving current, Default EQ disable GPIO[8:7]=0,0: Normal mode
weak pull-up for input.
GPIO[8:7]=0,1: Gaming mode
GPIO[8:7]=1,0: Communication mode
General purpose input/output
GPIO[8:7]=1,1: Movie mode
3.3V I/O, 5V tolerance,
EQ function can enable via configuration
bidirectional buffer with 8mA
driving current, Default EQ disable tool or firmware.
weak pull-up for input.
General purpose input/output (default Rec Clip Indicator).
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 3 in 1 I/O interface. GPIO / Digital MIC Clock (DMIC_CLK) /
MCU_TRX select by firmware.
GPIO (Default MIC Jack Detect):
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
Programmable 3 in 1 I/O interface. GPIO / Digital MIC Data (DMIC_DAT) /
UART RX input(MCU_RXD) select by firmware.
GPIO (Default Headphone Jack Detect):
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
4-Wire SPI Serial Bus
SPI data master in/slave out,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-down for input.
SPI data master out/slave in,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-down for input.
SPI chip select,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-up for input.
SPI clock,
3.3V I/O, 5V tolerance, bidirectional buffer with 8mA driving current,
Default weak pull-down for input.
2-Wire Serial Bus (I2C)
2-wire serial data,
3.3V I/O, 5V tolerant, bidirectional buffer with 8mA driving current, Default
weak pull-up for input.
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4
I2C_SCLK
DIO
2
PDSW
DO
3
TEST
DI
2-wire serial clock,
3.3V I/O, 5V tolerant, bidirectional buffer with 8mA driving current, Default
weak pull-up for input.
Miscellaneous
Power Down Switch is an output buffer with 8mA Tri-state output.
Normal mode: 0
Suspend mode: 1
The TEST pin is used for IC test, another one is in the situation when F/W
was crash or USB was not recognized, Set TEST pin to 3.3V before USB
connect can force MCU into boot loader mode and able to update F/W via
configuration tool, Default weak pull-down for input.
1: Boot loader mode
0 or floating: Normal operation
**Note: GPIOs, I2C, SPI, SPDIF, MIC_SWOUT, MICL, MICR_RING2, MBIASL, MBIASR_SLEEVE, VAG, LOUTL, LOCOM, LOUTR,
VOLADJ, PDSW, TEST pins can be left floating if not in use.
Page 16 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
4.6 Pin Circuit Diagrams
VAG, MIC_BAIS
VAG
AGND
VSS
Analog input pins LINE, MIC
ADC
AGND
Output pins LOUTL, LOUTR
LOUT_n
AGND
Output pins LOUTL, LOUTR
VDD
VREG
VSS
Page 17 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
5 USB Audio Topology
5.1 CM6533N/CM6533 Headset Topology
USB
Streaming
Interface #1
01
Mute Control
Volume Control
-45dB(Mute) ~ 0dB
Mixer
08
05
IT
03

OT
Speaker
2CH Out
07
02
Microphone
2CH In
Mute Control
Volume Control
0dB ~ 30dB
Mute Control
Volume Control
-15dB(Mute) ~ 22dB
04
06
IT
OT
USB Streaming
Interface #2
USB Interfaces List
Interface Description
Endpoint
Interface 0
Audio Control Interface
Interface 1
Audio Stream Interface for Playback
0x01
Interface 2
Audio Stream Interface for Record
0x82
Interface 3
HID Interface
0x87(Interrupt In 16 bytes)
Audio Stream Interfaces’ Alternate Setting List
Interface 1
(Speaker)
Interface 2
(MIC In)
Page 18 / 60
Rev.1.6
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
5.2 CM6533X1/CM6533DH Headset Topology
USB
Streaming
Interface #1
01
Mute Control
Volume Control
-45dB(Mute) ~ 0dB
Mixer
08
05
IT
03

OT
Speaker
2CH Out
07
02
Microphone
2CH In
Mute Control
Volume Control
0dB ~ 30dB
Mute Control
Volume Control
-15dB(Mute) ~ 22dB
04
06
IT
OT
USB Streaming
Interface #2
USB Interfaces List
Interface Description
Endpoint
Interface 0
Audio Control Interface
Interface 1
Audio Stream Interface for Playback
0x01
Interface 2
Audio Stream Interface for Record
0x82
Interface 3
HID Interface
0x87 (Interrupt In 16 bytes)
Audio Stream Interfaces’ Alternate Setting List
Interface 1
(Speaker)
Interface 2
(MIC In)
Page 19 / 60
Rev.1.6
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
Alt 5
2CH, 16Bits AC3
44.1K,48K
Alt 1
2CH, 16Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 2
2CH, 24Bits PCM
8K,11.025K,16K,22.05K,32K,44.1K,48K
Alt 3
2CH, 16Bits PCM
88.2K,96K
Alt 4
2CH, 24Bits PCM
88.2K,96K
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6 Function Description
6.1 Playback Equalizer
6.1.1 5-band equalizer
CM6533/CM6533N/CM6533X1/CM6533DH has integrated five (5)-band hardware digital equalizer (EQ) engine inside
the chips to fulfill various application usages. It provides up to four (4)-preset modes on client’s product design for
different user scenarios including default/music, movies, gaming and communication modes. Clients could also
change the gain parameters for each of the preset application EQ mode via embedded FLASH coding. Also, the EQ
engine could also be utilized for compensating and fine-tuning the headphone driver for Sound Pressure Level (SPL)
performance to a specific preference. In this case, clients could fully customize all EQ coefficients such as center
frequency, gain values, and bandwidth to one optimized frequency response curve and setting in terms of the
headphone driver and housing’s acoustics characteristics, also via embedded FLASH programming.
Digital Equalizer
Digital
PCM
Attenuation
PCM
(5-Band Fc, Gain,
Digital-Analog
PCM
Bandwidth, OPA Gain)
-Converter
Analog
Analog
Analog
Gain
Gain
The EQ engine contains five (5) frequency bands (Fc) of digital filters to conduct transfer functions of the frequency
response over the audio band. It allows maximum +-12dB digital gain (Gain) for each band with 0.5dB adjustment per
step. Each filter will have its bandwidth (BW) factor between 0 and 1.0.
Fc: Center Frequency, F1~F5, 20<Fc<20K (Hz)
Gain: Digital Frequency Gain, -12dB <= Gain <=+12dB, 0.5dB/step
BW: Filter Bandwidth Factor, 0<BW<1
OPA Gain: Analog Gain Compensation setting for each equalizer mode
The EQ engine already provides four (4)-preset modes/settings based on the same preset F1~F5 center frequencies
and OPA gain:
F1 (Bass)= 100Hz
F2 = 350Hz
F3 = 1KHz
F4 = 3.5KHz
F5 (Treble) = 13KHz
Page 20 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
With the four (4)-preset EQ modes, clients could use embedded FLASH parameters to change the gain values for each
band of the center frequency and hence customize the four (4)-preset EQ curves based on the preset center
frequencies and bandwidth.
Alternatively, clients could also skip the four (4) preset modes and create a customized
EQ curve by changing the center frequencies, gain values and even the bandwidth factors in embedded FLASH
parameters to make the headphone sound better or meet some frequency requirements. However, in this case, the
product will always use one optimized EQ setting and could not allow users to dynamically change into different
preset modes. Clients could also consider reporting Treble/Bass feature unit by embedded FLASH to Windows UAA
driver to allow end-users to adjust Bass (F1) and Treble (F5) by themselves. Therefore there are three
usage/application scenarios as shown by the summary table below:
3 EQ Usage/Application Scenarios
Configurable
Configurable
Center Frequency /
Bandwidth Factor
Fixed
Configurable
Number of
Modes
4
1
Configurable
Configurable
1
No
Scenario
Gain Value
1
2
4 Switchable Presets
Full-Customized EQ
Treble/Bass Feature
Unit
3
User Control Type
Hardware
N.A.
Software
**Note: Hardware user control type means end-users could select which EQ mode they are going to use by a hardware
switch/button on the product; software control means they could control the treble/bass gain values by GUI in
Windows OS sound device advanced settings.
Page 21 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.1.2 Four (4) Preset EQ Mode
As mentioned above, EQ engine already provides four (4)-preset EQ modes for different user scenarios/applications.
The EQ function default was disable but it can enable via configuration tool or firmware, End users could use the
hardware switch on the product (determined by 2 EQ configuration input pins) to dynamically change to different EQ
modes. The following shows the frequency response of each mode.
Mode
Default
Gaming
Communication
Movie
GPIO8
0
0
1
1
GPIO7
0
1
0
1
Color
-------------------------------------------------------------
Audio Precision
04/20/11 15:35:35
+1
-0
Gaming
Communication
-1
-2
Movie
-3
d
B
r
-4
Default
-5
A
-6
-7
-8
-9
-10
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
2
3
4
1
1
1
1
Red
Magenta
Cyan
Blue
Solid
Solid
Solid
Solid
2
2
2
2
Anlr.Ampl
Anlr.Ampl
Anlr.Ampl
Anlr.Ampl
Left
Left
Left
Left
00
11
10
DA-EQ-SPDIF_In_DA_Out.at27
Page 22 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.2 Recording Equalizer
CM6533/CM6533N/CM6533X1/CM6533DH also provide five (5)-band equalizer for the input. It can be used to
compensate the frequency response of microphone unit. Clients could fully customize all EQ coefficients (center
frequency, gain values, and bandwidth) through embedded FLASH.
6.3 Recording AGC
Automatic Gain Control (AGC) is an automatically controlled method to adjust with respect to the intensity of
signal; AGC closes the return circuit which is by the negative response system too.
AGC is by way of compressing volume, will increase Gain first when AGC is started to set up the upper and lower
limits of the signal. Then, it will compress the dynamic range of sound. It usually uses the occasion of AGC, should
there be recording and producing and speaking sound, or volume is being changed under little environment. If the
lasting low voice of volume, AGC will enlarge volume then volume is sustained loudly while AGC will reduce volume.
Features
Programmable AGC Parameters
Selectable Gain from –12 dB to 45 dB in 1-dB Steps
Selectable Attack, Release and Hold Times
AGC Enable/Disable Function
Limiter Enable/Disable Function
Pre-Detect Limiter Level Function
Two-Channel AGC Independent
Under input source types, to set AGC gain max/min limit
Dig mic
+20 ~ -16DB
Analog mic
+30 ~ 0DB
0xf9= 0x24 (max)+fix gain(9db) =0x2d
0xfA= 0x00(min)
0xf9=0x0F+fix gain(9db)
0xfA=0x2D
inv ->
inv ->
0x39(max)
0x12(min)
AGC variable description
Fixed Gain:
The normal gain of the device when the AGC is inactive
Limiter Level: The value that sets the maximum allowed output amplitude
Attack Time:
The minimum time between two gain decrements
Release Time: The minimum time between two gain increments
Hold Time:
Page 23 / 60
Rev.1.6
The time it takes for the very first gain increment after the input signal amplitude decreases
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
Max Threshold
Input
Signal
Max Threshold
Output
Signal
Attack
time
Decrease
Gain
Page 24 / 60
Rev.1.6
Hold
time
Release
time
Hold
Gain
increase
Gain
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.4 HID Function
6.4.1 HID Interrupt in
Input Data Format:
byte0
always 1 for org HID event report ID
byte1
for defined HID event, each event occupies one bit
byte2
byte3
start address of returned data (H-start_addr)
byte4
start address of returned data (L-start_addr)
byte5
bit7
bit6:UART_INT
bit5:GPI_INT
bit4:SPIS_INT(slave mode int)
bit3: SPIM_INT(master mode int)
bit2:I2CS_INT(slave mode int)
bit1:I2CM_INT(master mode int)
bit0: IR_INT
byte6
read data of [start_addr]
byte7
read data of [start_addr+1]
byte8
read data of [start_addr+2]
byte9
read data of [start_addr+3]
byte10
read data of [start_addr+4]
byte11
read data of [start_addr+5]
byte12
read data of [start_addr+6]
byte13
read data of [start_addr+7]
byte14
read data of [start_addr+8]
byte15
read data of [start_addr+9]
Page 25 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.4.2 HID get_input_report
Command Format:
bmRequestType
8’h A1
bRequest
8’h 01
(Get_Report)
wValue
16’h 01 01
(Rpt Type + Rpt ID)
wIndex
16’h 00 03
(Interface)
wLength
16’h 00 10
(16 bytes)
Data
Report
**Note: The Start_Addr value in the input reported is put in the Internal Register Address 0xff. Software must set the
value of Start_Addr Register to make sure get_input_report can read the proper data desired.
Input Data Format:
byte0
always 1 for org HID event report ID
byte1
for defined HID event, each event occupies one bit
byte2
byte3
start address of returned data (H-start_addr)
byte4
start address of returned data (L-start_addr)
byte5
bit7
bit6:UART_INT
bit5:GPI_INT
bit4:SPIS_INT(slave mode int)
bit3: SPIM_INT(master mode int)
bit2:I2CS_INT(slave mode int)
bit1:I2CM_INT(master mode int)
bit0: IR_INT
byte6
read data of [start_addr]
byte7
read data of [start_addr+1]
byte8
read data of [start_addr+2]
byte9
read data of [start_addr+3]
byte10
read data of [start_addr+4]
byte11
read data of [start_addr+5]
byte12
read data of [start_addr+6]
byte13
read data of [start_addr+7]
byte14
read data of [start_addr+8]
byte15
read data of [start_addr+9]
Page 26 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.4.3 HID set_output_report
Command Format:
bmRequestType
8’h 21
bRequest
8’h 09
(Set_Report)
wValue
16’h 02 01
(Rpt Type + Rpt ID)
wIndex
16’h 00 03
(Interface)
wLength
16’h 00 10
(16 bytes)
Data
Report
**Note: Byte5 is the beginning address of this write sequence.
Output Data Format:
byte0
always 1 for org HID event report ID
byte1
start address of write reg (H-start_addr)
byte2
start address of write reg (L-start_addr)
byte3
effective write/read data length (<=12)
byte4
write data to [start_addr]
byte5
write data to [start_addr+1]
byte6
write data to [start_addr+2]
byte7
write data to [start_addr+3]
byte8
write data to [start_addr+4]
byte9
write data to [start_addr+5]
byte10
write data to [start_addr+6]
byte11
write data to [start_addr+7]
byte12
write data to [start_addr+8]
byte13
write data to [start_addr+9]
byte14
write data to [start_addr+10]
byte15
write data to [start_addr+11]
Page 27 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.5 Vendor Command Definition
6.5.1 Vendor Command Read
Command Format:
bmRequestType
bRequest
8’h C3
8’h 02
(Command 2)
wValue
16’h -- -(Start Address of
input Data)
wIndex
wLength
Data
16’h 00 00
16’h 00 –
(<=64 bytes)
Data
wIndex
wLength
Data
16’h 00 00
16’h 00 –
(<=64 bytes)
Data
Input Data Format:
Byte 0
Byte 1
Byte 2
…
Byte 63
Data
Data
Data
…
Data
of Reg[wValue]
of Reg[wValue + 1]
of Reg[wValue + 2]
of Reg[wValue + 63]
6.5.2 Vendor Command Write
Command Format:
bmRequestType
bRequest
8’h 43
8’h 01
(Command 1)
wValue
16’h -- -(Start Address of
Output Data)
Output Data Format:
Byte 0
Byte 1
Byte 2
…
Byte 63
Data
Data
Data
…
Data
of Reg[wValue]
of Reg[wValue + 1]
of Reg[wValue + 2]
of Reg[wValue + 63]
6.5.3 USB Vendor Requests
bmRequestType
0x43
(Vendor Other)
0xC3
(Vendor Other)
0x43
(Vendor Other)
0xC3
(Vendor Other)
bRequest
0x01
Register Write
0x02
Register Read
0x03
Flash Write
0x04
Flash Read
0x43
(Vendor Other)
0x05
Flash Control
0xC3
(Vendor Other)
0x06
Flash Control Get Status
Page 28 / 60
Rev.1.6
wValue
wIndex
wLength
Data Length
(<=64 bytes)
Data Length
(<=64 bytes)
Data Length
(<=64 bytes)
Data Length
(<=64 bytes)
Data
Address
0x0000
Address
0x0000
Address
0x0000: Write only
0x0001: Auto Verify
Address
0x0000
0x0000
0x0001: Chip Erase
Address
0x0002: Sector
Erase
0x0000
None
0x0000
0x0000
0x0001
1-byte data
0x01: Erasing
0x00: Ready
Data
Data
Data
Data
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.5.4 Simple Process of Firmware Update
Host
Device
1. Get register 0x3E
2. Modify CS_SEL to CS2, then write back to register 0x3E
3. When CS_SEL is changed to CS2, firmware will erase the whole flash automatically
4. Send vendor command 0x06 to check if the erase process finished
5. Use vendor command 0x03 with auto-verify option to write flash
If the data verification fails, the device will stall the vendor command
Repeat writing flash ……
6. Firmware update complete
Page 29 / 60
Rev.1.6
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USB Audio Chip
6.6 SPDIF Control Description
6.6.1 SPDIF Frame Description
 Audio format: linear 16 bit default.
 Allowed sampling frequencies (Fs) of the audio:

44.1kHz from CD

48 kHz from DAT

32 kHz from DSR
 One-way communication: from a transmitter to a receiver.
 Control information:

V (validity) bit: indicates if audio sample is valid

U (user) bit: user free coding i.e. running time song, track number

C (channel status) bit: emphasis, sampling rate and copy permit

P (parity) bit: error detection bit to check for good reception
 Coding format: biphase mark except the headers (preambles), for sync purposes
 Bandwidth occupation: 100kHz up to 6Mhz (no DC)
 Signal bitrate is 2.8Mhz (Fs=44.1kHz), 2Mhz (Fs=32kHz) and 3.1Mhz (Fs=48kHz)
Clock
Data Signal
Biphase Mark
Signal
1
0
0
1
1
0
1
0
0
1
0
1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0
Figure -17 Biphase Mark signal of SPDIF
Preamble
cell-order
cell-order
(last cell "0")
(last cell "1")
-----------------------------------------------------"B"
11101000
00010111
"M"
11100010
00011101
"W"
11100100
00011011
Preamble “B”:
Page 30 / 60
Rev.1.6
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Marks a word containing data for channel A (left) at the start of the data-block.
Preamble “M”:
Marks a word with data for channel A that is not at the start of the data-block.
Preamble “W”:
Marks a word containing data for channel B (right, for stereo). When using more than 2 channels, this could also be
any other channel (except for A).
The number of subframes that are used depends on the number of channels that is transmitted. A CD-player uses
Channels A and B (left/right) and so each frame contains two subframes. A block contains 192 frames and starts with
a preamble "B":
Sub-frame
0
3
4
Preamble
7
8
Aux Data
27 28 29 30 31
LSB
Audio Data
MSB
V U C P
V: Valid, U:User-Data, C:Channel-Status-Data, P:Parity-Bit
Figure -1 SPDIF Subframe Description
In each block, 384 bits of channel status and subcode info are transmitted. The Channel-status bits are equal for both
subframes, so actually only 192 useful bits are transmitted:
M ChannelA W ChannelA B ChannelA W ChannelA M ChannelA W ChannelA
SubFrame
Frame 191
SubFrame
Frame 0
Frame 1
Figure -2 Preamble Description of 192 SPDIF frame
6.6.2 SPDIF Out Channel Status
bit0
bit1
bit2
byte0
consumer
/professional
audio/
non-audio
copyright
default
0(P)
0(P)
1(P)
byte1
default
0(P)
bit5
bit6
pre-emphasis
0(P)
0(fixed)
bit7
mode
0(fixed)
0(fixed)
0(fixed)
0(P)
0(P)
0(P)
L
0(P)
source number
0(fixed)
byte3
default
bit4
category code
byte2
default
bit3
0(fixed)
0(fixed)
0(P)
0(P)
0(P)
0(P)
channel number
0(fixed)
sampling frequency
0(P)
0(P)
0(fixed)
0(fixed)
0(fixed)
clock accuracy
0(P)
0(fixed)
0(fixed)
0(fixed)
reserved
0(fixed)
0(fixed)
**Note: (P) These bits can be programmed by USB HID or USB vendor command
Page 31 / 60
Rev.1.6
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6.7 Digital Microphone
CM6533/CM6533N/CM6533X1/CM6533DH series IC provide digital microphone interface for recording. There are two
microphone signals transmitted on a single DATA line from DMIC module. The oversampling bit stream output from
DMIC module connects to internal decimation filter to generate PCM output.
VDD
VDD
DAT
IN
MIC
GND
A
CLOCK
L/R
DAT
A
CLOCK
CM6533
Series
DMIC Module
CLOCK
DATA1
DATA2
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Rev.1.6
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6.8 I2C Interface
6.8.1 I2C Master Mode
I2C protocol timing
Write Transaction
Slave Address
0
A
Map Address
Data0
A
A
Data1
A
Read Transaction
Slave Address
0
A
Map Address
Slave Address
A
1
Data0
A
A
From Master to Slave
From Slave to Master
SCL
1. N Byte Write Transaction
SDA
Slave Address 0
A
MAP
A
Data 1
A
Data
Data
A
Stop
2. N Byte Read Transaction
SDA
Slave Address 1
A
Data 1
A
Data
Data
A
Stop
SCL
3. Auto Read Transaction (= Write- MAP- Only + N Byte Read Transaction)
SDA
Slave Address 0
A
Start
A
Slave Address
1
A
Data
Data
A
Stop Start
from master to slave
from slave to master
Page 33 / 60
Rev.1.6
MAP
A  acknowledg e ( SDA Low )
A  not acknowledg e ( SDA High )
Stop
MAP: Memory Address Pointer
(the target register address
in slave device )
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6.8.2 I2C-Master Read with clk_sync mode
6.8.3 I2C Master Device Address and Control Register
Address:
0x80
Bits
R/W
Bit Mnemonic
7-1
R/W
SA_reg
The target slave device address.
0
R/W
SA_reg
1: read, 0: write
Description
Default
0xA8
(POR)
1’b0
(POR)
6.8.4 I2C Master Memory Address Pointer (MAP) Register
Address:
0x81
Bits
R/W
Bit Mnemonic
7-0
R/W
MAP_reg
Description
The register low byte address of salve
device to be read or written.
Default
8’b0
(POR)
6.8.5 I2C Master Memory Address Pointer (MAP2) Register
Address:
0x82
Bits
R/W
Bit Mnemonic
7-0
R/W
MAP2_reg
Page 34 / 60
Rev.1.6
Description
Default
The register high byte address of salve
8’b0
device to be read or written.
(POR)
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6.8.6 I2C Master Data Register
Address:
0x83 ~ 0x92
Bits
R/W
Bit Mnemonic
7-0
R/W
data0~ data15
Description
The data read from or written to the
slave device.
Default
8’b0
(POR)
6.8.7 I2C Master Control and Status Register 0
Address:
Bits
7-0
0x93
R/W
R/W
Bit Mnemonic
i2c_ctrl_reg1
Description
Data length of read/write command
8’h1: 1 byte, minimum length
8’h2: 2 bytes
…
8’hFE: 254 bytes
8’hFF: 256 bytes, maximum length
Default
0x14
(POR)
6.8.8 I2C Master Control and Status Register 1
Address:
Bits
0x94
R/W
Bit Mnemonic
7
R/W
i2c_start
6
R/W
i2c_reset
5
R/W
map_len
4
R/W
clk_sync
3
R/W
fast_std
2
R/W
map_only
1
R/W
auto_rd
Page 35 / 60
Rev.1.6
Description
Trigger I2C read/write command
0->1: trigger I2C read/write command.
1->0: I2C interface had completed
current task.
0 : I2C interface is idle and ready for
work.
1
: I2C interface is running.
Reset I2C interface
0 : Not reset I2C interface
1 : Reset I2C interface
MAP length
0 : 8-bit MAP
1 : 16-bit MAP
Clock Synchronization
0: off
1: on, when slave pull-down SCLK,
master would pause
I2C speed mode
0 : Standard mode, 100kHz
1 : Fast mode, 400kHz
MAP only write command
0 : Write command.
1 : MAP only write command.
Auto read command
0 : Read command.
1 : Auto read command.
Default
1’b0
(POR)
1’b0
(POR)
1’b0
(POR)
1’b1
(POR)
1’b0
(POR)
1’b0
(POR)
1’b1
(POR)
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Slave NACK error occur
1’b0
0
R
i2c_ctrl_reg2
1 : No error
(POR)
2 : Slave NACK error occur
*Note: Write-MAP-Only: An operation which only writes the register MAP the salve device
6.8.9 I2C Master Download Control and Status Register
Address:
0x95
Bits R/W
7
R/W
Bit Mnemonic
I2c_mas_sel
Description
Default
1’b1
I2C master/slave select
(POR)
Flag_8byte (RO): Flag to status I2C is
transmitting at 1st 8 bytes data or 2nd 8
bytes data.
If the flag index it’s transmitting the 2nd 8
bytes data, then F/W can prepare the next
8 bytes data into 1st 8byte buffer.
6
5:4
RO
WO
R/W
Flag_8byte
Flag_ready
LD_BLOCK
Flag_ready (WO): Flag to index F/W has
prepared next data ready.
After prepare done, F/W need set this bit
to index the data had been written. If F/W
didn’t catch on when all data has been
transmitted, the I2C clock would be keep
low to till it ready.
Download to which block of SRAM.
00: Load to 1st 8KB block.
01: Load to 2nd 8KB block.
10: Load to 3rd 8KB block.
11: Load to 4th 8KB block.
1’b0
(POR)
2’b00
(POR)
Check sum Error
1. If in LD_PHASE, the check sum
value was calculated by I2C load
data.
2. If in CHK_PHASE, the check sum
value was calculated by SRAM read
content.
1’b0
1’b0
3
RO
CHKSUM_ERR
2
RO
CHK_FINISH
CHECK phase done
1: finish download data CHECK
CHK_PHASE
MCU select CHECK phase to read SRAM
data for check-sum check.
1: enable (after disable LD_PHASE)
0: set 0 after complete
1’b0
(POR)
LD_PHASE
MCU select LOAD phase to access SRAM
from download.
1: enable
0: set 0 after complete
1’b0
(POR)
1
0
R/W
R/W
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6.8.10
Address:
0x96
Bits R/W
7
I2C Master Clock Period Setting Register
W
Bit Mnemonic
CHG_ENABLE
Description
MCU can program I2C clock; 1’b1: enable
MCU download select
6
R/W
LD_SEL
1’b0 : SPI download
1’b1 : I2C download
5-0
W
Page 37 / 60
Rev.1.6
CHG_FREQ
Set I2C-master clock period.
The clock
period=83.3*5*(CHG_FREQ+1)
Ex: CHG_FREQ = 6’d48
I2C Clock
Period=83.3*5*(48+1)=20408ns
HW limitation CHG_FREQ >= 6’h3
Default
1’b0
(POR)
1’b0
(POR)
6’h0
(POR)
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6.8.11
I2C Slave Mode
“7-bit slave address = 7’b0001000 to 7’b0001011”
CM6533/CM6533N/CM6533X1/CM6533DH can serves as a slave device with bit rate up to 400Kbps (fast mode).
External MCU can write data to CM6533/CM6533N/CM6533X1/CM6533DH or read data from
CM6533/CM6533N/CM6533X1/CM6533DH (No Size limitation in I2C Interface). Since host side and MCU can both
access to all the internal registers.
CM6533/CM6533N/CM6533X1/CM6533DH will transfer an interrupt to internal MCU until the INT bit of I2C
control Register have been clean by internal MCU. The interrupt will be trigger when write transaction done or
detect read-slave-address.
The main usage of 2-wire slave bus is to become the interface between the
CM6533/CM6533N/CM6533X1/CM6533DH and a external micro control unit (EMCU).
6.8.12
I2C Slave Data Register
Address: 30~33h
Bits
R/W
Bit Mnemonic
31:0
R/W
MCU_data0~F
6.8.13
Description
The data received from or transmitted to master device.
This register cannot be written when 2-wire slave serial
bus status is busy.
Default
0000h
(POR)
I2C Slave Status Register
Address: 34~35h
Bits
15
14:12
R/W
Bit Mnemonic
11
R/W
10
R
9
R/W
I2c_s_reset
8
R/W
Dri_tran_st
7
R/W
Rd_tran_st
6
R/W
Wr_tran_st
5:1
R
Data_len
R
Page 38 / 60
Rev.1.6
Thld_int_mask
Description
Reserved
Reserved
Threshold interrupt mask:
1: mask; 0: non-mask ; default :0
Write_data_ready Interrupt happened, auto-cleared after read
0: 2-wire serial bus in normal operation (default)
1: 2-wire serial bus in reset state
initiated transaction status
1: The last initiated transaction failed, write 1 to clear.
Read transaction status
1: a new read transaction received, write 1 to clear.
Write transaction status
1: a new write transaction received, write 1 to clear.
The data length of the last write transaction received,
00000: 1 byte (MAP only)
00001: 2 byte (MAP + 1 byte data)
00010: 3 byte (MAP + 2 byte data)
00011: 4 byte (MAP + 3 byte data)
00100: 5 byte (MAP + 4 byte data)

01111: 16 byte (MAP + 15 byte data)
.
10000: 17 byte (MAP + 16 byte data)
Default
1b
0h
0b
(POR)
0b
(POR)
0b
(POR)
0b
(POR)
0b
(POR)
0b
(POR)
0b
(POR)
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Others:
Reserved
0b
(POR)
**Note: When I2C issue interrupt to MCU, MCU needs to read the data numbers that threshold data count specified.
And waits another interrupt until the total data transfer completed.
0
R
6.8.14
busy
The 2-wire serial bus status, 0: idle, 1: busy
I2C Slave Memory Address Pointer(MAP) Register
Address: 36h
Bits
R/W
Bit Mnemonic
7:0
R/W
MCU_MAP
6.8.15
Description
The memory addresses of the read or write transactions
from MCU. Address 0 is reserved for initiated
transaction.
Default
00h
(POR)
I2C Slave Status Register
Address: 37h
Bits
R/W
Bit Mnemonic
7
R/W
Sync_en
6
R/W
Int_polarity
5:4
R/W
Slave_addr
3
R/W
Sync_sel
2
R/W
Int_mask
1
R/W
Dri_init_tran
Page 39 / 60
Rev.1.6
Description
Synchronization Enable
1: enable (the synchronization selection bit will decide
the method adopted).
0: disable (MCU and ARC should guarantee no data lost
themselves).
The polarity control of pin INT_OUT (initiated
transaction interrupt),
0: high active, 1: low active
Slave Device Address
00: select 0001000 (10h) as slave address
01: select 0001001 (12h) as slave address
10: select 0001010 (14h) as slave address
11: select 0001011 (16h) as slave address
Synchronization Method Selection
1: Data synchronization. When this bit is one, if the
current transaction has not been serviced by ARC, the
clock line of the 2-wire serial bus will be pulled low.
Under this situation, the MCU cannot start a new
transaction or continue the current read transaction
until the clock line goes back to high.
0: Ready pin synchronization. If the MCU cannot support
open drain 2-wire serial bus, this bit should be set to
zero. Under this situation, the MCU cannot start a new
transaction or continue the current read transaction
until the pin XSLAVE_RDY goes high to signal that the
driver has serviced the current transaction. Driver
should use “driver acknowledge” to signal the processing
of the current transaction is completed.
Interrupt Mask
0: interrupt will happen at a read/write transaction
received or a driver initiated transaction failed
1: interrupt will not happen
Driver initiated transaction
Write 1 to start Driver initiated transaction. This bit is
cleared automatically, after ARC initiated transaction
starts. The ARC initiated transaction should be issued
only when the 2-wire slave serial bus is idle. Otherwise,
it will be ignored. The ARC initiated transaction will
Default
1b
(POR)
0b
(POR)
01b
(POR)
1b
(POR)
0b
(POR)
0b
(POR)
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0
R/W
6.8.16
ack
cause pin INT_OUT to send out an interrupt for MCU.
After MCU responded with a Write-MAP-Address-0-Only
transaction and a subsequent read transaction, interrupt
INT_OUT will be de-asserted. However, if the MCU does
not act as what is expected (a write MAP-Address-0-Only
transaction and a subsequent read transaction), the
interrupt INT_OUT will be still de-asserted, but the ARC
initiated transaction status is used to signal a fail status
to ARC. In this case, the driver should consider to repeat
the failed Driver initiated transaction again.
Driver Acknowledge means driver has processed the
current transaction.
Write 1 to acknowledge. This bit will be cleared
automatically.
0b
(POR)
I2C Using Example
Master mode write:
I2C write 2 bytes (Slave address =92, MAP address =01, Data=55, AA)
Write 0x80= 92 (Slave address)
Write 0x81 = 01 (MAP address)
Write 0x83~0x84 = 55 AA (Data register)
Write 0x93 = 02 (Data length 2 bytes)
Write 0x94 = 92 (I2C start)
Master mode read:
I2C read 2 bytes (Slave address=92, MAP address =01)
Write 0x80= 93 (Slave address)
Write 0x81 = 01 (MAP address)
Write 0x93 = 02 (Data length 2 bytes)
Write 0x94 = 92 (I2C start)
Read 0x83~0x84 (Data register)
Page 40 / 60
Rev.1.6
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6.9
SPI Interface
The SPI interface is used to transfer control data between the CM6533/CM6533N/CM6533X1/CM6533DH and external
codec.
In a SPI interface there is only one central clock source producing a reference clock to which SPI data processing is
synchronized. This clock is often referred to as the MCU clock, e.g. for SPI clock 12Mhz, When the MCU clock equal
48Mhz and SPI clock div4.
6.9.1 SPI Control Register 0
Address: 3ch
Bits
R/W
Bit Mnemonic
Description
SPI master/slave mode
0: master mode
1: slave mode
SPI slave address length
0: 1-byte address
1: 2-byte address
7
R/W
slv_mst
6
R/W
long_mode
5
--
--
Reserved
4
--
--
Reserved
3
R/W
si_mode
2
R/W
si_mode_rs
1
RO
flag_rd
0
RO
flag_wr
default
1’b1
(POR)
1’b1
(POR)
1’b0
(POR)
1’b0
(POR)
Serial interface mode
0: normal SPI mode
1: Serial interface mode
Serial interface RS/A0 output
0: RS/A0==0 for 8th bit
1: RS/A0==1 for 8th bit
Flag read
0: mcu can’t read spi data
1:mcu need to read spi data
Flag write
0: mcu can’t write spi data
1:mcu need to write spi data
1’b0
(POR)
1’b0
(POR)
1’b0
1’b0
6.9.2 SPI Control Register 1
Address: 3dh
Bits
R/W
Bit Mnemonic
7
R/W
spi_start
6
R/W
spi_lh_edge
5
R/W
Spi_flash_rd_wr
Page 41 / 60
Rev.1.6
Description
Trigger SPI read/write command
0->1: trigger SPI read/write command.
1->0: SPI interface had completed current task.
0 : SPI interface is idle and ready for work.
1 : SPI interface is running.
SPI CEN control
0: codec latch control data at SPI clock low (default)
1: codec latch control data at SPI clock high
SPI Flash Read/Write
0:spi flash read (default)
1:spi flash write
default
1’b0
(POR)
1’b1
(POR)
1’b0
(POR)
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4-3
R/W
frq_sel
2
1
R/W
R/W
first_leading_bit
second_leading_bit
0
R/W
leading_bit_mode
SPI clock period
2’b00: by MCU clk div 4
2’b01: by MCU clk div 12
2’b10: by MCU clk div 16
2’b11: by MCU clk div 20
First data bit of 2-bit leading mode
Second data bit of 2-bit leading mode
RA8815 2-bit leading mode
0: No leading bits
1: 2-bit leading for each transaction
2’b0
(POR)
1’b0(POR)
1’b0(POR)
1’b0
(POR)
6.9.3 SPI Interrupt
Address: 3eh
Bits
7
6
R/W
R/W
R/W
Bit Mnemonic
CPOL
CPHA
5-4
R/W
CS_SEL
3
RO
slv_hid
2
RO
slv_rw
1
R/W
slv_int_en
0
R/W
mst_int_en
Description
Clock Polarity
Clock Phase
SPI CS Select
00: CS0
01: CS1
10: CS2(Default)
11: CS2
SPI slave flag to HID interrupt
0: access to internal register
1: flag to HID interrupt
SPI slave read/write flag
0: read
1: write
SPI slave interrupt
0: no interrupt
1: interrupt (Default)
Ext MCU can program this bit to make slave
mode interrupt
SPI master interrupt enable
0: disable
1: enable (Default)
Control HW to make master mode interrupt
default
1’b1(POR)
1’b1(POR)
2’b10(POR)
1’b0
(POR)
1’b0
(POR)
1’b1
(POR)
1’b1
(POR)
**Note:
1. Bit [1]: When SPI interface is slave mode, SPI interrupt happened when bit [1] ==1, which is written by external
MPU via SPI. Interrupt (HID) would be cleaned once address 0x10 was written.
2. Bit [0]: When SPI interface is master mode, SPI interrupt happened when bit [0] ==1 and every SPI master command
completed. Interrupt (HID) would be cleaned once address 0x10 was written.
6.9.4 SPI Control Register 3
Address: 3fh
Bits
R/W
Bit Mnemonic
7-0
R/W
data_len
Page 42 / 60
Rev.1.6
Description
The data length of read/write,
0000_0000: Reserved
0000_0001: 1 bytes
0000_0010: 2 bytes
0000_0011: 3 bytes
.
.
.
1111_1111:255 bytes
default
8’d0
(POR)
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6.9.5 SPI Using Example
SPI write 3 bytes ( AD=92,DATA=55,AA)
Write 0x38~0x3A= 92 55 AA (Data register)
Write 0x3F = 03 (Write length 3 bytes)
Write 0x3D = A0 (SPI start)
SPI read 3 bytes (AD=92)
Write 0x38= 92 (Data register)
Write 0x3F = 03 (Read length 3 bytes)
Write 0x3D = 80 (SPI start)
Read 0x38~0x3A
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Rev.1.6
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6.10 GPIO
6.10.1
Address Offset:
Bits
R/W
15:0
R/W
6.10.2
Address Offset:
Bits
R/W
15:0
R
6.10.3
Address Offset:
GPO Data Register
C0-C1h
Bit Mnemonic
GPO_0_reg
GPO_1_reg
Bit Mnemonic
Description
Default
16’h0
(POR)
GPI data register which represents
GPIO Direction Control Register
C4-C5h
Bit Mnemonic
15:0
R/W
GPOE_0
GPOE_1
Description
GPIO output enable register which
represents for pin XGPIO[15:0]
1: the corresponding pins are used as
output
0: the corresponding pins are used as input
Default
16’h0
(POR)
GPIO Interrupt Enable Mask Register
C6-C7h
Bits
R/W
Bit Mnemonic
15:0
R/W
GPI_EN
6.10.5
GPO data register which represents
C2-C3h
R/W
Address Offset:
Default
16’h0
(POR)
GPI Data Register
Bits
6.10.4
Description
Description
GPIO_E, GPIO interrupt enable mask which
represents for pins, XGPIO[15:0]
1: enable,
0: disable
Default
16’h0
(POR)
GPIO Debouncing Register
Address Offset: C8-C9h
Default Value: 0000h (MSB -> LSB)
Bits
R/W
Bit Mnemonic
15:0
R/W
GPI_Deb
Page 44 / 60
Rev.1.6
Description
Enable the clock scale of mini-second (32
ms) for de-bouncing, default 1
1: enable,
0: disable
Default
16’h0
(POR)
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.10.6
GPI Remote Choose
Address Offset: 0xE2~E3h
Bits
R/W
Bit Mnemonic
15:0
R/W
GPI_RWL
GPI_RWH
6.10.7
Description
D0==1’b1:GPI[0] remote wake up
enable
D1==1’b1:GPI[1] remote wake up
enable
D2==1’b1:GPI[2] remote wake up
enable
D3==1’b1:GPI[3] remote wake up
enable
D4==1’b1:GPI[4] remote wake up
enable
D5==1’b1:GPI[5] remote wake up
enable
D6==1’b1:GPI[6] remote wake up
enable
D7==1’b1:GPI[7] remote wake up
enable
D8==1’b1:GPI[8] remote wake up
enable
D9==1’b1:GPI[9] remote wake up
enable
D10==1’b1:GPI[10] remote wake
up enable
D11==1’b1:GPI[11] remote wake
up enable
D12==1’b1:GPI[12] remote wake
up enable
D13==1’b1:GPI[13] remote wake
up enable
D14==1’b1:GPI[14] remote wake
up enable
D15==1’b1:GPI[15] remote wake
up enable
default
16’h0
(POR)
GPIO Pull-up/Down
Address Offset: 0xE4
Bits
R/W
Bit Mnemonic
7
R/W
GPIO_PD0[7]
6
R/W
GPIO_PD0[6]
5
R/W
GPIO_PD0[5]
4
R/W
GPIO_PD0[4]
3
R/W
GPIO_PD0[3]
2
R/W
GPIO_PD0[2]
1
R/W
GPIO_PD0[1]
0
R/W
GPIO_PD0[0]
Page 45 / 60
Rev.1.6
Description
GPIO_7 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_6 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_5 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_4 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_3 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_2 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_1 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_0 pad control
1’b1 : floating ; 1’b0 : 75k
default
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
Address Offset: 0xE5
Bits
R/W
Bit Mnemonic
7
R/W
GPIO_PD1[7]
6
R/W
GPIO_PD1[6]
5
R/W
GPIO_PD1[5]
4
R/W
GPIO_PD1[4]
3
R/W
GPIO_PD1[3]
2
R/W
GPIO_PD1[2]
1
R/W
GPIO_PD1[1]
0
R/W
GPIO_PD1[0]
Description
GPIO_15 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_14 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_13 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_12 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_11 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_10 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_9 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_8 pad control
1’b1 : floating ; 1’b0 : 75k
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
default
1’b1
(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
Address Offset: 0xE6
Bits
R/W
Bit Mnemonic
7
R/W
GPIO_PD2[7]
6
R/W
GPIO_PD2[6]
5
R/W
GPIO_PD2[5]
4
R/W
GPIO_PD2[4]
3
R/W
GPIO_PD2[3]
2
R/W
GPIO_PD2[2]
1
R/W
GPIO_PD2[1]
0
R/W
GPIO_PD2[0]
Page 46 / 60
Rev.1.6
Description
GPIO23 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_22 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_21 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_20 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_19 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_18 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_17 pad control
1’b1 : floating ; 1’b0 : 75k
GPIO_16 pad control
1’b1 : floating ; 1’b0 : 75k
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
default
1’b1
(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
1’b1(POR)
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.11 Arbitrary Sine-tone Generator
There are four (4) memory banks to store user defined waveform in CM6533/CM6533N/CM6533X1/CM6533DH
design. This function would generate waveform data that is desired to be heard from earphones. For example
when function keys were pressed or do other operations. User can predefine two different waveforms with 96K and
88.2K sampling rates and stores it in corresponding memory banks. The waveform data format must comply with
the following specifications:
1. 16 bits PCM with 2’s complement
2. First word must define waveform length (Length[9:0]= {byte1[2:0], byte0[7:0]})
3. Waveform length must less than 2046
4. Four memory banks
Bank1: 0x6000~0x67FF (Length: 0x6000~0x6001, Waveform data 0x6002~0x67FF)
Bank2: 0x6800~0x6FFF (Length: 0x6800~0x6801, Waveform data 0x6802~0x6FFF)
Bank3: 0x7000~0x77FF (Length: 0x7000~0x7001, Waveform data 0x7002~0x77FF)
Bank4: 0x7800~0x7FFF (Length: 0x7800~0x7801, Waveform data 0x7802~0x7FFF)
Generating sine-tone is based on a look-up table and the step size of look-up table for different sampling rates
would be adjusted automatically.
Page 47 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.12 Tri-Colored LED Control Setting
PWM function is generated by LED counter and output the PWM signal to GPIO pin. The 8-bit counter counts modulus
256 controlled by LED freq, LED duty register. The LED unit register controls PWM resolution. When the LED freq
register value is equal to the LED duty register (high), the PWM output also goes high. When the LED freq, LED duty
register reaches zero, the PWM output is forced to go low. The low-to-high ratio (duty) of the PWM output is LED
duty/LED freq.
LED duty
LED freq
00H
01H
80H
FEH
FFH
FFH
FFH
FFH
LED unit
(256 step)
00:10.5ms
01:5.45ms
10:2.73ms
11:1.36ms
PWM duty range
00H/FFH
~FEH/FFH
The Output Duty of PWM has different timings. Duty range is from 0/256~255/256.
LED duty/LED freq
=00H/FFH
LED duty/LED freq
=01H/FFH
LED duty/LED freq
=80H/FFH
LED duty/LED freq
=FEH/FFH
Page 48 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
6.13 Reset
VDD
Power
VSS
Flash Initial Time
Ready
(Read 16K Firmware from
internal flash)
Reset
Flash Initial Time
Ready
(Read 32K Firmware from
internal flash)
Reset
55m sec
95m sec
Normal Run
Watchdog
Overflow Time
6.13.1
WDT Reset
Default 1 sec
Watchdog Reset Timer
The watchdog timer is a 15-bit counter that is incremented every 24 or 384 clock cycles. It is used to provide the
system supervision in case of software or hardware upset. If the software was not able to refresh the Watchdog Timer
after 786336 or 12581376 clock cycles (65ms or 1s when using 12MHz clock), an internal reset is generated.
Page 49 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
7 CM6533X1 Xear™ Sound Processing
Xear™ is the core name of C-Media sound effect technology; it includes audio and voice processing. These
sections describe the main sound processing on CM6533X1.
7.1 Xear™ Surround Headphone
Xear™ Surround Headphone creates a realistic 5.1/7.1CH surround sound field over stereo headphones. Combined
with 3D sound processing in games, gamers could enjoy amazing 3D gaming sound experience and combat advantages.
It also delivers natural sound space for stereo music as real as playback on speakers for longer listening on
headphones without fatigue.
Xear Surround Headphone provides music/gaming and movie modes for different applications. User can switch the
surround mode to get the best effect in different situation.
7.2 Xear™ Software 10 Band Equalizer
It provides 10-band EQ function, User will able to adjust the EQ band by manual and create customize preset items or
click on the preset EQ mode. There are 12 preset modes such as Bass, Treble, Live, Rock, Jazz, etc.
7.3 Xear™ Audio Brilliant
Xear™ Audio Brilliant restores the clarity and details of compressed audio in music, movies and games (MP3, WMA,
AAC, AC3, etc.). Make the sound more dynamic and brilliant. Audio compression algorithms will usually sacrifice some
audio frequency signals. It might result in flat, thin, and lifeless sounds. Audio Brilliant recreates the subtleties of the
original performance.
7.4 Xear™ Dynamic Bass
Xear™ Dynamic Bass reproduces the deep and vibrating bass in music, games, and movies, and music even over small
speaker/headphone drivers and enclosures. Applying psychoacoustic techniques to make users feel stronger bass
signals of drums, bass guitars, explosions, automobile engines, etc.
It can overcome small speaker driver’s poor bass limitation without damage.
7.5 Xear™ Voice Clarity
Xear™ Voice Clarity can increase the clarity, intelligibility, and prominence of receiving voice in games, VOIP, music,
or movies without suppressing or changing other background audio. Adjustable voice clarity levels make you hear the
voice more clearly or learn language more easily.
Optional background stationary noise suppression in communication simultaneously.
7.6 Xear™ Smart Volume
Xear™ Smart Volume normalizes sound levels of music, Internet AV clips, and movies to reduce the probabilities that
require volume adjustments on Docking Speakers and PCs.
7.7 Xear™ Surround Max
Xear Surround Max can expand stereo audio content to each output channel.
When you playing mp3 music file and enable this function, you can hear music from each speaker (8 speakers).
7.8 Xear™ Magic Voice
Xear™ Magic Voice is a great feature for disguising your voice (using cartoon/monster/male/female effects) for VOIP
and online gaming Applications.
Page 50 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
7.9 Xear™ Environmental Noise Cancellation
Xear™ VoClear Environmental Noise Cancellation (ENC) utilizes dual microphone signal capturing via gaming headset,
which could effectively identify the dynamic ambient noises, and cancel them out significantly even in noisy gaming
environments (Internet Café, game champion spot, living room, etc.) to ensure the far-end teammate could hear
your voice clearly over the Internet or LAN, and create team gaming advantages.
8 CM6533DH Dolby® and Xear™ Sound Processing
Dolby is the trademark from Dolby Laboratories, Inc., is an American company specializing in audio noise
reduction and audio encoding/compression. Dolby licenses its technologies to consumer electronics manufacturers.
8.1 Dolby® Headphone v2
Dolby Surround effect creates the sensation of multiple loudspeakers in a room, and is closer to home theater sound
than traditional headphone audio.
8.2 Dolby® Pro Logic IIx
Dolby Pro Logic IIx expands stereo or 5.1-channel audio to 7.1-channel sound.
8.3 Xear™ Environment Effect
It provides 28 special environment emulations, User can hear different sound reflection and reverberation.
8.4 Xear™ Software 10 Band Equalizer
It provides 10-band EQ function, User will able to adjust the EQ band by manual and create customize preset items or
click on the preset EQ mode. There are 12 preset modes such as Bass, Treble, Live, Rock, Jazz, etc.
8.5 Xear™ Magic Voice
Xear™ Magic Voice is a great feature for disguising your voice (using cartoon/monster/male/female effects) for VOIP
and online gaming Applications.
Page 51 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
9 Electrical Characteristics
9.1 Absolute Maximum Ratings
Test conditions: DV50 = 5V, AV50 = 5V, DGND =0V, TA=+25oC
Parameter
Symbol
Min.
Storge temperature
TS
-25
Operating ambient temperature
TA
-15
Digital supply voltage(DV50)
4.5
Analog supply voltage(AV50)
4.5
I/O pin voltage
GND
ESD (Body mode)
ESD (Machine mode)
Typ
25
5.0
5.0
±4000
±200
Max.
150
70
5.5
5.5
3.3
Unit
o
C
o
C
V
V
V
V
V
Typ
5
5
25
12.000
Max.
Unit
V
V
o
C
MHz
9.2 Recommended Operation Conditions
Parameter
Digital supply voltage(DV50)
Analog supply voltage(AV50)
Operating ambient temperature
MCU Clock
Symbol
-
Min.
-
9.3 Power Consumption
Test Conditions: DV50=5V, AV50 = 5V, DGND =0V, TA=+25oC, MCU Clock = 12MHz.
Sample Rate=48kHz, 16Bits, Operation: HP-Out Playback+Mic-In Recording, EQ disable, Spdif out disable, No loading
Parameter
Min.
Typ
Max.
Unit
Total power consumption
65.9
mA
(including Playback and Recording)
= Digital 27.9mA + Analog 38mA
Standby power consumption
64
mA
(excluding Playback and Recording)
Suspend mode power consumption
2.4
mA
9.4 DC Characteristics
Test Conditions: DV50=5V, VDD = 3.3V, DGND =0V, TA=+25oC, VDD = 3.3V
Parameter
Operation Voltage range
DC Input voltage range
(GPIO,I2C,SPI,SPDIF)
Input High-level voltage
(GPIO,I2C,SPI,SPDIF)
Input Low-level voltage
(GPIO,I2C,SPI,SPDIF)
Output High-level voltage
(GPIO,I2C,SPI,SPDIF)
Output Low-level voltage
(GPIO,I2C,SPI,SPDIF)
Output source current
(GPIO, I2C,SPI,SPDIF)
Output sink current
(GPIO, I2C,SPI,SPDIF)
VREG33 driver current
Symbol
DVDD
Min.
4.5
DCVin
-0.3
Vih
2
Vil
Typ
5
Max.
5.5
Unit
V
5.5
V
2
V
0.8
0.8
V
Voh
2.4
-
3.6
V
Vol
0
-
0.4
V
IOH
8
mA
IOL
8
mA
IVREG
10
mA
**Note: DVDD18,AVDD36,AV42_DA,AV36_DAL,AV36_DAR without current drive capacity
Page 52 / 60
Rev.1.6
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
9.5 Analog Audio
Parameter
Symbol
Pin Name
XVAG
XVAG
Microphone Input Clipping
Level (at minimum input
volume, i.e., 0 dB)
VMI
XMICL
XMICR
Analog Output Voltage AC
VAO
Microphone Input Impedance
MII
Signal Reference Voltage
Microphone A-A Input
Impedance
Headphone Output
Impedance
MAII
HPOI
XLNOUTL
XLNOUTR
XMICL
XMICR
XMICL
XMICR
XLNOUTL
XLNOUTR
Limit Values
Min.
Typ.
Max
1.65
1.75
1.85
2.828
Unit
Test Conditions
V
RLoad>> 10 M
Vpp
2.828
Vpp
45
k
20
20
k
32

Volume =
dB
Volume =
dB
9.6 USB Transceiver
Parameter
Regulator Voltage
Driver Output Impedance
including the 22External
Serial Resistor
Rise and Fall Times
Symbol
Pin Name
XV33
RO
Limit Values
Unit
Test Conditions
3.6
V
CL =10uF
40

static, LOW or HIGH
19
ns
CL = 50 pF, driver mode
110
%
CL = 50 pF, driver mode
2.0
V
CL = 50 pF, driver mode
Min.
Typ.
Max
XV33
3.0
3.3
D+/D−
24
tr/tf
3
Rise/Fall Time Matching
MA_TRT
F
90
Crossover Voltage
VXOVER
1.30
Differential Receiver
Common-Mode Range
Single-ended Receiver
Threshold Voltage
VCM_DR
EC
0.8
2.5
V
VT_SREC
0.8
2.0
V
Switchable Pull-up Resistor
RPU
VREG, D+
Symbol
Pin Name
Open Circuit Voltage
Microphone Bias
VMICBIA
S
MICBIAS
Output Current
Microphone Bias
IMICBIAS
MICBIAS
Output Impedance
Microphone Bias
ROUTMI
CB
MICBIAS
Power Supply Rejection
Ratio for Microphone Bias
PSRRMIC
B
AVDD,
MICBIAS
10
1.75
1.5
k
9.7 Microphone Bias
Parameter
Page 53 / 60
Rev.1.6
Limit Values
Unit
Min.
Typ.
Max
2.55
2.75
2.95
V
1.25
mA
700

600
650
100
dB
Test Conditions
RMIN=2.2k
Internal regulators active,
at maximum load current
(0.5 mA), 1 kHz sine wave at
100 mVrms
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
10 Audio Performance
10.1 DAC Audio Quality
TA=25℃, DV50=5V, AV50=5V, Equalizer disabled, Typical Fs/Bit-depth=48KHz/16bit (except remarked in Test
Conditions), Master Volume= 0dB, Platform=DELL Desktop 32BWS02, 4G RAM, Windows 8.1 CHT
Items
Test Conditions
Test Values
Min.
Typ.
Max.
Unit
10KΩ loading
1.04
Vrms
32Ω loading
0.99
Vrms
10KΩ loading, 20~20KHz
-87
dB
-71
(@1KHZ)
dB
10KΩ loading, A-Weighted
91
dB
32Ω loading, A-Weighted
92
dB
10KΩ loading, A-Weighted
93
dB
32Ω loading, A-Weighted
93
dB
Full Scale Output Voltage
THD+N @ -3dB Full Scale
32Ω loading, 20~20KHz
Dynamic Range (with -60dBFs
Output Signal)
Noise Level (SNR, with -96dBFs
Output Signal)
Inter-Channel Phase Delay
100Hz ~ 20kHz
Sampling Frequency Accuracy
10KΩ loading
Channel Separation(Crosstalk)
Passband Ripple Range
Page 54 / 60
Rev.1.6
+0.01
+1.01
Deg
-0.0046
+0.0078
%
10KΩ loading, 20~20KHz
-95
dB
32Ω loading (Normal Jack),
20~20KHz
-60
dB
32Ω loading (4-ring Combo
Jack), 20~20KHz
Frequency Response
-86.7
-61
-53
(@1KHz)
-52
dB
10KΩ loading, Fs=48kHz/16bits,
20~20KHz
-0.064
(20Hz)
-0.949
(20KHz)
dB
10KΩ loading, Fs=96kHz/24bits,
20~48KHz
-0.017
(20Hz)
-3
(42KHz)
dB
0.278
dB
10KΩ loading, 20~20KHz
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
10.2 ADC Audio Quality
TA=25℃, DV50=5V, AV50=5V, input test signal is 997Hz sine wave, measure bandwidth is 120Hz to 20kHz, Equalizer
disable, AGC off, Mic Gain= 0dB, Typical Fs/Bit-depth=48KHz/16bit (except remarked in Test Conditions)
Platform=DELL Desktop 32BWS02, 4G RAM, Windows 8.1CHT
Items
Test Conditions
Test Values
Min.
Full Scale Input Voltage
THD+N @-3dB Full Scale Input
20~20KHz
Dynamic Range (with -60dBFs Input
Signal)
A-Weighted
-85
Typ.
Max.
Unit
0.74
Vrms
-83
(@1KHz)
dB
88
dB
Fs=48kHz/16bits
-0.0032
-0.0069
Fs=96kHz/24bits
-0.0057
-0.0078
%
Sampling Frequency Accuracy
Channel Separation(Crosstalk)
20~20KHz
Page 55 / 60
Rev.1.6
dB
Fs=48kHz/16bits, 20~20KHz
-0.043
(20Hz)
-0.512
(20KHz)
dB
Fs=96kHz/24bits, 20~48KHz
-0.005
(20Hz)
-3
(43KHz)
dB
0.265
dB
Frequency Response
Passband Ripple Range
-80
20~20KHz
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
10.3 Analog Monitoring / Sidetone (A-A ) Path Audio Quality
TA=25℃, DV50=5V, AV50=5V, Microphone-In to Line-Out, 10Kohms loading, Master Volume=0dB, Mic Gain=0dB
Platform=DELL Desktop 32BWS02, 4G RAM, Windows 8.1 CHT
Items
Test Conditions
Test Values
Min.
Full Scale Output Voltage
Max.
Unit
1.05
Vrms
-89
(@1KHz)
dB
THD+N @ -3dB Full Scale Input
20~20KHz
Dynamic Range (with -60dBFs Input
Signal)
A-Weighted
92
dB
Channel Separation (Crosstalk)
20~20KHz
-90
dB
Frequency Response
20~20KHz
Passband Ripple Range
20~20KHz
Page 56 / 60
Rev.1.6
-90
Typ.
-0.036
(20Hz)
-0.133
(20KHz)
dB
0.002
dB
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CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
11 Package Dimension
Model Number
CM6533
CM6533N
CM6533X1
CM6533DH
Page 57 / 60
Rev.1.6
Package
48-Pin LQFP 7mm×7mm×1.4mm
(Plastic)
48-Pin QFN 7mm×7mm×0.85mm
(Plastic)
48-Pin LQFP 7mm×7mm×1.4mm
(Plastic)
48-Pin LQFP 7mm×7mm×1.4mm
(Plastic)
Outline Dimensions *Dimensions
Operating Ambient
Temperature
Supply Range
-15°C to +70°C
DVdd = 5V, AVdd = 5V
-15°C to +70°C
DVdd = 5V, AVdd = 5V
-15°C to +70°C
DVdd = 5V, AVdd = 5V
-15°C to +70°C
DVdd = 5V, AVdd = 5V
shown in inches and (mm)
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
11.1 Package Dimension of CM6533/6533X1/6533DH
48-Lead Thin Plastic Quad Flatpack (LQFP)
Page 58 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
11.2 Package Dimension of CM6533N
48-Lead Thin Plastic Quad Flatpack (QFN)
Page 59 / 60
Rev.1.6
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Copyright© C-Media Electronics Inc.
CM6533,CM6533N,CM6533X1,CM6533DH
USB Audio Chip
－End of Datasheet－
C-MEDIA ELECTRONICS INC.
6F., 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106 R.O.C.
TEL：+886-2-8773-1100
FAX：+886-2-8773-2211
E-MAIL：[email protected]
Disclaimer:
Information furnished by C-Media Electronics Inc. is believed to be accurate and reliable. However, no responsibility
is assumed by C-Media Electronics Inc. for its use, nor for any infringements of patents or other rights of third parties
that may result from its use. Specifications are subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of C-Media. Trademark and registered trademark are the property of
their respective owners.
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