Cypress CY7C195B-25PC 256 kb (64k x 4) static ram Datasheet

CY7C194B
CY7C195B
256 Kb (64K x 4) Static RAM
General Description1
Features
• Fast access time: 12 ns, 15 ns, and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ
The CY7C194B-CY7C195B is a high-performance CMOS
Asynchronous SRAM organized as 64K × 4 bits that supports
an asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected. Output enable (OE) is
supported only in CY7C195B.2
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C194B-CY7C195B is available in 24 DIP, 24 SOJ, 28
DIP, and 28 SOJ package(s).
Logic Block Diagram
RAM Array
Sense Amps
Row Decoder
Input Buffer
I/Ox
CE
Column Decoder
WE
Power
Down
Circuit
OE
(7C195 only)
X
A
X
Product Portfolio
12 ns
15 ns
25 ns
Unit
Maximum Access Time
12
15
25
ns
Maximum Operating Current
90
80
80
mA
Maximum CMOS Standby Current
10
10
10
mA
Notes:
1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. All OE-specific descriptions and parameters in this datasheet pertain to CY7C195 only.
Cypress Semiconductor Corporation
Document #: 38-05409 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised September 17, 2003
CY7C194B
CY7C195B
Pin Layout and Specifications
CY7C195B 28 DIP (6.9 × 35.6 × 3.5 mm) – P21
NC
1
28
VCC
A6
2
27
A5
A7
3
26
A4
A8
4
25
A3
A9
5
24
A2
A10
6
23
A1
A11
7
22
A0
A12
8
21
NC
A13
9
20
NC
A14
10
19
I/O3
A15
11
18
I/O2
CE
12
17
I/O1
OE
13
16
I/O0
GND
14
15
WE
CY7C195B 28 SOJ (8 × 18 × 3.5 mm) – V21
Document #: 38-05409 Rev. *A
NC
1
28
VCC
A6
2
27
A5
A7
3
26
A4
A8
4
25
A3
A9
5
24
A2
A10
6
23
A1
A11
7
22
A0
A12
8
21
NC
A13
9
20
NC
A14
10
19
I/O3
A15
11
18
I/O2
CE
12
17
I/O1
OE
13
16
I/O0
GND
14
15
WE
Page 2 of 13
CY7C194B
CY7C195B
Pin Layout and Specifications (continued)
CY7C194B 24 SOJ (8 × 15 × 3.5 mm) – V13
A6
1
24
VCC
A7
2
23
A5
A8
3
22
A4
A9
4
21
A3
A10
5
20
A2
A11
6
19
A1
A12
7
18
A0
A13
8
17
I/O3
A14
9
16
I/O2
A15
10
15
I/O1
CE
11
14
I/O0
GND
12
13
WE
CY7C194B 24 DIP (6.6 × 31.8 × 3.5 mm) – P13
Document #: 38-05409 Rev. *A
A6
1
24
VCC
A7
2
23
A5
A8
3
22
A4
A9
4
21
A3
A10
5
20
A2
A11
6
19
A1
A12
7
18
A0
A13
8
17
I/O3
A14
9
16
I/O2
A15
10
15
I/O1
CE
11
14
I/O0
GND
12
13
WE
Page 3 of 13
CY7C194B
CY7C195B
Pin Description
Pin
Type
Description
AX
Input
Address Inputs.
CE
Control
Chip Enable.
I/OX
Input or
Output
Data Input/Outputs.
NC
–
No Connect. Pins are not internally connected to
the die.
28 DIP
24 DIP
24 SOJ
28 SOJ
2, 3, 4, 5, 6,
7, 8, 9, 10,
11, 22, 23,
24, 25, 26,
27
1, 2, 3, 4, 5,
6, 7, 8, 9,
10, 18, 19,
20, 21, 22,
23
1, 2, 3, 4, 5,
6, 7, 8, 9,
10, 18, 19,
20, 21, 22,
23
2, 3, 4, 5, 6,
7, 8, 9, 10,
11, 22, 23,
24, 25, 26,
27
12
11
11
12
16, 17, 18,
19
14, 15, 16,
17
14, 15, 16,
17
16, 17, 18,
19
1, 20, 21
–
–
1, 20, 21
OE
Control
Output Enable (CY7C195 only).
13
–
–
13
VCC
Supply
Power (5.0V).
28
24
24
28
WE
Control
Write Enable.
15
13
13
15
CY7C195B Truth Table
CE
OE
WE
I/Ox
Mode
Power
H
X
X
High Z
Deselect / Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC )
L
X
L
Data In
Write
Active (ICC )
L
H
H
High Z
Selected, outputs disabled
Active (ICC )
CY7C194B Truth Table
CE
WE
Input/Output
Mode
Power
H
X
High Z
Power-Down
Standby (I SB )
L
H
Data Out
Read
Active (I CC )
L
L
Data In
W rite
Active (I CC )
Document #: 38-05409 Rev. *A
Page 4 of 13
CY7C194B
CY7C195B
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Value
Unit
TSTG
Parameter
Storage Temperature
Description
–65 to +150
°C
TAMB
Ambient Temperature with Power Applied (i.e. case temperature)
–55 to +125
°C
VCC
Core Supply Voltage Relative to VSS
–0.5 to +7.0
V
VCC
DC Voltage Applied to any Pin Relative to VSS
IOUT
Output Short-Circuit Current
VESD
Static Discharge Voltage (per MIL-STD-883, Method 3015)
> 2001
V
ILU
Latch-up Current
> 200
mA
–0.5 to VCC + null
V
20
mA
Operating Range
Range
Ambient Temperature (TA)
Voltage Range (VCC)
Commercial
0°C to 70°C
5.0V ± 10%
DC Electrical Characteristics3
12 ns
Parameter
Description
Condition
15 ns
25 ns
Min
Max
Min
Max
Min
Max
Unit
VIH
Input HIGH Voltage
2.2
VCC +
0.3
2.2
VCC +
0.3
2.2
VCC +
0.3
V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
–0.5
0.8
V
VOH
Output HIGH Volt- VCC = Min., loh = -4.0 ma
age
2.4
–
2.4
–
2.4
–
V
VOL
Output LOW Volt- VCC = Min., lol = 8.0 ma
age
–
0.4
–
0.4
–
0.4
V
ICC
VCC Operating
Supply Current
–
90
–
80
–
80
mA
ISB1
Automatic CE
VCC = Max., CE ≥ VIH, VIN ≥ VIH
Power-down Cur- or VIN ≤ VIL, f = FMAX
rent TTL Inputs
–
30
–
30
–
30
mA
ISB2
Automatic CE
VCC = Max., CE ≥ VCC - 0.3v,
Power-down Cur- VIN > VCC - 0.3v or VIN ≤ 0.3,f
rent CMOS Inputs = 0 Commercial
–
10
–
10
–
10
mA
IOZ
Output Leakage
Current
GND ≤ Vi ≤ VCC, Output Disabled
–5
+5
–5
+5
–5
+5
uA
IIX
Input Load Current
GND ≤ Vi ≤ VCC
–5
+5
–5
+5
–5
+5
uA
VCC = Max., IOUT = 0 mA, f =
FMAX = 1 / tRC
Capacitance4
Max
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
ALL - PACKAGES
Unit
TA = 25C, f = 1 MHz,
VCC = 5.0V
7
pF
10
Notes:
3. VIL (min) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05409 Rev. *A
Page 5 of 13
CY7C194B
CY7C195B
AC Test Loads
Output Loads
Output Loads
for tHZOE, tHZCE & tHZWE
R1
R3
VCC
VCC
Output
C1
R2
C2
(A)*
(B)*
Thevenin Equivalent
Output
Rth
R4
All Input Pulses
VCC
VT
VSS
90%
90%
10%
10%
Rise Time
1 V/ns
Fall Time
1 V/ns
* including scope and jig capacitance
AC Test Conditions
Parameter
C1
Description
Capacitor 1
Nom.
Unit
30
pF
C2
Capacitor 2
5
R1
Resistor 1
480
R2
Resistor 2
255
R3
Resistor 3
480
R4
Resistor 4
255
RTH
Resistor Thevenin
167
VTH
Voltage Thevenin
1.73
Ω
V
Thermal Resistance5
Parameter
Description
Conditions
28 SOJ
24 SOJ
28 DIP
24 DIP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
69
TBD
TBD
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
Still Air, soldered on a
3 x 4.5 square inches, two-layer printed
circuit board
29.84
TBD
TBD
TBD
Notes:
5. Test Conditions assume a transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
Document #: 38-05409 Rev. *A
Page 6 of 13
CY7C194B
CY7C195B
AC Electrical Characteristics2 6
7 8
12 ns
Parameter
Description
Min
15 ns
Max
Min
25 ns
Max
Min
Max
Unit
tRC
Read Cycle Time
12
–
15
–
25
–
ns
tAA
Address to Data Valid
–
12
–
15
–
25
ns
tOHA
Data Hold from Address
Change
3
–
3
–
3
–
ns
tACE
CE to Data Valid
–
12
–
15
–
25
ns
tDOE
OE to Data Valid
–
6
–
7
–
10
ns
tLZOE
OE to Low Z
0
–
0
–
0
–
ns
tHZOE
OE to High Z
–
5
–
7
–
10
ns
tLZCE
CE to Low Z
3
–
3
–
3
–
ns
tHZCE
CE to High Z
–
5
–
7
–
10
ns
tPU
CE to Power-up
0
–
0
–
0
–
ns
tPD
CE to Power-down
–
12
–
15
–
25
ns
tWC
Write Cycle Time
12
–
15
–
25
–
ns
tSCE
CE to Write End
9
–
10
–
18
–
ns
tAW
Address Set-up to Write End
9
–
10
–
20
–
ns
tHA
Address Hold from Write
End
0
–
0
–
0
–
ns
tSA
Address Set-up to Write
Start
0
–
0
–
0
–
ns
tPWE
WE Pulse Width
8
–
9
–
18
–
ns
tSD
Data Set-Up to Write End
7
–
8
–
10
–
ns
tHD
Data Hold from Write End
0
–
0
–
0
–
ns
tHZWE
WE LOW to High Z
–
6
–
7
-
10
ns
tLZWE
WE HIGH to Low Z
3
–
3
–
3
–
ns
Notes:
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
8. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage
Document #: 38-05409 Rev. *A
Page 7 of 13
CY7C194B
CY7C195B
Timing Waveforms
Read Cycle No. 1 9
10
tRC
Address
tAA
tOHA
Data Out
Previous Data Valid
Read Cycle No. 2 2 11
Data Valid
12
tRC
Address
CE
tHZCE
tACE
OE
tDOE
tHZOE
tLZOE
High Z
Data Out
VCC
Current
ICC
tLZCE
tPU
ISB
High Z
Data Valid
tPD
50%
50%
Notes:
9. Device is continuously selected. OE = VIL = CE.
10. WE is HIGH for Read Cycle.
11. This cycle is OE Controlled and WE is HIGH read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05409 Rev. *A
Page 8 of 13
CY7C194B
CY7C195B
Write Cycle No. 1 (WE Controlled) 2 13
14 15
tWC
Address
tSCE
CE
tAW
tHA
tPWE
tSA
WE
OE
tHZOE
Data In/Out
tSD
Undefined
Data-In Valid
see footnotes
Write Cycle No. 2 (CE Controlled)16
tHD
17 18
tWC
Address
tSCE
CE
tSA
tHA
tAW
WE
tSD
Data In/Out
High Z
Data-In Valid
tHD
High Z
Notes:
13. This cycle is WE controlled, OE is HIGH during write.
14. Data In/Out is high impedance if OE = VIH.
15. During this period the I/Os are in output state and input signals should not be applied.
16. This cycle is CE controlled.
17. Data In/Out is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05409 Rev. *A
Page 9 of 13
CY7C194B
CY7C195B
Write Cycle No. 3 (WE Controlled, OE Low) 2 19
t WC
Address
tSCE
CE
tAW
tHA
tPWE
tSA
WE
tSD
Data
In/Out
Undefined
tHD
Undefined
See Footnotes
Data-In Valid
see footnotes
tHZWE
tLZWE
Ordering Information
Speed
Ordering Code
Package
Name
Package Type
Power
Option
Operating
Range
12 ns
CY7C195B-12VC
V21
28 SOJ (8 x 18 x 3.5 mm)
Standard
Commercial
15 ns
CY7C194B-15PC
P13
24 DIP (6.6 x 31.8 x 3.5 mm)
Standard
Commercial
15 ns
CY7C194B-15VC
V13
24 SOJ (8 x 15 x 3.5 mm)
Standard
Commercial
15 ns
CY7C195B-15VC
V21
28 SOJ (8 x 18 x 3.5 mm)
Standard
Commercial
25 ns
CY7C194B-25VC
V13
24 SOJ (8 x 15 x 3.5 mm)
Standard
Commercial
25 ns
CY7C195B-25PC
P21
28 DIP (6.9 x 35.6 x 3.5 mm)
Standard
Commercial
Notes:
19. The cycle is WE controlled, OE low. The minimum write cycle time is the sum of tHZWE and tSD.
Document #: 38-05409 Rev. *A
Page 10 of 13
CY7C194B
CY7C195B
Package Diagram
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
28-Lead (300-Mil) Molded SOJ V21
MIN.
MAX.
DIMENSIONS IN INCHES
PIN 1 ID
14
DETAIL
A
EXTERNAL LEAD DESIGN
1
0.291
0.300
15
0.330
0.350
OPTION 1
0.697
0.713
Document #: 38-05409 Rev. *A
0.014
0.020
OPTION 2
SEATING PLANE
0.120
0.140
0.050
TYP.
0.026
0.032
0.013
0.019
28
A
0.004
0.025 MIN.
0.007
0.013
0.262
0.272
51-85031-*B
Page 11 of 13
CY7C194B
CY7C195B
Package Diagram (continued)
24-Lead (300-Mil) PDIP P13
51-85013-*B
28-Lead (300-Mil) Molded DIP P21
51-85014-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05409 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C194B
CY7C195B
Document History Page
Document Title: CY7C194B-CY7C195B 256 Kb (64K x 4) Static RAM
Document Number: 38-05409
REV.
ECN No.
Issue Date
Orig. of
Change
**
129234
09/16/03
HGK
New Data Sheet
*A
129786
09/18/03
AJU
Found typos in AC Electrical Characteristics table. Modified the following:
tSCE from 10, 12 and 20 to 9, 10 and 18;
tAW from 10, 12 and 20 to 9, 10 and 20;
tPWE from 10, 12 and 20 to 8, 9 and 18.
Document #: 38-05409 Rev. *A
Description of Change
Page 13 of 13
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