Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 AMC1304x-Q1 High-Precision, Reinforced Isolated Delta-Sigma Modulators with LDO 1 Features 3 Description • • The AMC1304-Q1 is a precision, delta-sigma (ΔΣ) modulator with the output separated from the input circuitry by a capacitive double isolation barrier that is highly resistant to magnetic interference. This barrier is certified to provide reinforced isolation of up to 7000 VPEAK according to the DIN V VDE V 0884-10, UL1577 and CSA standards. Used in conjunction with isolated power supplies, the device prevents noise currents on a high common-mode voltage line from entering the local system ground and interfering with or damaging low voltage circuitry. 1 • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified with the Following Results: – Temperature Grade 1: –40°C to +125°C – HBM ESD Classification Level 2 – CDM ESD Classification Level C6 Pin-Compatible Family with: – ±50-mV or ±250-mV Input Voltage Ranges – CMOS or LVDS Digital Interface Options Excellent DC Performance: – Offset Error: ±50 µV or ±100 µV (max) – Offset Drift: 1.3 µV/°C (max) – Gain Error: ±0.2% or ±0.3% (max) – Gain Drift: ±40 ppm/°C (max) Safety-Related Certifications: – 7000-VPK Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 – 5000-VRMS Isolation for 1 Minute per UL1577 – CAN/CSA No. 5A-Component Acceptance Service Notice Transient Immunity: 15 kV/µs (min) High Electromagnetic Field Immunity (see Application Note SLLA181A) External 5-MHz to 20-MHz Clock Input On-Chip 18-V LDO Regulator The input of the AMC1304-Q1 is optimized for direct connection to shunt resistors or other low voltagelevel signal sources. The unique low input voltage range of the ±50-mV device allows significant reduction of the power dissipation through the shunt while supporting excellent ac and dc performance. By using an appropriate digital filter (that is, as integrated on the TMS320F2807x or TMS320F2837x families) to decimate the bit stream, the device can achieve 16 bits of resolution with a dynamic range of 81 dB (13.2 ENOB) at a data rate of 78 kSPS. On the high-side, the modulator is supplied by an integrated low-dropout (LDO) regulator that allows an unregulated input voltage between 4 V and 18 V (LDOIN). The isolated digital interface operates from a 3.3-V or 5-V power supply (DVDD). The AMC1304-Q1 is available in a wide-body SOIC16 (DW) package. Device Information(1) 2 Applications • PART NUMBER Shunt-Based Current Sensing or Resistor-DividerBased Voltage Sensing In: – Traction Inverters – Onboard Chargers (OBC) – DC-DC Converters – Battery Management Systems (BMS) AMC1304x-Q1 PACKAGE SOIC (16) BODY SIZE (NOM) 10.30 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic Floating Power Supply AMC1304-Q1 4 V to 18 V LDOIN VCAP AGND RSHUNT AINN To Load AINP DVDD Reinforced Isolation HV+ 3.3 V or 5.0 V DGND TMS320F2837x DOUT SD-Dx CLKIN SD-Cx PWMx HV- Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configurations and Functions ....................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 1 1 1 2 3 4 5 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 21 21 21 24 Application and Implementation ........................ 25 9.1 Application Information............................................ 25 9.2 Typical Applications ................................................ 26 10 Power-Supply Recommendations ..................... 30 11 Layout................................................................... 31 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Power Ratings........................................................... 5 Insulation Specifications............................................ 6 Safety-Related Certifications..................................... 7 Safety Limiting Values .............................................. 7 Electrical Characteristics: AMC1304x05-Q1............. 8 Electrical Characteristics: AMC1304x25-Q1......... 10 Switching Characteristics ...................................... 12 Insulation Characteristics Curves ......................... 13 Typical Characteristics .......................................... 14 11.1 Layout Guidelines ................................................. 31 11.2 Layout Examples................................................... 31 12 Device and Documentation Support ................. 33 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 33 33 33 33 13 Mechanical, Packaging, and Orderable Information ........................................................... 34 Detailed Description ............................................ 21 4 Revision History 2 DATE REVISION NOTES February 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 5 Device Comparison Table DEVICE INPUT VOLTAGE RANGE DIFFERENTIAL INPUT RESISTANCE DIGITAL OUTPUT INTERFACE AMC1304L05-Q1 ±50 mV 5 kΩ LVDS AMC1304L25-Q1 ±250 mV 25 kΩ LVDS AMC1304M05-Q1 ±50 mV 5 kΩ CMOS AMC1304M25-Q1 ±250 mV 25 kΩ CMOS Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 3 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 6 Pin Configurations and Functions DW Package: LVDS Interface Versions (AMC1304Lx-Q1) 16-Pin SOIC Top View NC 1 16 DGND AINP 2 15 AINN 3 AGND DW Package: CMOS Interface Versions (AMC1304Mx-Q1) 16-Pin SOIC Top View NC 1 16 DGND NC AINP 2 15 NC 14 DVDD AINN 3 14 DVDD 4 13 CLKIN AGND 4 13 CLKIN NC 5 12 CLKIN_N NC 5 12 NC LDOIN 6 11 DOUT LDOIN 6 11 DOUT VCAP 7 10 DOUT_N VCAP 7 10 NC AGND 8 9 DGND AGND 8 9 DGND Pin Functions PIN NO. NAME I/O AMC1304Lx-Q1 (LVDS) AMC1304Mx-Q1 (CMOS) 4 4 — This pin is internally connected to pin 8 and can be left unconnected or tied to high-side ground 8 8 — High-side ground reference AINN 3 3 I Inverting analog input AINP 2 2 I Noninverting analog input CLKIN 13 13 I Modulator clock input, 5 MHz to 20.1 MHz CLKIN_N 12 — I Inverted modulator clock input DGND 9, 16 9, 16 — Controller-side ground reference DOUT 11 11 O Modulator data output DOUT_N 10 — O Inverted modulator data output DVDD 14 14 — Controller-side power supply, 3.0 V to 5.5 V. See the Power-Supply Recommendations section for decoupling recommendations. LDOIN 6 6 — Low dropout regulator input, 4 V to 18 V 1 1 — This pin can be connected to VCAP or left unconnected 5 5 — This pin can be left unconnected or tied to AGND only — 10, 12 — These pins have no internal connection 15 15 — This pin can be left unconnected or tied to DVDD only 7 7 — LDO output. See the Power-Supply Recommendations section for decoupling recommendations. AGND NC VCAP 4 Submit Documentation Feedback DESCRIPTION Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 7 Specifications 7.1 Absolute Maximum Ratings over the operating ambient temperature range (unless otherwise noted) (1) Supply voltage DVDD to DGND LDO input voltage LDOIN to AGND Analog input voltage at AINP, AINN Digital input voltage at CLKIN, CLKIN_N MIN MAX UNIT –0.3 6.5 V –0.3 26 V AGND – 6 3.7 V DGND – 0.3 DVDD + 0.3 V Input current to any pin except supply pins –10 Junction temperature, TJ Storage temperature, Tstg (1) –65 10 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2500 Charged device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V LDOIN LDO input supply voltage (LDOIN pin) 4.0 15.0 18.0 DVDD Digital (controller-side) supply voltage (DVDD pin) 3.0 3.3 5.5 V TA Operating ambient temperature range –40 125 °C 7.4 Thermal Information AMC1304x-Q1 THERMAL METRIC (1) DW (SOIC) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 80.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.5 °C/W RθJB Junction-to-board thermal resistance 45.1 °C/W ψJT Junction-to-top characterization parameter 11.9 °C/W ψJB Junction-to-board characterization parameter 44.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Power Ratings VALUE UNIT PD Maximum power dissipation (both sides) PARAMETER LDOIN = 18 V, DVDD = 5.5 V 161 mW PD1 Maximum power dissipation (high-side supply) LDOIN = 18 V 117 mW PD2 Maximum power dissipation (low-side supply) DVDD = 5.5 V, LVDS, RLOAD = 100 Ω 44 mW Copyright © 2017, Texas Instruments Incorporated TEST CONDITIONS Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 5 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 7.6 Insulation Specifications PARAMETER TEST CONDITIONS VALUE UNIT GENERAL Minimum air gap (clearance) (1) Shortest pin-to-pin distance through air ≥8 mm CPG Minimum external tracking (creepage) (1) Shortest pin-to-pin distance across the package surface ≥8 mm DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm) 0.027 mm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V Material group According to IEC 60664-1 CLR Overvoltage category per IEC 60664-1 I Rated mains voltage ≤ 300 VRMS I-IV Rated mains voltage ≤ 600 VRMS I-III Rated mains voltage ≤ 1000 VRMS I-II At ac voltage (bipolar or unipolar) 1414 VPK At ac voltage (sine wave) 1000 VRMS At dc voltage 1500 VDC VTEST = VIOTM, t = 60 s (qualification test) 7000 VTEST = 1.2 x VIOTM, t = 1 s (100% production test) 8400 Test method per IEC 60065, 1.2/50-μs waveform, VTEST = 1.6 x VIOSM = 10000 VPK (qualification) 6250 VPK Method a, after input/output safety test subgroup 2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 x VIORM = 1697 VPK, tm = 10 s ≤5 pC Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 x VIORM = 2263 VPK, tm = 10 s ≤5 pC Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 x VIORM = 2652 VPK, tm = 1 s ≤5 pC 1.2 pF > 109 Ω DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 (2) VIORM Maximum repetitive peak isolation voltage VIOWM Maximum-rated isolation working voltage VIOTM Maximum transient isolation voltage VIOSM Maximum surge isolation voltage (3) Apparent charge (4) qpd CIO Barrier capacitance, input to output (5) VIO = 0.5 VPP at 1 MHz RIO Insulation resistance, input to output (5) VIO = 500 V at TS = 150°C Pollution degree 2 Climatic category 40/125/21 VPK UL1577 VISO (1) (2) (3) (4) (5) 6 Withstand isolation voltage VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification test), VTEST = 1.2 x VISO = 6000 VRMS, t = 1 s (100% production test) 5000 VRMS Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier are tied together, creating a two-pin device. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 7.7 Safety-Related Certifications VDE UL Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60095 (VDE 0860): 2005-11 Recognized under UL1577 component recognition and CSA component acceptance NO 5 programs Reinforced insulation Single protection File number: 40040142 File number: E181974 7.8 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN IS Safety input, output, or supply current θJA = 80.2°C/W, LDOIN = 18 V, TJ = 150°C, TA = 25°C, see Figure 3 PS Safety input, output, or total power θJA = 80.2°C/W, TJ = 150°C, TA = 25°C, see Figure 4 TS Maximum safety temperature (1) TYP MAX UNIT 86.5 mA 1558 (1) mW 150 °C Input, output, or the sum of input and output power must not exceed this value. The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 7 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 7.9 Electrical Characteristics: AMC1304x05-Q1 All minimum and maximum specifications are at TA = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS VClipping Maximum differential voltage input range (AINP-AINN) FSR Specified linear full-scale range (AINP-AINN) VCM Operating common-mode input range CID Differential input capacitance IIB Input bias current RID Differential input resistance IIO Input offset current CMTI Common-mode transient immunity CMRR Common-mode rejection ratio BW ±62.5 –50 mV 50 –0.032 1.2 2 Inputs shorted to AGND –97 –72 mV V pF –57 5 μA kΩ ±5 nA 15 kV/μs fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max –98 fIN from 0.1 Hz to 50 kHz, VCM min ≤ VIN ≤ VCM max –85 dB Input bandwidth 800 kHz DC ACCURACY DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB INL Integral nonlinearity (1) Resolution: 16 bits –5 ±1.5 5 LSB EO Offset error –50 ±2.5 50 µV TCEO Offset error thermal drift 1.3 μV/°C EG Gain error TCEG Gain error thermal drift PSRR Initial, at 25°C (2) –1.3 Initial, at 25°C (3) Power-supply rejection ratio –0.3% –0.02% 0.3% –40 ±20 40 LDOIN from 4 V to 18 V, at dc –110 LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz –110 ppm/°C dB AC ACCURACY SNR Signal-to-noise ratio fIN = 1 kHz 76 81.5 SINAD Signal-to-noise + distortion fIN = 1 kHz 76 81 THD Total harmonic distortion fIN = 1 kHz SFDR Spurious-free dynamic range fIN = 1 kHz –90 81 dB dB –81 90 dB dB DIGITAL INPUTS/OUTPUTS External Clock fCLKIN Input clock frequency DutyCLKIN Duty cycle (1) (2) 20 20.1 50% 60% MHz value MAX value MIN TempRange Gain error drift is calculated using the box method, as described by the following equation: TCE G ( ppm ) 8 5 40% Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR). Offset error drift is calculated using the box method, as described by the following equation: TCE O (3) 5 MHz ≤ fCLKIN ≤ 20.1 MHz § value MAX value MIN ¨¨ © value u TempRange · ¸¸ u 10 6 ¹ Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Electrical Characteristics: AMC1304x05-Q1 (continued) All minimum and maximum specifications are at TA = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS Logic Family (AMC1304M05-Q1, CMOS with Schmitt Trigger) DGND ≤ VIN ≤ DVDD IIN Input current CIN Input capacitance VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 VIL Low-level input voltage –0.3 0.3 × DVDD CLOAD Output load capacitance VOH High-level output voltage VOL Low-level output voltage LVDS Logic Family (AMC1304L05-Q1) –1 1 5 fCLKIN = 20 MHz pF 30 IOH = –20 µA DVDD – 0.1 IOH = –4 mA DVDD – 0.4 μA V V pF V IOL = 20 µA 0.1 IOL = 4 mA 0.4 V (4) VT Differential output voltage VOC Common-mode output voltage VID Differential input voltage VIC Common-mode input voltage II Receiver input current RLOAD = 100 Ω 250 350 450 1.125 1.23 1.375 mV 100 350 600 VID = 100 mV 0.05 1.25 3.25 V DGND ≤ VIN ≤ 3.3 V –24 0 20 µA 4.0 15.0 18.0 V 5.3 6.5 mA V V mV POWER SUPPLY LDOIN LDOIN pin input voltage VCAP VCAP pin voltage ILDOIN LDOIN pin input current DVDD Controller-side supply voltage IDVDD (4) Controller-side supply current 3.45 3.0 V 3.3 5.5 LVDS, RLOAD = 100 Ω 6.1 8 CMOS, 3.0 V ≤ DVDD ≤ 3.6 V, CLOAD = 5 pF 2.7 4.0 CMOS, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 5 pF 3.2 5.5 mA For further information on electrical characteristics of LVDS interface circuits, see the TIA-644-A standard and design note Interface Circuits for TIA/EIA-644 (LVDS). Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 9 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 7.10 Electrical Characteristics: AMC1304x25-Q1 All minimum and maximum specifications are at TA = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS VClipping Maximum differential voltage input range (AINP-AINN) FSR Specified linear full-scale range (AINP-AINN) –250 VCM Operating common-mode input range –0.16 CID Differential input capacitance IIB Input bias current RID Differential input resistance IIO Input offset current CMTI Common-mode transient immunity CMRR Common-mode rejection ratio BW ±312.5 mV 250 1.2 1 Inputs shorted to AGND –82 –60 mV V pF –48 25 μA kΩ ±5 nA 15 kV/μs fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max –98 fIN from 0.1 Hz to 50 kHz, VCM min ≤ VIN ≤ VCM max –98 dB Input bandwidth 1000 kHz DC ACCURACY DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB INL Integral nonlinearity (1) Resolution: 16 bits –4 ±1.5 4 LSB EO Offset error Initial, at 25°C –100 ±25 100 µV TCEO Offset error thermal drift (2) 1.3 μV/°C EG Gain error TCEG Gain error thermal drift (3) PSRR –1.3 Initial, at 25°C Power-supply rejection ratio –0.2% –0.05% 0.2% –40 ±20 40 LDOIN from 4 V to 18 V, at dc –110 LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz –110 ppm/°C dB AC ACCURACY SNR Signal-to-noise ratio fIN = 1 kHz 82 85 SINAD Signal-to-noise + distortion fIN = 1 kHz 80 84 THD Total harmonic distortion fIN = 1 kHz SFDR Spurious-free dynamic range fIN = 1 kHz –90 81 dB dB –81 90 dB dB DIGITAL INPUTS/OUTPUTS External Clock fCLKIN Input clock frequency DutyCLKIN Duty cycle (1) (2) 20 20.1 50% 60% MHz value MAX value MIN TempRange . Gain error drift is calculated using the box method as described by the following equation: TCE G ( ppm ) 10 5 40% Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR. Offset error drift is calculated using the box method as described by the following equation: TCE O (3) 5 MHz ≤ fCLKIN ≤ 20.1 MHz § value MAX value MIN ¨¨ © value u TempRange · ¸¸ u 10 6 ¹ . Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Electrical Characteristics: AMC1304x25-Q1 (continued) All minimum and maximum specifications are at TA = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS Logic Family (AMC1304M25-Q1, CMOS with Schmitt Trigger) DGND ≤ VIN ≤ DVDD IIN Input current CIN Input capacitance VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 VIL Low-level input voltage –0.3 0.3 × DVDD CLOAD Output load capacitance VOH High-level output voltage VOL Low-level output voltage –1 1 μA 5 fCLKIN = 20 MHz pF V V 30 IOH = –20 µA DVDD – 0.1 IOH = –4 mA DVDD – 0.4 pF V V IOL = 20 µA 0.1 V IOL = 4 mA 0.4 V mV LVDS Logic Family (AMC1304L25-Q1) (4) VT Differential output voltage VOC Common-mode output voltage VID Differential input voltage VIC Common-mode input voltage II Receiver input current RLOAD = 100 Ω 250 350 450 1.125 1.23 1.375 100 350 600 VID = 100 mV 0.05 1.25 3.25 V DGND ≤ VIN ≤ 3.3 V –24 0 20 µA 4.0 15.0 18.0 V 5.3 6.5 mA V V mV POWER SUPPLY LDOIN LDOIN pin input voltage VCAP VCAP pin voltage ILDOIN LDOIN pin input current DVDD Controller-side supply voltage IDVDD (4) Controller-side supply current 3.45 3.0 V 3.3 5.5 LVDS, RLOAD = 100 Ω 6.1 8.0 CMOS, 3.0 V ≤ DVDD ≤ 3.6 V, CLOAD = 5 pF 2.7 4.0 CMOS, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 5 pF 3.2 5.5 mA For further information on electrical characteristics of LVDS interface circuits, see the TIA-644-A standard and design note Interface Circuits for TIA/EIA-644 (LVDS). Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 11 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 7.11 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tCLK CLKIN, CLKIN_N clock period 49.75 50 200 ns tHIGH CLKIN, CLKIN_N clock high time 19.9 25 120 ns tLOW CLKIN, CLKIN_N clock low time 19.9 25 120 ns tD Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay 0 15 ns tISTART Interface startup time DVDD at 3.0 V (min) to DOUT, DOUT_N valid with LDO_IN > 4 V 32 32 CLKIN cycles tASTART Analog startup time LDOIN step to 4 V with DVDD ≥ 3.0 V, and 0.1 µF at VCAP pin tCLK 1 ms tHIGH CLKIN CLKIN_N tLOW tD DOUT DOUT_N Figure 1. Digital Interface Timing DVDD CLKIN ... DOUT Data not valid Valid data tISTART = 32 CLKIN cycles Figure 2. Digital Interface Startup Timing 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 7.12 Insulation Characteristics Curves 100 1600 90 1400 80 1200 60 PS (mW) IS (mA) 70 50 40 1000 800 600 30 400 20 200 10 0 0 0 50 100 TA (°C) 150 200 0 50 100 TA (°C) D043 150 200 D044 LDOIN = 18 V (worst case) Figure 3. Thermal Derating Curve for Safety Limiting Current per VDE Figure 4. Thermal Derating Curve for Safety Limiting Power per VDE TA up to 150°C, stress voltage frequency = 60 Hz Figure 5. Reinforced Isolation Capacitor Lifetime Projection Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 13 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 7.13 Typical Characteristics At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. AMC1304x05-Q1 AMC1304x25-Q1 AMC1304x05-Q1 AMC1304x25-Q1 Figure 7. Common-Mode Rejection Ratio vs Input Signal Frequency 4 4 3 3.5 2 3 1 2.5 INL (|LSB|) INL (LSB) Figure 6. Input Current vs Input Common-Mode Voltage 0 -1 2 1.5 -2 1 -3 0.5 -4 -50 -40 -30 -20 -10 0 10 VIN (mV) 20 30 40 0 -40 50 100 50 80 40 60 30 40 20 20 10 EO (µV) EO (µV) -10 5 20 35 50 65 Temperature (°C) 0 -20 95 110 125 D004 0 -10 -40 -20 -60 -30 -80 -40 -100 80 Figure 9. Integral Nonlinearity vs Temperature Figure 8. Integral Nonlinearity vs Input Signal Amplitude -50 4 6 8 10 12 VLDOIN (V) 14 16 18 D005 AMC1304x25-Q1 Figure 10. Offset Error vs LDO Input Supply Voltage 14 -25 D003 Submit Documentation Feedback 4 6 8 10 12 VLDOIN (V) 14 16 18 D006 AMC1304x05-Q1 Figure 11. Offset Error vs LDO Input Supply Voltage Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Typical Characteristics (continued) 100 50 80 40 60 30 40 20 20 10 EO (µV) EO (µV) At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. 0 -20 0 -10 -40 -20 -60 -30 -80 -40 -100 -40 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 -50 -40 110 125 -25 -10 5 D007 AMC1304x25-Q1 20 35 50 65 Temperature (qC) 80 95 110 125 D008 AMC1304x05-Q1 Figure 12. Offset Error vs Temperature Figure 13. Offset Error vs Temperature 0.3 AMC1304x05-Q1 AMC1304x25-Q1 0.2 EG (%FS) 0.1 0 -0.1 -0.2 -0.3 4 0.3 0.2 0.2 0.1 0.1 0 10 12 VLDOIN (V) 14 16 18 D010 0 -0.1 -0.1 -0.2 -0.2 -0.3 -40 8 Figure 15. Gain Error vs LDO Input Supply Voltage 0.3 EG (%FS) EG (%FS) Figure 14. Offset Error vs Clock Frequency 6 -0.3 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 Figure 16. Gain Error vs Temperature Copyright © 2017, Texas Instruments Incorporated D011 5 10 15 fCLKIN (MHz) 20 D012 Figure 17. Gain Error vs Clock Frequency Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 15 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Typical Characteristics (continued) At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. 0 SNR (AMC1304x05-Q1) SINAD (AMC1304x05-Q1) SNR (AMC1304x25-Q1) SINAD (AMC1304x25-Q1) -20 PSRR (dB) -40 -60 -80 -100 -120 0.001 0.01 0.1 1 Ripple Frequency (kHz) 10 100 D013 Figure 18. Power-Supply Rejection Ratio vs Ripple Frequency Figure 19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs LDO Input Supply Voltage SNR (AMC1304x05-Q1) SINAD (AMC1304x05-Q1) SNR (AMC1304x25-Q1) SINAD (AMC1304x25-Q1) SNR (AMC1304x05-Q1) SINAD (AMC1304x05-Q1) SNR (AMC1304x25-Q1) SINAD (AMC1304x25-Q1) Figure 21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Clock Frequency Figure 20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Temperature 100 SNR SINAD 95 90 SNR and SINAD (dB) SNR (AMC1304x05-Q1) SINAD (AMC1304x05-Q1) SNR (AMC1304x25-Q1) SINAD (AMC1304x25-Q1) 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 VIN (mVpp) 350 400 450 500 D018 AMC1304x25-Q1 Figure 22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Frequency 16 Submit Documentation Feedback Figure 23. SNR and SINAD vs Input Signal Amplitude Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Typical Characteristics (continued) At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. -60 100 SNR SINAD -65 90 -70 85 -75 80 -80 THD (dB) SNR and SINAD (dB) 95 75 70 -85 -90 65 -95 60 -100 55 -105 -110 50 0 10 20 30 40 50 60 VIN (mVpp) 70 80 90 4 100 6 8 10 12 VLDOIN (V) D019 14 16 18 D020 AMC1304x05-Q1 Figure 25. Total Harmonic Distortion vs LDO Input Supply Voltage -60 -60 -65 -65 -70 -70 -75 -75 -80 -80 THD (dB) THD (dB) Figure 24. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Amplitude -85 -90 -90 -95 -95 -100 -100 -105 -105 -110 -40 -110 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 5 110 125 -65 -70 -70 -75 -75 -80 -80 THD (dB) -65 -90 20 D022 Figure 27. Total Harmonic Distortion vs Clock Frequency -60 -85 15 fCLKIN (MHz) -60 -85 -90 -95 -95 -100 -100 -105 -105 -110 0.1 10 D021 Figure 26. Total Harmonic Distortion vs Temperature THD (dB) -85 -110 1 10 fIN (kHz) 100 D023 0 50 100 150 200 250 300 VIN (mVpp) 350 400 450 500 D024 AMC1304x25-Q1 Figure 28. Total Harmonic Distortion vs Input Signal Frequency Copyright © 2017, Texas Instruments Incorporated Figure 29. Total Harmonic Distortion vs Input Signal Amplitude Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 17 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Typical Characteristics (continued) -60 110 -65 105 -70 100 -75 95 SFDR (dB) THD (dB) At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. -80 -85 -90 90 85 80 -95 75 -100 70 -105 65 60 -110 0 50 100 150 VIN (mVpp) 4 6 8 10 12 VLDOIN (V) D025 14 16 18 D026 AMC1304x05-Q1 Figure 31. Spurious-Free Dynamic Range vs LDO Input Supply Voltage 110 110 105 105 100 100 95 95 SFDR (dB) SFDR (dB) Figure 30. Total Harmonic Distortion vs Input Signal Amplitude 90 85 80 90 85 80 75 75 70 70 65 65 60 -40 60 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 5 110 125 105 100 100 95 95 SFDR (dB) SFDR (dB) 110 105 85 80 20 D028 Figure 33. Spurious-Free Dynamic Range vs Clock Frequency 110 90 15 fCLKIN (MHz) Figure 32. Spurious-Free Dynamic Range vs Temperature 90 85 80 75 75 70 70 65 65 60 0.1 10 D027 60 1 10 fIN (kHz) 100 D029 0 50 100 150 200 250 300 VIN (mVpp) 350 400 450 500 D030 AMC1304x25-Q1 Figure 34. Spurious-Free Dynamic Range vs Input Signal Frequency 18 Submit Documentation Feedback Figure 35. Spurious-Free Dynamic Range vs Input Signal Amplitude Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Typical Characteristics (continued) At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. 110 0 105 -20 100 -40 Magnitude (dB) SFDR (dB) 95 90 85 80 75 -60 -80 -100 70 -120 65 60 -140 0 50 100 150 VIN (mVpp) 0 AMC1304x05-Q1 15 20 25 Frequency (kHz) 30 35 40 D032 Figure 37. Frequency Spectrum with 1-kHz Input Signal 0 0 -20 -20 -40 -40 Magnitude (dB) Magnitude (dB) 10 AMC1304x05-Q1, 4096-point FFT, VIN = 100 mVPP Figure 36. Spurious-Free Dynamic Range vs Input Signal Amplitude -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 15 20 25 Frequency (kHz) 30 35 0 40 5 10 D033 15 20 25 Frequency (kHz) 30 35 40 D034 AMC1304x25-Q1, 4096-point FFT, VIN = 500 mVPP AMC1304x05-Q1, 4096-point FFT, VIN = 100 mVPP Figure 39. Frequency Spectrum with 1-kHz Input Signal Figure 38. Frequency Spectrum with 5-kHz Input Signal 0 10 -20 9 -40 8 ILDOIN (mA) Magnitude (dB) 5 D031 -60 -80 7 6 -100 5 -120 4 -140 3 0 5 10 15 20 25 Frequency (kHz) 30 35 40 D035 4 6 8 10 12 VLDOIN (V) 14 16 18 D036 AMC1304x25-Q1, 4096-point FFT, VIN = 500 mVPP Figure 40. Frequency Spectrum with 5-kHz Input Signal Copyright © 2017, Texas Instruments Incorporated Figure 41. LDO Input Supply Current vs LDO Input Supply Voltage Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 19 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Typical Characteristics (continued) At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, unless otherwise noted. 10 12 11 9 10 8 8 ILDOIN (mA) ILDOIN (mA) 9 7 6 5 7 6 5 4 3 4 2 1 -40 3 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 5 110 125 Figure 42. LDO Input Supply Current vs Temperature D038 12 LVDS CMOS 11 10 10 9 9 8 8 IDVDD (mA) IDVDD (mA) 20 Figure 43. LDO Input Supply Current vs Clock Frequency LVDS CMOS 11 7 6 5 7 6 5 4 4 3 3 2 2 1 1 4.5 3 3.1 3.2 3.3 DVDD (V) 3.4 3.5 3.6 D039 Figure 44. Controller-Side Supply Current vs Controller-Side Supply Voltage (3.3 V, min) 4.6 4.7 4.8 4.9 5 5.1 DVDD (V) 5.2 5.3 5.4 5.5 D040 Figure 45. Controller-Side Supply Current vs Controller-Side Supply Voltage (5 V, min) 12 12 LVDS 5 V LVDS 3.3 V CMOS 5 V CMOS 3.3 V 11 10 9 10 9 8 7 6 5 8 7 6 5 4 4 3 3 2 2 1 -40 1 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D041 Figure 46. Controller-Side Supply Current vs Temperature Submit Documentation Feedback LVDS 5 V LVDS 3.3 V CMOS 5 V CMOS 3.3 V 11 IDVDD (mA) IDVDD (mA) 15 fCLKIN (MHz) 12 20 10 D037 5 10 15 Clock Frequency (MHz) 20 D042 Figure 47. Controller-Side Supply Current vs Clock Frequency Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 8 Detailed Description 8.1 Overview The differential analog input (AINP and AINN) of the AMC1304-Q1 is a fully-differential amplifier feeding the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a 1-bit output stream. The isolated data output (DOUT and DOUT_N) of the converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 5 MHz to 20.1 MHz. The time average of this serial bit-stream output is proportional to the analog input voltage. The Functional Block Diagram section shows a detailed block diagram of the AMC1304-Q1. The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the ISO72x Digital Isolator Magnetic-Field Immunity application report (SLLA181A), available for download at www.ti.com. The external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The extended frequency range of up to 20 MHz supports higher performance levels compared to the other solutions available on the market. 8.2 Functional Block Diagram DVDD VCAP Voltage Regulator (LDO) BUF TX + TX AINN 1.25-V Reference Receiver BUF BUF Isolation Barrier û -Modulator DOUT DOUT_N (AMC1304Lx-Q1 only) Interface AINP Receiver LDOIN TX CLKIN CLKIN_N (AMC1304Lx-Q1 only) TX AMC1304-Q1 AGND DGND Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Analog Input The AMC1304-Q1 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for devices with a specified input voltage range of ±250 mV (this value is for the AMC1304x25-Q1), or to a factor of 20 in devices with a ±50-mV input voltage range (for the AMC1304x05-Q1), resulting in a differential input impedance of 5 kΩ (for the AMC1304x05-Q1) or 25 kΩ (for the AMC1304x25-Q1). Consider the input impedance of the AMC1304-Q1 in designs with high-impedance signal sources that can cause degradation of gain and offset specifications. The importance of this effect, however, depends on the desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at the output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal. See the Isolated Voltage Sensing section for more details on reducing these effects. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 21 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Feature Description (continued) There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the range AGND – 6 V to 3.7 V, the input current must be limited to 10 mA because the device input electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is ±250 mV (for the AMC1304x25-Q1) or ±50 mV (for the AMC1304x05-Q1), and within the specified input common-mode range. 8.3.2 Modulator The modulator implemented in the AMC1304-Q1 is a second-order, switched-capacitor, feed-forward ΔΣ modulator, such as the one conceptualized in Figure 48. The analog input voltage VIN and the output V5 of the 1bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage V5, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input. fCLKIN V1 V2 V3 Integrator 1 VIN V4 Integrator 2 CMP 0V V5 DAC Figure 48. Block Diagram of a Second-Order Modulator The modulator shifts the quantization noise to high frequencies, as shown in Figure 49. Therefore, use a lowpass digital filter at the output of the device to increase the overall performance. This filter is also used to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1304-Q1 family. Alternatively, a field-programmable gate array (FPGA) can be used to implement the digital filter. 0 Magnitude (dB) -20 -40 -60 -80 -100 -120 -140 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 49. Quantization Noise Shaping 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Feature Description (continued) 8.3.3 Digital Output A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 250 mV (for the AMC1304x25-Q1) or 50 mV (for the AMC1304x05-Q1) produces a stream of ones and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1304x05-Q1) produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified linear ranges of the different AMC1304-Q1 versions with performance as specified in this data sheet. If the input voltage value exceeds these ranges, the output of the modulator shows non-linear behavior when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to –312.5 mV (–62.5 mV for the AMC1304x05-Q1) or with a stream of only ones with an input greater than or equal to 312.5 mV (62.5 mV for the AMC1304x05-Q1). In this case, however, the AMC1304-Q1 generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in Figure 50. The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using Equation 1: V IN V Clipping 2 * V Clipping (1) The AMC1304-Q1 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details, see the Switching Characteristics table. Modulator Output +FS (Analog Input) -FS (Analog Input) Analog Input Figure 50. Analog Input versus AMC1304-Q1 Modulator Output Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 23 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 8.4 Device Functional Modes 8.4.1 Fail-Safe Output In the case of a missing high-side supply voltage (LDOIN), the output of a ΔΣ modulator is not defined and can cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. Therefore, the AMC1304-Q1 implements a fail-safe output function that ensures the device maintains its output level in case of a missing LDOIN, as shown in Figure 51. CLKIN LDOIN LDOIN GOOD LDOIN FAIL DOUT DOUT Figure 51. Fail-Safe Output of the AMC1304-Q1 8.4.2 Output Behavior in Case of a Full-Scale Input If a full-scale input signal is applied to the AMC1304-Q1 (that is, VIN ≥ VClipping), the device generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52. In this way, differentiating between a missing LDOIN and a full-scale input signal is possible on the system level. CLKIN ... DOUT DOUT ... VIN ” -312.5 mV (AMC1304x05-Q1: -61.5 mV) ... ... ... ... VIN • 312.5 mV (AMC1304x05-Q1: 61.5 mV) 127 CLKIN cycles 127 CLKIN cycles Copyright © 2016, Texas Instruments Incorporated Figure 52. Overrange Output of the AMC1304-Q1 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Digital Filter Usage The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort and hardware, is a sinc3-type filter, as shown in Equation 2: § 1 z OSR · ¸ H ( z ) ¨¨ 1 ¸ © 1 z ¹ 3 (2) This filter provides the best output performance at the lowest hardware size (count of digital gates) for a secondorder modulator. All the characterization in this document is also done with a sinc3 filter with an oversampling ratio (OSR) of 256 and an output word duration of 16 bits. The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. Figure 53 shows the ENOB of the AMC1304-Q1 with different oversampling ratios. In this document, this number is calculated from the SNR by using Equation 3: SNR 1.76dB 6.02dB * ENOB (3) 16 14 ENOB (bits) 12 10 8 6 4 sinc1 sinc2 sinc3 2 0 1 10 100 OSR 1000 D053 Figure 53. Measured Effective Number of Bits versus Oversampling Ratio An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications application note (SBAA094), available for download at www.ti.com. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 25 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 9.2 Typical Applications 9.2.1 Traction Inverter Application Isolated ΔΣ modulators are being widely used in new-generation traction inverter designs because of their high ac and dc performance. Traction inverters are critical parts of electrical and hybrid electrical vehicles. The input structure of the AMC1304-Q1 is optimized for use with low-impedance shunt resistors and is therefore tailored for isolated current sensing using shunts. DC link Gate Driver Gate Driver Gate Driver RSHUNT L1 RSHUNT RSHUNT Gate Driver Gate Driver L3 L2 Gate Driver AMC1304-Q1 15 V 3.3 V TMS320F28x7x LDOIN DVDD AINP DOUT SD-D1 AINN CLKIN SD-C1 AGND DGND AMC1304-Q1 15 V AMC1304-Q1 AMC1304-Q1 15 V 15 V 3.3 V LDOIN DVDD AINP DOUT SD-D2 AINN CLKIN SD-C2 AGND DGND 3.3 V 3.3 V LDOIN DVDD LDOIN DVDD AINP DOUT AINP DOUT SD-D3 AINN CLKIN AINN CLKIN SD-C3 AGND DGND AGND DGND PWMx SD-D4 SD-C4 Copyright © 2016, Texas Instruments Incorporated Figure 54. The AMC1304-Q1 in a Traction Inverter Application 9.2.1.1 Design Requirements A typical operation of the device in a traction inverter application is shown in Figure 54. When the inverter stage is part of a motor drive system, measurement of the motor phase current is done via the shunt resistors (RSHUNT). Depending on the system design, either all three or only two phase currents are sensed. In this example, an additional fourth AMC1304-Q1 is used to support isolated voltage sensing of the dc link. This high voltage is reduced using a high-impedance resistive divider before being sensed by the device across a smaller resistor. The value of this resistor can degrade the performance of the measurement, as described in the Isolated Voltage Sensing section. 9.2.1.2 Detailed Design Procedure The typically recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the signal path is not required for the AMC1304-Q1. By design, the input bandwidth of the analog front-end of the device is limited to 1 MHz. For modulator output bit-stream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers (MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These families support up to eight channels of dedicated hardwired filter structures that significantly simplify system level design by offering two filtering paths per channel: one providing high accuracy results for the control loop and one fast response path for overcurrent detection. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Typical Applications (continued) 9.2.1.3 Application Curve In motor control applications, a very fast response time for overcurrent detection is required. The time for fully settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc3 filter requires three data updates for full settling (with fDATA = fCLK / OSR). Therefore, for overcurrent protection, filter types other than sinc3 can be a better choice; an alternative is the sinc2 filter. Figure 55 compares the settling times of different filter orders. The delay time of the sinc filter with a continuous signal is half of its settling time. 16 14 ENOB (bits) 12 10 8 6 4 sinc1 sinc2 sinc3 2 0 0 2 4 6 8 10 12 settling time (µs) 14 16 18 20 D054 Figure 55. Measured Effective Number of Bits versus Settling Time Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 27 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Typical Applications (continued) 9.2.2 Isolated Voltage Sensing The AMC1304-Q1 is optimized for usage in current-sensing applications using low-impedance shunts. However, the device can also be used in isolated voltage-sensing applications if the affect of the (usually higher) impedance of the resistor used in this case is considered. High Voltage Potential 15 V R1 AMC1304-Q1 LDOIN R2 R4 AINP IIB - rID R3 R5 û Modulator + AINN R3' R4' R5' AGND VCM = 2 V GND Copyright © 2016, Texas Instruments Incorporated Figure 56. Using the AMC1304-Q1 for Isolated Voltage Sensing 9.2.2.1 Design Requirements Figure 56 shows a simplified circuit typically used in high-voltage-sensing applications. The high impedance resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of the sensing resistor R3 is chosen to meet the input voltage range of the AMC1304-Q1. This resistor and the differential input impedance of the device (the AMC1304x25-Q1 is 25 kΩ, the AMC1304x05-Q1 is 5 kΩ) also create a voltage divider that results in an additional gain error. With the assumption of R1, R2, and RIN having a considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with EG being the gain error of the AMC1304-Q1. EGtot = EG + R3 RIN (4) This gain error can be easily minimized during the initial system-level gain calibration procedure. 9.2.2.2 Detailed Design Procedure As indicated in Figure 56, the output of the integrated differential amplifier is internally biased to a common-mode voltage of 2 V. This voltage results in a bias current IIB through the resistive network R4 and R5 (or R4' and R5') used for setting the gain of the amplifier. The value range of this current is specified in the Electrical Characteristics table. This bias current generates additional offset error that depends on the value of the resistor R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as illustrated in Figure 57), the initial system offset calibration does not minimize its effect. Therefore, in systems with high accuracy requirements, TI recommends using a series resistor at the negative input (AINN) of the AMC1304-Q1 with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 56) to eliminate the affect of the bias current. 28 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 Typical Applications (continued) This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1304x05-Q1) or 12.5 kΩ (for the AMC1304x25-Q1). EG (%) § ¨1 © R4 · ¸ * 100 % R 4' R 3' ¹ (5) 9.2.2.3 Application Curve Figure 57 shows the dependency of the input bias current on the common-mode voltage at the input of the AMC1304-Q1. AMC1304x05-Q1 AMC1304x25-Q1 Figure 57. Input Current vs Input Common-Mode Voltage 9.2.3 Do's and Don'ts Do not leave the inputs of the AMC1304-Q1 unconnected (floating) when the device is powered up. If both modulator inputs are left floating, the input bias current drives them to the output common-mode of the analog front end of approximately 2 V that is above the specified input common-mode range. As a result, the front gain diminishes and the modulator outputs a bitstream resembling a zero input differential voltage. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 29 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 10 Power-Supply Recommendations In a typical traction-inverter application, the high-side power supply (LDOIN) for the device is directly derived from the floating power supply of the upper gate driver. A low-ESR decoupling capacitor of 0.1 µF is recommended for filtering this power-supply path. Place this capacitor (C2 in Figure 58) as close as possible to the LDOIN pin of the AMC1304-Q1 for best performance. If better filtering is required, an additional 10-µF capacitor can be used. The output of the internal LDO requires a decoupling capacitor of 0.1 µF to be connected between the VCAP pin and AGND as close as possible to the device. The floating ground reference (AGND) is derived from the end of the shunt resistor, which is connected to the negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads and AGND is connected to one of the outer leads of the shunt. For decoupling of the digital power supply on the controller side, TI recommends using a 0.1-µF capacitor assembled as close to the DVDD pin of the AMC1304-Q1 as possible, followed by an additional capacitor in the range of 1 µF to 10 µF. HV+ Floating Power Supply 18 V (max) AMC1304-Q1 LDOIN Gate Driver C1 10 F 3.3 V or 5.0 V DVDD C2 0.1 F C4 0.1 F VCAP C5 2.2 F DGND C3 0.1 F TMS320F28x7x AGND RSHUNT To Load AINN DOUT SD-Dx AINP CLKIN SD-Cx PWMx Gate Driver HV- Copyright © 2016, Texas Instruments Incorporated Figure 58. Decoupling the AMC1304-Q1 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 11 Layout 11.1 Layout Guidelines A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the AMC1304-Q1) and placement of the other components required by the device is shown in Figure 59. For best performance, place the shunt resistor close to the VINP and VINN inputs of the AMC1304-Q1 and keep the layout of both connections symmetrical. For the AMC1304Lx-Q1 version, place the 100-Ω termination resistor as close as possible to the CLKIN, CLKIN_N inputs of the device to achieve highest signal integrity. If not integrated, an additional termination resistor is required as close as possible to the LVDS data inputs of the MCU or filter device; see Figure 60. 11.2 Layout Examples Top View Clearance area, to be kept free of any conductive materials. Shunt resistor NC 1 16 DGND AINP NC AINN DVDD AGND CLKIN 0.1 µF 2.2 µF SMD 0603 SMD 0603 AMC1304Mxx-Q1 0.1 µF To Floating Power Supply LEGEND SMD 0603 NC NC LDOIN DOUT VCAP NC AGND DGND To or From MCU (Filter) Top Layer: Copper Pour and Traces 0.1 µF High-Side Area Controller-Side Area SMD 0603 Via to Ground Plane Via to Supply Plane Copyright © 2016, Texas Instruments Incorporated Figure 59. Recommended Layout of the AMC1304Mx-Q1 Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 31 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com Layout Examples (continued) Top View Clearance area, to be kept free of any conductive materials. Shunt resistor NC 1 16 DGND AINP NC AINN DVDD AGND CLKIN AMC1304Lxx-Q1 0.1 µF SMD 0603 To Floating Power Supply LEGEND NC CLKIN_N 0.1 µF 2.2 µF SMD 0603 SMD 0603 100 : SMD 0603 To or From MCU (Filter) LDOIN DOUT VCAP DOUT_N AGND DGND 100 : Top Layer: Copper Pour and Traces High-Side Area Controller-Side Area 0.1 µF SMD 0603 SMD 0603 Via to Ground Plane Via to Supply Plane Copyright © 2016, Texas Instruments Incorporated Figure 60. Recommended Layout of the AMC1304Lx-Q1 32 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 www.ti.com SBAS799 – FEBRUARY 2017 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • TMS320F2807x Piccolo™ Microcontrollers • TMS320F2837xD Dual-Core Delfino™ Microcontrollers • Isolation Glossary • ISO72x Digital Isolator Magnetic-Field Immunity • Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY AMC1304L05-Q1 Click here Click here Click here Click here Click here AMC1304L25-Q1 Click here Click here Click here Click here Click here AMC1304M05-Q1 Click here Click here Click here Click here Click here AMC1304M25-Q1 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 33 AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1 SBAS799 – FEBRUARY 2017 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 34 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2017 PACKAGING INFORMATION Orderable Device Status (1) AMC1304M25QDWRQ1 PREVIEW Package Type Package Pins Package Drawing Qty SOIC DW 16 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 125 1304M25Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Feb-2017 OTHER QUALIFIED VERSIONS OF AMC1304M25-Q1 : • Catalog: AMC1304M25 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. 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