TI CDCLVP111RHBT Low-voltage 1:10 lvpecl with selectable input clock driver Datasheet

CDCLVP111
www.ti.com
SCAS859D – JANUARY 2009 – REVISED MARCH 2010
LOW-VOLTAGE 1:10 LVPECL
WITH SELECTABLE INPUT CLOCK DRIVER
Check for Samples: CDCLVP111
FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
•
Distributes One Differential Clock Input Pair
LVPECL to 10 Differential LVPECL
Fully Compatible With LVECL/LVPECL
Supports a Wide Supply Voltage Range From
2.375 V to 3.8 V
Selectable Clock Input Through CLK_SEL
Low-Output Skew (Typ 15 ps) for
Clock-Distribution Applications
– Additive Jitter Less Than 1 ps
– Propagation Delay Less Than 350 ps
– Open Input Default State
– LVDS, CML, SSTL input compatible
VBB Reference Voltage Output for
Single-Ended Clocking
Available in a 32-Pin LQFP and QFN Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With MC100 Series
EP111, ES6111, LVEP111, PTN1111
Designed for Driving 50 Ω Transmission Lines
High Performance Clock Distribution
LQFP AND QFN PACKAGE
(TOP VIEW)
PowerPAD
(0)
DESCRIPTION
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of
differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can
accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω
transmission lines. When an output pin is not used, leaving it open is recommended to reduce power
consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically
terminated to 50 Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin
should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP111 is characterized for operation from –40°C to 85°C.
Table 1. FUNCTION TABLE
CLK_SEL
ACTIVE CLOCK INPUT
0
CLK0, CLK0
1
CLK1, CLK1
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
CDCLVP111
SCAS859D – JANUARY 2009 – REVISED MARCH 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
31
30
29
28
27
26
24
3
CLK0
CLK0
+
4
-
CLK1
CLK1
23
0
22
21
6
+
7
-
20
1
19
-
18
17
CLK_SEL
2
15
14
-
13
12
11
VBB
5
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
PIN FUNCTIONS (1)
PIN
NAME
CLK_SEL
DESCRIPTION
NO.
2
CLK0, CLK0
3, 4
CLK1, CLK1
6, 7
Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality
compatible.
Differential LVECL/LVPECL input pair
Q [9:0]
11, 13, 15, 18,
20, 22, 24, 27,
29, 31
LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn.
Q[9:0]
10, 12, 14, 17,
19, 21,23, 26,
28, 30
LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn.
VBB
5
VCC
1, 9, 16, 25, 32
VEE
8
Device ground or negative supply voltage in ECL mode
PowerPAD™
0
The PowerPAD of the QFN32 and LQFP package is thermally connected to the die to improve the heat
transfer out of the package. The pad of the LQFP with PowerPAD must be left floating or connected to
VEE. The pad of the QFN32 with PowerPAD must be connected to VEE.
(1)
2
Reference voltage output for single-ended input operation
Supply voltage
CLKn, CLK_SEL pull down resistor = 75 kΩ; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ.
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SCAS859D – JANUARY 2009 – REVISED MARCH 2010
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.3 to 4.6
V
Input voltage
–0.3 to VCC + 0.5
V
VO
Output voltage
–0.3 to VCC + 0.5
V
IIN
Input current
±20
mA
VEE
Negative supply voltage (Relative to VCC)
–4.6 to 0.3
V
IBB
Sink/source current
–1 to 1
mA
IO
DC output current
–50
mA
Tstg
Storage temperature range
–65 to 150
°C
TJ
Maximum operating junction temperature
125
°C
VCC
Supply voltage (Relative to VEE)
VI
(1)
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage (relative to VEE)
TA
Operating free-air temperature
TJ
Operating junction temperature
MIN
NOM
MAX
2.375
2.5/3.3
3.8
V
85
°C/W
110
°C
–40
UNIT
PACKAGE THERMAL IMPEDANCE, VF (LQFP)
qJA
qJC
(1)
TEST CONDITION
VALUE
UNIT
0 LFM
74
°C/W
150 LFM
66
°C/W
250 LFM
64
°C/W
500 LFM
61
°C/W
39
°C/W
TEST CONDITION
VALUE
UNIT
0 LFM
49
°C/W
150 LFM
37
°C/W
250 LFM
36
°C/W
500 LFM
32
°C/W
19
°C/W
Thermal resistance junction to ambient (1)
Thermal resistance junction to case
According to JESD 51-7 standard.
PACKAGE THERMAL IMPEDANCE, RHB (QFN)
qJA
qJC
(1)
Thermal resistance junction to ambient (1)
Thermal resistance junction to case
According to JESD 51-7 standard.
LVECL DC ELECTRICAL CHARACTERISTICS
Vsupply: VCC = 0 V, VEE = -2.375 V to -3.8 V over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IEE
Supply internal
current
ICC
Output and internal All outputs terminated 50 Ω to
supply current
VCC – 2 V
IIN
Input current
Absolute value of current
Includes pullup/pulldown
resistors,
VIH = VCC, VIL = VCC - 2 V
MIN
–40°C, 25°C, 85°C
40
TYP
MAX
85
–40°C
354
25°C
380
85°C
405
–40°C, 25°C, 85°C
–150
150
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UNIT
mA
mA
mA
3
CDCLVP111
SCAS859D – JANUARY 2009 – REVISED MARCH 2010
www.ti.com
LVECL DC ELECTRICAL CHARACTERISTICS (continued)
Vsupply: VCC = 0 V, VEE = -2.375 V to -3.8 V over operating free-air temperature range (unless otherwise noted)
PARAMETER
VBB
Internally
generated bias
voltage
TEST CONDITIONS
MIN
TYP
MAX
For VEE = –3 to –3.8 V,
IBB = –0.2 mA
–40°C, 25°C, 85°C
–1.45
–1.3
–1.15
VEE = –2.375 to –2.75 V,
IBB = –0.2 mA
-40°C, 25°C, 85°C
–1.4
–1.25
–1.1
UNIT
V
VIH
High-level input
voltage (CLK_SEL)
–40°C, 25°C, 85°C
–1.165
–0.88
V
VIL
Low-level input
voltage (CLK_SEL)
–40°C, 25°C, 85°C
–1.81
–1.475
V
VID
Input amplitude
(CLKn, CLKn)
–40°C, 25°C, 85°C
0.5
1.3
V
VCM
Common-mode
voltage (CLKn,
CLKn)
–40°C, 25°C, 85°C
VEE + 1
–0.3
V
–1.26
–0.85
VOH
High-level output
voltage
25°C
–1.2
–0.85
85°C
–1.15
–0.85
–40°C
–1.85
–1.5
25°C
–1.85
–1.45
85°C
–1.85
–1.4
Difference of input
, See (1)
VIH - VIL
DC offset relative to VEE
–40°C
VOL
VOD
(1)
Low-level output
voltage
Differential output
voltage swing
IOH = –21 mA
IOL = –5 mA
Terminated with 50 Ω to
VCC –2 V, See Figure 3
–40°C, 25°C, 85°C
600
V
V
mV
VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV.
LVPECL DC ELECTRICAL CHARACTERISTICS
Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IEE
Supply internal
current
ICC
Output and internal All outputs terminated 50 Ω to
supply current
VCC - 2 V
Absolute value of current
MIN
-40°C, 25°C, 85°C
TYP
40
MAX
85
-40°C
354
25°C
380
85°C
405
Includes pullup/pulldown
resistors
VIH=VCC, VIL= VCC–2V
-40°C, 25°C, 85°C
–150
VCC = 3 to 3.8 V, IBB= –0.2 mA
-40°C, 25°C, 85°C
VCC – 1.45
VCC – 1.3
VCC – 1.15
VCC = 2.375 to 2.75 V, IBB =
–0.2 mA
-40°C, 25°C, 85°C
VCC – 1.4
VCC – 1.25
VCC – 1.1
mA
mA
IIN
Input current
VBB
Internally
generated bias
voltage
VIH
High-level input
voltage (CLK_SEL)
-40°C, 25°C, 85°C
VCC – 1.165
VCC – 0.88
V
VIL
Low-level input
voltage (CLK_SEL)
-40°C, 25°C, 85°C
VCC – 1.81
VCC – 1.475
V
VID
Input amplitude
(CLKn, CLKn)
-40°C, 25°C, 85°C
0.5
1.3
V
VCM
Common-mode
voltage (CLKn,
CLKn)
-40°C, 25°C, 85°C
1
VCC – 0.3
V
VCC – 1.26
VCC – 0.85
VOH
High-level output
voltage
25°C
VCC – 1.2
VCC – 0.85
85°C
VCC – 1.15
VCC – 0.85
Difference of input
, see (1)
VIH - VIL
DC offset relative to VEE
-40°C
(1)
4
IOH = -21 mA
150
UNIT
mA
V
V
VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV.
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SCAS859D – JANUARY 2009 – REVISED MARCH 2010
LVPECL DC ELECTRICAL CHARACTERISTICS (continued)
Vsupply: VCC = 2.375 V to 3.8 V, VEE= 0 V over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-level output
voltage
VOL
Differential output
voltage swing
VOD
IOL = -5 mA
Terminated with 50 Ω to
VCC - 2 V, See Figure 3
MIN
TYP
MAX
-40°C
VCC – 1.85
VCC – 1.5
25°C
VCC – 1.85
VCC – 1.45
85°C
VCC – 1.85
VCC – 1.4
-40°C, 25°C, 85°C
UNIT
V
600
mV
AC ELECTRICAL CHARACTERISTICS
Vsupply: VCC = 2.375 V to 3.8 V, VEE = 0 V or LVECL/LVPECL input VCC = 0 V, VEE = -2.375 V to -3.8 V over operating
free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpd
Differential propagation delay CLKn,
CLKn to all Q0, Q0… Q9, Q9
See
tsk(o)
Output-to-output skew
See , and Figure 1
tsk(pp)
Part-to-part skew
See , and Figure 1
taj
Additive phase jitter
Integration bandwidth of 20 kHz to 20 MHz,
fout = 125 MHz at 25°C
f(max)
Maximum frequency
Functional up to 3.5 GHz, see Figure 3
tr/tf
Output rise and fall time (20%, 80%)
See
MIN
TYP
200
15
0.04
90
MAX
UNIT
350
ps
30
ps
70
ps
< 0.8
ps
3500
MHz
200
ps
CLKn
CLKn
Q0
tPLH0
tPLH0
tPLH1
tPLH1
Q0
Q1
Q1
Q2
tPLH2
tPLH2
Q2
tPLH9
o
o
o
o
o
Q9
tPLH9
Q9
A.
Output skew is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) or
the difference between the fastest and the slowest tPHLn (n = 0, 1,...9).
B.
Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0,
1,...9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9) across
multiple devices.
C.
Typical value measured at ambient when clock input is 155.52MHz for an integration bandwidth of 20 kHz to 5 MHz.
D.
Input conditions: VCM = 1 V, VID = 0.5 V and FIN = 1GHz.
Figure 1. Waveform for Calculating Both Output and Part-to-Part Skew
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5
CDCLVP111
SCAS859D – JANUARY 2009 – REVISED MARCH 2010
www.ti.com
VCC
ZO = 50 Ω
Yn
CDCLVP111
Driver
LVPECL
Receiver
ZO = 50 Ω
Yn
50 Ω
50 Ω
VEE
VT = VCC - 2 V
Figure 2. Typical Termination for Output Driver (See the Interfacing Between LVPECL, LVDS, and CML
Application Note, Literature Number SCAA056)
VODtyp - Differential Output Voltage Swing - mV
DIFFERENTIAL OUTPUT VOLTAGE SWING
vs
FREQUENCY
900
800
Worst Case Condition,
VCC = 2.375 V,
o
TA = 85 C
700
600
500
400
300
200
100
0
1
1.5
2
2.5
3
3.5
f - Frequency - GHz
Figure 3. LVPECL Input Using CLK0 Pair, VCM = 1 V, VID = 0.5 V
6
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SCAS859D – JANUARY 2009 – REVISED MARCH 2010
REVISION HISTORY
Changes from Original (January 2009) to Revision A
Page
•
Changed note referneces within the AC ELECTRICAL CHARACTERISTICS table ............................................................ 5
•
Added a Typ value of 0.04ps to the Additive phase jitter in the AC ELECTRICAL CHARACTERISTICS ........................... 5
Changes from Revision A (March 2009) to Revision B
•
Page
Added LVTTL/LVCMOS functionality compatible. ................................................................................................................ 2
Changes from Revision B (April 2009) to Revision C
Page
•
Changed PowerPAD information to the Pinout Package ..................................................................................................... 1
•
Added PowerPAD information to the Pin Functions table .................................................................................................... 2
Changes from Revision C (November 2009) to Revision D
Page
•
Changed the PowerPAD description in the PIN FUNCTIONS table to include the LQFP package information. ................. 2
•
Deleted duplicate information covering the PowerPAD from Note 1 of the Pin Functions table. ......................................... 2
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7
PACKAGE OPTION ADDENDUM
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5-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCLVP111RHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCLVP111RHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCLVP111VF
ACTIVE
LQFP
VF
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCLVP111VFR
ACTIVE
LQFP
VF
32
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Mar-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCLVP111RHBR
Package Package Pins
Type Drawing
QFN
RHB
32
CDCLVP111RHBT
QFN
RHB
CDCLVP111VFR
LQFP
VF
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.0
12.0
Q2
3000
330.0
12.4
5.3
5.3
1.5
32
250
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
32
1000
330.0
16.4
9.6
9.6
1.9
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Mar-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCLVP111RHBR
QFN
RHB
32
3000
340.5
333.0
20.6
CDCLVP111RHBT
QFN
RHB
32
250
340.5
333.0
20.6
CDCLVP111VFR
LQFP
VF
32
1000
333.2
345.9
28.6
Pack Materials-Page 2
MECHANICAL DATA
MTQF002B – JANUARY 1995 – REVISED MAY 2000
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,45
0,25
0,80
24
0,20 M
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,05 MIN
0,25
0°– 7°
1,45
1,35
Seating Plane
0,75
0,45
0,10
1,60 MAX
4040172/D 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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