BSN045NE2LS OptiMOSTM Power-MOSFET Product Summary Features • Optimized for high performance Buck converter • Very low parasitic inductance • Low profile (<0.5 mm) • Double side cooling • N-channel VDS 25 V RDS(on),max 4.5 mW ID 50 A QOSS 7.6 nC QG(0V..10V) 11 nC • 100% avalanche tested • Very low on-resistance R DS(on) @ V GS=4.5 V LG-USON-6-1 • Pb-free lead plating; RoHS compliant • Halogen-free according to IEC61249-2-21 • Qualified according to JEDEC1) for target applications Type Package Marking BSN045NE2LS LG-USON-6-1 045NE2L Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value V GS=10 V, T C=25 °C 50 V GS=10 V, T C=100 °C 47 V GS=4.5 V, T C=25 °C 50 V GS=4.5 V, T C=100 °C 39 V GS=10 V, T A=25 °C, R thJA=50 K/W 2) 19 Pulsed drain current3) I D,pulse T C=25 °C 200 Avalanche current, single pulse4) I AS T C=25 °C 35 Avalanche energy, single pulse E AS I D=35 A, R GS=25 W 5 Gate source voltage V GS 1) ±20 Unit A mJ V J-STD20 and JESD22 Rev. 2.0 page 1 2014-05-23 BSN045NE2LS Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Power dissipation P tot Value T C=25 °C 39 T A=25 °C, T j, T stg -55 ... 150 IEC climatic category; DIN IEC 68-1 Parameter W 2.5 R thJA=50 K/W 2) Operating and storage temperature Unit °C 55/150/56 Values Symbol Conditions Unit min. typ. max. bottom - - 3.2 top - - 1 6 cm2 cooling area2) - - 50 Thermal characteristics Thermal resistance, junction - case Device on PCB R thJC R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 25 - - Gate threshold voltage V GS(th) V DS=V GS, I D=250 µA 1.2 - 2 Zero gate voltage drain current I DSS V DS=30 V, V GS=0 V, T j=25 °C - 0.1 1 V µA V DS=30 V, V GS=0 V, T j=125 °C - 10 100 Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=30 A - 5.2 6.5 V GS=10 V, I D=30 A - 3.8 4.5 0.4 0.8 1.6 W 39 78 - S nA mW Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=30 A 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 3) See figure 3 for more detailed information Rev. 2.0 page 2 2014-05-23 BSN045NE2LS Parameter Values Symbol Conditions Unit min. typ. max. - 780 1100 - 290 400 Dynamic characteristics Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 32 - Turn-on delay time t d(on) - 1.8 - Rise time tr - 3.4 - Turn-off delay time t d(off) - 12 - Fall time tf - 2.4 - Gate to source charge Q gs - 2.2 3 Gate charge at threshold Q g(th) - 1.3 - Gate to drain charge Q gd - 1.4 2 Switching charge Q sw - 2.4 - Gate charge total Qg - 5.3 7 Gate plateau voltage V plateau - 2.8 - Gate charge total Qg V DD=15 V, I D=30 A, V GS=0 to 10 V - 11 15 Gate charge total, sync. FET Q g(sync) V DS=0.1 V, V GS=0 to 4.5 V - 4.5 - Output charge Q oss V DD=15 V, V GS=0 V - 7.6 10 - - 36 - - 200 V GS=0 V, V DS=15 V, f =1 MHz V DD=15 V, V GS=10 V, I D=30 A, R G,ext=1.6 W pF ns Gate Charge Characteristics5) V DD=15 V, I D=30 A, V GS=0 to 4.5 V nC V nC Reverse Diode Diode continuous forward current IS Diode pulse current I S,pulse Diode forward voltage V SD V GS=0 V, I F=30 A, T j=25 °C - 0.9 Reverse recovery charge Q rr V R=15 V, I F=I S, di F/dt =400 A/µs - 5 4) 5) A T C=25 °C V - nC See figure 13 for more detailed information See figure 16 for gate charge parameter definition Rev. 2.0 page 3 2014-05-23 BSN045NE2LS 1 Power dissipation 2 Drain current P tot=f(T C) I D=f(T C); V GS≥10 V 45 60 40 50 35 40 25 ID [A] Ptot [W] 30 30 20 15 20 10 10 5 0 0 0 40 80 120 160 0 40 80 TC [°C] 120 160 TC [°C] 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 103 10 limited by on-state resistance 1 µs 102 0.5 1 10 µs 0.2 0.1 0.05 101 ZthJC [K/W] ID [A] DC 100 µs 10 ms 0.02 0.01 0.1 single pulse 1 ms 100 0.01 10-1 0.001 10-1 100 101 102 VDS [V] Rev. 2.0 10-6 10-5 10-4 10-3 10-2 10-1 100 tp [s] page 4 2014-05-23 BSN045NE2LS 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 200 10 10 V 8V 5V 9 3.2 V 150 8 4.5 V 3.5 V ID [A] RDS(on) [mW] 7 100 3.3 V 4V 6 4.5 V 5 5V 7V 4 8V 10 V 3 50 2 2.8 V 1 0 0 1 2 0 3 0 VDS [V] 10 20 30 40 50 ID [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 160 240 140 120 160 ID [A] gfs [S] 100 80 60 80 40 25 °C 150 °C 20 0 0 0 1 2 3 4 0 5 Rev. 2.0 20 40 60 80 100 ID [A] VGS [V] page 5 2014-05-23 BSN045NE2LS 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=30 A; V GS=10 V V GS(th)=f(T j); V GS=V DS; I D=250 µA 8 2 6 1.5 VGS(th) [V] 2.5 RDS(on) [mW] 10 4 1 typ 2 0.5 0 0 -60 -20 20 60 100 140 180 -60 -20 20 Tj [°C] 60 100 140 180 Tj [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 104 103 1000 10000 100 1000 150 °C 25 °C 102 IF [A] C [pF] Ciss Coss 10 100 Crss 101 1 10 0 10 20 30 0.2 VDS [V] Rev. 2.0 0.6 1 1.4 VSD [V] page 6 2014-05-23 BSN045NE2LS 13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 W V GS=f(Q gate); I D=30 A pulsed parameter: T j(start) parameter: V DD 100 12 15 V 10 5V 25 V 8 VGS [V] IAV [A] 25 °C 10 6 100 °C 4 125 °C 2 1 0 1 10 100 1000 0 3 tAV [µs] 6 9 12 15 Qgate [nC] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=1 mA 28 V GS 27 Qg VBR(DSS) [V] 26 25 24 V gs(th) 23 22 Q g(th) Q sw 21 Q gs Q gate Q gd 20 -60 -20 20 60 100 140 180 Tj [°C] Rev. 2.0 page 7 2014-05-23 BSN045NE2LS Package Outline LG-USON-6-1 LG-USON-6-1: Outline Rev. 2.0 page 8 2014-05-23 BSN045NE2LS Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 2.0 page 9 2014-05-23