AN2067 Application note VIPower™: dimmable white LED power supply with the VIPer53-E Introduction LED manufacturers propose white LEDs inside a monolithic chip, or single-chip white LED. A current source is the most appropriate way to drive LEDs. A large voltage range must be supported on the output due to the threshold of these white LEDs. Furthermore, these dimmed LEDs must be driven by a PWM (current generator). As a consequence, the key feature for this offline power supply is a current generator, which can work as a pulse width-modulated mode, with a wide output voltage range, and with any input voltage standard, and a galvanic isolation. The VIPer53-E, the first multichip device of the VIPer® family, has a very low RDS(on) of 1 Ω allowing a typical power of 35 W in wide range in a standard DIP8 package without a heatsink. Thanks to a lower power dissipation, the VIPer53-E meets higher efficiency and reduced space. Some general features: – The block diagram is given in Figure 1. An adjustable oscillator drives a current controlled PWM at a fixed switching frequency. – The peak drain current is set for each cycle by the voltage present on the COMP pin. – The useful range of the COMP pin extends from 0.5 V to 4.5 V, with a corresponding drain current range from 0 A to 2 A. This COMP pin can be either used as an input in case of secondary feedback configuration, or as an output when the internal error amplifier connected on the VDD pin operates in primary feedback to regulate the VDD voltage to 15 V. The VDD undervoltage comparator drives a high voltage start-up current source, which switches off during the normal operation of the device. This feature together with the burst mode capability allows a very low level of input power in standby mode, when the converter is lightly loaded. Table 1. White LED power supply specifications Parameter Name Conditions Output current IOUT VOUT = 20 V Output voltage VOUT IOUT = 1 A Output power POUT Input voltage VIN November 2014 Min. Max. Unit 200 1000 mA 5 40 V 40 W 265 VAC 82 DocID10973 Rev 2 Typ. 1/25 www.st.com 25 Contents AN2067 Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 White LED power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 Primary section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.2 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.3 Secondary section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.4 Current regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Dimming purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Dimming in the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.3 Audible noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.4 Dynamic behavior of the current regulation loop . . . . . . . . . . . . . . . . . . . 9 2.2.5 Voltage limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 No-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Short-circuit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Low voltage load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Primary inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Primary auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2.1 Secondary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Secondary auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 Transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Switching cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 2/25 Dynamic response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Discrete load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 LED load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DocID10973 Rev 2 AN2067 6 Contents 5.2 Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 Voltage limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 Power supply efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 Efficiency vs output power (VIN=100 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 Extreme load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DocID10973 Rev 2 3/25 25 Block diagram 1 AN2067 Block diagram Figure 1. VIPer53-E block diagram 26& '5$,1 212)) 26&,//$725 3:0 /$7&+ 29(57(03 '(7(&725 5 6 %/$1.,1*7,0( 6(/(&7,21 )) 4 5 5 5 5 9 +&203 9 89/2 &203$5$725 QV %/$1.,1* 9'' 9 3:0 &203$5$725 67$1'%< &203$5$725 9 9 &855(17 $03/,),(5 9 N 9 (5525 $03/,),(5 9 29(5/2$' &203$5$725 29(592/7$*( &203$5$725 9 9 729/ 1.1 &203 6285&( Overload protection 4.35 V typical threshold is present on the COMP pin. This overload threshold is 150 mV below the clamping voltage of 4.5 V, which corresponds to the current limitation of the device. In case of a COMP voltage exceeds the overload threshold, the pull- up resistor on TOVL pin is released and the external capacitor connected on this pin begins to charge. When a value of 4 V typical is reached, the device stops switching and remains in this state until the VDD voltage reaches VDDoff, or resumes the normal operation if the COMP voltage returns to a value below the overload threshold. The drain current that the device delivers without triggering the overload threshold is called “current capability”, specified as IDmax in the datasheet. This value sizes correctly the converter versus its maximum output power. When an overload occurs on secondary side of the converter, the output power is limited by the current limitation of the device. If this overload lasts more than a constant time defined by a capacitor connected on the TOVL pin, the device is reset, and a new sequence starts by turning on the start-up current source. Capacitors on the VDD pin and on the TOVL pin are defined together in order to insure a correct startup and a low restart duty cycle in overload or short-circuit operation. Below the equations: 4/25 DocID10973 Rev 2 AN2067 Block diagram C OVL > 12.5 × 10 –6 ⋅ T SS C OVL ⋅ I DDch2 1 4 C VDD > 8 × 10 ⋅ -------------- – 1 ⋅ ----------------------------------D RST V DDhyst I DD1 ⋅ t SS C VDD > ------------------------ V DDhyst Where tss and DRST are respectively the time needed for the output voltages to pass from 0 V to their nominal values at startup, and the restart duty cycle in overload or short-circuit condition. A typical value of 10% is generally set for this last parameter, as it insures that the output diodes and the transformer don't overheat. The other parameters can be found in the datasheet of the device. As the VDD capacitor has to respect two conditions, the maximum value defines its value. 1.2 Standby operation On the opposite load configuration, the converter is lightly loaded and the COMP voltage decreases until the shutdown threshold is reached at typically 0.5 V. At this point, the switching is disabled and energy doesn’t pass to secondary side. So, the output voltage decreases and the regulation loop rises again above the shutdown threshold, thus the normal switching operation is resumed. A burst mode with pulse skipping takes place, as long as the output power is below the one corresponding to the minimum turn-on of the device. As the COMP voltage works at 0.5 V, the peak drain current is very low (it is defined by the minimum turn-on time of the device, and by the primary winding of the transformer) and no audible noise is generated. In addition, the minimum turn-on time depends on the COMP voltage. Below 1 V (VCOMPbl), the blanking time increases till 400 ns, whereas it is 150 ns for higher voltages. The minimum turn-on time, resulting from these values, is respectively 600 ns and 350 ns, when the internal propagation time is taken into account. This feature brings the following benefits: – This change induces the hysteresis between the normal operation and burst mode which is reached when the output power decreases. – A short value in normal operation assures a good drain current control in case of short-circuit on secondary side. – A long value in standby operation reinforces the burst mode by skipping the switching cycles, thus decreasing the switching losses. Further details regarding the standby operation can be found in the datasheet. DocID10973 Rev 2 5/25 25 White LED power supply AN2067 2 White LED power supply 2.1 Schematic The power topology is an offline flyback, working at a fixed frequency of 66 kHz. The overall schematic is presented in Figure 2. 2.1.1 Primary section On the left side of the schematic, the fuse F1, inrush current limiter CTN1, input filter T1, followed by the rectifier BR1 and its bulk capacitance C3 can be found. R4, C4 and D4 build the RCD clamper, to discharge the leakage inductance of the transformer. D2, R2 and C5 are the rectifiers and filters of the primary auxiliary winding, used in forward mode (refer to Section 3). This generates a voltage supply from 21 V up to 80 V, proportional to turn ratio between main primary winding and auxiliary primary winding, and versus input voltage range (110 VAC up to 250 VAC). A serial voltage regulator is required to supply the VIPer53-E with the correct voltage (around 12 V). It is built with R14, DZ14, Q1 and C12. The VCE0 of the transistor must be higher than 80 V. This transistor may also dissipate 0.7 W when the input voltage is 250 VAC. The COMP pin filter is made of C8, R9 and C9. 2.1.2 Transformer A current generator may have a large output voltage variation, according to the output load. If the auxiliary winding is used in flyback mode, a wide voltage variation on auxiliary winding may happen, as it is proportional to the reflected voltage. So, it is used in forward mode in order to limit the voltage variation to supply the VIPer53-E. In order to guarantee the functionality even with low output voltage load, an auxiliary winding at secondary side has been added. This auxiliary winding is also used in forward mode. 6/25 DocID10973 Rev 2 DocID10973 Rev 2 &7 &71 $&,1387 & Q)9 ) $ &20021 02'( ),/7(5 7 & Q)9 %5 $9 & X)9 & X)9 '= 9: & X)9 5 .: 4 1 & Q) 5 . 5 & Q) 729/ 9'' 9 & Q) 26& & Q)9 '5$,1 & Q) 5 . &203 6285&( 9,3(5 ' %$6 ' (%5 5 .: 7 &B<&$3 Q).9 8% 3& ' %$6 ' 677+ 5 5 & X)9 & X)9 / + 5 . 8 & Q) 760 5 . 8$ 3& & X)9 5 & Q) *1' 9UHI 9&& & Q) 5 . 5 5 . 5 . & Q) 5 . 5 5 . 3 .$ - 95(),1387 $287387 AN2067 White LED power supply Figure 2. Current generator schematic *,3*07 7/25 25 White LED power supply 2.1.3 AN2067 Secondary section On the right side of the schematic, the secondary winding is used in flyback mode. D101, C112 are respectively the rectifying diode and its filtering. L101 and C110 build another lowpass filter. The auxiliary secondary winding, used in forward mode (refer to Section 3) in association with R122, D122 and C121, builds the rectifier and filtering for the supply of the regulation loop, using a dedicated component (TSM101). This supply is independent from the load voltage. The TSM101 has been designed as voltage and current controller, which can be used for the control of a current generator, in association with a voltage limitation. It includes its own reference voltage (bandgap), and two operational amplifiers. 2.1.4 Current regulation loop The output current is sensed through the shunt resistor R100. The shunt voltage is amplified using R101 and R107 in association with one op-amp of the TSM101, building the error amplifier. The current target is set through the trimmer P101. R103 and P101 provide a fraction of the reference voltage provided by the TSM101 (U103). There is also another way to set the current target, using the connector J107 for dimming (see Section 5.4). C113 with R107 is the integrator network of this amplifier, in order to cancel the static error of the regulation loop. The regulation loop continues with the optocoupler U2 (diode and transistor). The level of the COMP pin filter sets the peak drain current of the VIPer53-E (current control mode). Thus, the energy stored inside the transformer during each cycle is transferred to the secondary side, supplying the output current. R131 and C131 are a phase lead network to compensate the phase delay due to L101/C110 filter. 2.2 Dimming 2.2.1 Dimming purpose The main purpose of this application is to supply “single-chip white LEDs”, and to dim the brightness of these LEDs. Since white color is obtained by two peaks in the spectrum (a blue ray and a yellow ray), there is a dependency on the driving current and the white color spectrum. 2.2.2 Dimming in the application This application proposes how to apply an external PWM signal to the node VREF_INPUT. Provided that output impedance of the generator is not higher than 50 Ω, the input voltage is forced by the external generator instead of the DC reference voltage of the TSM101. The low level voltage of this PWM signal must be 0 V, and the high level voltage must be around 1 V. The peak current of the PWM generator can be set using the trimmer P101, as in DC mode, from 0 up to 1 A. 8/25 DocID10973 Rev 2 AN2067 White LED power supply The allowed maximum frequency is limited by the dynamic behavior of the PWM current generator (refer to Section 2.2.4). The best way to use this power supply, is to set the lowest frequency convenient for human eye versus flicker. The higher the period, the higher the dimming range. 2.2.3 Audible noise When the power supply with a PWM signal is used, some audible noise may be heard, especially if the frequency of the external signal is inside the audible range. This noise is emitted by the core of the transformer, and is a normal way to work. This noise is proportional to the output power transferred through it. This noise can be reduced by the optimization of the transformer. 2.2.4 Dynamic behavior of the current regulation loop As explained above, the power supply has to generate a PWM current, at a sufficient frequency in order to avoid flicker, with the possibility to adjust the duty cycle. The time response of the regulation loop should be short so to be linear (from 0% up to 100% characteristics of the dimming range). Thanks to LED threshold, its current can be pulsed and the voltage can be maintained to avoid charging and discharging the output capacitance. Since the output filtering capacitance is quite wide, this helps the dynamic behavior of the current generator. The dynamic behavior of this current generator is limited by several root causes in the whole schematic. The first origin of limitation is the RC couple R101 + R107 / C113. When the reference level changes on the error amplifier (TSM101 pin 5), the op-amp moves to the new operating point, by charging the node TSM101 pin 3. This is limited by the charging of the capacitor C113 through the resistor R101 + R107. Secondly, the filtering capacitance C121 must be large enough to properly sustain the supply voltage of the op-amp and the resistor R102. During a transient, the op-amp has to compensate its output level for the loop stabilization. The dynamic behavior is limited by the discharging/charging of the capacitor C113 through the resistor R102, once the supply voltage of the amplifier is stable during that transient. Third, the serial resistance of the load, the shunt resistance R100, and the serial resistor of the capacitor C112 limit the time response of the current generator. When the output current switches from off (low current level) to on (high current level), the output voltage has to increase as per below formula: Δv out = ΔI out ⋅ ( R sload + R shunt ) The output current capability is limited until the charging of the capacitance C112 is not completed. When this capacitor is charged, then the current capability is available for the load itself. DocID10973 Rev 2 9/25 25 White LED power supply 2.2.5 AN2067 Voltage limitation The output voltage limitation is built by R106, R105, R108, C114 and the corresponding opamp of the TSM101. R106, R105 create a bridge divider of the output voltage, in order to compare the fraction with the reference voltage of the TSM101. The voltage limit is set by the below formula: R105 + R106 V out = V ref ⋅ ----------------------------------- R105 If the voltage limit is reached, the cable AND of the TSM101 allows the voltage limitation circuit to force the whole loop and reduce the output power. The stability of the voltage limitation loop is given by R108 and C114. Against electrical shocks, the limit is set to 40 V, as advised by safety standards. 2.3 No-load operation The design of the VIPer53-E refers to burst mode in case of low load output. The application designer doesn’t enter hiccup mode (or bad burst mode) when no-load is connected. Resistors R106 and R105 have been designed in the application to have the VIPer53-E in burst mode when no-load is connected. The current is drawn into R106 and R105, dissipating the power transferred to the secondary side of the transformer during the burst mode and using the minimum turn-on time (see Figure 7, Figure 9 and Section 5.7, Figure 17 for measurements). 2.4 Short-circuit operation Due to current generator structure, in case of short-circuit any malfunction or damage can occur. The current is limited and the output power is low in that condition (refer to Section 5.7 and Figure 18 for measurements). 2.5 Low voltage load In case of low voltage load (less than 4 V on output), some instability problems may occur, (inductive or capacitive load). Since poles and zeros change a lot, the whole transfer function is instable. This instability may be associated to audible noise due to some low frequency oscillations. The user must avoid loads with a voltage below than 4 V, in order to ensure a correct operation of the power supply. 10/25 DocID10973 Rev 2 AN2067 Transformer design 3 Transformer design 3.1 Primary inductance The primary inductance is set to 0.5 mH, according to the output power required, and the current capability of the VIPer53-E. The VIPer53-E software helps to define the number of turns of the primary inductance. It provides a result of 52 turns, in 2 wires. A diameter of 0.4 mm has been chosen. 3.2 Primary auxiliary winding To guarantee a correct operation, the VIPer53-E should be supplied with at least 12.8 V. This winding is also used in forward mode. The turn ratio between primary winding and primary auxiliary winding according to the minimum input voltage (100 VDC) is 0.18. 0.21 is the value used with 11 turns on auxiliary. At maximum input voltage (400 VDC), the auxiliary supply is 85 V. This provides a constraint on the voltage regulator for the VIPer53E. 3.2.1 Secondary winding The output voltage may vary from 4 V to 40 V, and the reflected voltage must not exceed 100 V. The turn ratio should be 0.5 (26 turns) in order to avoid current mode instability. A diameter of 0.7 mm is provided by the VIPer53-E software. 3.3 Secondary auxiliary winding This secondary auxiliary output must guarantee a voltage from 6 V to maximum 32 V (supply voltage range of the TSM101). The turn ratio is 0.077 (4 turns). This provides a supply voltage from 7.7 V up to 30.8 V, which is in line with the specification of the TSM101. 3.4 Transformer specifications Table 2 shows the specifications of the power supply transformer. DocID10973 Rev 2 11/25 25 Measurements 4 AN2067 Measurements Measurements on the application board have been performed at room temperature (27 °C), using an open application board, in still-air conditions. Static measurements have been performed using a programmable electronic load as a voltage generator (so called “static load”). In order to be as closer as possible to the LED load, a discrete voltage generator, as described in Figure 3 (so called “dynamic load”) has been used, in line to the serial resistance and parasitic capacitance. Figure 3. Discrete voltage load *,3*07 12/25 DocID10973 Rev 2 AN2067 5 Switching cycle Switching cycle Figure 4 and Figure 5 show the drain voltage and drain current respectively in discontinuous mode and continuous mode, with a 40 W static load, and input voltage respectively at 400 V and 100 V. Figure 7 and Figure 9 present drain voltage, drain current, VCOMP and VOUT voltage in burst mode. The output (static) load is 4 W (40 V, 100 mA), and input voltage is respectively at 100 V and 400 V. Table 2. Transformer specifications Parameter Primary inductance Primary auxiliary winding Secondary winding Secondary auxiliary winding Max. current Turn ratio Number of turns Number of wires Wire (mm) Lprim: 0.5 mH Lleak < 4 µH (0.8%) core: E25H 52 2 0.4 2.3 0.211 11 1 ~0.2 <0.1 0.5 26 1 0.7 1 0.077 4 1 ~0.2 <0.1 Figure 4. Discontinuous mode (40 W/VIN=400 V) (A) Figure 5. Burst mode (PLOAD=4 W; VIN=100 V) DocID10973 Rev 2 13/25 25 Switching cycle AN2067 Figure 6. Continuous mode (40 W/VIN=100 V) Figure 7. Burst mode (PLOAD=4 W; VIN=400 V) Figure 8. Dynamic response 50% duty cycle at 100 Hz 5.1 Dynamic response 5.1.1 Discrete load An external signal is applied to connector J107 (node VREF_IN), to replace the static internal reference voltage of the TSM101 with a PWM signal. The amplitude of this signal is 0 V (low level), 1 V (high level) in order to get the full range up to 1 A. The frequency of this signal is 100 Hz. The generator allows the duty cycle of this (PWM) signal to be adjusted from 10% up to 90%. The load used during these measurements is a discrete load (dynamic load). 14/25 DocID10973 Rev 2 AN2067 Switching cycle Figure 9. Dynamic response 10% duty cycle at 100 Hz Figure 8, Figure 9 and Figure 10 show the dynamic response of the current generator, when used in PWM mode, respectively with 50%, 10% and 90% of duty cycle. 10% and 90% of duty cycle at 100 Hz, is roughly the minimum and maximum duty cycle to get an acceptable shape for the current pulse. The minimum turn-on/off time is 1 ms with a maximum frequency of 500 Hz (2 ms period) Figure 10. Dynamic response 90% duty cycle at 100 Hz 5.1.2 LED load Figure 11 and Figure 12 represent the dynamic response on real load, respectively on 4 white LEDs, and 1 white LED. The dynamic response is worst than the discrete load and also worst with 4 LEDs than 1 LED. This typically shows the LED serial resistance limitation, as explained in Section 2.2.4. The poor dynamic response on LED load is due to the discrete load, which has different serial resistances. There is a margin of improvement on LED load, until the signal VCOMP doesn’t reach its maximum value (4.5 V). Poles and zeros may be tuned in order to improve VCOMP and IOUT dynamic response. DocID10973 Rev 2 15/25 25 Switching cycle AN2067 Figure 11. Dynamic response on 4 white LEDs Figure 12. Dynamic response on 1 white LED 16/25 DocID10973 Rev 2 AN2067 5.2 Switching cycle Line regulation Figure 13 presents the output current variation versus AC line input voltage. It shows a variation of 0.4%. Figure 13. AC line regulation ,RXW P$ 5.3 9LQ 9 Load regulation The regulation versus the load is represented in Figure 14. The regulation is 0.4%. Figure 14. Load regulation ,RXW P$ 9RXW 9 5.4 Voltage limitation Figure 15 is the extension of the load regulation in Figure 14 (up to the voltage limit). The voltage limitation acts on the output power through the whole regulation loop, and the output current decreases down to 0. Note: Since the bridge divider has been slightly tuned, the voltage limit may be different than these measures according to R105 and R106 standard values. DocID10973 Rev 2 17/25 25 Switching cycle AN2067 Figure 15. Voltage limitation ,RXW P$ 9RXW 9 5.5 Power supply efficiency Figure 16 shows the efficiency of the power supply when the output power increases from 0 up to 40 W, using several input voltages. The output voltage varies while the output current is 1 A. The efficiency is lower than the expected offline converter, because the current generator structure has the VIPer53-E supply connected to a forward winding, and because of its associated serial voltage regulator. Figure 16. Efficiency (IOUT=1 A) 9LQ 9 Q 9LQ 9 9LQ 9 9LQ 9 3RXW : 5.6 Efficiency vs output power (VIN=100 V) The transformer, the inrush current limiter, primary and secondary rectifier, and the clamper are the main contributors in the power budget. When the output load increases, the ratio between the dissipated power and the output power decreases, since the power of main contributors is quite constant versus the output load. 18/25 DocID10973 Rev 2 AN2067 Extreme load conditions Figure 17 and Figure 18 show the power supply consumption respectively when no-load is connected on the output and in short-circuit condition. Figure 17. Input power in no-load mode 3LQ : 9LQ 9 Figure 18. Input power in short-circuit mode 3LQ : 5.7 Switching cycle 9LQ 9 Figure 19 presents DRAIN, COMP pin, output voltage and drain current during short-circuit condition. The converter is in continuous mode (VIN=100 V). Figure 19. Short-circuit condition (VIN=100 V) DocID10973 Rev 2 19/25 25 Board description AN2067 6 Board description 6.1 Printed circuit board Figure 20 to Figure 22 present the PCB of the application. They respectively show all the layers of the PCB, the bottom and the top overlay layer of the PCB. Figure 20. All layers (not in scale) Figure 21. Bottom layer (not in scale) 20/25 DocID10973 Rev 2 AN2067 Board description Figure 22. Top overlay layer (not in scale) DocID10973 Rev 2 21/25 25 Bill of material 7 AN2067 Bill of material The Table 3 presents the bill of material of the application. Table 3. Bill of material Symbol Description Quantity BR1 1 A/500 V 1 C1 100 n/400 V 1 C2 100 n/400 V 1 C3 100 u/400 V/159 PUL-SI 1 C4 1 nF/250 V 1 C5 1 µF/100 V/RLI135 1 C8 4.7 nF 1 C9 470 nF 1 C10 100 nF 1 C11 4.7 nF 1 C12 22 µF/25 V 1 C104 NC 1 C105 NC 1 C107 NC 1 C110 10 uF/63 V 1 C111 100 nF 1 C112 220 uF/63 V/RLI 135 1 C113 22 nF 1 C114 100 nF 1 C121 22 uF/40 V 1 C131 10 nF 1 COR1 Corner 1 COR2 Corner 1 COR3 Corner 1 COR4 Corner 1 COR5 Corner 1 COR6 Corner 1 CTN1 1 C_YCAP 2.2 n/2 kV 1 D2 BAS21 1 D4 EBR44-600 1 D101 STTH302 1 D122 BAS21 1 22/25 DocID10973 Rev 2 AN2067 Bill of material Table 3. Bill of material (continued) Symbol Description Quantity DZ14 12 V/0.5 W 1 F1 Fuse 1 J1 1 J2 1 J3 1 J101 1 J102 1 J103 1 J107 Vref_in 1 L101 10 uH 1 P101 1K 1 P1011 1K 1 Q1 BC546/VCEO=100 V/1 W 1 R2 10 1 R4 47 kΩ/4 W 1 R5 5.1 kΩ 1 R9 6.8 kΩ 1 R14 3.3 kΩ/0.5 W 1 R100 0.25 Ω 1 R101 12 kΩ 1 R102 680 Ω 1 R103 2.2 kΩ 1 R104 1Ω 1 R105 1.8 kΩ 1 R106 56 kΩ 1 R107 6.8 kΩ 1 R108 100 kΩ 1 R109 1 kΩ 1 R122 3.3 Ω 1 R131 1.8 kΩ 1 TR1 LN_FILTER 1 TR2 E25 1 U1 VIPer53DIP-E 1 U2 PC817 1 U101 TSM101 1 DocID10973 Rev 2 23/25 25 Revision history 8 AN2067 Revision history Table 4. Document revision history 24/25 Date Revision 14-Nov-2014 2 Changes Modified title in cover page. Content reworked to improve readability, no technical changes. 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