TI1 ADS5273IPFPG4 8-channel, 12-bit, 70msps analog-to-digital converter Datasheet

ADS5273
www.ti.com .............................................................................................................................................. SBAS305D – JANUARY 2004 – REVISED JANUARY 2009
8-Channel, 12-Bit, 70MSPS Analog-to-Digital Converter
with Serial LVDS Interface
FEATURES
1
•
•
•
•
23
•
•
•
•
•
•
•
•
•
•
Maximum Sample Rate: 70MSPS
12-Bit Resolution
No Missing Codes
Total Power Dissipation:
Internal Reference: 1W
External Reference: 937mW
CMOS Technology
Simultaneous Sample-and-Hold
71dBFS SNR at 5MHz IF
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Bit Patterns
Option to Double LVDS Clock Output Currents
Four Current Modes for LVDS
Pin- and Format-Compatible Family
TQFP-80 PowerPAD™ Package
An integrated phase lock loop (PLL) multiplies the
incoming ADC sampling clock by a factor of 12. This
high-frequency LVDS clock is used in the data
serialization and transmission process. The word
output of each internal ADC is serialized and
transmitted either MSB or LSB first. In addition to the
eight data outputs, a bit clock and a word clock are
also transmitted. The bit clock is at 6x the speed of
the sampling clock, whereas the word clock is at the
same speed of the sampling clock.
The ADS5273 provides an internal reference, or can
optionally be driven with an external reference. Best
performance is achieved through the internal
reference mode.
The device is available in a PowerPAD TQFP-80
package and is specified over a –40°C to +85°C
operating range.
L CL K P
6 x A D C LK
L CL K N
1 2 x A D CL K
PLL
A D C LK P
1 x A D C LK
ADCLK
1 2 − B it
ADC
S eria lize r
1 2 − B it
ADC
S eria lize r
1 2 − B it
ADC
S eria lize r
S/H
1 2 − B it
ADC
S eria lize r
S/H
1 2 − B it
ADC
S eria lize r
1 2 − B it
ADC
S eria lize r
1 2 − B it
ADC
S eria lize r
1 2 − B it
ADC
S eria lize r
IN 3 P
IN 3 N
DESCRIPTION
S/H
IN 4 P
The ADS5273 is a high-performance, CMOS,
70MSPS, 8-channel analog-to-digital converter
(ADC). An internal reference is provided, simplifying
system design requirements. Low power consumption
allows for the highest of system integration densities.
Serial LVDS (low-voltage differential signaling)
outputs reduce the number of interface lines and
package size.
RELATED PRODUCTS
IN 4 N
IN 5 P
IN 5 N
IN 6 P
S/H
IN 6 N
IN 7 P
IN 7 N
S/H
IN 8 P
S/H
IN 8 N
RESOLUTION
(BITS)
SAMPLE RATE
(MSPS)
CHANNELS
ADS5270
12
40
8
ADS5271
12
50
8
ADS5272
12
65
8
ADS5277
10
65
8
IN T /E X T
REFT
MODEL
O U T 2N
O U T 3P
O U T 3N
O U T 4P
O U T 4N
O U T 5P
O U T 5N
O U T 6P
O U T 6N
O U T 7P
O U T 7N
O U T 8P
O U T 8N
R e g isters
Re feren ce
O U T 2P
C on trol
PD
S/H
RESET
IN 2 P
IN 2 N
O U T 1P
O U T 1N
SDATA
IN 1 N
CS
S/H
Portable Ultrasound Systems
Test Equipment
Military
V CM
REFB
•
•
•
A D C LK N
IN 1 P
SCLK
APPLICATIONS
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2009, Texas Instruments Incorporated
ADS5273
SBAS305D – JANUARY 2004 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
ADS5273
(1)
(2)
PACKAGE-LEAD
(2)
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PFP
–40°C to +85°C
ADS5273IPFP
HTQFP-80
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5273IPFP
Tray, 96
ADS5273IPFPT
Tape and Reel, 250
For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
web site at www.ti.com.
Thermal pad size: 4.69mm × 4.69mm (min), 6.20mm × 6.20mm (max).
ABSOLUTE MAXIMUM RATINGS (1)
Analog Supply Voltage Range, AVDD
–0.3V to +3.8V
Output Driver Supply Voltage Range, LVDD
–0.3V to +3.8V
Voltage Between AVSS and LVSS
–0.3V to +0.3V
Voltage Between AVDD and LVDD
–0.3V to +0.3V
Voltages Applied to External REF Pins
–0.3V to +2.4V
All LVDS Data and Clock Outputs
–0.3V to +2.4V
Analog Input Pins (2)
–0.3V to min. [3.3V, (AVDD + 0.3V)]
Digital Input Pins, Set 1 (pins 69, 76-78)
–0.3V to min. [3.9V, (AVDD + 0.3V)] (3)
Digital Input Pins, Set 2 (pins 16, 45)
–0.3V to min. [3.9V, (LVDD + 0.3V)] (3)
Operating Free-Air Temperature Range, TA
–40°C to +85°C
Lead Temperature, 1.6mm (1/16" from case for 10s)
+260°C
Junction Temperature
+105°C
Storage Temperature Range
(1)
(2)
(3)
2
–65°C to +150°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
The dc voltage applied on the input pins should not go below –0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
It is recommended that a series resistor of 1kΩ or greater be used if the digital input pins are tied to AVDD or LVDD.
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www.ti.com .............................................................................................................................................. SBAS305D – JANUARY 2004 – REVISED JANUARY 2009
RECOMMENDED OPERATING CONDITIONS
ADS5273
PARAMETER
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
3.0
3.3
3.6
V
REFT — External Reference Mode
1.825
1.95
2.0
V
REFB — External Reference Mode
0.9
0.95
1.075
V
1.4
VCM ± 50mV
1.5
V
0.75
1.0
1.1
V
REFCM = (REFT + REFB)/2 – External Reference Mode
(1)
Reference = (REFT – REFB) – External Reference Mode
Analog Input Common-Mode Range (2)
VCM ± 50mV
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
20
70
MSPS
ADCLK Duty Cycle
45
55
%
0.6
V
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
2.2
ADCLKP and ADCLKN Outputs (LVDS)
20
70
MHz
V
LCLKP and LCLKN Outputs (LVDS) (2)
120
420
MHz
Operating Free-Air Temperature, TA
–40
+85
°C
Thermal Characteristics:
(1)
(2)
θJA
19.4
°C/W
θJC
4.2
°C/W
These voltages need to be set to 1.45V ± 50mV if they are derived independent of VCM.
6 × ADCLK.
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ELECTRICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5273
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LSB
DC ACCURACY
No Missing Codes
Tested
DNL Differential Nonlinearity
INL Integral Nonlinearity
fIN = 5MHz
–0.99
±0.34
+1.2
fIN = 5MHz
–3.0
±0.43
+3.0
LSB
+0.75
%FS
Offset Error (1)
–0.75
Offset Temperature Coefficient
Fixed Attenuation in Channel
±6
(2)
1.5
Fixed Attenuation Matching Across Channels
Gain Error/Reference Error (3)
ppm/°C
VREFT – VREFB
–2.5
Gain Error Temperature Coefficient
%FS
0.01
0.2
dB
±1.0
+2.5
%FS
±20
ppm/°C
POWER REQUIREMENTS (4)
Internal Reference
Power Dissipation
Analog Only (AVDD)
800
868
mW
Output Driver (LVDD)
203
231
mW
1003
1099
mW
Total Power Dissipation
External Reference
Power Dissipation
Analog Only (AVDD)
734
mW
Output Driver (LVDD)
203
mW
937
mW
Total Power Dissipation
Total Power-Down
Clock Running
95
149
mW
REFERENCE VOLTAGES
VREFT Reference Top (internal)
1.9
1.95
2.0
V
VREFB Reference Bottom (internal)
0.9
0.95
1.0
V
VCM Common-Mode Voltage
1.4
1.45
1.5
VCM Output Current (5)
±50mV Change in Voltage
VREFT Reference Top (external)
1.825
VREFB Reference Bottom (external)
(1)
(2)
(3)
(4)
(5)
(6)
4
±2.0
0.9
V
mA
1.95
2.0
V
0.95
1.075
V
External Reference Common-Mode
VCM ± 50mV
V
External Reference Input Current (6)
1.0
mA
Offset error is the deviation of the average code from mid-code with –1dBFS sinusoid from ideal mid-code (2048). Offset error is
expressed in terms of % of full-scale.
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential
voltage at the analog input pins are changed from –VREF to +VREF, the swing of the output code is expected to deviate from the
full-scale code (4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT – REFB).
The reference voltages are trimmed at production so that (VREFT – VREFB) is within ± 25mV of the ideal value of 1V. It does not include
fixed attenuation.
Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
VCM provides the common-mode current for the inputs of all eight channels when the inputs are ac-coupled. The VCM output current
specified is the additional drive of the VCM buffer if loaded externally.
Average current drawn from the reference pins in the external reference mode.
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ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5273
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Differential Input Capacitance
4.0
Analog Input Common-Mode Range
Differential Full-Scale Input Voltage Range
VCM ± 50
mV
Internal Reference
2.03
VPP
External Reference
2.03 × (VREFT – VREFB)
VPP
3.0
CLK Cycles
300
MHz
Voltage Overload Recovery Time (7)
–3dBFS, 25Ω Series
Resistances
Input Bandwidth
pF
DIGITAL DATA INPUTS
VIH High-Level Input Voltage
2.2
V
VIL Low-Level Input Voltage
0.6
CIN Input Capacitance
V
3.0
pF
DIGITAL DATA OUTPUTS
Data Format
Straight Offset Binary
Data Bit Rate
240
840
Mbps
20
MHz
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
(7)
A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
Internal Reference; FSR = 2.03VPP
1
Default with internal pull-up.
External Reference; FSR = 2.03x (REFT – REFB)
0
Internal reference is powered down. The common-mode voltage of
the external reference should be within 50mV of VCM. VCM is
derived from the internal bandgap voltage.
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ADS5273
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AC CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, sampling rate = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All voltages are applicable after the device has been reset.
ADS5273
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
SFDR Spurious-Free Dynamic Range
HD2 2nd-Order Harmonic Distortion
fIN = 5MHz
76
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
Crosstalk
IMD3
6
Two-Tone, Third-Order
Intermodulation Distortion
dBc
90
dBc
fIN = 10MHz
87
dBc
fIN = 20MHz
86
dBc
fIN = 1MHz
101
dBc
95
dBc
fIN = 10MHz
fIN = 5MHz
82
92
dBc
fIN = 20MHz
86
dBc
92
dBc
90
dBc
87
dBc
fIN = 1MHz
HD3 3rd-Order Harmonic Distortion
92
fIN = 5MHz
76
fIN = 10MHz
fIN = 20MHz
86
dBc
fIN = 1MHz
71.1
dBFS
71
dBFS
fIN = 10MHz
fIN = 5MHz
69
70.8
dBFS
fIN = 20MHz
70
dBFS
fIN = 1MHz
71
dBFS
70.8
dBFS
fIN = 10MHz
70.6
dBFS
fIN = 20MHz
69.8
dBFS
11.5
Bits
–89
dBc
97
dBFS
fIN = 5MHz
68.5
fIN = 5MHz
11.1
5MHz Full-Scale Signal Applied to 7 Channels;
Measurement Taken on the Channel with No Input Signal
f1 = 9.5MHz at –7dBFS
f2 = 10.2MHz at –7dBFS
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LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, CLOAD = 6pF, and 50% duty cycle. IO refers to the current setting for the LVDS buffer. RLOAD is
the differential load resistance between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between each of the
LVDS pins and ground. CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch
transmission line of 100Ω characteristic impedance between the device and the load. All LVDS specifications are characterized, but not
parametrically tested at production. LCLKOUT refers to (LCLKP – LCLKN); ADCLKOUT refers to (ADCLKP – ADCLKN); DATA OUT refers to
(OUTP – OUTN); and ADCLK refers to the input sampling clock.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOH Output Voltage High, OUTP or OUTN
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8
1265
1365
1465
mV
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω ± 1%
940
1040
1140
mV
|VOD| Output Differential Voltage
RLOAD = 100Ω ± 1%
275
325
375
mV
VOS Output Offset Voltage (2)
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8
1.1
1.2
1.3
DC SPECIFICATIONS (1)
V
RO Output Impedance, Differential
Normal Operation
13
kΩ
RO Output Impedance, Differential
Power-Down
20
kΩ
CO Output Capacitance (3)
4
|ΔVOD| Change in |VOD| Between 0 and 1
pF
RLOAD = 100Ω ± 1%
10
mV
ΔVOS Change Between 0 and 1
RLOAD = 100Ω ± 1%
25
mV
ISOUT Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
Drivers Shorted Together
12
mA
%
ISOUTNP Output Current
DRIVER AC SPECIFICATIONS
ADCLKOUT Clock Duty Cycle (4)
45
50
55
LCLKOUT Duty Cycle (4)
40
50
60
Data Setup Time (5) (6)
%
0.35
Data Hold Time (6) (7)
ns
0.20
LVDS Outputs Rise/Fall Time (8)
IO = 2.5mA
ns
400
IO = 3.5mA
180
300
IO = 4.5mA
230
IO = 6.0mA
180
ps
500
ps
ps
ps
LCLKOUT Rising Edge to ADCLKOUT Rising Edge (9)
0.33
0.60
0.86
ns
ADCLKOUT Rising Edge to LCLKOUT Falling Edge (9)
0.33
0.60
0.86
ns
ADCLKOUT Rising Edge to DATA OUT Transition (9)
–0.3
0
+0.3
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
The dc specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
VOS refers to the common-mode of OUTP and OUTN.
Output capacitance inside the device, from either OUTP or OUTN to ground.
Measured between zero crossings.
DATA OUT (OUTP – OUTN) crossing zero to LCLKOUT (LCLKP – LCLKN) crossing zero.
Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, and effects of clock jitter in the device.
LCLKOUT crossing zero to DATA OUT crossing zero.
Measured from –100mV to +100mV on the differential output for rise time, and +100mV to –100mV for fall time.
Measured between zero crossings.
SWITCHING CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless
otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
50
ns
4
6.5
SWITCHING SPECIFICATIONS
tSAMPLE
14.3
tD(A) Aperture Delay (1)
2
Aperture Jitter (uncertainty)
1
tD(pipeline) Latency
6.5
tPROP Propagation Delay (2)
(1)
(2)
3
4.8
ns
ps rms
Cycles
6.5
ns
Rising edge of ADCLK to actual instant when data is sampled within the ADC.
Falling edge of ADCLK to zero-crossing of rising edge of ADCLKOUT.
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LVDS TIMING DIAGRAM (PER ADC CHANNEL)
Sample n
Sample n + 6
Input
1
tSAMPLE
ADCLK
tS
2
LCLKP
6X ADCLK
LCLKN
OUTP
SERIAL DATA
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1
OUTN
Sample n data
ADCLKP
1X ADCLK
ADCLKN
tD(A)
tPROP
6.5 Clock Cycles
NOTE: Serial data bit format shown in LSB first mode.
RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
AVDD (3V to 3.6V)
t1
AVDD
LVDD (3V to 3.6V)
t2
LVDD
t3
t4
t7
t5
Device Ready
For ADC Operation
t6
RESET
Device Ready
For Serial Register Write
CS
Device Ready
For ADC Operation
Start of Clock
ADCLK
t8
NOTE: 10µs < t1 < 50ms; 10µs < t 2 < 50ms; −10ms < t3 < 10ms; t4 > 10ms; t 5 > 100ns; t6 > 100ns; t 7 > 10ms; and t8 > 100µs.
8
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POWER-DOWN TIMING
1µs
500µs
PD
Device Fully
Powers Down
Device Fully
Powers Up
NOTE: The shown power−up time is based on 1µF bypass capacitors on the reference pins.
See the Theory of Operation section for details.
SERIAL INTERFACE TIMING
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
CS
Start Sequence
t6
t1
t7
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
D7
(MSB)
SDATA
D6
D5
D4
D3
D2
D1
D0
t4
t5
NOTE: Data is shifted in MSB first.
PARAMETER
DESCRIPTION
MIN
t1
Serial CLK Period
50
TYP
MAX
UNIT
ns
t2
Serial CLK High Time
20
ns
t3
Serial CLK Low Time
20
ns
t4
Data Setup Time
5
ns
t5
Data Hold Time
5
ns
t6
CS Fall to SCLK Rise
8
ns
t7
SCLK Rise to CS Rise
8
ns
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SERIAL INTERFACE REGISTERS
ADDRESS
DATA
D7
D6
D5
D4
0
0
0
0
0
0
0
DESCRIPTION
D1
REMARKS
D3
D2
D0
LVDS BUFFERS (Register 0)
All Data Outputs
0
0
Normal ADC Output
(default after reset)
0
1
Deskew Pattern
1
0
Sync Pattern
1
1
Custom Pattern
See Test Patterns
0
0
Output Current in LVDS = 3.5mA
0
1
Output Current in LVDS = 2.5mA
1
0
Output Current in LVDS = 4.5mA
1
1
Output Current in LVDS = 6.0mA
1
(default after reset)
CLOCK CURRENT (Register 1)
0
X
X
0
LVDS Clock Output Current
IOUT = 3.5mA (default)
0
X
X
1
2x LVDS Clock Output Current (1)
IOUT = 7.0mA
LSB/MSB MODE (Register 1)
0
0
1
0
0
X
X
LSB Mode
0
1
X
X
MSB Mode
0
POWER-DOWN ADC CHANNELS
(Register 2)
X
0
0
1
(default after reset)
X
X
X
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
1
Example: 1010 Powers Down
Channels 4 and 2 and
Keeps Channels 1 and 3 Active
POWER-DOWN ADC CHANNELS
(Register 3)
X
X
X
X
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
D3
D2
D1
D0
CUSTOM PATTERN (Registers 4–6)
(1)
0
1
0
0
X
X
X
X
0
1
0
1
X
X
X
X
0
1
1
0
X
X
X
X
Bits for Custom Pattern
See Test Patterns
Output current drive for the two clock LVDS buffers (LCLKP and LCLKN and ADCLKP and ADCLKN) is twice the output current setting
programmed in register 0. The current drive of the data buffers remains the same as the setting in register 0.
TEST PATTERNS
Serial Output (1)
ADC Output (2)
LSB
MSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Deskew Pattern
1
0
1
0
1
0
1
0
1
0
1
0
Sync Pattern
0
0
0
0
0
0
1
1
1
1
1
1
D0(4)
D1(4)
D2(4)
D3(4)
D0(5)
D1(5)
D2(5)
D3(5)
D0(6)
D1(6)
D2(6)
D3(6)
Custom Pattern (3)
(1)
(2)
(3)
10
The serial output stream comes out LSB first by default.
D11...D0 represent the 12 output bits from the ADC.
D0(4) represents the content of the bit D0 of register 4, D3(6) represents the content of bit D3 of register 6, etc.
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PIN CONFIGURATION
CS
AVDD
AVSS
AVSS
AVSS
ADCLK
AVDD
INT/EXT
AVSS
REFT
REFB
VCM
ISET
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
AVSS
SDATA
79
AVSS
SCLK
80
AVDD
AVSS
HTQFP
AVSS
Top View
63
62
61
AVDD
1
60 AVDD
IN1P
2
59 IN8N
IN1N
3
58 IN8P
AVSS
4
57 AVSS
IN2P
5
56 IN7N
IN2N
6
55 IN7P
AVDD
7
54 AVDD
AVSS
8
53 AVSS
IN3P
9
52 IN6N
51 IN6P
IN3N 10
ADS5273
AVSS 11
50 AVSS
IN4P 12
49 IN5N
IN4N 13
48 IN5P
AVDD 14
47 AVDD
LVSS 15
46 LVSS
45 RESET
PD 16
LVSS 17
44 LVSS
LVSS 18
43 LVSS
33
34
35
36
37
38
39
40
OUT8N
OUT3N
32
OUT8P
OUT3P
31
OUT7N
LVSS
30
OUT7P
LVDD
29
LVSS
28
LVDD
27
OUT6N
26
OUT6P
25
OUT5N
24
OUT5P
23
OUT4N
22
OUT4P
21
OUT2N
41 ADCLKP
OUT2P
LCLKN 20
OUT1N
42 ADCLKN
OUT1P
LCLKP 19
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PIN DESCRIPTIONS
NAME
PIN #
I/O
ADCLK
71
I
Data Converter Clock Input
ADCLKN
42
O
Negative LVDS ADC Clock Output
ADCLKP
41
O
Positive LVDS ADC Clock Output
AVDD
1, 7, 14, 47, 54, 60, 63, 70, 75
I
Analog Power Supply
AVSS
4, 8, 11, 50, 53, 57, 61, 62, 68, 72–74, 79, 80
I
Analog Ground
CS
76
I
Chip Select; 0 = Select, 1 = No Select
IN1N
3
I
Channel 1 Differential Analog Input Low
IN1P
2
I
Channel 1 Differential Analog Input High
IN2N
6
I
Channel 2 Differential Analog Input Low
IN2P
5
I
Channel 2 Differential Analog Input High
IN3N
10
I
Channel 3 Differential Analog Input Low
IN3P
9
I
Channel 3 Differential Analog Input High
IN4N
13
I
Channel 4 Differential Analog Input Low
IN4P
12
I
Channel 4 Differential Analog Input High
IN5N
49
I
Channel 5 Differential Analog Input Low
IN5P
48
I
Channel 5 Differential Analog Input High
IN6N
52
I
Channel 6 Differential Analog Input Low
IN6P
51
I
Channel 6 Differential Analog Input High
IN7N
56
I
Channel 7 Differential Analog Input Low
IN7P
55
I
Channel 7 Differential Analog Input High
IN8N
59
I
Channel 8 Differential Analog Input Low
IN8P
58
I
Channel 8 Differential Analog Input High
INT/EXT
69
I
Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply.
ISET
64
I/O
LVDD
25, 35
I
LVDS Power Supply
LVSS
15, 17, 18, 26, 36, 43, 44, 46
I
LVDS Ground
LCLKN
20
O
Negative LVDS Clock
LCLKP
19
O
Positive LVDS Clock
OUT1N
22
O
Channel 1 Negative LVDS Data Output
OUT1P
21
O
Channel 1 Positive LVDS Data Output
OUT2N
24
O
Channel 2 Negative LVDS Data Output
OUT2P
23
O
Channel 2 Positive LVDS Data Output
OUT3N
28
O
Channel 3 Negative LVDS Data Output
OUT3P
27
O
Channel 3 Positive LVDS Data Output
OUT4N
30
O
Channel 4 Negative LVDS Data Output
OUT4P
29
O
Channel 4 Positive LVDS Data Output
OUT5N
32
O
Channel 5 Negative LVDS Data Output
OUT5P
31
O
Channel 5 Positive LVDS Data Output
OUT6N
34
O
Channel 6 Negative LVDS Data Output
OUT6P
33
O
Channel 6 Positive LVDS Data Output
OUT7N
38
O
Channel 7 Negative LVDS Data Output
OUT7P
37
O
Channel 7 Positive LVDS Data Output
OUT8N
40
O
Channel 8 Negative LVDS Data Output
OUT8P
39
O
Channel 8 Positive LVDS Data Output
PD
16
I
Power-Down; 0 = Normal, 1 = Power-Down. Weak pull-down to ground.
REFB
66
I/O
Reference Bottom Voltage (2Ω resistor in series with a ≥ 0.1µF capacitor to ground)
REFT
67
I/O
Reference Top Voltage (2Ω resistor in series with a ≥ 0.1µF capacitor to ground)
RESET
45
I
Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground.
SCLK
78
I
Serial Data Clock
SDATA
77
I
Serial Data Input
VCM
65
O
Common-Mode Output Voltage
12
DESCRIPTION
Bias Current Setting Resistor of 56.2kΩ to Ground
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DEFINITION OF SPECIFICATIONS
Minimum Conversion Rate
Analog Bandwidth
The analog input frequency at which the spectral
power of the fundamental frequency (as determined
by FFT analysis) is reduced by 3dB.
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Duty Cycle
Pulse width high is the minimum amount of time that
the ADCLK pulse should be left in logic ‘1’ state to
achieve rated performance. Pulse width low is the
minimum time that the ADCLK pulse should be left in
a low state (logic ‘0’). At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are
exactly 1 LSB apart. DNL is the deviation of any
single LSB transition at the digital output from an
ideal 1 LSB step at the analog input. If a device
claims to have no missing codes, it means that all
possible codes (for a 12-bit converter, 4096 codes)
are present over the full operating range.
This is the minimum sampling rate where the ADC
still works.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but not
including dc.
PS
SINAD + 10Log 10
PN ) PD
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
P
SNR + 10Log 10 S
PN
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Spurious-Free Dynamic Range
Effective Number of Bits (ENOB)
The ENOB is a measure of converter performance as
compared to the theoretical limit based on
quantization noise.
ENOB + SINAD * 1.76
6.02
Integral Nonlinearity (INL)
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a
best straight line or best fit determined by a least
square curve fit. INL is independent from effects of
offset, gain or quantization errors.
Maximum Conversion Rate
The encode rate at which parametric testing is
performed. This is the maximum sampling rate where
certified operation is given.
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier).
Two-Tone, Third-Order Intermodulation
Distortion
Two-tone IMD3 is the ratio of power of the
fundamental (at frequencies f1 and f2) to the power of
the worst spectral component of third-order
intermodulation distortion at either frequency 2f1 – f2
or 2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full-scale)
when the power of the fundamental is extrapolated to
the full-scale range of the converter.
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TYPICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel,
16kFFT, and 8 averages, unless otherwise noted.
SPECTRAL PERFORMANCE
f IN = 1MHz, −1dBFS
SNR = 71.1dBFS
SINAD = 71dBFS
SFDR = 92dBc
16 Averages
−20
−30
Amplitude (dBFS)
SPECTRAL PERFORMANCE
−40
−50
−60
−70
−80
−90
0
−10
f IN = 5MHz, −1dBFS
SNR = 71dBFS
SINAD = 70.8dBFS
SFDR = 90dBc
16 Averages
−20
−30
Amplitude (dBFS)
0
−10
−40
−50
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
0
5
10
15
20
25
30
35
0
5
25
Figure 2.
−40
−50
−60
−70
−80
−90
0
−10
35
fIN = 20MHz
SNR = 70dBFS
SINAD = 69.8dBFS
SFDR = 86dBc
16 Averages
−20
−30
Amplitude (dBFS)
−30
30
SPECTRAL PERFORMANCE
fIN = 10MHz, −1dBFS
SNR = 70.8dBFS
SINAD = 70.6dBFS
SFDR = 87dBc
16 Averages
−20
−40
−50
−60
−70
−80
−90
−100
−100
−110
−110
−120
−120
0
5
10
15
20
25
30
35
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
Figure 3.
Figure 4.
INTERMODULATION DISTORTION
f1 = 9.5MHz
f 2 = 10.2MHz
IMD3 = 97dBFS
16 Averages
−20
−30
−40
30
35
CROSSTALK
−50
−60
−70
−80
−90
0
−10
−30
−40
−50
−60
−70
−80
−90
−100
−100
−110
−110
−120
fIN = 5MHz
Crosstalk = 90dBFS
16 Averages
−20
Amplitude (dBFS)
0
−10
Amplitude (dBFS)
20
Figure 1.
SPECTRAL PERFORMANCE
−120
0
14
15
Frequency (MHz)
0
−10
Amplitude (dBFS)
10
Frequency (MHz)
5
10
15
20
25
30
35
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
Figure 5.
Figure 6.
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30
35
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel,
16kFFT, and 8 averages, unless otherwise noted.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
0.45
0.60
fIN = 5MHz
f IN = 5MHz
0.45
0.30
0.30
INL (LSB)
DNL (LSB)
0.15
0
−0.15
0.15
0
−0.15
−0.30
−0.30
−0.45
−0.45
−0.60
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
70
68
66
64
62
60
50
60
70
Signal−to−Noise Ratio+Distortion (dBFS)
Signal−to−Noise Ratio (dBFS)
72
40
3584
4096
72
External Reference
70
68
66
64
62
60
80
0
10
20
30
40
50
Input Frequency (MHz)
Input Frequency (MHz)
Figure 9.
Figure 10.
SFDR vs INPUT FREQUENCY
60
70
80
70
80
SNR vs INPUT FREQUENCY
100
74
External Reference
95
Signal−to−Noise Ratio (dBFS)
Spurious-Free Dynamic Range (dBc)
3072
SINAD vs INPUT FREQUENCY
External Reference
30
2560
Figure 8.
74
20
2048
Figure 7.
SNR vs INPUT FREQUENCY
10
1536
Code
76
0
1024
Code
90
85
80
75
70
65
72
70
68
66
64
62
60
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
Input Frequency (MHz)
Input Frequency (MHz)
Figure 11.
Figure 12.
60
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel,
16kFFT, and 8 averages, unless otherwise noted.
SINAD vs INPUT FREQUENCY
SFDR vs INPUT FREQUENCY
94
Spurious−Free Dynamic Range (dBc)
74
72
SINAD (dBFS)
70
68
66
64
62
92
90
88
86
84
82
80
78
76
74
60
0
10
20
30
40
50
60
70
0
80
10
20
60
Figure 14.
105
60
90
SFDR (dBc, dBFS)
70
50
dBc
40
70
80
SWEPT POWER — SFDR
120
fIN = 10MHz
dBFS
SINAD (dBc, dBFS)
50
Figure 13.
SWEPT POWER — SNR
30
20
10
fIN = 10MHz
dBFS
75
dBc
60
45
30
15
0
0
−60
−50
−40
−30
−20
−10
−60
0
−50
−40
−30
−20
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 15.
Figure 16.
SWEPT POWER — SINAD
80
dBFS
−10
0
SWEPT POWER — SNR
90
fIN = 10MHz
fIN = 5MHz
70
75
60
dBFS
SNR (dBc, dBFS)
SINAD (dBc, dBFS)
40
Input Frequency (MHz)
80
50
dBc
40
30
60
45
dBc
30
20
15
10
0
0
−60
16
30
Input Frequency (MHz)
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel,
16kFFT, and 8 averages, unless otherwise noted.
SWEPT POWER — SINAD
SWEPT POWER — SFDR
105
90
dBFS
fIN = 5MHz
dBFS
SFDR (dBFS, dBc)
SINAD (dBFS, dBc)
75
60
45
dBc
30
15
75
dBc
60
45
30
15
0
0
−60
−50
−40
−30
−20
−10
−60
0
−50
Figure 20.
fIN = 5MHz
72
70
68
66
64
62
60
45
50
55
−10
0
SINAD vs DUTY CYCLE
Signal−to−Noise Ratio+Distortion (dBFS)
Signal-to_Noise Ratio (dBFS)
−20
Figure 19.
74
40
−30
Input Amplitude (dBFS)
SNR vs DUTY CYCLE
35
−40
Input Amplitude (dBFS)
76
60
76
fIN = 5MHz
74
72
70
68
66
64
65
35
40
45
50
55
Duty Cycle (%)
Duty Cycle (%)
Figure 21.
Figure 22.
SFDR vs DUTY CYCLE
60
65
SNR vs SAMPLE RATE
76
105
fIN = 5MHz
100
fIN = 5MHz
Signal−to−Noise Ratio (dBFS)
Spurious−Free Dynamic Range (dBc)
f IN = 5MHz
90
95
90
85
80
75
70
74
72
70
68
66
64
65
35
40
45
50
55
60
65
20
25
30
35
40
45
50
55
Duty Cycle (%)
Sample Rate (MSPS)
Figure 23.
Figure 24.
60
65
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel,
16kFFT, and 8 averages, unless otherwise noted.
SFDR vs SAMPLE RATE
fIN = 5MHz
74
72
70
68
66
Spurious-Free Dynamic Range (dBc)
Signal−to−Noise Ratio+Distortion (dBFS)
SINAD vs SAMPLE RATE
76
64
95
fIN = 5MHz
90
85
80
75
70
20
25
30
35
40
45
50
55
60
65
20
70
25
30
71
70
69
68
67
40
45
50
55
60
65
Signal−to−Noise Ratio+Distortion (dBFS)
Signal−to−Noise Ratio (dBFS)
72
66
65
70
f IN = 10MHz
73
72
71
70
69
68
67
66
25
30
35
40
45
50
55
Sample Rate (MSPS)
Sample Rate (MSPS)
Figure 27.
Figure 28.
SFDR vs SAMPLE RATE
60
65
70
CURRENT vs SAMPLE RATE
300
fIN = 10MHz
250
90
IAVDD
Current (mA)
Spurious−Free Dynamic Range (dBc)
60
74
20
70
92
88
86
200
150
100
ILVDD
84
50
0
82
20
18
55
SINAD vs SAMPLE RATE
fIN = 10MHz
35
50
Figure 26.
73
30
45
Figure 25.
SNR vs SAMPLE RATE
25
40
Sample Rate (MSPS)
74
20
35
Sample Rate (MHz)
25
30
35
40
45
50
55
60
65
70
10
20
30
40
50
Sample Rate (MSPS)
Sample Rate (MSPS)
Figure 29.
Figure 30.
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70
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 70MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel,
16kFFT, and 8 averages, unless otherwise noted.
TOTAL POWER vs TEMPERATURE
1050
1000
1025
950
Total Power (mW)
Total Power (mW)
TOTAL POWER vs SAMPLE RATE
1050
900
850
800
1000
975
950
925
750
900
700
0
10
20
30
40
50
60
70
−40
80
−15
Figure 31.
SNR vs TEMPERATURE
Signal-to-Noise Ratio+Distortion (dBFS)
Signal−to−Noise Ratio (dBFS)
71
70
69
68
35
85
73
72
71
70
69
68
10
60
SINAD vs TEMPERATURE
72
−15
35
Figure 32.
73
−40
10
Temperature (_ C)
Sample Rate (MSPS)
60
85
−40
−15
10
33
Temperature (_ C)
Temperature (_ C)
Figure 33.
Figure 34.
60
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19
ADS5273
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THEORY OF OPERATION
OVERVIEW
The ADS5273 is an 8-channel, high-speed, CMOS
ADC.
It
consists
of
a
high-performance
sample-and-hold circuit at the input, followed by a
12-bit ADC. The 12 bits given out by each channel
are serialized and sent out on a single pair of pins in
LVDS format. All eight channels of the ADS5273
operate from a single clock referred to as ADCLK.
The sampling clocks for each of the eight channels
are generated from the input clock using a carefully
matched clock buffer tree. The 12x clock required for
the serializer is generated internally from ADCLK
using a phase lock loop (PLL). A 6x and a 1x clock
are also output in LVDS format along with the data to
enable easy data capture. The ADS5273 operates
from internally-generated reference voltages that are
trimmed to improve performance to a high level of
accuracy. This feature eliminates the need for
external routing of reference lines and also improves
matching of the gain across devices. The nominal
values of REFT and REFB are 1.95V and 0.95V,
respectively. These values imply that a differential
input of –1V corresponds to the zero code of the
ADC, and a differential input of +1V corresponds to
the full-scale code (4095 LSB). VCM (common-mode
voltage of REFT and REFB) is also made available
externally through a pin, and is nominally 1.45V.
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the
digital error correction logic, ensuring excellent
differential linearity and no missing codes at the
12-bit level. The pipeline architecture results in a data
latency of 6.5 clock cycles.
The output of the ADC goes to a serializer that
operates from a 12x clock generated by the PLL. The
12 data bits from each channel are serialized and
sent LSB first. In addition to serializing the data, the
serializer also generates a 1x clock and a 6x clock.
These clocks are generated in the same way the
serialized data is generated, so these clocks maintain
perfect synchronization with the data. The data and
clock outputs of the serializer are buffered externally
using LVDS buffers. Using LVDS buffers to transmit
20
data externally has multiple advantages, such as a
reduced number of output pins (saving routing space
on the board), reduced power consumption, and
reduced effects of digital noise coupling to the analog
circuit inside the ADS5273.
The ADS5273 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
DRIVING THE ANALOG INPUTS
The analog input biasing is shown in Figure 35. The
inputs are biased internally using two 600Ω resistors
to enable ac-coupling. A resistor greater than 20Ω is
recommended in series with each input pin.
A 4pF sampling capacitor is used to sample the
inputs. The choice of the external ac coupling
capacitor is dictated by the attenuation at the lowest
desired input frequency of operation. The attenuation
resulting from using a 10nF ac-coupling capacitor is
0.04%.
ADS5273
IN+
600Ω
Input
Circuitry
600Ω
IN−
VCM
CM Buffer
Internal
Voltage
Reference
NOTE: Dashed area denotes one of eight channels.
Figure 35. Analog Input Bias Circuitry
If the input is dc-coupled, then the output
common-mode voltage of the circuit driving the
ADS5273 should match the VCM (which is provided as
an output pin) to within ±50mV. It is recommended
that the output common-mode of the driving circuit be
derived from the VCM provided by the device.
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Figure 36 shows a detailed RLC model of the
sample-and-hold circuit. The circuit operates in two
phases. In the sample phase, the input is sampled on
two capacitors that are nominally 4pF. The sampling
circuit consists of a low-pass RC filter at the input to
filter out noise components that might be differentially
coupled on the input pins. The next phase is the hold
phase wherein the voltage sampled on the capacitors
is transferred (using the amplifier) to a subsequent
pipeline ADC stage.
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale range supported by the
ADS5273 is nominally 2.03V. The ADS5273 is
specially designed to handle an over-voltage
condition where the differential peak-to-peak voltage
can exceed up to twice the ADC full-scale range. If
the input common-mode is not considerably off from
VCM during overload (less than 300mV around the
nominal value of 1.45V), recovery from an
over-voltage pulse input of twice the amplitude of a
full-scale pulse is expected to be within three clock
cycles when the input switches from overload to zero
strength. All of the amplifiers in the sample-and-hold
amplifier (SHA) and ADC are specially designed for
excellent recovery from an overload signal.
In most applications, the ADC inputs are driven with
differential sinusoidal inputs. While the pulse-type
signal remains at peak overload conditions
throughout its HIGH state, the sinusoid signal only
attains peak overload intermittently, at its minima and
maxima. This condition is much less severe for the
ADC input and the recovery of the ADC output (to 1%
of full-scale around the expected code). This typically
happens within the second clock when the input is
driven with a sinusoid of amplitude equal to twice that
of the ADC differential full-scale range.
IN
OUT
5nH
to 9nH
INP
1.5pF to
2.5pF
15Ω
to 25Ω
15Ω
to 25Ω
1Ω
IN
3.2pF
to 4.8pF
60Ω
to 120Ω
OUT
IN
OUT
500Ω
to 720Ω
OUT
OUTP
1.5pF
to 1.9pF
IN
OUTN
500Ω
to 720Ω
15Ωto 35Ω
15Ω
to 25Ω
15Ω
to 25Ω
IN
3.2pF
to 4.8pF
OUT
60Ω
to 120Ω
IN
OUT
5nH
to 9nH
INN
1.5pF to
2.5pF
Switches that are ON
in SAMPLE phase.
1Ω
Switches that are ON
in HOLD phase.
IN
OUT
Figure 36. Overall Structure of the Sample-and-Hold Circuit
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REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies on gain
matching across all receiver channels. For example,
a typical system has 12 octal ADCs on the board. In
such a case, it is critical to ensure that the gain is
matched, essentially requiring the reference voltages
seen by all the ADCs to be the same. Matching
references within the eight channels of a chip is done
by using a single internal reference voltage buffer.
Trimming the reference voltages on each chip during
production ensures the reference voltages are
well-matched across different chips.
All bias currents required for the internal operation of
the device are set using an external resistor to
ground at the ISET pin. Using a 56.2kΩ resistor on ISET
generates an internal reference current of 20µA. This
current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
resistor at ISET reduces the reference bias current,
and thereby scales down the device operating power.
However, it is recommended that the external resistor
be within 10% of the specified value of 56.2kΩ so
that the internal bias margins for the various blocks
are proper.
Buffering the internal bandgap voltage also generates
a voltage called VCM, which is set to the midlevel of
REFT and REFB, and is accessible on a pin. It is
meant as a reference voltage to derive the input
common-mode in case the input is directly coupled. It
can also be used to derive the reference
common-mode voltage in the external reference
mode.
When using the internal reference mode, a 2Ω
resistor should be added between the reference pins
(REFT and REFB) and the decoupling capacitor, as
shown in Figure 37. If the device is used in the
external reference mode, this 2Ω resistor is not
required.
ADS5273
ISET
REFT
REFB
2Ω
2Ω
0.1µF
2.2µF
56.2kΩ
2.2µF
0.1µF
Figure 37. Internal Reference Mode
22
The device also supports the use of external
reference voltages. This mode involves forcing REFT
and REFB externally. In this mode, the internal
reference buffer is tri-stated. Since the switching
current for the eight ADCs comes from the
externally-forced references, it is possible for the
performance to be slightly less than when the internal
references are used. It should be noted that in this
mode, VCM and ISET continue to be generated from
the internal bandgap voltage, as in the internal
reference mode. Therefore, it is important to ensure
that
the
common-mode
voltage
of
the
externally-forced reference voltages matches to
within 50mV of VCM. The state of the reference
voltages during various combinations of PD and
INT/EXT is shown in Table 1.
Table 1. State of Reference Voltages for Various
Combinations of PD and INT/EXT
PD
0
0
1
INT/EXT
0
1
0
1
1
REFT
Tri-State
1.95V
Tri-State
Tri-State
REFB
Tri-State
0.95V
Tri-State
Tri-State
VCM
1.45V
1.45V
Tri-State(1)
Tri-State(1)
(1) Weak pull-down (approximately 5kΩ) to ground.
CLOCKING
The eight channels on the chip operate from a single
ADCLK input. To ensure that the aperture delay and
jitter are same for all the channels, a clock tree
network is used to generate individual sampling
clocks to each channel. The clock paths for all the
channels are matched from the source point all the
way to the sample-and-hold amplifier. This ensures
that the performance and timing for all the channels
are identical. The use of the clock tree for matching
introduces an aperture delay, which is defined as the
delay between the rising edge of ADCLK and the
actual instant of sampling. The aperture delays for all
the channels are matched to the best possible extent.
However, a mismatch of ±20ps (±3σ) could exist
between the aperture instants of the eight ADCs
within the same chip. However, the aperture delays of
ADCs across two different chips can be several
hundred picoseconds apart. Another critical
specification is the aperture jitter that is defined as
the uncertainty of the sampling instant. The gates in
the clock path are designed to provide an rms jitter of
approximately 1ps.
Ideally, the input ADCLK should have a 50% duty
cycle. However, while routing ADCLK to different
components onboard, the duty cycle of the ADCLK
reaching the ADS5273 could deviate from 50%. A
smaller (or larger) duty cycle reduces the time
available for sample or hold phases of each circuit,
and is therefore not optimal. For this reason, the
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internal PLL is used to generate an internal clock that
has 50% duty cycle. The input sampling instant,
however, is determined by the rising edge of the
external clock and is not affected by jitter in the PLL.
In addition to generating a 50% duty cycle clock for
the ADC, the PLL also generates a 12x clock that is
used by the serializer to convert the parallel data from
the ADC to a serial stream of bits.
serializes it into a single data stream. For a clock
frequency of 70MHz, the data rate output of the
serializer is 840Mbps. The data comes out LSB first,
with a register programmability that allows it to revert
to MSB first. The serializer also transmits a 1x clock
and a 6x clock. The 6x clock (denoted as
LCLKP/LCLKN) is meant to synchronize the capture of
the LVDS data.
The use of the PLL automatically dictates the
minimum sample rate to be about 20MSPS. The PLL
also requires the input clock to be free-running. If the
input clock is momentarily stopped (for a duration of
less than 300ns) then the PLL would require
approximately 10µs to lock back to the input clock
frequency.
Deskew mode can be enabled as well, using a
register setting. This mode gives out a data stream of
alternate 0s and 1s and can be used determine the
relative delay between the 6x clock and the output
data for optimum capture. A 1x clock is also
generated by the serializer and transmitted through
the LVDS buffer. The 1x clock (referred to as
ADCLKP/ADCLKN) is used to determine the start of
the 12-bit data frame. Sync mode (enabled through a
register setting) gives out a data of six 0s followed by
six 1s. Using this mode, the 1x clock can be used to
determine the start of the data frame. In addition to
the deskew mode pattern and the sync mode pattern,
a custom pattern can be defined by the user and
output from the LVDS buffer. The LVDS buffers are
tri-stated in the power-down mode. The LVDS outputs
are weakly forced to 1.2V through 10kΩ resistors
(from each output pin to 1.2V).
LVDS BUFFERS
The LVDS buffer has two current sources, as shown
in Figure 38. OUTP and OUTN are loaded externally
by a resistive load that is ideally about 100Ω.
Depending on whether the data is 0 or 1, the currents
are directed in one direction or the other through the
resistor. The LVDS buffer has four current settings.
The default current setting is 3.5mA, and provides a
differential drop of about ±350mV across the 100Ω
resistor.
The single-ended output impedance of the LVDS
drivers is very high because they are current-source
driven. If there are excessive reflections from the
receiver, it might be necessary to place a 100Ω
termination resistor across the outputs of the LVDS
drivers to minimize the effect of reflections. In such a
situation, the output current of the LVDS drivers can
be increased to regain the output swing.
High
External
Termination
Resistor
Low
OUTP
OUTN
Low
High
Figure 38. LVDS Buffer
The LVDS buffer receives data from a serializer that
takes the output data from each channel and
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various
types of noise coupling. One of the main sources of
noise is the switching noise from the serializer and
the output buffers. Maximum care is taken to isolate
these noise sources from the sensitive analog blocks.
As a starting point, the analog and digital domains of
the chip are clearly demarcated. AVDD and AVSS
are used to denote the supplies for the analog
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the device. The extent of noise coupled and
transmitted from the digital to the analog sections
depends on the following:
1. The effective inductance of each of the
supply/ground sets.
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground
pins leads to better noise suppression. For this
reason, multiple pins are used to drive each
supply/ground. It is also critical to ensure that the
impedances of the supply and ground lines onboard
are kept to the minimum possible values. Use of
ground planes in the board as well as large
decoupling capacitors between the supply and
ground lines are necessary to get the best possible
SNR from the device.
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ADS5273
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RESET
It is recommended that the isolation be maintained
onboard by using separate supplies to drive AVDD
and LVDD, as well as separate ground planes for
AVSS and LVSS.
After the supplies have stabilized, it is required to
give the device an active RESET pulse. This results
in all internal registers getting reset to their default
value of 0 (inactive). Without a reset, it is possible
that some registers might be in their non-default state
on power-up. This could cause the device to
malfunction. When a reset is active, the device
outputs 0 code on all channels. However, the LVDS
output clocks are unaffected by reset.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The
current in the LVDS buffer is independent of the
direction of switching. Also, the low output swing, as
well as the differential nature of the LVDS buffer,
results in low-noise coupling.
POWER-DOWN MODE
LAYOUT OF PCB WITH PowerPAD
THERMALLY-ENHANCED PACKAGES
The ADS5273 has a power-down pin, referred to as
PD. Pulling PD high causes the device to enter the
power-down mode. In this mode, the reference and
clock circuitry, as well as all the channels, are
powered down. Device power consumption drops to
less than 100mW in this mode. In power-down mode,
the internal buffers driving REFT and REFB are
tri-stated and their outputs are forced to a voltage
roughly equal to half of the voltage on AVDD. Speed
of recovery from power-down mode depends on the
value of the external capacitance on the REFT and
REFB pins. For capacitances on REFT and REFB less
than 1µF, the reference voltages settle to within 1%
of their steady-state values in less than 500µs.
Individual channels can also be selectively powered
down by programming registers.
The ADS5273 is housed in an 80-lead PowerPAD
thermally-enhanced package. To make optimum use
of the thermal efficiencies designed into the
PowerPAD package, the printed circuit board (PCB)
must be designed with this technology in mind.
Please refer to PowerPAD brief SLMA004,
PowerPAD Made Easy (available for download at
www.ti.com),
which
addresses
the
specific
considerations
required
when
integrating
a
PowerPAD package into a PCB design. For more
detailed information, including thermal modeling and
repair procedures, please see technical brief
SLMA002, PowerPAD Thermally-Enhanced Package
(www.ti.com).
Interfacing High-Speed LVDS Outputs (SBOA104),
an application report discussing the design of a
simple deserializer that can deserialize LVDS outputs
up to 840Mbps, can be found on the TI web site
(www.ti.com).
The ADS5273 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped (or if it runs at a speed less than 3MHz), this
monitoring circuit generates a logic signal that puts
the device in a power-down state. As a result, the
power consumption of the device is reduced to less
than 100mW when ADCLK is stopped. The recovery
from such a power-down could take approximately
100µs; this is described in Table 2.
CONNECTING HIGH-SPEED,
MULTI-CHANNEL ADCs TO XILINX FPGAs
A separate application report (XAPP774) describing
how to connect TI's high-speed, multi-channel ADCs
with serial LVDS outputs to Xilinx FPGAs can be
downloaded directly from the Xilinx web site
(http://www.xilinx.com).
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
TYP
Recovery from power-down mode (PD = 1 to PD = 0).
500µs
Recovery from momentary clock stoppage ( < 300ns).
10µs
Recovery from extended clock stoppage ( > 300ns).
100µs
24
REMARKS
Capacitors on REFT and REFB less than 1µF.
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Revision History
Changes from Revision C (September 2005) to Revision D .......................................................................................... Page
•
Updated Absolute Maximum Ratings table: added entries for Digital Input Pins, Set 1 and Set 2 and added footnote 3.... 2
Changes from Revision B (August 2005) to Revision C ................................................................................................ Page
•
•
•
•
•
•
Deleted parallel from first paragraph of Description section.................................................................................................. 1
Changed front page figure. .................................................................................................................................................... 1
Changed unit values in Lead Temperature and Storage Temperature rows in Absolute Maximum Ratings table............... 2
Deleted condition value for CO row in LVDS table................................................................................................................. 7
Changed Figure 30. ............................................................................................................................................................. 18
Changed 2.0ps to 20ps and added (±3σ) to seventh sentence of first paragraph of Clocking section in Theory of
Operation. ............................................................................................................................................................................ 22
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS5273IPFP
ACTIVE
HTQFP
PFP
80
96
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5273IPFP
ADS5273IPFPG4
ACTIVE
HTQFP
PFP
80
96
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5273IPFP
ADS5273IPFPT
ACTIVE
HTQFP
PFP
80
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5273IPFP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS5273IPFPT
Package Package Pins
Type Drawing
HTQFP
PFP
80
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
24.4
Pack Materials-Page 1
15.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5273IPFPT
HTQFP
PFP
80
250
213.0
191.0
55.0
Pack Materials-Page 2
www.ti.com
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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DLP® Products
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