11 August 2011 AUIRS2334S 3 PHASE GATE DRIVER HVIC Product Summary Features Floating channel designed for bootstrap operation Fully operational to 600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Integrated dead time protection Shoot-through (cross-conduction) prevention logic Under-Voltage lockout for both channels Independent 3 half-bridge drivers 3.3 V input logic compatible Advanced input filter Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity Outputs in phase with inputs RoHS compliant, lead free Automotive qualified Topology 3 phase VOFFSET ≤ 600 V 10 V – 20 V VOUT Io+ & I o- (typical) 200 mA & 350 mA tON & tOFF (typical) 530 ns Package Options Typical Applications Motor Control Low Power Fans General Purpose Inverters Micro/Mini Inverter Drivers 20 leads wide body SOIC Typical Connection Diagram Up to 600V Vcc Vcc HIN1,2,3 HIN1,2,3 LIN1,2,3 LIN1,2,3 VB1,2,3 HO1,2,3 VS 1,2,3 TO LOAD LO1,2,3 COM IRS2334 GND www.irf.com 02-Apr-10 1 © 2010 International Rectifier AUIRS2334S Table of Contents Page Description 3 Simplified Block Diagram 3 Typical Application Diagram 4 Qualification Information 5 Absolute Maximum Ratings 6 Recommended Operating Conditions 6 Static Electrical Characteristics 7 Dynamic Electrical Characteristics 7 Functional Block Diagram 8 Input/Output Pin Equivalent Circuit Diagram 9 Lead Definitions 10 Lead Assignments 10 Application Information and Additional Details 11 - 22 Parameter Temperature Trends 22 - 25 Package Details 26 Tape and Reel Details 27 Part Marking Information 28 Ordering Information 28 www.irf.com © 2010 International Rectifier 2 AUIRS2334S Description The AUIRS2334S is a high voltage, high speed power MOSFET and IGBT driver with three independent high side and low side referenced output channels for 3-phase applications. Proprietary HVIC and latch immune CMOS technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration up to 600 V. Simplified Block Diagram VCC HV floating well Schmitt trigger, minimum dead time and shoot-through protection bootstrap diode VB high side power supply high side output high side input HV Level Shifters VS high side supply return low side input to high side power switches (x3) low side output Delay COM to low side power switches (x3) GND www.irf.com © 2010 International Rectifier 3 AUIRS2334S Typical Application Diagram Rail Voltage ≤ 600 V To Load Input Voltage IRS2334 AUIRS2334 VCC Control Inputs www.irf.com © 2010 International Rectifier 4 AUIRS2334S Qualification Information† Automotive (per AEC-Q100††) Comments: This family of ICs has passed an Automotive qualification. IR‘s Industrial and Consumer qualification level is granted by extension of the higher Automotive level. Qualification Level SOIC20W Moisture Sensitivity Level Class M2(+/-150V) (per AEC-Q100-003) Class H1B(+/-750V) (per AEC-Q100-002) Class C4(+/-1000V) (per AEC-Q100-011) Class II, Level A (per AEC-Q100-004) Yes Machine Model ESD MSL3††† 260°C (per IPC/JEDEC J-STD-020) Human Body Model Charged Device Model IC Latch-Up Test RoHS Compliant † Qualification standards can be found at International Rectifier‘s web site http://www.irf.com/ †† Exceptions (if any) to AEC-Q100 requirements are noted in the qualification report. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com © 2010 International Rectifier 5 AUIRS2334S Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO1,2,3 VCC VLO1,2,3 VIN PWHIN dVS/dt PD RthJA TJ TS TL † Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic and analog input voltages High-side input pulse width Allowable offset supply voltage slew rate Package power dissipation @ TA ≤ 25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) 20 lead SOIC 20 lead SOIC Min. Max. -0.3 † VB1,2,3 - 25 VS1,2,3 - 0.3 -0.3 -0.3 -0.3 500 — — — — -55 — 625 VB1,2,3 + 0.3 VB1,2,3 + 0.3 † 25 VCC + 0.3 VCC + 0.3 — 50 1.14 65.8 150 150 300 Units V ns V/ns W °C/W °C All supplies are fully tested at 25 V. An internal 25 V clamp exists for each supply. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM unless otherwise specified. The VS1,2,3 offset ratings are tested with all supplies biased at 15 V. Symbol VB1,2,3 VS1,2,3 VS1,2,3(t) VHO1,2,3 VCC VLO1,2,3 VIN TA † †† Definition Min. High side floating supply voltage † Static high side floating supply offset voltage Transient high side floating supply offset voltage†† High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Ambient temperature VS1,2,3 +10 -8 -50 VS1,2,3 10 0 0 -40 Max. VS1,2,3 + 20 600 600 VB1,2,3 20 VCC VCC 125 Units V °C Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Operational for transient negative VS of -50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com © 2010 International Rectifier 6 AUIRS2334S Static Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of (VCC-COM) = (VB1,2,3-VS1,2,3) = 15 V. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the output leads LO1,2,3 and HO1,2,3 respectively. The VCCUV and VBSUV parameters are referenced to COM and VS respectively. Symbol VIH VIL VIN,TH+ VIN,THVOH VOL VCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH ILK IQBS IQCC IIN+ IINIo+ Io- Definition Min. Typ. Max. Units 2.5 — — — — — — — 1.9 1 0.9 0.4 — 0.8 — — 1.4 0.6 V 10.4 11.1 11.6 10.2 10.9 11.4 VCC and VBS supply under-voltage hysteresis 0.05 0.2 — Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic ―1‖ input bias current Logic ―0‖ input bias current Output high short circuit pulsed current Output low short circuit pulsed current — — — — — 120 200 1 40 300 150 50 120 700 250 1 — — Logic ―1‖ input voltage Logic ―0‖ input voltage Input positive going threshold Input negative going threshold High level output voltage Low level output voltage VCC and VBS supply under-voltage positive going threshold VCC and VBS supply under-voltage negative going threshold 200 350 µA µA Test Conditions IO = 20 mA VB =VS = 600 V VIN = 0 V µA VIN = 5 V VIN = 0 V mA VO = 0 V or 15 V PW ≤ 10 µs Dynamic Electrical Characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C with bias conditions of VCC = VB1,2,3 = 15 V, VS1,2,3 = COM, and CL = 1000 pF unless otherwise specified. Symbol ton toff tr tf tFILIN DT MDT MT PM † Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Input filter time Dead time Dead time matching ton, toff propagation delay matching time † PW pulse width distortion Min. Typ. Max. 400 400 — — 200 180 — — — 530 530 125 50 350 290 — — — 750 750 190 75 510 420 70 60 75 Units Test Conditions VIN = 0V and 5V ns VIN = 0V & 5V External dead time 0s PW input =10µs PM is defined as PWIN - PWOUT. www.irf.com © 2010 International Rectifier 7 AUIRS2334S Functional Block Diagram HIN1 Input Noise Filter LIN1 Input Noise Filter HIN2 Input Noise Filter LIN2 Input Noise Filter HIN3 Input Noise Filter LIN3 Input Noise Filter AUIRS2334 SD VB1 HV Level Shifter Deadtime & Shoot-Through Prevention SET Latch RESET UV Detect Driver HO1 VS1 VB2 SD HV Level Shifter Deadtime & Shoot-Through Prevention SET Latch RESET UV Detect SET Latch RESET UV Detect Driver HO2 VS2 VB3 SD Deadtime & Shoot-Through Prevention HV Level Shifter Driver HO3 VS3 VCC UV Detect Delay Driver LO1 Delay Driver LO2 Delay Driver LO3 COM www.irf.com © 2010 International Rectifier 8 AUIRS2334S Input/Output Pin Equivalent Circuit Diagrams VB1,2,3 ESD Diode 25 V Clamp HO1,2,3 ESD Diode VCC ESD Diode VS1,2,3 600 V LIN, HIN ESD Diode R VCC pulldown ESD Diode COM 25 V Clamp LO1,2,3 ESD Diode COM www.irf.com © 2010 International Rectifier 9 AUIRS2334S Lead Definitions Symbol VCC VB1 VB2 VB3 VS1 VS2 VS3 HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 HO1 HO2 HO3 LO1 LO2 LO3 COM Description Low side and logic power supply High side floating power supply (phase 1) High side floating power supply (phase 2) High side floating power supply (phase 3) High side floating supply return (phase 1) High side floating supply return (phase 2) High side floating supply return (phase 3) Logic input for high side gate driver output HO1, input is in-phase with output Logic input for high side gate driver output HO2, input is in-phase with output Logic input for high side gate driver output HO3, input is in-phase with output Logic input for low side gate driver output LO1, input is in-phase with output Logic input for low side gate driver output LO2, input is in-phase with output Logic input for low side gate driver output LO3, input is in-phase with output High side gate driver output (phase 1) High side gate driver output (phase 2) High side gate driver output (phase 3) Low side gate driver output (phase 1) Low side gate driver output (phase 2) Low side gate driver output (phase 3) Low side supply return Lead Assignments 20 leads wide body SOIC 1 HIN1 VB1 20 2 HIN2 HO1 19 3 HIN3 VS1 18 4 LIN1 VB2 17 5 LIN2 HO2 16 6 LIN3 VS2 15 7 COM VB3 14 8 LO3 HO3 13 9 LO2 VS3 12 10 LO1 VCC 11 www.irf.com © 2010 International Rectifier 10 AUIRS2334S Application Information and Additional Details IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Shoot-Through Protection Under-Voltage Lockout Protection Truth Table: Under-Voltage lockout Advanced Input Filter Short-Pulse and Noise Rejection Tolerant to Negative VS Transients PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The AUIRS2334 HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and 2 show the definition of some of the relevant parameters associated with the gate driver output functionality. The output current that drives the gate of the external power switches is defined as IO. The output voltage that drives the gate of the external power switches is defined as VHO for the high side and VLO for the low side; this parameter is sometimes generically called VOUT and in this case the high side and low side output voltages are not differentiated. VB (or VCC) VB (or VCC) IO+ H (orOLO) H (orOLO) + VH (or VL ) VS - O IO - O VS (or ) COM (or ) COM Figure 1: HVIC sourcing current Figure 2: HVIC sinking current www.irf.com © 2010 International Rectifier 11 AUIRS2334S Switching and Timing Relationships The relationship between the input and output signals of the AUIRS2334 HVIC is shown in Figure 3. The definitions of some of the relevant parameters associated with the gate driver input to output transmission are given. LIN or HIN 50% 50% PWIN t ON LO or HO tOFF tR tF PWOUT 90% 10% 90% 10% Figure 3: Switching time waveforms During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at the same time; correspondingly, the shoot-through protection prevents the high and low side signals HO and LO turn on by keeping them low. A HIN LIN HO LO Figure 4: Input/output timing diagram Deadtime The AUIRS2334 HVIC provides an integrated deadtime protection circuitry. The deadtime interval for this HVIC is fixed; while other ICs within IR‘s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time interval in which both the gate driver outputs LO and HO are held off; to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime commanded by the host www.irf.com © 2010 International Rectifier 12 AUIRS2334S microcontroller is shorter than DT, while external deadtimes larger than DT are not modified by the gate driver. Figure 7 illustrates the deadtime interval definition and the relationship between the output gate signals. The deadtime interval introduced is matched with respect to the commutation from HIN turning off to LIN turning on, and viceversa. Figure 5 defines the two deadtime parameters DT1 and DT2. The deadtime matching parameter MDT is defined as the maximum difference between DT1 and DT2. LIN HIN 50% LO HO 50% DT1 DT2 50% 50% Figure 5: Deadtime definition Matched Propagation Delays The AUIRS2334 HVIC is designed for propagation delay matching. With this feature, the input to output propagation delays tON, tOFF are the same for the low side and the high side channels; the maximum difference being specified by the delay matching parameter MT as defined in Figure 6. 50 % HIN LIN 50% LO HO 10% MT MT 90% LO HO Figure 6: Delay Matching Waveform Definition Input Logic Compatibility The AUIRS2334 HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5 V logic level signals. Figure 7 shows how an input signal is logically interpreted. www.irf.com © 2010 International Rectifier 13 AUIRS2334S VIL Level Input Logic Input Signal VIH High Low Low Figure 7: HIN & LIN input thresholds Shoot-Through Protection The AUIRS2334 is equipped with a shoot-through protection circuitry which prevents cross-conduction of the power switches. Table 1 shows the input to output relationship in the form of a truth table. Note that the HVIC has non-inverting inputs (the output is in-phase with the respective input). HIN LIN HO LO 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 Table 1: Input/output truth table Under-Voltage Lockout Protection The AUIRS2334 HVIC provides under-voltage lockout protection on both the VCC low side and logic fixed power supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the VCC (or VBS) plotted over time: as the waveform crosses the UVLO threshold, the under-voltage protection is entered or exited. Upon power up, should the VCC voltage fail to reach the VCCUV+ threshold, the gate driver outputs LO and HO will remain disabled. Additionally, if the VCC voltage decreases below the VCCUV- threshold during normal operation, the under-voltage lockout circuitry will shutdown the gate driver outputs LO and HO. Upon power up, should the VBS voltage fail to reach the VBSUV threshold, the gate driver output HO will remain disabled. Additionally, if the VBS voltage decreases below the VBSUV threshold during normal operation, the undervoltage lockout circuitry will shutdown the high side gate driver output HO. The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven www.irf.com © 2010 International Rectifier 14 AUIRS2334S with a low voltage, which would result in power switches conducting current while with a high channel impedance, which would produce very high conduction losses possibly leading to power device failure. VCC (or B ) V S V CCU + ( or V BSU + ) V V VCCU (or V BSU - ) V V Time UVLO Protection ( Gate Driver Outputs Disabled ) Norma l Operation Norma l Operation Figure 8: UVLO protection Truth Table: Under-Voltage lockout Table 2 provides the truth table for the AUIRS2334 HVIC. The 1st line shows that for VCC below the UVLO threshold both the gate driver outputs LO and HO are disabled. After VCC returns above VCCUV, the gate driver outputs return functional. The 2nd line shows that for VBS below the UVLO threshold, the gate driver output HO is disabled. After VBS returns above VBSUV, HO remains low until a new rising transition of HIN is received. The last line shows the normal operation of the HVIC. UVLO VCC UVLO VBS Normal operation VCC VBS <VCCUV 15 V 15 V <VBSUV 15 V outputs LO 0 LIN LIN HO 0 0 HIN Table 2: UVLO truth table Advanced Input Filter The AUIRS2334 HVIC provides an advanced input filter that improves the input/output pulse symmetry of the signals processed by the HVIC. This input filter is inserted at the HIN and LIN input pins. The working principle of the filter is shown in Figures 9 and 10. Figure 9 shows a typical input filter and the asymmetry it produces on its output signal. The upper waveforms of Example 1 show an input signal with a pulse duration mush longer than the filtering time tFILIN; the resulting output www.irf.com © 2010 International Rectifier 15 AUIRS2334S signal has a duration given approximately by the difference between the input signal and tFILIN. The lower waveforms of Example 2 show an input signal with a pulse duration slightly longer than the filtering time tFILIN; the resulting output signal has a duration given approximately by the difference between the input signal and tFILIN, much shorter than it should be. IN tFIL,IN Example 1 Example 1 IN Example 2 Figure 10 shows the advanced input filter and the symmetry it produces on its output signal. The upper waveforms of Example 1 show an input signal with a pulse duration much longer than the filtering time tFILIN; the resulting output signal has approximately the same duration as the input signal. The lower waveforms of Example 2 show an input signal with a pulse duration slightly longer than the filtering time tFILIN; the resulting output signal has approximately the same duration as the input signal. OUT Example 2 tFIL,IN OUT Figure 9: Typical input filter IN tFIL,IN OUT IN tFIL,IN OUT Figure 10: Advanced input filter Short-Pulse and Noise Rejection The advanced input filter that improves the input/output pulse symmetry of the signals processed by the HVIC also helps the rejection of noise spikes and of short pulses on the input signals. Example 1 IN Example 2 Input signals with a pulse duration less than the filtering time tFILIN will be filtered out. In Figure 11 Example 1 shows an input signal in the low state with superimposed positive noise spikes of duration less than tFILIN; the advanced input filter filters out the noise spikes and the output signal remains in the low state. Example 2 shows an input signal in the high state with superimposed negative noise spikes of duration less than tFILIN; the advanced input filter filters out the noise spikes and the output signal remains in the high state. IN tFIL,IN OUT tFIL,IN OUT Figure 11: Noise rejection of the advanced input filter www.irf.com © 2010 International Rectifier 16 AUIRS2334S The measured characteristic of the advanced input filter is shown in Figure 12. On the left side the characteristic for narrow ON pulses is shown (short positive pulse) while on the left side the characteristic for narrow OFF pulses is shown (short negative pulse). The x-axis represents the input pulse duration PWIN, while the y-axis the resulting output pulse duration PWOUT. For pulses with input pulse duration PWIN less than the filtering time tFILIN the resulting output pulse duration PWOUT is zero because the filter rejects the input signal. For pulses with input pulse duration PWIN greater than the filtering time tFILIN the resulting output pulse duration PWOUT tracks the input pulse durations well, the higher the duration the better the symmetry. Narrow Pulse ON Narrow Pulse OFF 1000 PWOUT PWIN PWOUT PWIN 800 800 600 600 Time (ns) Time (ns) 1000 400 400 200 200 0 0 0 200 400 600 800 0 1000 200 400 600 800 1000 Time (ns) Time (ns) Figure 12: Measured advanced input filter characteristic The difference between the output pulse duration PWOUT and the input pulse duration PWIN of both the narrow ON and narrow OFF cases is shown in Figure 13. The x-axis represents the input pulse duration PWIN, while the y-axis the resulting difference PWOUT–PWIN. Narrow Pulse ON Narrow Pulse OFF 120 120 PWOUT-PWIN PWOUT-PWIN 100 100 80 Short Pulse Filtered 60 40 Time (ns) Time (ns) 80 Short Pulse Filtered 60 40 20 20 0 0 0 200 400 600 800 1000 0 200 400 600 800 1000 Time (ns) Time (ns) Figure 13: Difference between the input pulse duration and the output pulse duration Tolerant to Negative VS Transients A common problem in today‘s high-power switching converters is the transient response of the switch node‘s voltage as the power devices switch on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 14; where we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 15 and 16) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. www.irf.com © 2010 International Rectifier 17 AUIRS2334S DC+ BUS D1 Q1 Input Voltage VS1 Q2 D3 Q3 VS2 U D2 Q4 D5 Q5 VS3 V D4 Q6 W To Load D6 DC- BUS Figure 14: Three phase inverter DC+ BUS DC+ BUS Q1 ON Q1 OFF D1 IU VS1 VS1 IU Q2 OFF D2 Q2 OFF DC- BUS D2 DC- BUS Figure 15: Q1 conducting Figure 16: D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 17 and 18), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. DC+ BUS Q3 OFF DC+ BUS D3 Q3 OFF D3 IV VS2 VS2 IV Q4 OFF D4 Q4 ON DC- BUS DC- BUS Figure 17: D3 conducting Figure 18: Q4 conducting However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the level of the negative DC bus. This undershoot voltage is called ―negative VS transient‖. www.irf.com © 2010 International Rectifier 18 AUIRS2334S The circuit shown in Figure 19 depicts one leg of the three phase inverter; Figures 20 and 21 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). DC+ BUS DC+ BUS + LC1 D1 Q1 VLC1 - Q1 ON VLE1 VS1 IU - VS1 LC2 Q2 D2 DC- BUS - VLC2 IU + D2 Q2 OFF - Q2 OFF VD2 + - LE2 Figure 19: Parasitic Elements D1 Q1 OFF + LE1 VS1 DC+ BUS VLE2 + DC- BUS Figure 20: VS positive DC- BUS Figure 21: VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. International Rectifier‘s HVICs have been designed for the robustness required in many of today‘s demanding applications. An indication of the AUIRS2334‘s robustness can be seen in Figure 22, where there is represented the AUIRS2334 Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; vice versa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA. At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design the high-side outputs in the off state for 4.5 μs. www.irf.com © 2010 International Rectifier 19 AUIRS2334S Figure 22: Negative VS transient SOA @ VBS=15V Even though the AUIRS2334 has been shown able to handle these large negative VS transient conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use. www.irf.com © 2010 International Rectifier 20 AUIRS2334S PCB Layout Tips Distance between high and low voltage components: It‘s strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case Outline information in this datasheet for the details. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 23). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. VB (or CC ) V H (orO ) LO IGC CGC RG Gate Drive Loo p VS (or COM VGE ) Figure 23: Antenna Loops Supply Capacitor: It is recommended to place a bypass capacitor between the VCC and COM pins. This connection is shown in Figure 24. A ceramic 1 μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce parasitic elements. Up to 600V Vcc Vcc HIN1,2,3 HIN1,2,3 LIN1,2,3 LIN1,2,3 VB1,2,3 HO1,2,3 VS 1,2,3 TO LOAD LO1,2,3 COM GND Figure 24: Supply capacitor www.irf.com © 2010 International Rectifier 21 AUIRS2334S Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side source to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 25), and in some cases using a clamping diode between COM and VS (see Figure 26). See DT04-4 at www.irf.com for more detailed information. DC+ BU S DC+ BUS VB VB C BS C BS HO HO VS R VS VS To Load L O RVS T Load o D VS L O CO M CO M DC- BUS DC- BU S Figure 25: VS resistor Figure 26: VS clamping diode Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs Parameter Temperature Trends Figures 27-44 provide information on the experimental performance of the AUIRS2334 HVIC. The line plotted in each figure is generated from actual experimental data. A small number of individual samples were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). www.irf.com © 2010 International Rectifier 22 600 Turn-off Propagation Delay (ns) Turn-on Propagation Delay (ns) AUIRS2334S M ax. 575 Typ. 550 M in. 525 500 -50 -25 0 25 50 75 100 650 M ax. 600 Typ. 550 M in. 500 450 -50 125 -25 0 Fig. 27. Turn-on Propagation Delay vs. Temperature 75 100 125 Fig. 28. Turn-off Propagation Delay vs. Temperature 70 Turn-Off fall Time (ns) - 175 Turn-On Rise Time (ns) 50 Temperature ( C) Temperature ( C) 150 125 M ax. 100 Typ. 60 50 M ax. 40 Typ. M in. 75 M in. 30 -50 -25 0 25 50 75 100 125 -50 -25 0 o 25 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 29. Turn-on Rise Time vs. Temperature Fig.30. Turn-off Fall Time vs. Temperature 400 1,100 900 M ax. 700 Typ. M in. 500 -50 -25 0 25 50 75 100 125 Temperature (oC) Low Level Output Voltage (mV) 1,300 High Level Output Voltage (mV) . 25 o o 350 300 M ax 250 Typ. 200 M in. 150 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 31. High Level Output Voltage (IO = 20mA) vs. Temperature Fig. 32. Low Level Output Voltage (IO = 20mA) vs. Temperature www.irf.com © 2010 International Rectifier 23 16 12 M ax. 8 4 Typ. M in. 0 -50 -25 0 25 50 75 100 125 Quiescent VCC Supply Current (mA) Offset Supply Leakage Current (uA). AUIRS2334S 1.00 0.75 0.50 M ax. Typ. 0.25 M in. 0.00 -50 -25 0 o Input Filter Time (ns) . Typ. 375 M in. 325 275 225 0 25 50 75 100 125 50 M ax. 40 30 Typ. M in. 20 -50 -25 0 25 M ax. 11.00 Typ. 10.75 M in. 10.50 75 100 125 VCC Supply UV- Going Threshold (V) VCC Supply UV+ Going Threshold (V) 11.25 50 100 125 Fig. 36. Quiescent VBS Supply Current vs. Temperature 11.50 25 75 Temperature ( C) Fig. 35. Input Filter Delay Time vs. Temperature 0 50 o Temperature ( C) -25 125 60 o -50 100 Fig. 34. Quiescent VCC Supply Current vs. Temperature Quiescent VBS Supply Current (uA) M ax. -25 75 Temperature ( C) Fig. 33. Offset Supply Leakage Current vs. Temperature -50 50 o Temperature ( C) 425 25 11.30 11.05 10.80 M ax . Typ. 10.55 M in. 10.30 -50 -25 0 25 50 75 100 125 o o Temperature ( C) Temperature ( C) Fig. 37. VCC Supply Under-voltage Positive Going Threshold vs. Temperature Fig. 38. VCC Supply Under-voltage Negative Going Threshold vs. Temperature www.irf.com © 2010 International Rectifier 24 11.50 11.25 M ax. 11.00 Typ. 10.75 M in. 10.50 -50 -25 0 25 50 75 100 125 Temperature (oC) 11.30 11.05 M ax. 10.80 Typ. 10.55 M in. 10.30 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 39. VBS Supply Under-voltage Positive Going Threshold vs. Temperature Fig. 40. VBS Supply Under-voltage Negative Going Threshold vs. Temperature 500 500 400 400 Io+ (mA) Io- (mA) VBS Supply UV- Going Threshold (V) VBS Supply UV+ Going Threshold (V) AUIRS2334S 300 Exp. 200 100 300 Exp. 200 100 0 0 -50 -25 0 25 50 75 100 125 o -50 -25 0 25 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 41. Output Low Short Circuit Pulsed Current vs. Temperature www.irf.com Fig. 42. Output High Short Circuit Pulsed Current vs. Temperature © 2010 International Rectifier 25 AUIRS2334S Package Details www.irf.com © 2010 International Rectifier 26 AUIRS2334S Tape and Reel Details LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 20SOICW Metri Imperial Cod Mi c Ma Min Ma e n x x A 11.9 12.1 0.46 0.47 03.9 04.1 8 6 B 0.15 0.16 0 0 3 1 C 23.7 24.3 0.93 0.95 0 0 3 6 D 11.4 11.6 0.44 0.45 0 0 8 6 E 10.8 11.0 0.42 0.43 013.2 013.4 50.52 30.52 F 01.5 0n/ 0 8n/ G 0.05 0 a 9 a H 1.5 1.6 0.05 0.06 0 0 9 2 F D C B A E G H REEL DIMENSIONS FOR 20SOICW Metri Imperial Cod Mi c Ma Min Ma e n x x A 329.6 330.2 12.97 13.00 020.9 521.4 60.82 10.84 B 5 5 4 4 C 12.8 13.2 0.50 0.51 01.9 02.4 3 9 D 0.76 0.09 5 5 7 6 E 98.0 102.0 3.85 4.01 0n/ 030.4 8n/ 5 F 1.19 a 0 a 6 G 26.5 29.1 1.0 1.14 0 0 4 5 H 24.4 26.4 0.9 1.03 0 0 6 9 www.irf.com © 2010 International Rectifier 27 AUIRS2334S Part Marking Information Part number AUIRS2334 Date code AYWW ? IR logo Pin 1 Identifier ? XXXX ? MARKING CODE P Lead Free Released Lot Code (Prod mode – 4 digit SPN code) Assembly site code Per SCOP 200-002 Non-Lead Free Released Ordering Information Standard Pack Base Part Number AUIRS2334 Package Type SOIC20W Complete Part Number Form Quantity Tube/Bulk 36 AUIRS2334S Tape and Reel 1000 AUIRS2334STR www.irf.com © 2010 International Rectifier 28 AUIRS2334S IMPORTANT NOTICE Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. Part numbers designated with the ―AU‖ prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance and process change notification. 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