Order Now Product Folder Support & Community Tools & Software Technical Documents CSD95496QVM SLPS675 – JUNE 2017 CSD95496QVM Synchronous Buck NexFET™ Smart Power Stage 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • • 40-A Continuous Operating Current Capability Over 93% System Efficiency at 20 A High-Frequency Operation (up to 1.25 MHz) Diode Emulation Function Temperature Compensated Bi-Directional Current Sense Analog Temperature Output Fault Monitoring 3.3-V and 5-V PWM Signal Compatible Tri-State PWM Input Integrated Bootstrap Switch Optimized Dead Time for Shoot-Through Protection High-Density VSON 4-mm × 5-mm Footprint Ultra-Low-Inductance Package System Optimized PCB Footprint RoHS Compliant – Lead-Free Terminal Plating Halogen Free Multiphase Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications POL DC-DC Converters Memory and Graphic Cards Desktop and Server VR12.x / VR13.x VRM Synchronous Buck Converters • • • 3 Description The CSD95496QVM NexFET™ power stage is a highly optimized design for use in a high-power, highdensity synchronous buck converter. This product integrates the driver IC and power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 4-mm × 5-mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. Device Information(1) Application Diagram P12V AVSP AVSN TPS53659 BOOT VIN ASKIP# P5V EN/FCCM VOS QTY PACKAGE SHIP 2500 CSD95496QVMT 7-Inch Reel 250 VSON 4.00-mm × 5.00-mm Package Tape and Reel VSW VDD TAO LSET MEDIA 13-Inch Reel BOOT_R CSD95496QVM PWM PWM1 DEVICE CSD95496QVM PGND IOUT REFIN LOAD (1) For all available packages, see the orderable addendum at the end of the data sheet. ACSP1 P12V BOOT VIN P5V BOOT_R CSD95496QVM PWM APWM2 EN/FCCM VOS Typical Power Stage Efficiency and Power Loss VSW VDD TAO LSET PGND 100 IOUT REFIN VREF ADDR ACSP2 3.3V VIN_CSNIN P5V CSD95496QVM EN/FCCM VOS VSW VDD TAO CSPIN LSET PGND IOUT REFIN BEN_VCCIO ACSP3 TSEN VREF 6.4 85 5.6 80 V = 5 V DD 75 VIN = 12 V VOUT = 1.2 V 70 LOUT = 220 nH fSW = 500 kHz 65 TA = 25qC 4.8 60 1.6 4 3.2 2.4 55 0.8 50 0 3.3V AGND 90 ACSP4 Power Loss (W) PWM APWM3 P12V BOOT_R Efficiency (%) BOOT VIN SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT# SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# 7.2 P12V V3P3 VCCIO 8 95 4 8 12 16 20 24 28 Output Current (A) 32 36 0 40 D000 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD95496QVM SLPS675 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 8 8.1 8.2 8.3 8.4 8.5 9 6.1 Absolute Maximum Ratings ...................................... 4 6.2 ESD Ratings.............................................................. 4 6.3 Recommended Operating Conditions....................... 4 7 Device and Documentation Support.................... 6 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 6 6 6 6 6 Mechanical, Packaging, and Orderable Information ............................................................. 7 9.1 Mechanical Drawing.................................................. 7 9.2 Recommended PCB Land Pattern............................ 8 9.3 Recommended Stencil Opening ............................... 9 Application Schematic .......................................... 5 4 Revision History 2 DATE REVISION NOTES June 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM CSD95496QVM www.ti.com SLPS675 – JUNE 2017 5 Pin Configuration and Functions Top View Pin Functions PIN DESCRIPTION NAME NO. REFIN 1 External reference voltage input for current sensing amplifier. IOUT 2 Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current. LSET 3 A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry. VDD 4 Supply voltage for gate drivers and internal circuitry. VOS 5 Output voltage sensing pin for the internal current sensing circuitry. SW 6-9 VIN 10-13 Phase node connecting the HS MOSFET Source and LS MOSFET drain – pin connection to the output inductor. Input voltage pin. Connect input capacitors close to this pin. BOOTR 14 Return path for HS gate driver. It is connected to VSW internally. BOOT 15 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic cap from BOOT to BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. PWM 16 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for greater than the tri-state shutdown holdoff time (t3HT). EN/FCCM 17 This dual function pin either enables the diode emulation function or can be used as a simple enable for the device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time, Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left floating. TAO/FAULT 18 Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown, LSOC, or HSS detection circuit is tripped. PGND 19 Power ground. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM 3 CSD95496QVM SLPS675 – JUNE 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings TA = 25°C (unless otherwise stated) (1) MIN MAX UNIT VIN to PGND –0.3 20 V VIN to VSW –0.3 20 V 23 V –0.3 20 V VIN to VSW (10 ns) VSW to PGND VSW to PGND (10 ns) –7 23 V VDD to PGND –0.3 7 V EN/FCCM, TAO/FLT, LSET to PGND (2) –0.3 VDD + 0.3 V IOUT, VOS, PWM to PGND –0.3 7 V REFIN –0.3 3.6 V BOOT to BOOTR (2) –0.3 VDD + 0.3 V BOOT to PGND –0.3 30 V TJ Operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Should not exceed 7 V. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 Charged-device model (CDM) ±500 UNIT V 6.3 Recommended Operating Conditions TA = 25°C (unless otherwise stated) VDD Driver supply voltage (1) MIN MAX 4.5 5.5 V 4.5 UNIT VIN Input supply voltage 16 V VOUT Output voltage 5.5 V PWM PWM to PGND VDD V IOUT Continuous output current A Peak output current (3) VIN = 12 V, VDD = 5 V, VOUT = 1.2 V, ƒSW = 500 kHz (2) 40 IOUT-PK ƒSW Switching frequency CBST = 0.1 µF (min), VOUT = 2.5 V (max) On-time duty cycle ƒSW = 1 MHz Minimum PWM on-time (2) (3) 4 1250 A kHz 85% 20 Operating junction temperature (1) 60 –40 ns 125 °C Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings. Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins. System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM CSD95496QVM www.ti.com SLPS675 – JUNE 2017 7 Application Schematic P12V AVSP TPS53659 AVSN BOOT VIN ASKIP# EN/FCCM P5V BOOT_R CSD95496QVM PWM1 PWM VOS VSW VDD TAO LSET PGND LOAD IOUT REFIN ACSP1 P12V BOOT VIN P5V BOOT_R CSD95496QVM PWM APWM2 EN/FCCM VOS VSW VDD TAO LSET PGND IOUT REFIN VREF ADDR ACSP2 3.3V P12V V3P3 BOOT VIN PWM APWM3 P12V VIN_CSNIN P5V BOOT_R CSD95496QVM EN/FCCM VOS VSW VDD TAO CSPIN VCCIO LSET PGND IOUT REFIN BEN_VCCIO SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT# SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# ACSP3 TSEN VREF 3.3V AGND ACSP4 Copyright © 2016, Texas Instruments Incorporated Figure 1. Application Schematic Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components not shown. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM 5 CSD95496QVM SLPS675 – JUNE 2017 www.ti.com 8 Device and Documentation Support 8.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 8.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 8.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 8.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM CSD95496QVM www.ti.com SLPS675 – JUNE 2017 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 9.1 Mechanical Drawing 4.1 3.9 A B PIN 1 INDEX AREA 5.1 4.9 1.05 MAX C SEATING PLANE 0.08 C 0.05 0.00 2X 2.4 0.1 EXPOSED THERMAL PAD 0.6 0.4 (0.2) TYP 2X (0.31) 9 10 2X 4 4.4 0.1 1 18 16X 0.5 PIN 1 ID (OPTIONAL) 18X 0.6 10X 0.4 0.3 0.2 0.1 0.05 C A B C 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM 7 CSD95496QVM SLPS675 – JUNE 2017 www.ti.com 9.2 Recommended PCB Land Pattern (2.5) SYMM 10X (0.7) 1 18 2X (1.275) 10X (0.25) 8X (0.5) SYMM 2X (0.725) 5 14 6 (R0.05) TYP (4.5) 13 2X (1.85) METAL UNDER SOLDER MASK 10 9 SOLDER MASK OPENING 2X (0.31) 2X (0.8) 2X (1) ( 0.2) VIA TYP (3.7) 0.05 MIN ALL AROUND 0.05 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB Attachment (SLUA271). 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM CSD95496QVM www.ti.com SLPS675 – JUNE 2017 9.3 Recommended Stencil Opening METAL TYP SYMM 10X (0.7) (0.655) (R0.05) TYP 1 18 10X (0.25) 8X (0.5) SYMM (1.45) TYP 5 14 6 13 2X (1.75) 6X (1.25) 10 9 2X (0.31) 2X (0.7) 6X (1.11) (3.7) 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95496QVM 9 PACKAGE OPTION ADDENDUM www.ti.com 20-Sep-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD95496QVM ACTIVE VSON-CLIP DMH 18 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -55 to 150 95496QM CSD95496QVMT ACTIVE VSON-CLIP DMH 18 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -55 to 150 95496QM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 20-Sep-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CSD95496QVM VSONCLIP DMH 18 2500 330.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 CSD95496QVMT VSONCLIP DMH 18 250 180.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD95496QVM VSON-CLIP DMH 18 2500 370.0 355.0 55.0 CSD95496QVMT VSON-CLIP DMH 18 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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